TDA8754EL/11/C1_技术文档

TDA8754

Triple 8-bit video ADC up to 270 Msample/s

Rev. 07 — 3 May 2007

Product data sheet

1. General description

The TDA8754 is a complete triple 8-bit Analog-to-Digital Converter (ADC) with an

integrated Phase-Locked Loop (PLL) running up to 270 Msample/s and analog

preprocessing functions (clamp and programmable gain ampliﬁer) optimized for capturing

RGB/YUV graphic signals.

The PLL generates a pixel clock from inputs HSYNC and COAST.

The TDA8754 offers full sync processing for Sync-On-Green (SOG) applications. A clamp

signal may be generated internally or provided externally.

The clamp levels, gains and other settings are controlled via the I²C-bus interface.

This IC supports display resolutions up to QXGA (2048 × 1536) at 85 Hz.

2. Features

I 3.3 V power supply

I Temperature range from −10 °C to +70 °C

I Triple 8-bit ADC:

N 0.25 LSB Differential Non-Linearity (DNL)

N 0.6 LSB Integral Non-Linearity (INL)

I Analog sampling rate from 12 Msample/s up to 270 Msample/s

I Maximum data rate:

N Single port mode: 140 MHz

N Dual port mode: 270 MHz

N 3.3 V LV-TTL outputs

I PLL control via I²C-bus:

N 390 ps PLL jitter peak to peak at 270 MHz

N Low PLL drift with temperature (2 phase steps maximum)

N PLL generates the ADC sampling clock which can be locked on the line frequency

from 15 kHz to 150 kHz

N Integrated PLL divider

N Programmable phase clock adjustment cells

I Three clamp circuits for programming a clamp code from −24 to +136 by steps of

1 LSB (mid-scale clamping for YUV signal)

I Internal generation of clamp signal

I Three independent blanking functions

I Input:

N 700 MHz analog bandwidth

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

N Two independent analog inputs selectable via I²C-bus

N Analog input from 0.5 V to 1 V (p-p) to produce a full-scale ADC input of 1 V (p-p)

N Three controllable ampliﬁers: gain control via I²C-bus to produce full-scale

peak-to-peak output with a half LSB resolution

I Synchronization:

N Frame and ﬁeld detection for interlaced video signal

N Parasite synchronization pulse detection and suppression

N Sync processing for composite sync, 3-level sync and sync-on-green signals

N Polarity and activity detection

I IC control via I²C-bus serial interface

I Power-down mode

I LQFP144 and LBGA208 package:

N LBGA208 package pin-to-pin compatible with TDA8756

3. Applications

I LCD panels drive

I RGB/YUV high-speed digitizing

I LCD projection system

I New TV concept

4. Quick reference data

Table 1.

Quick reference data

Symbol Parameter

Conditions

Min

3.0

10

-

Typ

3.3

-

Max

3.6

270

-

Unit

V

V_CCA

V_CCD

V_CCO

f_PLL

analog supply voltage

digital supply voltage

output supply voltage

output clock frequency

effective number of bits

V

MHz

bit

ENOB

f_clk= 270 MHz;

f_i= 10 MHz

7.6

INL

DNL

P_tot

integral non-linearity

differential non-linearity

total power dissipation

f_clk= 270 MHz;

f_i= 10 MHz

-

±0.6

±1.3

bit

W

f_clk= 270 MHz;

f_i= 10 MHz

±0.25 ±0.6

1.0 1.3

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

2 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

5. Ordering information

Table 2.

Ordering information

Type number

Maximum Package

sampling

frequency

Name

Description

Version

TDA8754HL/11/C1

TDA8754HL/14/C1

TDA8754HL/17/C1

TDA8754HL/21/C1

TDA8754HL/27/C1

TDA8754EL/11/C1

TDA8754EL/14/C1

TDA8754EL/17/C1

TDA8754EL/21/C1

TDA8754EL/27/C1

110 MHz

140 MHz

170 MHz

210 MHz

270 MHz

110 MHz

140 MHz

170 MHz

210 MHz

270 MHz

LQFP144

plastic low proﬁle quad ﬂat package;

144 leads; body 20 × 20 × 1.4 mm

SOT486-1

LBGA208^[1]plastic low proﬁle ball grid array package; 208 balls; body

SOT774-1

17 × 17 × 1.05 mm

[1] Values are not yet guaranteed.

6. Block diagram

3×

RGB

output A

LV-TTL

BUFFERS

3×

RGB1

input

CLAMP

AGC

DMX

ADC

RGB2

input

RGB

output B

LV-TTL

BUFFERS

ACTIVITY

DETECTION

HPDO

TDA8754

SOGIN1

SOGIN2

CKDATA

DEO

SYNC

SEPARATOR

HSYNC1

CLKDMX

HCOUNTER

CHSYNC1

HSYNC2

CHSYNC2

COAST

POWER

MANAGEMENT

PLL

VSYNC1

VSYNC2

2

I C-BUS

SLAVE

mgu895

VSYNCO

HSYNCO

CKEXT CKREFO SDA SCL A0

FIELDO

Fig 1. Block diagram

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

3 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

7. Pinning information

7.1 Pinning

1

108

TDA8754HL

36

73

001aac980

Fig 2. Pin conﬁguration LQFP144 package

ball A1

index area

2

4

6

8

10 12 14 16

9 11 13 15

1

3

5

7

A

B

C

D

E

F

G

H

J

TDA8754EL

K

L

M

N

P

R

T

001aac981

Transparent top view

Fig 3. Pin conﬁguration LBGA208 package

7.2 Pin description

Table 3.

Pin description for LQFP144 package

Symbol

1

Description

GNDD(TTL)

V_CCD(TTL)

HSYNC2

CHSYNC2

V_CCA(PLL)

HSYNC1

CHSYNC1

TTL input digital ground

TTL input digital supply voltage

2

3

horizontal synchronization pulse input 2

composite horizontal synchronization pulse input 2

PLL analog supply voltage

4

5

6

horizontal synchronization pulse input 1

composite horizontal synchronization pulse input 1

7

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

4 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 3.

Pin description for LQFP144 package …continued

Symbol

GNDA(PLL)

CZ

8

Description

PLL analog ground

9

PLL ﬁlter input

GNDA(CPO)

CP

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

CPO analog ground

PLL ﬁlter input

PMO

phase measurement output (test)

SUB analog ground

GNDA(SUB)

CAPSOGIN1

CAPSOGO

CAPSOGIN2

GNDA(SOG)

SOGIN1

V_CCA(SOG)

SOGIN2

V_CCA(R)

decoupling SOG input 1

decoupling SOG output

decoupling SOG input 2

SOG analog ground

sync-on-green input 1

SOG analog supply voltage

sync-on-green input 2

red channel analog supply voltage

red channel analog input 1

red channel 1 analog ground

red channel analog input 2

red channel 2 analog ground

main regulator decoupling input

red channel ladder decoupling input

red channel clamp capacitor input

green channel analog supply voltage

green channel analog input 1

green channel 1 analog ground

green channel analog input 2

green channel 2 analog ground

green channel ladder decoupling input

green channel clamp capacitor input

blue channel analog supply voltage

blue channel analog input 1

blue channel 1 analog ground

blue channel analog input 2

blue channel 2 analog ground

blue channel ladder decoupling input

blue channel clamp capacitor input

Automatic Gain Control (AGC) output

ADC digital ground

RIN1

GNDA(R1)

RIN2

GNDA(R2)

DEC

RBOT

RCLPC

V_CCA(G)

GIN1

GNDA(G1)

GIN2

GNDA(G2)

GBOT

GCLPC

V_CCA(B)

BIN1

GNDA(B1)

BIN2

GNDA(B2)

BBOT

BCLPC

AGCO

GNDD(ADC)

V_CCD(ADC)

GNDD(SUB)

PWD

ADC digital supply voltage

SUB digital ground

power-down control input

TEST

test input; must be connected to ground

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

5 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 3.

Pin description for LQFP144 package …continued

Description

Symbol

BB0

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

blue channel ADC output B bit 0

blue channel ADC output B bit 1

blue channel ADC output B bit 2

blue channel ADC output B bit 3

blue channel ADC output B bit 4

blue channel ADC output B bit 5

blue channel ADC output B bit 6

blue channel ADC output B bit 7

blue channel B output supply voltage

blue channel B output ground

BB1

BB2

BB3

BB4

BB5

BB6

BB7

V_CCO(BB)

GNDO(BB)

BOR

blue channel ADC output bit out of range

blue channel ADC output A bit 0

blue channel ADC output A bit 1

blue channel ADC output A bit 2

blue channel ADC output A bit 3

blue channel ADC output A bit 4

blue channel ADC output A bit 5

blue channel ADC output A bit 6

blue channel ADC output A bit 7

blue channel A output supply voltage

blue channel A output ground

BA0

BA1

BA2

BA3

BA4

BA5

BA6

BA7

V_CCO(BA)

GNDO(BA)

GB0

green channel ADC output B bit 0

green channel ADC output B bit 1

green channel ADC output B bit 2

green channel ADC output B bit 3

green channel ADC output B bit 4

green channel ADC output B bit 5

green channel ADC output B bit 6

green channel ADC output B bit 7

green channel B output supply voltage

green channel B output ground

green channel ADC output bit out of range

green channel ADC output A bit 0

green channel ADC output A bit 1

green channel ADC output A bit 2

green channel ADC output A bit 3

green channel ADC output A bit 4

green channel ADC output A bit 5

green channel ADC output A bit 6

green channel ADC output A bit 7

green channel A output supply voltage

GB1

GB2

GB3

GB4

GB5

GB6

GB7

V_CCO(GB)

GNDO(GB)

GOR

GA0

GA1

GA2

GA3

GA4

GA5

GA6

GA7

V_CCO(GA)

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

6 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 3.

Pin description for LQFP144 package …continued

Symbol

GNDO(GA)

RB0

90

Description

green channel A output ground

red channel ADC output B bit 0

red channel ADC output B bit 1

red channel ADC output B bit 2

red channel ADC output B bit 3

red channel ADC output B bit 4

red channel ADC output B bit 5

red channel ADC output B bit 6

red channel ADC output B bit 7

red channel B output supply voltage

red channel B output ground

red channel ADC output bit out of range

red channel ADC output A bit 0

red channel ADC output A bit 1

red channel ADC output A bit 2

red channel ADC output A bit 3

red channel ADC output A bit 4

red channel ADC output A bit 5

red channel ADC output A bit 6

red channel ADC output A bit 7

red channel A output supply voltage

red channel A output ground

clock output digital supply voltage

data clock output

91

RB1

92

RB2

93

RB3

94

RB4

95

RB5

96

RB6

97

RB7

98

V_CCO(RB)

GNDO(RB)

ROR

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

V_CCO(RA)

GNDO(RA)

V_CCO(CLK)

CKDATA

GNDO(CLK)

GNDD(I2C)

V_CCD(I2C)

A0

clock output digital ground

I²C-bus lines digital ground

I²C-bus lines digital supply voltage

I²C-bus address control input

I²C-bus serial data input and output

I²C-bus serial clock input

SDA

SCL

DIS

I²C-bus disable control input

TDO

scan test output

TCK

scan test mode input; must be connected to ground

clamp pulse input

CLP

STBDVI

GNDD(MCF)

V_CCD(MCF)

HSYNCO

DEO

DVI standby output

MCF digital ground

MCF digital supply voltage

horizontal synchronization pulse output

data enable output

HPDO

GNDO(TTL)

hot plug detector output

TTL output digital ground

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

7 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 3.

Pin description for LQFP144 package …continued

Description

Symbol

V_CCO(TTL)

VSYNCO

FIELDO

CLPO

131

132

133

134

135

136

137

138

139

140

141

142

143

144

TTL output digital supply voltage

vertical synchronization pulse output

ﬁeld information output

clamp output

CKREFO

CSYNCO

ACRX2

reference output clock; re-synchronized horizontal negative pulse

composite synchronization output

test pin; should be connected to ground

SLC digital ground

ACRX1

GNDD(SLC)

V_CCD(SLC)

CKEXT

SLC output digital supply voltage

external clock input

COAST

PLL coast control input

VSYNC2

VSYNC1

vertical synchronization pulse input 2

vertical synchronization pulse input 1

Table 4.

Symbol

SOGIN1

GNDA(PLL)

SOGIN2

GNDA(PLL)

HSYNC2

CHSYNC2

COAST

CSYNCO

FIELDO

HSYNCO

SCL

Pin description for LBGA208 package

Ball

A1

Description

sync-on-green input 1

A2

PLL analog ground

A3

sync-on-green input 2

A4

PLL analog ground

A5

horizontal synchronization pulse input 2

composite horizontal synchronization pulse input 2

PLL coast control input

A6

A7

A8

composite synchronization output

ﬁeld information output

A9

A10

A11

A12

A13

A14

A15

A16

B1

horizontal synchronization pulse output

I²C-bus serial clock input

not connected

n.c.

not connected

DIS

I²C-bus disable control input

I²C-bus address control input

data clock output

A0

CKDATA

GNDA(PLL)

PMO

PLL analog ground

B2

phase measurement output (test)

PLL analog ground

GNDA(PLL)

V_CCA(PLL)

CLP

B3

B4

PLL analog ground

B5

PLL analog supply voltage

clamp pulse input

B6

CKEXT

CKREFO

B7

external clock input

B8

reference output clock; re-synchronized horizontal negative pulse

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

8 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 4.

Pin description for LBGA208 package …continued

Symbol

VSYNCO

DEO

Ball

B9

Description

vertical synchronization pulse output

B10

B11

B12

B13

B14

B15

B16

C1

data enable output

SDA

I²C-bus serial data input and output

not connected

n.c.

not connected

n.c.

not connected

GNDO(CLK)

V_CCO(CLK)

RIN1

clock output digital ground

clock output digital supply voltage

red channel analog input 1

analog ground

GNDA

CAPSOGIN1

CAPSOGIN2

CAPSOGO

HSYNC1

VSYNC1

CLPO

C2

C3

decoupling SOG input 1

decoupling SOG input 2

decoupling SOG output

horizontal synchronization pulse input 1

vertical synchronization pulse input 1

clamp output

C4

C5

C6

C7

C8

n.c.

C9

not connected

n.c.

C10

C11

C12

C13

C14

C15

C16

D1

not connected

TCK

scan test mode input

TDO

scan test output

V_CCD(I2C)

n.c.

I²C-bus lines digital supply voltage

not connected

n.c.

not connected

n.c.

not connected

GNDA

CZ

analog ground

D2

analog ground

D3

PLL ﬁlter input

CP

D4

PLL ﬁlter input

GNDA(CPO)

CHSYNC1

VSYNC2

HPDO

n.c.

D5

CPO analog ground

D6

composite horizontal synchronization pulse input 1

vertical synchronization pulse input 2

hot plug detector output

not connected

D7

D8

D9

n.c.

D10

D11

D12

D13

D14

D15

D16

E1

not connected

V_CCO(TTL)

GNDO(TTL)

GNDD(I2C)

n.c.

TTL output digital supply voltage

TTL output digital ground

I²C-bus lines digital ground

not connected

n.c.

not connected

n.c.

not connected

RIN2

red channel analog input 2

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

9 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 4.

Pin description for LBGA208 package …continued

Symbol

GNDA

GNDD(TTL)

V_CCD(TTL)

GNDD(SLC)

V_CCD(SLC)

n.c.

Ball

E2

Description

analog ground

E3

E4

E7

TTL input digital ground

TTL input digital supply voltage

SLC digital ground

SLC output digital supply voltage

not connected

E8

E9

E10

E13

E14

E15

E16

F1

n.c.

not connected

n.c.

not connected

n.c.

not connected

GNDA

RBOT

GNDA

n.c.

analog ground

F2

analog ground

F3

red channel ladder decoupling input

analog ground

F4

F13

F14

F15

F16

G1

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

GIN1

GNDA

DEC

green channel analog input 1

analog ground

G2

G3

main regulator decoupling input

analog supply voltage

not connected

V_CCA

n.c.

G4

G5

G12

G13

G14

G15

G16

H1

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

GNDA

RCLPC

V_CCA

n.c.

analog ground

H2

analog ground

H3

analog ground

H4

red channel clamp capacitor input

analog supply voltage

not connected

H5

H12

H13

H14

H15

H16

J1

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

GIN2

GNDA

green channel analog input 2

analog ground

J2

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

10 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 4.

Pin description for LBGA208 package …continued

Symbol

GBOT

GNDA

GCLPC

n.c.

Ball

J3

Description

green channel ladder decoupling input

analog ground

J4

J5

green channel clamp capacitor input

not connected

J12

J13

J14

J15

J16

K1

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

GNDA

BCLPC

V_CCA

n.c.

analog ground

K2

analog ground

K3

analog ground

K4

blue channel clamp capacitor input

analog supply voltage

not connected

K5

K12

K13

K14

K15

K16

L1

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

BIN1

GNDA

BBOT

V_CCA

n.c.

blue channel analog input 1

analog ground

L2

L3

blue channel ladder decoupling input

analog supply voltage

not connected

L4

L13

L14

L15

L16

M1

M2

M3

M4

M7

M8

M9

M10

M13

M14

M15

M16

N1

n.c.

not connected

n.c.

not connected

n.c.

not connected

GNDA

AGCO

TEST

V_CCO

GNDO

n.c.

analog ground

AGC output

test input

data output digital supply voltage

data output digital ground

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

BIN2

GNDA

GNDD(ADC)

blue channel analog input 2

analog ground

N2

N3

ADC digital ground

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

11 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 4.

Pin description for LBGA208 package …continued

Symbol

GNDD(ADC)

BA2

Ball

N4

Description

ADC digital ground

N5

blue channel ADC output A bit 2

data output digital supply voltage

green channel ADC output B bit 4

green channel ADC output B bit 0

green channel ADC output A bit 4

green channel ADC output A bit 0

data output digital ground

V_CCO

GB4

N6

N7

GB0

N8

GA4

N9

GA0

N10

N11

N12

N13

N14

N15

N16

P1

GNDO

PWD

n.c.

power-down control input

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

V_CCD(ADC)

BB1

ADC digital supply voltage

P2

ADC digital supply voltage

P3

blue channel ADC output B bit 1

blue channel ADC output A bit 6

blue channel ADC output A bit 3

blue channel ADC output bit out of range

green channel ADC output B bit 5

green channel ADC output B bit 1

green channel ADC output A bit 5

green channel ADC output A bit 1

red channel ADC output B bit 6

red channel ADC output B bit 3

red channel ADC output B bit 0

red channel ADC output A bit 5

red channel ADC output A bit 2

red channel ADC output bit out of range

blue channel ADC output B bit 6

blue channel ADC output B bit 4

blue channel ADC output B bit 2

blue channel ADC output A bit 7

blue channel ADC output A bit 4

blue channel ADC output A bit 0

green channel ADC output B bit 6

green channel ADC output B bit 2

green channel ADC output A bit 6

green channel ADC output A bit 2

red channel ADC output B bit 7

red channel ADC output B bit 4

BA6

P4

BA3

P5

BOR

GB5

P6

P7

GB1

P8

GA5

P9

GA1

P10

P11

P12

P13

P14

P15

P16

R1

RB6

RB3

RB0

RA5

RA2

ROR

BB6

BB4

R2

BB2

R3

BA7

R4

BA4

R5

BA0

R6

GB6

R7

GB2

R8

GA6

R9

GA2

R10

R11

R12

RB7

RB4

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

12 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 4.

Pin description for LBGA208 package …continued

Symbol

RB1

RA6

RA3

RA0

BB7

BB5

BB3

BB0

BA5

BA1

GB7

GB3

GA7

GA3

GOR

RB5

RB2

RA7

RA4

RA1

Ball

R13

R14

R15

R16

T1

Description

red channel ADC output B bit 1

red channel ADC output A bit 6

red channel ADC output A bit 3

red channel ADC output A bit 0

blue channel ADC output B bit 7

blue channel ADC output B bit 5

blue channel ADC output B bit 3

blue channel ADC output B bit 0

blue channel ADC output A bit 5

blue channel ADC output A bit 1

green channel ADC output B bit 7

green channel ADC output B bit 3

green channel ADC output A bit 7

green channel ADC output A bit 3

green channel ADC output bit out of range

red channel ADC output B bit 5

red channel ADC output B bit 2

red channel ADC output A bit 7

red channel ADC output A bit 4

red channel ADC output A bit 1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

8. Functional description

8.1 Functional description

This triple high-speed 8-bit ADC is designed to convert RGB/YUV signals coming from an

analog source into digital data used by a LCD driver (pixel clock up to 270 MHz with

analog source) or projections systems.

8.1.1 Power management

It is possible to put the TDA8754 in Standby mode by setting bit STBY = 1 or to put the

whole device in Power-down mode by setting pin PWD to HIGH level.

8.1.1.1 Standby mode

In Standby mode, the status of the blocks is as follows:

• Activity detection, I²C-bus slave, sync separator and SOG are still active

• Pixel counter, ADCs, demultiplexers, AGC and clamp cells are inactive

• Output buffers to the RGB block (RGB 0 to 7, CKDATA, DEO, HSYNCO and

VSYNCO) are in high-impedance state

• Output HPDO is still active

• Output buffers (ROR, BOR, GOR, CKREFO, CSYNCO, CLPO and FIELDO) are in a

LOW-level state.

TDA8754_7

Product data sheet

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TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

8.1.1.2 Power-down mode

In Power-down mode the status of the blocks is as follows:

• All digital inputs and outputs are in high-impedance state

• All blocks are inactive (I²C-bus, activity detection, ADCs, etc.)

• Analog output is left uncontrolled

• I²C-bus is left in high-impedance state.

8.2 Analog video input

The RGB/YUV video inputs are externally AC coupled and are internally DC polarized.

The synchronization signals are also used by the device as input for the internal PLL and

the automatic clamp.

8.2.1 Analog multiplexers

The TDA8754 has two analog inputs (RGB input 1 and RGB input 2) selectable via the

I²C-bus.

The sync management can be achieved in several ways:

• Choice between two analog inputs HSYNC and two analog inputs VSYNC

• Choice between two analog inputs CHSYNC

• Choice between two analog inputs SOG.

8.2.2 Activity detection

When a signal is connected or disconnected on pins HSYNC1(2), CHSYNC1(2),

VSYNC1(2) and SOG1(2), then bit HPDO is set to logic 1 and pin HPDO is set to HIGH to

advise the user of a change. Bit HPDO is set to logic 0 and pin HPDO is set to LOW when

register ACTIVITY2 has been read.

When the synchronization pulse on pin SOG is 3-level, the system will automatically be

able to detect that a 3-level sync is present and will force bit 3LEVEL to logic 1. It is

possible to disable this function with bit FTRILEVEL.

When an interlaced signal is detected, bit ACFIELD is set to logic 1. When the signal

detected is progressive, this bit is set to logic 0. Any change in this bit results into setting

bit HPDO = 1 and pin HPDO = HIGH.

A ﬁeld detection unit is available on pin FIELDO which output is given by the sync

separator. The ﬁeld identity is given by pin FIELDO. This pin gives the ﬁeld of interlaced

signal input.

An automatic polarity detection is also available on pins HSYNC1(2), VSYNC1(2) and

CHSYNC1(2). The output on pin HPDO is not affected by the change of polarity of these

inputs.

8.2.3 ADC

The three ADCs are designed to convert R, G and B (or Y, U and V) signals at a

maximum frequency of 270 Msample/s. The ADC input range is 1 V (p-p) full-scale and

the pipeline delay is 2 ADC clock cycles from the input sampling to the data output.

TDA8754_7

Product data sheet

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TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

The reference ladders regulators are integrated.

8.2.4 Clamp

Three independent parallel clamping circuits are used to clamp the video input signals on

programmable black levels. The clamp levels may be set from −24 to +136 LSBs in steps

of 1 LSB. They are controlled by three 9-bit I²C-bus registers (OFFSETR, OFFSETG and

OFFSETB).

The clamp pulse can be generated internally (based on the PLL clock reference) or can

be externally applied on pin CLP.

Remark: To prevent clamp noise when using internal clamp generated by the pixel

counter (bit CLPSEL2 = 0), it is advised to delay the clamp pulse by 16 pixels using the

HSYNCL register.

By setting correctly the I²C-bus bits, it is possible to inhibit the clamp request with the

Vsync signal. This inhibition will be effected by forcing logic 0 on the clamp request output.

It should be noted that the clamp period can start on the falling edge of the clamp request

and that the high level of the clamp request sets the ADC outputs in the blanking mode.

This means that by forcing the clamp signal request to logic 0 by using Vsync, a falling

edge may happen on the clamp request if this signal was at logic 1 before enforcing the

inhibition. To avoid this, the user has to guarantee that the Vsync signal used for the clamp

inhibition will not be set during a high level of the clamp request signal.

Remark: If signal Vsync is coming from the external pin VSYNC, this signal may be used

to coast the PLL. In order to properly do the coast, the edge of signal Vsync (COAST)

must not appear at the same time as the edge of signal Hsync. This condition is similar to

the pin CLP inhibition condition.

8.2.5 AGC

Three independent variable gain ampliﬁers are used to provide, for each channel, a

full-scale input signal to the 8-bit ADC. The gain adjustment range is designed in such a

way that for an input range varying from 0.5 to 1 V (p-p), the output signal corresponds to

the ADC full-scale input of 1 V (p-p).

8.3 HSOSEL, DEO and SCHCKREFO

Bit HSOSEL allows to have a full correlation phase behavior between outputs CKDATA

and HSYNCO when bit HSOSEL = 0 (Hsync from counter). If HSOSEL = 0 and bits PA4

to PA0 of register PHASE are changed to chose the best sampling time, the phase

relationship between outputs CKDATA and HSYNCO will stay unchanged. After the video

standard is determined, bit HSOSEL must be set to a logic 0 for normal operation mode.

To use the Hsync from the counter the registers HSYNCL, HBACKL, HDISPLMSB and

HDISPLLSB should be set properly in order to create the correct HSYNCO and DEO

output signals (see Figure 5 and Figure 6), which is depending on video standard. Output

signal DEO should be used to determine the ﬁrst active pixel.

The demultiplexed mode should be used (bit DMXRGB = 1) and the output ﬂow is

alternated between port A and port B in case the sampling frequency is over

140 Msample/s (clock frequency). It is necessary, in order to warrant that the outputs

HSYNCO and DEO are always changing on CKDATA output rising edge (see Figure 7),

TDA8754_7

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TDA8754

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Triple 8-bit video ADC up to 270 Msample/s

that the values HSYNCL, HBACKL and HDISPL (see Figure 5) are even value. If an odd

value is entered the outputs HSYNCO and DEO can change state during falling edge,

which is not compliant with the t_h(o)and t_d(o)speciﬁed output timing.

Bit SCHCKREFO is used if in demultiplexed mode one pixel shift is needed in the DEO

signal (to move the screen one vertical line). By setting bit SCHCKREFO from a logic 0 to

a logic 1 a left move is obtained, also the timing relationship between HSYNCO, DEO and

CKDATA stays unchanged. An even number of pixel moves is done by changing the value

of HBACKL and HSYNCL. The correct combination of bits HBACKL, HSYNCL and

SCHCKREFO places the ﬁrst active pixel at the beginning of the screen with always the

correct phase relationship between outputs DEO, HSYNCO and CKDATA.

Bit HSOSEL should be set to a logic 0 only after the PLL is stable, so only after the video

standard has been found and correct PLL parameters have been set in the TDA8754. Bit

HSOSEL should be set to a logic 1 to have a stable HSYNCO signal during the video

recognition. The video standard can be recognized by using the signals FIELDO,

VSYNCO and HSYNCO. The phase relation between CKDATA and HSYNCO (or DEO) is

undeﬁned if bit HSOSEL = 1.

8.4 PLL

The ADCs are clocked by either the internal PLL locked to the reference clock (Hsync

from input or Hsync from sync separator) or to an external clock connected to pin CKEXT.

This selection is performed via the I²C-bus by setting bit CKEXT. To use the external

clock, bit CKEXT must be reset to logic 1.

The PLL phase frequency detector can be disconnected during the frame ﬂyback (vertical

blanking) or the unavailability of the Ckref signal by using the coast function. The coast

signal can be derived from the VSYNC1(2) input, from the Vsync extracted by the sync

separator or from the coast input. The coast function can be disabled with bit COE.

The coast signal may be active either HIGH or LOW by setting bit COS.

It is possible to control the phase of the ADC clock via the I²C-bus with the included digital

phase-shift controller. The phase register (5 bits) enables to shift the phase by steps of

11.25 deg.

The PLL also provides a CKDATA clock. This clock is synchronized with the data outputs

whatever the output mode is.

It is possible to delay the CKDATA clock with a constant delay (t = 2 ns compared to the

outputs) by setting bit DLYCLKRGB = 1. Moreover, it is possible to invert this output by

setting bit CKDATINV = 1.

When the PLL reference signal comes from the separator, the PLL rising edge must be

preferably used in order to not use the PLL coast mode. It should be noted that the

HSYNCO output of the sync separator is always a mostly LOW signal, whatever is the

polarity of the composite sync input. The VSYNCO output signal of the sync separator is

also mostly LOW signal. It is at a high state during the vertical blanking.

8.5 Sync-on-green

When the SOG input is selected (bit SOGSEL = 1), the SOG charge pump current bits

SOGI[1:0] should be programmed in function of the input signal; see Table 5.

TDA8754_7

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TDA8754

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Triple 8-bit video ADC up to 270 Msample/s

A hum remover is implemented in the SOG. It removes completely the hum perturbation

on the ﬁrst or second edge of the horizontal sync pulse for digital video input like VESA,

and on the second edge only for analog video input signal like TV or HDTV.

The maximum hum perturbation is 250 mV (p-p) at 60 Hz to have a correct SOG

functionality.

Table 5.

Charge pump current programming^[1]

BITS SOGI[1:0]

Maximum value

Standard

∆Tvideo / ∆Tline ∆Tsync / ∆Tline

00

83.5 %

14.8 %

TV standards and non-VESA

standards

01

10

86.0 %

90.5 %

12.6 %

8.6 %

all TV, HDTV and VESA standards

HDTV standards or non-VESA

standards

11

test mode

[1] Deﬁnitions:

∆Tvideo — Total time in 2 frames when video signal is strictly superior to black level.

∆Tline — Total time of 2 frames.

∆Tsync — Total time in 2 frames when the video signal is strictly inferior to black level.

8.6 Programmable coast

When the values of PRECOAST[2:0] = 0 and POSTCOAST[4:0] = 0, the coast pulse

equals the Vsync input.

When an interlaced signal is used, the regenerated coast pulse width may vary from one

frame to another of one Hsync pulse. In that case, the programmed value of

PRECOAST[2:0] needs to be increased by one compared to the expected minimum

number of Hsync coast pulses before the vertical sync signal.

8.7 Data enable

This signal qualiﬁes the active data period on the horizontal line. Pin DEO = HIGH during

the active display time and LOW during the blank time. The start of this signal can be

adjusted with bits HSYNCL[9:0] and HBACKL[9:0]. The length of this signal can be

adjusted with bits HDISPL[11:0].

8.8 Sync separator

The sync separator is compatible with TV, HDTV and VESA standards.

If the green video signal has composite sync on it (sync-on-green), the SOG function

allows to separate the Chsync and the active video part. The Chsync signal coming from

this SOG function is accessible through pin CSYNCO.

It is possible to extract the Hsync and the Vsync signals by using the sync separator from

this (C)Hsync signal coming from SOG or coming from the (C)Hsync input.

This function is able to get rid of the additional synchronization pulses in vertical blanking

like equalization or serration pulses.

TDA8754_7

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TDA8754

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8.9 3-level

Triple 8-bit video ADC up to 270 Msample/s

When the synchronization pulse of the input of the SOG is 3-level, the system will be able

to detect that a 3-level sync is present and will advise the customer if a change is

observed by setting bit HPDO = 1 and pin HPDO = HIGH. It is possible to disable this

function with bit FTRILEVEL. When this automatic function is disabled, the manual mode

will only inﬂuence the separator circuitry.

9. I²C-bus register description

9.1 I²C-bus formats

9.1.1 Write 1 register

Each register is programmed independently by giving its subaddress and its data content.

Table 6.

SDA line Description

I²C-bus sequence for writing 1 register

S

master starts with a start condition

Byte 1

master transmits device address (7 bits) plus write command bit (R/W = 0)

slave generates an acknowledge

A

Byte 2

master transmits programming mode and register subaddress to write to

slave generates an acknowledge

A

Byte 3

master transmits data 1

A

P

slave generates an acknowledge

master generates a stop condition

Table 7.

Bits

Byte format for writing 1 register

7

6

5

4

3

2

1

0

R/W

-

Byte 1

device address

A6

1

A5

0

A4

0

A3

1

A2

1

A1

0

A0

X

0

Byte 2

Byte 3

programming mode

register subaddress

-

MODE

SA4

-

SA3

SA2

-

SA1

SA0

-

X

0

-

data 1

D4

D7

D6

D5

D3

D2

D1

D0

TDA8754_7

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TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 8.

Write format bit description

Bit

Symbol

Description

Byte 1

7 to 1

A[6:0]

R/W

Device address; the TDA8754 address is 1001 10X; bit A0 relates

with the voltage level on pin A0

0

Write command bit; if R/W = 0, then write action

Byte 2

7 to 6

5

-

not used

MODE

Mode selection bit; if MODE = 0, then each register can be written

independently

4 to 0

SA[4:0]

D[7:0]

Register subaddress; subaddress of the selected register (from

0 0000 to 1 1111)

Byte 3

7 to 0

Data 1; this value is written in the selected register

9.1.2 Write all registers

All registers are programmed one after the other, by giving this initial condition

(XX11 1111) as the subaddress state; thus, the registers are charged following the

predeﬁned sequence of 32 bytes (from subaddress 0 0000 to 1 1111).

Table 9.

SDA line Description

I²C-bus sequence for writing all registers

S

master starts with a start condition

Byte 1

master transmits device address (7 bits) plus write command bit (R/W = 0)

slave generates an acknowledge

A

Byte 2

master transmits programming mode and register subaddress to write to

slave generates an acknowledge

A

Byte 3

master transmits data 1

A

slave generates an acknowledge

:

Byte 34

master transmits data 32

A

P

slave generates an acknowledge

master generates a stop condition

Table 10. Byte format for writing all registers

Bits

7

6

5

4

3

2

1

0

R/W

-

Byte 1

device address

A6

1

A5

0

A4

0

A3

1

A2

1

A1

0

A0

X

0

Byte 2

programming mode

register subaddress

-

MODE

SA4

1

SA3

SA2

1

SA1

SA0

1

X

0

1

Byte (2 + n)

data n

D7

D6

D5

D4

D3

D2

D1

D0

TDA8754_7

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TDA8754

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Triple 8-bit video ADC up to 270 Msample/s

Table 11. Write format bit description

Bit

Symbol

Description

Byte 1

7 to 1

A[6:0]

R/W

Device address; the TDA8754 address is 1001 10X; bit A0 relates

with the voltage level on pin A0

0

Write command bit; if R/W = 0, then write action

Byte 2

7 to 6

5

-

not used

MODE

Mode selection bit; if MODE = 1, then all registers can be written one

after the other

4 to 0

SA[4:0]

Register subaddress; initial condition is XX11 to 1111

Data n; this value is written in register 00h + n

Byte (2 + n)

7 to 0

D[7:0]

9.1.2.1 Read register

Table 12. I²C-bus sequence for reading one register

SDA line Description

S

master starts with a start condition

Byte 1

master transmits device address (7 bits) plus write command bit (R/W = 0)

slave generates an acknowledge

A

Byte 2

master transmits programming mode and register subaddress to read from

slave generates an acknowledge

A

Byte 3

master transmits read register subaddress

A

slave generates an acknowledge

Byte 4

master transmits device address (7 bits) plus read command bit (R/W = 1)

slave generates an acknowledge

A

Byte 5

slave transmits data to master

A

P

master generates an not-acknowledge after reading the data byte

master generates a stop condition

Table 13. Byte format for reading register

Bits

7

6

5

4

3

2

1

0

R/W

-

Byte 1

device address

A6

1

A5

0

A4

0

A3

1

A2

1

A1

0

A0

X

0

Byte 2

Byte 3

programming mode

register subaddress

-

MODE

SA4

1

SA3

SA2

1

SA1

SA0

1

X

0

1

read subaddress

-

RA1

-

RA0

-

0

TDA8754_7

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Triple 8-bit video ADC up to 270 Msample/s

Table 13. Byte format for reading register …continued

Bits

7

6

5

4

3

2

1

0

R/W

-

Byte 4

device address

A6

1

A5

0

A4

0

A3

A2

1

A1

0

A0

X

1

Byte 5

data 1

D4

D7

D6

D5

D3

D2

D1

D0

Table 14. Read format bit description

Bit

Symbol Description

Byte 1

7 to 1

A[6:0]

R/W

Device address; the TDA8754 address is 1001 10X; bit A0 relates to the

voltage level on pin A0

0

Write command bit; if R/W = 0, then write action

Byte 2

7 to 6

5

-

not used

MODE

Mode selection bit; if MODE = 0, then each register can be written

independently

4 to 0

Byte 3

7 to 0

Byte 4

7 to 1

SA[4:0]

RA[1:0]

Register subaddress; subaddress of the read register (1 1111)

Read address; this is the value of the read register to be selected

A[6:0]

R/W

Device address; the TDA8754 address is 1001 10X. Bit A0 relates with the

voltage level on pin A0

0

Read command bit; if R/W = 1, then read action

Byte 5

7 to 0

D[7:0]

Data 1; the value from read register is sent from the slave to the master

TDA8754_7

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TDA8754

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Triple 8-bit video ADC up to 270 Msample/s

9.3 Offset registers (R, G and B)

The offset registers contain a 9-bit value which controls the clamp level for the RGB

channels. The 8 LSBs are in the offset registers and the 1 MSB is in the coarse gain

control register. The relationship between the programming code and the level of the

clamp code is given in Table 19. The reset value is: clamp code = 0 and ADC output = 0.

Table 17. Offset registers (00h, 03h, 06h) bit allocation

Register

7

6

5

4

3

2

1

0

OFFSETR (00h)

OFFSETG (03h)

OFFSETB (06h)

Reset

OR7

OG7

OB7

0

OR6

OG6

OB6

0

OR5

OG5

OB5

0

OR4

OG4

OB4

0

OR3

OG3

OB3

0

OR2

OG2

OB2

0

OR1

OG1

OB1

0

OR0

OG0

OB0

0

Table 18. Offset registers (00h, 03h, 06h) bit description

Bit Symbol Description

OFFSETR (address: 00h)

7 to 0 OR[7:0]

offset R channel; LSB in this register and MSB bit OR8 in register

COARSER

OFFSETG (address: 03h)

7 to 0 OG[7:0]

offset G channel; LSB in this register and MSB bit OG8 in register

COARSEG

OFFSETB (address: 06h)

7 to 0 OB[7:0]

offset B channel; LSB in this register and MSB bit OB8 in register

COARSEB

Table 19. Coding for clamp level and ADC output

Value OR8 OR7 OR6 OR5 OR5 OR3 OR2 OR1 OR0 Clamp

ADC output

code

(decimal)

(code transition)

OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0

OB8 OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0

1E9h

1EAh

:

1

0

1

0

1

−24

−23

:

−24/−23

−23/−22

:

1FFh

000h

001h

:

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

−1

0

−1/0

0/1

+1

:

1/2

:

03Fh

040h

:

0

1

0

1

0

1

0

1

0

1

0

1

0

63

64

:

63/64

64/65

:

078h

079h

:

0

1

0

1

120

121

:

120/121

121/122

:

080h

0

1

0

128

128/129

TDA8754_7

Product data sheet

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TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 19. Coding for clamp level and ADC output …continued

Value OR8 OR7 OR6 OR5 OR5 OR3 OR2 OR1 OR0 Clamp

ADC output

code

(decimal)

(code transition)

OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0

OB8 OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0

:

086h

087h

0

1

0

1

0

1

134

135

134/135

135/136

9.4 Coarse registers (R, G and B)

The coarse gain of the AGC is controlled with 7 bits. The code gain can vary from

32 to 95; see Table 22.

Table 20. Coarse gain registers (01h, 04h, 07h) bit allocation with reset

Register

7

6

5

4

3

2

1

0

COARSER (01h)

COARSEG (04h)

COARSEB (07h)

Reset

OR8

OG8

OB8

0

CR6

CG6

CB6

1

CR5

CG5

CB5

0

CR4

CG4

CB4

0

CR3

CG3

CB3

0

CR2

CG2

CB2

1

CR1

CG1

CB1

1

CR0

CG0

CB0

0

Table 21. Coarse gain registers (01h, 04h, 07h) bit description

Bit

Symbol

Description

COARSER (address: 01h)

7

OR8

offset R channel; MSB bit of offset value

coarse gain of the AGC for R channel

6 to 0

CR[6:0]

COARSEG (address: 04h)

7

OG8

offset G channel; MSB bit of offset value

coarse gain of the AGC for G channel

6 to 0

CG[6:0]

COARSEB (address: 07h)

7

OB8

offset B channel; MSB bit of offset value

coarse gain of the AGC for B channel

6 to 0

CB[6:0]

Table 22. Coarse register

Value

CR6 CR5 CR4 CR3 CR2 CR1 CR0 V_i(full-scale)

CG6 CG5 CG4 CG3 CG2 CG1 CG0

Gain ADC

CB6 CB5 CB4 CB3 CB2 CB1 CB0

32

33

:

0

1

0

1

1.000

0.992

:

1.000

1.008

:

63

64

65

:

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.753

0.746

0.738

:

1.328

1.340

1.355

:

69

1

0

1

0

1

0.706

1.416

TDA8754_7

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TDA8754

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Triple 8-bit video ADC up to 270 Msample/s

Table 22. Coarse register …continued

Value

CR6 CR5 CR4 CR3 CR2 CR1 CR0 V_i(full-scale)

Gain ADC

CG6 CG5 CG4 CG3 CG2 CG1 CG0

CB6 CB5 CB4 CB3 CB2 CB1 CB0

70

:

1

0

1

0

0.698

:

1.432

:

95

1

0

1

0.500

2.000

9.5 Fine registers (R, G and B)

Fine gain control is done with 3 bits allowing 8 intermediate values between two values of

consecutive coarse gain.

Table 23. Fine gain registers (02h, 05h, 08h) bit allocation with reset

Register

7

-

6

-

5

-

4

-

3

-

2

1

0

FINER (02h)

FINEG (05h)

FINEB (08h)

Reset

FR2

FG2

FB2

0

FR1

FG1

FB1

0

FR0

FG0

FB0

0

-

X

Table 24. Fine gain registers (02h, 05h, 08h) bit description

Bit

Symbol

Description

FINER (address: 02h)

7 to 3

2 to 0

-

not used

FR[2:0]

ﬁne gain of the AGC for R channel

FINEG (address: 05h)

7 to 3

2 to 0

-

not used

FG[2:0]

ﬁne gain of the AGC for G channel

FINEB (address: 08h)

7 to 3

2 to 0

-

not used

FB[2:0]

ﬁne gain of the AGC for B channel

Table 25. Fine gain control bits (example for coarse register value 32)

Value

FR2

FR1

FR0

Fine steps of

gain ADC

FG2

FG1

FG0

FB2

0

FB1

0

FB0

0

1

2

3

4

5

6

7

1.000

1.001

1.002

1.003

1.004

1.005

1.006

1.007

0

1

0

1

0

1

0

1

0

1

0

1

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9.6 Sync-on-green register

Table 26. SOG - sync-on-green register (address 09h) bit allocation

Bit

7

DO

0

6

UP

0

5

4

3

2

1

SOGI1

0

SOGI0

1

Symbol

Reset

Access

FTRILEVEL STRILEVEL

CKREFS

SOGSEL

0

W

Table 27. SOG - sync-on-green register (address 09h) bit description

Bit

Symbol

Description

7

DO

test bit for forcing charge pump current down

0 = reset value

1 = forcing down

6

UP

test bit for forcing charge pump current up

0 = reset value

1 = forcing up

5

FTRILEVEL

STRILEVEL

CKREFS

SOGSEL

SOGI[1:0]

deﬁnes the 3-level function mode

0 = automatic 3-level

1 = level selection with bit STRILEVEL

forces the state of 3-level function

0 = not 3-level mode

4

1 = 3-level mode

3

enables the PLL Ckref signal to be selected

0 = same as input

1 = input inverted

2

enables the reference PLL between HSYNC input and SOG input to be selected

0 = HSYNC input

1 = SOG input

1 to 0

deﬁnes the SOG charge pump current; values are given in % of sync pulse/line length

00 = 14.8 % maximum (TV standards) and non-VESA standards

01 = 12.6 % maximum (all standards)

10 = 8.6 % maximum (HDTV standards) and non-VESA standards

11 = 0 test mode

9.7 PLL control register

Table 28. PLLCTRL- PLL control register (address 0Ah) bit allocation

Bit

7

IP1

0

6

IP0

1

5

Z2

0

4

Z1

1

3

Z0

1

2

DR2

1

DR1

0

DR0

0

Symbol

Reset

Access

W

TDA8754_7

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Table 29. PLLCTRL - PLL control register (address 0Ah) bit description

Bit

Symbol

Description

7 to 6

IP[1:0]

charge pump current value to increase the bandwidth of the PLL

00 = 800 µA

01 = 1200 µA

10 = 1600 µA

11 = 2000 µA

5 to 3

Z[2:0]

internal resistance value for the Voltage Controlled Oscillator (VCO) ﬁlter to be selected

000 = not used

001 = 1.56 kΩ

010 = 1.25 kΩ

011 = 1.00 kΩ

100 = 0.80 kΩ

101 = 0.64 kΩ

110 = 0.51 kΩ

111 = 0.41 kΩ

3 to 0

DR[2:0]

PLL temperature phase drift to be compensated. The optimized value of this register is 001. These

bits add a delay on the clock reference input of the PLL as a function of the temperature of the die.

000 = +1.75 step phase

001 = −0.3 step phase

010 = −4.3 step phase

011 = −6.2 step phase

100 = −2.2 step phase

9.8 Phase register

Table 30. PHASE - phase register (address 0Bh) bit allocation

Bit

7

PA4

0

6

PA3

0

5

PA2

0

4

PA1

0

3

PA0

0

2

VCO2

1

VCO1

0

VCO0

1

Symbol

Reset

Access

W

Table 31. PHASE - phase register (address 0Bh) bit description

Bit

Symbol

Description

7 to 4

3 to 0

PA[4:0]

phase shift value for the clock pixel; see Table 32

VCO[2:0] VCO gain control; see Table 33

TDA8754_7

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Table 32. Phase registers bits

PA4

PA3

PA2

PA1

PA0

Phase shift (deg)

0

:

0

:

0

:

0

:

0

1

:

0

11.25

:

1

0

1

337.50

348.75

Table 33. VCO gain control

VCO2

VCO1

VCO0

VCO gain

(MHz/V)

Pixel clock frequency

(MHz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

13

12 to 22

22 to 45

45 to 62

62 to 85

85 to 120

120 to 176

176 to 270

-

30

60

105

135

no oscillation

9.9 PLL divider registers

Table 34. DIVMSB - PLL divider ratio (MSB) register (address 0Ch) bit allocation

Bit

7

CKEXT

0

6

5

EPSI1

0

4

EPSI0

0

3

DI11

0

2

DI10

1

DI9

1

0

DI8

0

Symbol

Reset

Access

SCHCKREFO

0

W

Table 35. DIVMSB - PLL divider ratio (MSB) register (address 0Ch) bit description

Bit

Symbol

Description

7

CKEXT

external clock selection

0 = internal PLL

1 = external clock

6

SCH

shift of pixel counter reference (Ckref) with one clock pixel period

CKREFO

0 = not active

1 = active

5 to 4

3 to 0

EPSI[1:0] enables the resynchronization edge of CKREFO to be selected; they are test bits

00 = reset value for proper operation

DI[11:8]

PLL divider ratio; these are the 4 MSBs of the 12-bit value; see Table 38

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Table 36. DIVLSB - PLL divider ratio (LSB) register (address 0Dh) bit allocation

Bit

7

DI7

1

6

DI6

0

5

DI5

0

4

DI4

1

3

DI3

1

2

DI2

0

1

DI1

0

DI0

0

Symbol

Reset

Access

W

Table 37. DIVLSB - PLL divider ratio (LSB) register (address 0Dh) bit description

Bit

Symbol Description

DI[7:0] PLL divider ratio; these are the 8 LSBs of the 12-bit value; see Table 38

7 to 0

Table 38. PLL divider ratio

DI11

VDI10

VDI9

VDI8

VDI7

VDI6

VDI5

VDI4

DI3 DI2 DI1 DI0 PLL divider ratio

0

:

0

:

0

:

0

:

0

:

1

:

1

:

0

:

0

:

1

:

0

:

0

:

100

1

4095

9.10 Horizontal sync registers

Remark: The sum of HSYNCL[9:0] + HBACKL[9:0] + HDISPL[9:0] + 16 needs to be

smaller than the PLL divider.

Table 39. HSYNCL, HBACKL and HDISPL (address 0Eh, 0Fh, 10h, 11h) bit allocation

7

6

5

4

3

2

1

0

Register address 0Eh

HSYNCL9

0

HSYNCL8

0

HSYNCL7

1

HSYNCL6

0

HSYNCL5

0

HSYNCL4

1

HSYNCL3

0

HSYNCL2

0

Register address 0Fh

HSYNCL1

0

HSYNCL0

0

HBACKL9

0

HBACKL8

0

HBACKL7

1

HBACKL6

1

HBACKL5

1

HBACKL4

1

Register address 10h

HBACKL3

1

HBACKL2

0

HBACKL1

0

HBACKL0

0

HDISPL11

0

HDISPL10

1

HDISPL9

0

HDISPL8

1

Register address 11h

HDISPL7

0

HDISPL6

0

HDISPL5

0

HDISPL4

0

HDISPL3

0

HDISPL2

0

HDISPL1

0

HDISPL0

0

Table 40. Sync registers (0Eh to 11h) bit description

Bit Symbol Description

9 to 0 HSYNCL[9:0] length of the Hsync signal; in number of pixel clock cycles; minimum value is 16

9 to 0 HBACKL[9:0] interval between the Hsync active edge and the ﬁrst active pixel; in number of pixels; minimum

value is 16

11 to 0 HDISPL[11:0] number of active pixels for one line; length of the data enable signal; minimum value is 16

TDA8754_7

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9.11 Coast register

Remark: When POSTCOAST[4:0] = PRECOAST[2:0] = 0, then the coast pulse equals

the VSYNC input.

Table 41. COAST - coast register (address 12h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

PRE

POST

COAST2

COAST1

COAST0

COAST4

COAST3

COAST2

COAST1

COAST0

Reset

0

Access

W

Table 42. COAST - coast register (address 12h) bit description

Bit Symbol Description

7 to 5 PRECOAST[2:0] programs the length (in numbers of pixel clocks) of the coast pulse before the edge of the

vertical sync signal

4 to 0 POSTCOAST[4:0] programs the length (in numbers of pixel clocks) of the coast pulse after the edge of the vertical

sync signal

9.12 Horizontal sync selection register

Table 43. HSYNCSEL - horizontal sync selection register (address 13h) bit allocation

Bit

7

-

6

-

5

-

4

-

3

2

1

HSSEL

0

HSS

0

Symbol

Reset

Access

TESTCNT

BYSEPA

X

W

X

W

X

W

X

W

0

1

W

Table 44. HSYNCSEL - horizontal sync selection register (address 13h) bit description

Bit

7 to 4

3

Symbol

-

Description

not used

TESTCNT

this bit is used to test the pixel counter

0 = normal mode

1 = test mode

2

1

0

BYSEPA

HSSEL

HSS

enables the sync separator for the PLL reference to be bypassed

0 = Hsync from the separator

1 = bypass of the sync separator

enables either the HSYNC or CHSYNC input signal to be selected

0 = HSYNC input

1 = CHSYNC input

enables either the HSYNC or CHSYNC input signal to be inverted

0 = non-inverted

1 = inverted

TDA8754_7

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9.13 Vertical sync selection register

Table 45. VSYNCSEL - vertical sync selection register (address 14h) bit allocation

Bit

7

-

6

-

5

-

4

3

COE

0

2

VSS

0

1

0

Symbol

Reset

Access

TSTCOAST

COSSEL2 COSSEL1

X

W

X

W

X

W

0

W

Table 46. VSYNCSEL - vertical sync selection register (address 14h) bit description

Bit

7 to 5

4

Symbol

Description

-

not used

TSTCOAST

switches a multiplexer to select the output signal on pin VSYNCO

0 = output of the separator function

1 = output of the coast function

enables coast mode

3

2

1

0

COE

0 = coast mode

1 = no coast mode

VSS

enables VSYNC input signal to be inverted

0 = non-inverted

1 = inverted

COSSEL2

COSSEL1

selects signal for coast PLL mode

0 = signal selected with bit COSSEL1

1 = pin coast

can be used for the coast PLL mode; see bit COSSEL2

0 = VSYNC input

1 = VSYNC from the sync separator

9.14 Clamp register

Table 47. CLAMP - clamp register (address 15h) bit allocation

Bit

7

-

6

5

4

3

CLPH

0

2

1

ICLP

0

CLPT

0

Symbol

Reset

Access

HSOSEL

CLPSEL2

CLPSEL1

CLPENL

X

W

0

1

0

W

Table 48. CLAMP - clamp register (address 15h) bit description

Bit

7

Symbol

-

Description

not used

6

HSOSEL

deﬁnes the signal on the output HSYNCO; see Section 8.3

0 = Hsync from the Hcounter

1 = Ckref is reference of the PLL

5

CLPSEL2

can be used to select the clamp signal

0 = Hsync signal generated by the pixel counter

1 = signal selected with bit CLPSEL1

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Table 48. CLAMP - clamp register (address 15h) bit description …continued

Bit

Symbol

Description

4

CLPSEL1

can be used to select the clamp signal; see bit CLPSEL2

0 = PLL reference signal

1 = clamp input

3

2

CLPH

inhibits the clamp signal during the Vsynco or coast signal; see bit TSTCOAST (Table 46)

0 = clamp inhibited during Vsynco

1 = clamp active during Vsynco

CLPENL

deﬁnes if clamp input works on edge or on level

0 = on edge; for all frequencies (must be preferably chosen)

1 = on level; only for frequencies below 45 MHz to have proper clamp function

dedicated for test mode; should be forced to logic 0

deﬁnes if the test mode of the clamp is active

0 = not active

1

0

ICLP

CLPT

1 = active

9.15 Inverter register

Table 49. INVERTER - inverter register (address 16h) bit allocation

Bit

7

-

6

COS

0

5

CLPS

0

4

3

2

1

0

Symbol

Reset

Access

CKREFOINV DEOINVRGB HSOINVRGB VSOINVRGB FIELDOINV

X

W

0

W

Table 50. INVERTER - inverter register (address 16h) bit description

Bit

7

Symbol

Description

-

not used

6

COS

enables the COAST input signal to be inverted

0 = non-inverted

1 = inverted

5

4

3

2

CLPS

enables the CLAMP input signal to be inverted

0 = non-inverted

1 = inverted

CKREFOINV

DEOINVRGB

HSOINVRGB

enables the output CKREFO to be inverted

0 = non-inverted

1 = inverted

enables the output DEO to be inverted

0 = non-inverted

1 = inverted

enables the output HSYNCO to be inverted

0 = non-inverted

1 = inverted

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Table 50. INVERTER - inverter register (address 16h) bit description …continued

Bit

Symbol

Description

1

VSOINVRGB

enables the output VSYNCO to be inverted

0 = non-inverted

1 = inverted

0

FIELDOINV

enables the output FIELDO to be inverted

0 = non-inverted

1 = inverted

9.16 Output register

Table 51. OUTPUT - output register (address 17h) bit allocation

Bit

7

6

TEN

0

5

4

3

BLKEN

0

2

1

0

Symbol

Reset

Access

RGBSEL

AGCSEL1

AGCSEL0

DMXRGB ODDARGB SHIFTRGB

0

W

Table 52. OUTPUT- output register (address 17h) bit description

Bit

Symbol

Description

7

RGBSEL

deﬁnes which RGB input will be used

0 = input 1

1 = input 2

6

TEN

enables the track and hold operating mode to be selected

0 = mode enable; must be set to logic 0 for proper operation

1 = mode disable

deﬁne the output on pin AGCO

00 = RAGC

5 to 4

AGCSEL[1:0]

01 = GAGC

10 = BAGC

11 = not used

3

2

BLKEN

inhibits the blanking mode during clamp

0 = blanking active; during the blanking period, the RGB outputs of the ADC are ﬁxed at

the values of registers OFFSETR, OFFSETG and OFFSETB if these values are greater

or equal to 0, or forced to 0 if these values are negative.

1 = blanking not active

DMXRGB

determines whether all pixels go to port A or if pixels go alternately to port A and B. The

maximum data rate for single port mode is 140 MHz and it is 270 MHz in dual port mode.

0 = port A

1 = port A and B

1

ODDARGB

SHIFTRGB

deﬁnes the parity of the pixels

0 = even pixel on port A

1 = odd pixel on port A

deﬁnes output on port A and B

0 = synchronous

0

1 = interleaved

TDA8754_7

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9.17 Output enable register 1

Table 53. OUTPUTEN1 - output enable 1 register (address 18h) bit allocation

Bit

7

-

6

-

5

-

4

3

2

1

0

Symbol

Reset

Access

BOENRGB AOENRGB

OROEN

TOUTERGB TOUTSRGB

X

W

X

W

X

W

1

0

W

Table 54. OUTPUTEN1 - output enable 1 register (address 18h) bit description

Bit

7 to 5

4

Symbol

Description

-

not used

BOENRGB

enables output port B to be set to high-impedance

0 = active signal

1 = high-impedance

3

2

1

0

AOENRGB

OROEN

enables output port A to be set to high-impedance

0 = active signal

1 = high-impedance

enables outputs Out Of Range to be set to high-impedance

0 = active signal

1 = high-impedance

TOUTERGB

TOUTSRGB

deﬁnes if the test mode of the output buffer is active or not

0 = mode normal

1 = mode test

deﬁnes the state of the output in test mode

0 = forces output to LOW

1 = forces output to HIGH

9.18 Output enable register 2

Table 55. OUTPUTEN2 - output enable 2 register (address 19h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

CKROEN

CSOEN DEOENRGB HSOENRGB HPDOEN VSOENRGB CLPOEN FIELDOEN

1

W

Table 56. OUTPUTEN2 - output enable 2 register (address 19h) bit description

Bit

Symbol

Description

7

CKROEN

enables the output CKREFO to be set to high-impedance

0 = active signal

1 = high-impedance

6

CSOEN

enables the output CSYNCO to be set to high-impedance

0 = active signal

1 = high-impedance

TDA8754_7

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Table 56. OUTPUTEN2 - output enable 2 register (address 19h) bit description …continued

Bit

Symbol

Description

5

DEOENRGB

enables the output DEO to be set to high-impedance

0 = active signal

1 = high-impedance

4

3

2

1

0

HSOENRGB

HPDOEN

enables the output HSYNCO to be set to high-impedance

0 = active signal

1 = high-impedance

enables the output HPDO to be set to high-impedance

0 = active signal

1 = high-impedance

VSOENRGB

CLPOEN

enables the output VSYNCO to be set to high-impedance

0 = active signal

1 = high-impedance

enables the output CLPO to be set to high-impedance

0 = active signal

1 = high-impedance

FIELDOEN

enables the output FIELDO to be set to high-impedance

0 = active signal

1 = high-impedance

9.19 Clock output register

Table 57. CLKOUTPUT - clock output register (address 1Ah) bit allocation

Bit

7

-

6

-

5

-

4

3

2

1

0

Symbol

Reset

Access

CKSELRGB DLYCLKRGB CKDATINV OUTOSCILL CKOENRGB

X

E

X

W

X

W

0

1

W

Table 58. CLKOUTPUT - clock output register (address 1Ah) bit description

Bit

7 to 5

4

Symbol

Description

-

not used

CKSELRGB

enables the selection of the signal on the pin CKDATA

0 = clock of output buffers; signal Ckdata

1 = pixel clock of the converter; signal Ckadco

enables a delay of 2 ns to be added to the clock Ckdata

0 = no delay

3

2

DLYCLKRGB

CKDATINV

1 = 2 ns delay

enables the polarity of the output CKDATA to be inverted

0 = non-inverted

1 = inverted

TDA8754_7

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Table 58. CLKOUTPUT - clock output register (address 1Ah) bit description …continued

Bit

Symbol

Description

1

OUTOSCILL

enables pin CKDATA to be switched with a multiplexer to have signal Ckdata or the internal

oscillator on the output

0 = Ckdata

1 = for test

0

CKOENRGB

enables the output CKDATA to be set to high-impedance

0 = active signal

1 = high-impedance

9.20 Internal oscillator register

Table 59. INTOSC - internal oscillator register (address 1Bh) bit allocation

Bit

7

-

6

-

5

-

4

-

3

-

2

-

1

0

Symbol

Reset

Access

SWITCHOSC INTOSCOFF

X

W

X

W

X

W

X

W

X

W

X

W

0

W

Table 60. INTOSC - internal oscillator register (address 1Bh) bit description

Bit

7 to 2

1

Symbol

Description

-

not used

SWITCHOSC

enables a multiplexer to be switched; signal insertion on the input of the separator and

coast block, between the internal oscillator and pin CKEXT

0 = normal case; if this bit is switched from logic 1 to logic 0, then an internal reset of the

coast, activity detection and sync separator is done

1 = test mode

0

INTOSCOFF

disables the internal oscillator for the separator function, the coast gate and activity

detection

0 = active; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast,

activity detection and sync separator is done

1 = disabled

9.21 Power management register

Table 61. PWRMGT - power management register (address 1Eh) bit allocation

Bit

7

-

6

-

5

-

4

-

3

2

1

STBY

0

Symbol

Reset

Access

SHCKDMX SHCKADC

DVIRGB

X

W

X

W

X

W

X

W

0

W

Table 62. PWRMGT - power management register (address 1Eh) bit description

Bit

7 to 4

3

Symbol

-

Description

not used

SHCKDMX

SHCKADC

test bits; should be set to logic 0 for proper operation

2

test bits; should be set to logic 1 for better performances

TDA8754_7

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Table 62. PWRMGT - power management register (address 1Eh) bit description …continued

Bit

Symbol

Description

1

STBY

enables the RGB block to be forced into the Standby mode, except activity detection,

I²C-bus registers. In the Standby mode, all outputs are in high-impedance state, except

pin HPDO which is still active. If the IC is in the Power-down mode, this bit has no effect

0 = IC active

1 = Standby mode

0

DVIRGB

this bit must be set to logic 0 for proper operation

9.22 Read register

Table 63. READADDR - read register (address 1Fh) bit allocation

Bit

7

-

6

-

5

-

4

-

3

-

2

-

1

ADDR1

0

ADDR0

0

Symbol

Reset

Access

X

W

X

W

X

W

X

W

X

W

X

W

Table 64. READADDR - read register (address 1Fh) bit description

Bit

Symbol

-

Description

7 to 2

1 to 0

not used

ADDR[1:0]

register address to be read

00 = read register 0

01 = read register 1

10 = read register 2

11 = read register 3

9.23 Version register

Table 65. VERSION - version register (read register 0) bit allocation

Bit

7

-

6

-

5

-

4

-

3

VER3

0

2

VER2

0

1

VER1

0

VER0

0

Symbol

Reset

Access

X

R

X

R

X

R

X

R

Table 66. VERSION - version register (read register 0) bit description

Bit

Symbol

-

Description

not used

7 to 4

3 to 0

VER[3:0]

version of the IC

9.24 Sign detection register

The sign bits are set at logic 0 when the input is a mostly LOW input signal.

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TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 67. SIGN - sign register (read register 1) bit allocation

Bit

7

-

6

-

5

4

3

2

1

0

Symbol

Reset

Access

POLVS2

POLVS1

POLCHS2 POLCHS1

POLHS2

POLHS1

X

R

X

R

0

R

Table 68. SIGN - sign register (read register 1) bit description

Bit

7 to 6

5

Symbol

-

Description

not used

POLVS2

sign of VSYNC2 input

0 = non inverted

1 = inverted

4

3

2

1

0

POLVS1

sign of VSYNC1 input

0 = non inverted

1 = inverted

POLCHS2

POLCHS1

POLHS2

POLHS1

sign of CHSYNC2 input

0 = non inverted

1 = inverted

sign of CHSYNC1 input

0 = non inverted

1 = inverted

sign of HSYNC2 input

0 = non inverted

1 = inverted

sign of HSYNC1 input

0 = non inverted

1 = inverted

9.25 Activity detection 1 register

Table 69. ACTIVITY1 - activity detection 1 register (read register 2) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ACVS2

ACVS1

ACSOG2

ACSOG1

ACCHS2

ACCHS1

ACHS2

ACHS1

0

R

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

39 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 70. ACTIVITY1 - activity detection 1 register (read register 2) bit description

Bit

Symbol

Description

7

ACVS2

activity of VSYNC2 input

0 = not active

1 = active

6

5

4

3

2

1

0

ACVS1

activity of VSYNC1 input

0 = not active

1 = active

ACSOG2

ACSOG1

ACCHS2

ACCHS1

ACHS2

activity of SOGIN2 input

0 = not active

1 = active

activity of SOGIN1 input

0 = not active

1 = active

activity of CHSYNC2 input

0 = not active

1 = active

activity of CHSYNC1 input

0 = not active

1 = active

activity of HSYNC2 input

0 = not active

1 = active

ACHS1

activity of HSYNC2 input

0 = not active

1 = active

9.26 Activity detection register 2

Remark: It should be noted that activity, sign and polarity detection will be correctly set

after a maximum delay of: 6 frame periods + 50 ms.

Table 71. ACTIVITY2 - activity detection 2 register (read register 3) bit allocation

Bit

7

-

6

ASD

0

5

4

3

HPDO

0

2

1

0

Symbol

Reset

Access

3LEVEL

ACFIELD

ACVSSEP

ACRXC1

ACRXC0

X

R

0

R

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

40 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 72. ACTIVITY2 - activity detection 2 register (read register 3) bit description

Bit

7

Symbol

Description

-

not used

6

ASD

indicates if parasite sync pulses have been detected

0 = not detected

1 = detected

5

4

3

2

3LEVEL

ACFIELD

HPDO

state of the sync separator input

0 = Hsync

1 = 3-level Hsync

activity of the sync separator FIELDO output

0 = not active

1 = active

copy of the HPDO output state

0 = stable state on input

1 = new input

ACVSSEP

activity of the sync separator (Vsync output)

0 = not active

1 = active

1

0

ACRXC1

ACRXC0

test bit

10. Limiting values

Table 73. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

−0.5

-

Max

+5

Unit

V

supply voltage

∆V_CC

V_i

supply voltage differences

+0.5

+4.5

+6.5

50

V

input voltage

referred to GNDA

referred to GNDD

V

V_i(SCL)

V_i(SDA)

I_o

I²C-bus clock input voltage

I²C-bus data input voltage

output current

V

mA

°C

V

T_stg

storage temperature

ambient temperature

junction temperature

electrostatic discharge voltage

−55

−10

-

+150

+70

T_amb

T_j

150

V_esd

human body model,

LQFP144 package

−3000

+3000

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

41 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

11. Thermal characteristics

Table 74. Thermal Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R_th(j-a)

thermal resistance from junction in free air; JEDEC4L

to ambient

LQFP144 package

-

35

30

8.1

-

K/W

LBGA208 package

-

R_th(j-c)

thermal resistance from junction LQFP144 package

to case

8.5

12. Characteristics

Table 75. Characteristics

T_amb= 25 °C unless otherwise speciﬁed.

Symbol

Supplies

V_CCA

Parameter

Conditions

Min

Typ^[1]

Max

Unit

analog supply voltage

digital supply voltage

output stage supply voltage

analog supply current

digital supply current

output stage supply current

supply voltage difference

V_CCAto V_CCD

3.0

-

3.3

180

125

1

3.6

-

V

V_CCD

V

V_CCO

I_CCA

V

mA

I_CCD

-

I_CCO

-

∆V_CC

−100

-

+100

+165

1.3

-

mV

W

V_CCOto V_CCD

−165

-

V_CCAto V_CCO

−165

-

P_tot

P

total power dissipation

power dissipation

-

1.0

10

120

Power-down mode

Standby mode

mW

-

R, G and B ampliﬁers

RGB inputs: pins RIN1, GIN1, BIN1, RIN2, GIN2 and BIN2

V_i(p-p)

input voltage range

(peak-to-peak value)

0.5

-

1.0

V

I_i

input current

−40

-

+40

µA

pF

kΩ

C_i

input capacitance

input resistance

3

-

R_i

50

Ampliﬁers

B

bandwidth

−3 dB; T_amb= 25 °C

-

700

0

-

MHz

dB

G_c

coarse gain

minimum coarse gain;

code = 32

maximum coarse gain;

code = 95

-

6

2

-

dB

%

∆G/∆T

ampliﬁer gain stability variation minimum coarse gain;

with temperature code = 32

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

42 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 75. Characteristics …continued

T_amb= 25 °C unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

G_E(rms)

full-scale channel-to-channel

matching (RMS value)

minimum coarse gain;

code = 32

-

2.5

%

R, G and B clamp

N_clamp

clamp level accuracy

f_CLK= 25 MHz; clamp

code = 20

-

1

bit

ps

Phase-Locked Loop (PLL); see Table 76

J_PLL(p-p)

long term PLL phase jitter

(peak-to-peak value)

f_clk= 270 MHz; DR = 2160

390

480

DR

divider ratio

100

10

15

-

4095

270

150

2

f_PLL

f_ref

output clock frequency

reference clock frequency

MHz

kHz

∆ϕ_step

number of phase shift steps

from drift

ϕ_step

phase shift step

-

11.25

-

deg

Analog-to-Digital Converters (ADCs); minimum coarse gain

f_s(max)

INL

maximum sampling frequency

integral non-linearity

differential non-linearity

effective number of bits

crosstalk

270

-

MHz

bit

f_clk= 270 MHz; f_i= 10 MHz

f_clk= 270 MHz

-

±0.6

±0.25

7.6

-

±1.3

±0.6

-

DNL

ENOB

α_ct

-

bit

-

bit

-

−45

-

dB

S/N

signal-to-noise ratio

f_clk= 270 MHz; f_i= 10 MHz

-

48

SFDR

THD

spurious free dynamic range

total harmonic distortion

48

-

55

-

−55

−48

Data timing; 10 pF load; see Figure 4

t_d(o)

t_h(o)

t_su(o)

output delay

-

4

-

5.2

-

ns

output hold time

output setup time

1.9

-

6

LV-TTL digital inputs and outputs

Input pins CKEXT, COAST, VSYNC1, VSYNC2, HSYNC1, HSYNC2, CHSYNC1, CHSYNC2, PWD, A0, DIS, TCK and CLP

V_IL

V_IH

LOW-level input voltage

HIGH-level input voltage

0

-

0.8

V

2.0

V_CCD(TTL)

Output pins RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, CKDATA, TDO, DEO, HPDO, HSYNCO,

VSYNCO, FIELDO, CLPO, CKREFO and CSYNCO

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

I_OH= 1 mA

-

0.4

-

V

I_OL= −1 mA

2.4

Data clock output

Output pin CKDATA

f_CKDATA(max)maximum buffer frequency

Data outputs

-

140

-

MHz

Output pins RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, DEO, HSYNCO and CSYNCO

f_data(max)

maximum buffer frequency

-

70

-

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

43 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

Table 75. Characteristics …continued

T_amb= 25 °C unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Hsync inputs

Input pins HSYNC1, HSYNC2, CHSYNC1 and CHSYNC2

t_{W(Hsync)(min)}minimum pulse width

250

-

ns

%

t_{W(Hsync)(max)}maximum pulse width

SOG inputs

in % of total horizontal line

20

Input pins SOGIN1 and SOGIN2

V_sync(G)

sync-on-green pulse amplitude

150

-

mV

%

high/low differential amplitude

of 3-level pulse

20

I²C-bus (fast mode; 5 V tolerant)

Pins SCL and SDA

f_SCL

V_IL

V_IH

C_b

clock frequency

-

400

0.8

kHz

V

LOW-level input voltage

HIGH-level input voltage

capacitive load

0

2.0

-

5.5

V

400

pF

[1] Typical values are measured at V_CCA= V_CCA(SOG)to GNDA(SOG) or V_CCA(R)to GNDA(R) or V_CCA(G)to GNDA(G)

or V_CCA(B)to GNDA(B) = 3.3 V; V_CCD= V_CCD(TTL)to GNDD(TTL) or V_CCD(ADC)to GNDD(ADC) or V_CCD(I2C)to GNDD(I2C)

or V_CCD(MCF)to GNDD(MCF) or V_CCD(TTL)to GNDD(TTL) or V_CCD(SLC)to GNDD(SLC) = 3.3 V; V_CCO= V_CCO(BB)to GNDO(BB)

or V_CCO(BA)to GNDO(BA) or V_CCO(GB)to GNDO(GB) or V_CCO(GA)to GNDO(GA) or V_CCO(RB)to GNDO(RB) or V_CCO(RA)to GNDO(RA)

or V_CCO(CLK)to GNDO(CLK) = 3.3 V.

Table 76. Examples of PLL settings and performance

V_CCA= V_CCD= V_CCO= 3.3 V; T_amb= 25 °C^[1].

Video standard

f_ref

(kHz)

f_clk

(MHz)

DR

Ko

(MHz/V)

C_z(nF) C_P(pF) I_P(µA) Z (Ω)

Long-term time

jitter

RMS

(ps)

p-p (ps)

3000

1980

1320

1110

870

VGA 60 Hz; VESA:

640 × 480

31.469 25.175 800

30

220

680

1200

1600

2000

1600

2000

510

640

510

640

800

640

500

370

220

185

145

135

95

SVGA 72 Hz; VESA: 48.08

800 × 600

50

1040

1312

1688

2160

60

XGA 75 Hz; VESA:

1024 × 768

60.02

78.75

108

60

SXGA 60 Hz; VESA: 63.98

1280 × 1024

105

135

SXGA 75 Hz; VESA: 80.00

1280 × 1024

135

UXGA 60 Hz; VESA: 75.00

1600 × 1200

162

810

UXGA 75 Hz; VESA: 93.75

1600 × 1200

202.5

570

UXGA 85 Hz; VESA: 106.25 229.5

85

510

1600 × 1200

[1] PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

44 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

13. Timing

V

OH

OL

50 %

CKDATA

sample N

sample N + 1

sample N + 2

RGB input

t

h(o)

t

d(o)

RGB outputs

V

OH

OL

A7 to A0, B7 to B0,

DEO,

DATA

N − 2

DATA

N − 1

DATA

N

DATA

N + 1

50 %

HSYNCO,

CKREFO

t

su(o)

mce410

Fig 4. Data timing diagram

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

45 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

ckrefin

HSYNCO

CKREFO

DEO

CKDATA

RGB outputs

A7 to A0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

mdb201

HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckreﬁn.

CKREFO is LOW during 8 clock pulses.

Fig 6. Output format port A

ckrefin

HSYNCO

CKREFO

DEO

CKDATA

bit SHIFTRGB = 0

RGB outputs

A7 to A0

28

27

28

2

1

2

4

3

4

6

8

10

9

12

11

12

14

13

14

16

15

16

18

17

18

RGB outputs

B7 to B0

5

7

bit SHIFTRGB = 1

RGB outputs

A7 to A0

6

8

10

RGB outputs

B7 to B0

27

1

3

5

7

9

11

13

15

17

19

mdb108

HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckreﬁn.

CKREFO is LOW during 8 clock pulses.

Fig 7. Output formats ports A and B; even pixels port A and odd pixels port B

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

47 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

ckrefin

HSYNCO

CKREFO

DEO

CKDATA

bit SHIFTRGB = 0

RGB outputs

A7 to A0

27

28

1

2

3

4

5

7

9

11

12

13

14

15

16

17

RGB outputs

B7 to B0

6

8

10

18

mdb200

HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckreﬁn.

CKREFO is LOW during 8 clock pulses.

Fig 8. Output formats ports A and B; odd pixels port A; bit SHIFTRGB = 0

ckrefin

HSYNCO

CKREFO

DEO

CKDATA

bit SHIFTRGB = 1

RGB outputs

27

1

3

5

7

9

11

13

15

17

A7 to A0

RGB outputs

B7 to B0

28

2

4

6

8

10

12

14

16

18

mce411

HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckreﬁn.

CKREFO is LOW during 8 clock pulses.

Fig 9. Output formats ports A and B; odd pixels port A; bit SHIFTRGB = 1

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

48 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

14. Application information

V

CCD

V

CCD

SCL SDA

R21

4.7 kΩ

R20

4.7 kΩ

V

CCD

V

CCO

V

CCD

V

CCD

V

CCO CCO

GNDD(TTL)

RA6

RA5

RA4

RA3

RA2

RA1

RA0

ROR

1

108

107

106

105

104

103

102

101

100

99

V

CCD(TTL)

out red A

V

CCD

2

HSYNC2

3

CHSYNC2

4

V

CCA(PLL)

V

CCA

5

HSYNC1

CHSYNC1

GNDA(PLL)

CZ

6

7

8

C1

GNDO(RB)

9

V

GNDA(CPO)

CP

CCO(RB)

220 nF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

V

CCO

C2

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

98

PMO

680 pF

97

GNDA(SUB)

CAPSOGIN1

CAPSOGO

CAPSOGIN2

GNDA(SOG)

SOGIN1

96

C3

95

out red B

1 µF

94

C4

93

1 µF

92

C5

SOGIN1

SOGIN2

91

TDA8754HL

V

CCA(SOG)

GNDO(GA)

330 pF

C6

90

V

CCO(GA)

SOGIN2

89

V

CCO

V

CCA(R)

330 pF

C7

GA7

GA6

GA5

GA4

GA3

GA2

GA1

GA0

GOR

V

CCA

88

RIN1

87

RIN1

1 µF

GNDA(R1)

86

C8

RIN2

85

out green A

1 µF

GNDA(R2)

84

C9 100 nF

DEC

RBOT

83

C10 100 nF

C11 4.7 nF

82

RCLPC

81

V

CCA(G)

80

V

CCA

C12

GNDO(GB)

GIN1

79

GIN1

V

CCO(GB)

1 µF

GNDA(G1)

GIN2

78

V

CCO

C13

GB7

GB6

GB5

GB4

GB3

77

GIN2

1 µF

GNDA(G2)

76

C14 100 nF

C15 4.7 nF

GBOT

75

GCLPC

74

V

out green B

CCA(B)

73

V

CCA

001aac978

out blue B

out blue A

C19

4.7

nF

C17

1 µF

C16

1 µF

V

CCD

V

CCO

V

CCO

C18

100

nF

BIN1 BIN2

Fig 10. Application diagram

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

49 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

15. Package outline

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm

SOT486-1

y

X

A

108

109

73

72

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

L

pin 1 index

detail X

37

144

1

36

v

M

A

Z

w M

D

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 20.1

0.17 0.09 19.9 19.9

22.15 22.15

21.85 21.85

0.75

0.45

1.4

1.1

1.4

1.1

mm

1.6

0.25

1

0.2 0.08 0.08

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-03-14

03-02-20

SOT486-1

136E23

MS-026

Fig 11. Package outline SOT486-1 (LQFP144)

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

50 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

LBGA208: plastic low profile ball grid array package; 208 balls; body 17 x 17 x 1.05 mm

SOT774-1

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

C

e

1

y

1/2 e

v M

b

C

A

B

C

1

e

w M

T

R

N

L

P

M

K

H

F

e

J

e

2

G

E

C

A

1/2 e

D

B

ball A1

index area

1

3

5

7

9

11

13

15

2

4

6

8

10

12

14

16

X

5

10 mm

0

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

2

y

D

E

v

w

y

1

2

1

max.

0.45 1.20 0.55 17.2 17.2

0.35 0.95 0.45 16.8 16.8

mm 1.65

0.12 0.35

1

15

0.25

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

02-05-14

SOT774-1

- - -

MO-192

Fig 12. Package outline SOT774-1 (LBGA208)

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

51 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

16. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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Product data sheet

Rev. 07 — 3 May 2007

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TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

16.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 13) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 77 and 78

Table 77. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 78. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 13.

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

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TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 13. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

54 of 57

TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

17. Revision history

Table 79. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

TDA8754_7

20070503

Product data sheet

-

TDA8754_6

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 8.2.4: added remark on clamp noise

TDA8754_6 (9397 750 14984)

TDA8754_5 (9397 750 13199)

TDA8754_4 (9397 750 12016)

TDA8754_3 (9397 750 11551)

TDA8754_2 (9397 750 10598)

TDA8754_1 (9397 750 04134)

20050616

20040518

20030930

20030716

20030417

19980930

Product data sheet

-

TDA8754_5

TDA8754_4

TDA8754_3

TDA8754_2

TDA8754_1

-

Product speciﬁcation

Preliminary speciﬁcation

Objective speciﬁcation

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

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NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

18.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

18.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

19. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

TDA8754_7

Product data sheet

Rev. 07 — 3 May 2007

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TDA8754

NXP Semiconductors

Triple 8-bit video ADC up to 270 Msample/s

20. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

9.16

9.17

9.18

9.19

9.20

9.21

9.22

9.23

9.24

9.25

9.26

Output register . . . . . . . . . . . . . . . . . . . . . . . . 34

Output enable register 1. . . . . . . . . . . . . . . . . 35

Output enable register 2. . . . . . . . . . . . . . . . . 35

Clock output register . . . . . . . . . . . . . . . . . . . 36

Internal oscillator register. . . . . . . . . . . . . . . . 37

Power management register . . . . . . . . . . . . . 37

Read register . . . . . . . . . . . . . . . . . . . . . . . . . 38

Version register . . . . . . . . . . . . . . . . . . . . . . . 38

Sign detection register . . . . . . . . . . . . . . . . . . 38

Activity detection 1 register . . . . . . . . . . . . . . 39

Activity detection register 2 . . . . . . . . . . . . . . 40

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8

8.1

Functional description . . . . . . . . . . . . . . . . . . 13

Functional description. . . . . . . . . . . . . . . . . . . 13

Power management . . . . . . . . . . . . . . . . . . . . 13

Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-down mode . . . . . . . . . . . . . . . . . . . . . 14

Analog video input . . . . . . . . . . . . . . . . . . . . . 14

Analog multiplexers. . . . . . . . . . . . . . . . . . . . . 14

Activity detection. . . . . . . . . . . . . . . . . . . . . . . 14

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

HSOSEL, DEO and SCHCKREFO. . . . . . . . . 15

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Sync-on-green . . . . . . . . . . . . . . . . . . . . . . . . 16

Programmable coast. . . . . . . . . . . . . . . . . . . . 17

Data enable . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Sync separator . . . . . . . . . . . . . . . . . . . . . . . . 17

3-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

I²C-bus register description . . . . . . . . . . . . . . 18

I²C-bus formats. . . . . . . . . . . . . . . . . . . . . . . . 18

Write 1 register . . . . . . . . . . . . . . . . . . . . . . . . 18

Write all registers . . . . . . . . . . . . . . . . . . . . . . 19

Read register . . . . . . . . . . . . . . . . . . . . . . . . . 20

I²C-bus registers overview . . . . . . . . . . . . . . . 22

Offset registers (R, G and B) . . . . . . . . . . . . . 24

Coarse registers (R, G and B) . . . . . . . . . . . . 25

Fine registers (R, G and B). . . . . . . . . . . . . . . 26

Sync-on-green register . . . . . . . . . . . . . . . . . . 27

PLL control register. . . . . . . . . . . . . . . . . . . . . 27

Phase register. . . . . . . . . . . . . . . . . . . . . . . . . 28

PLL divider registers. . . . . . . . . . . . . . . . . . . . 29

Horizontal sync registers . . . . . . . . . . . . . . . . 30

Coast register . . . . . . . . . . . . . . . . . . . . . . . . . 31

Horizontal sync selection register. . . . . . . . . . 31

Vertical sync selection register . . . . . . . . . . . . 32

Clamp register . . . . . . . . . . . . . . . . . . . . . . . . 32

Inverter register. . . . . . . . . . . . . . . . . . . . . . . . 33

10

11

12

13

14

15

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 41

Thermal characteristics . . . . . . . . . . . . . . . . . 42

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Application information . . . . . . . . . . . . . . . . . 49

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 50

8.1.1

8.1.1.1

8.1.1.2

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.3

8.4

8.5

8.6

8.7

8.8

8.9

16

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Introduction to soldering. . . . . . . . . . . . . . . . . 52

Wave and reﬂow soldering . . . . . . . . . . . . . . . 52

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 52

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 53

16.1

16.2

16.3

16.4

17

Revision history . . . . . . . . . . . . . . . . . . . . . . . 55

18

Legal information . . . . . . . . . . . . . . . . . . . . . . 56

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 56

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 56

18.1

18.2

18.3

18.4

9

9.1

9.1.1

9.1.2

9.1.2.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

9.11

9.12

9.13

9.14

9.15

19

20

Contact information . . . . . . . . . . . . . . . . . . . . 56

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 May 2007

Document identifier: TDA8754_7


型号：	TDA8754EL/11/C1
厂家：	NXP
描述：	IC 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208, 17 X 17 MM, 1.05 MM HEIGHT, PLASTIC, MO-192, SOT774-1, LBGA-208, Analog to Digital Converter 转换器
文件：	总57页 (文件大小：259K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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