TDA8761A [NXP]
9-bit analog-to-digital converter for digital video; 9位模拟 - 数字转换器，用于数字视频
| 型号： | TDA8761A |
| 厂家： | 
NXP |
| 描述： | 9-bit analog-to-digital converter for digital video |
| 文件： | 总24页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8761A
9-bit analog-to-digital converter for
digital video
1998 Nov 03
Product specification
Supersedes data of 1997 Aug 21
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
FEATURES
APPLICATIONS
• 9-bit resolution
Analog-to-digital conversion for:
• Video data digitizing
• Sampling rate up to 40 MHz
• DC sampling allowed
• Digital Video Broadcasting (DVB)
• Cable TV.
• One clock cycle conversion only
• High signal-to-noise ratio over a large analog input
frequency range (8.2 effective bits at 10 MHz full-scale
input at fclk = 30 MHz)
GENERAL DESCRIPTION
The TDA8761A is a 9-bit Analog-to-Digital Converter
(ADC) for professional video and digital video set box
applications. It converts the analog input signal into 9-bit
binary-coded digital words at a maximum sampling rate of
40 MHz. Its linearity performance ensures the required
conversion accuracy in the event of 256-QAM
demodulator concept and for all symbol frequencies.
All digital inputs and outputs are TTL and CMOS
compatible, although a low-level sine wave clock input
signal is allowed.
• No missing codes guaranteed
• In Range (IR) CMOS output
• Levels TTL and CMOS compatible digital inputs
• 3 to 5 V CMOS digital outputs
• Low-level AC clock input signal allowed
• External reference voltage regulator
• Power dissipation only 158 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
VCCA
VCCD
VCCO
ICCA
ICCD
ICCO
INL
analog supply voltage
digital supply voltage
output stages supply voltage
analog supply current
digital supply current
4.75
4.75
3.0
−
5.0
5.0
3.3
18
5.25
5.25
5.25
24
V
V
V
mA
mA
mA
LSB
LSB
−
13
18
output stages supply current fclk = 30 MHz; ramp input
−
1
2
integral non-linearity
f
clk = 30 MHz; ramp input
−
±0.8
±1.6
AINL
AC integral non-linearity
full-scale input sine wave; note 1
−
±0.75 0.9
50% full-scale input sine wave; note 1
−
±0.5
±0.3
±0.5
±0.3
−
±0.75 LSB
±0.7 LSB
±0.75 LSB
DNL
differential non-linearity
fclk = 30 MHz; ramp input
−
ADNL
AC differential non-linearity
full-scale input sine wave; note 1
−
50% full-scale input sine wave; note 1
−
±0.5
−
LSB
MHz
mW
fclk(max)
Ptot
maximum clock frequency
total power dissipation
40
−
158
173
Note
1. fi = 10 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz.
1998 Nov 03
2
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8761AM
SSOP28
plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
BLOCK DIAGRAM
V
CLK
1
V
CCD2
OE
10
CCA
3
11
2
CLOCK DRIVER
TC
TDA8761A
V
RT
9
25 D8
24 D7
23 D6
22 D5
21 D4
20 D3
19 D2
18 D1
17 D0
MSB
R
LAD
V
I
8
7
ANALOG -TO - DIGITAL
CONVERTER
analog
voltage input
CMOS
OUTPUTS
LATCHES
data outputs
V
RM
LSB
V
CCO
13
V
RB
6
28
26
V
CCD1
IR
IN RANGE LATCH
CMOS OUTPUT
output
12
27
4
14
OGND
AGND
DGND2
DGND1
MBG910
analog ground
output ground
digital grounds
Fig.1 Block diagram.
3
1998 Nov 03
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
PINNING
SYMBOL PIN
DESCRIPTION
CLK
TC
1
2
3
4
5
6
7
8
9
clock input
two’s complement input (active LOW)
analog supply voltage (5 V)
analog ground
VCCA
AGND
n.c.
VRB
VRM
VI
not connected
handbook, halfpage
reference voltage BOTTOM input
reference voltage MIDDLE
analog input voltage
V
CLK
TC
1
2
28
CCD1
27 DGND1
V
3
IR
26
CCA
VRT
OE
reference voltage TOP input
AGND
n.c.
4
25 D8
24 D7
23 D6
22 D5
10 output enable input (CMOS level
input, active LOW)
5
VCCD2
DGND2
VCCO
11 digital supply voltage 2 (5 V)
12 digital ground 2
V
6
RB
V
7
RM
13 supply voltage for output stages
(3 to 5 V)
TDA8761A
V
I
D4
8
21
20 D3
D2
V
9
OGND
n.c.
n.c.
D0
14 output ground
RT
15 not connected
OE
10
11
19
16 not connected
V
18 D1
17 D0
16 n.c.
15 n.c.
CCD2
17 data output; bit 0 (LSB)
18 data output; bit 1
19 data output; bit 2
20 data output; bit 3
21 data output; bit 4
22 data output; bit 5
23 data output; bit 6
24 data output; bit 7
25 data output; bit 8 (MSB)
26 in range data output
27 digital ground 1
DGND2 12
D1
V
13
CCO
D2
OGND 14
D3
MBG909
D4
D5
D6
D7
D8
IR
DGND1
VCCD1
Fig.2 Pin configuration.
28 digital supply voltage 1 (5 V)
1998 Nov 03
4
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
CONDITIONS
note 1
MIN.
−0.3
MAX.
UNIT
analog supply voltage
digital supply voltage
+7.0
+7.0
+7.0
V
V
V
VCCD
VCCO
∆VCC
note 1
note 1
−0.3
−0.3
output stages supply voltage
supply voltage differences
between
V
V
V
CCA and VCCD
CCD and VCCO
CCA and VCCO
−1.0
−1.0
−1.0
−0.3
−
+1.0
+4.0
+4.0
+7.0
VCCD
V
V
V
V
V
VI
input voltage
referenced to AGND
referenced to DGND
Vi(p-p)
AC input voltage for switching
(peak-to-peak value)
IO
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
0
+150
+70
+150
−
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply
voltage differences ∆VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
110
K/W
1998 Nov 03
5
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
CHARACTERISTICS
VCCA = V3 to V4 = 4.75 to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 to 5.25 V; VCCO = V13 to V14 = 3.0 to 5.25 V;
AGND and DGND shorted together; Tamb = 0 to 70 °C; typical values measured at VCCA = VCCD = 5 V and
VCCO = 3.3 V; Vi(p-p) = 1.8 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
VCCD
VCCO
∆VCC
analog supply voltage
digital supply voltage
4.75
5.0
5.25
V
V
V
4.75
3.0
5.0
3.3
5.25
5.25
output stages supply voltage
supply voltage differences
between
VCCA and VCCD
−0.2
−0.2
−0.2
−
−
+0.2
+2.25
+2.25
24
V
V
V
V
CCA and VCCO
CCD and VCCO
−
V
−
ICCA
ICCD
ICCO
analog supply current
digital supply current
18
13
1
mA
mA
mA
−
18
output stages supply current
fclk = 30 MHz; ramp input
−
2
Inputs
CLOCK INPUT CLK (REFERENCED TO DGND); note 1
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input impedance
0
−
−
0
2
2
2
0.8
VCCD
+1
10
−
V
2
V
Vclk = 0.8 V
Vclk = 2 V
−1
−
µA
µA
kΩ
pF
IIH
Zi
fclk = 30 MHz
−
Ci
input capacitance
−
−
INPUTS OE AND TC (REFERENCED TO DGND); see Table 2
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
0
−
−
−
−
0.8
VCCD
−
V
2
V
VIL = 0.8 V
VIH = 2.0 V
−1
−
µA
µA
IIH
1
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND)
IIL
IIH
Zi
LOW-level input current
HIGH-level input current
input impedance
VI = VRB = 1.3 V
VI = VRT = 3.43 V
fi = 10 MHz
−
−
−
−
17
35
8
−
−
−
−
µA
µA
kΩ
pF
Ci
input capacitance
5
1998 Nov 03
6
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reference voltages for the resistor ladder; see Table 1
VRB
VRT
Vdiff
reference voltage BOTTOM
reference voltage TOP
1.2
3.2
2
1.3
2.45
V
3.43
2.13
VCCA − 0.8 V
differential reference voltage
3.0
V
VRT − VRB
Iref
reference current
resistor ladder
V
RT − VRB = 2.13 V
−
8.7
−
mA
Ω
RLAD
TCRLAD
−
245
1860
456
160
160
1.81
−
temperature coefficient of the
resistor ladder
−
−
ppm
mΩ/K
mV
mV
V
−
−
VosB
VosT
Vi(p-p)
offset voltage BOTTOM
offset voltage TOP
note 2
note 2
note 3
−
−
−
−
analog input voltage
(peak-to-peak value)
1.7
2.55
Outputs
DIGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND)
VOL
VOH
IOZ
LOW-level output voltage
HIGH-level output voltage
output current in 3-state mode
IOL = 1 mA
0
−
0.5
V
IOH = −1 mA
V
CCO − 0.5 −
VCCO
+20
V
0.5 V < VO < VCCO
−20
−
µA
Switching characteristics
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max)
tCPH
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
40
10
10
−
−
−
−
−
−
MHz
ns
tCPL
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 30 MHz; ramp input
−
−
±0.4
±1
LSB
LSB
AINL
AC integral non-linearity
full-scale input sine
wave; note 4
±0.75
±0.9
50% full-scale input sine
wave; note 4
−
±0.5
±0.75
LSB
DNL
differential non-linearity
f
clk = 30 MHz; ramp input
−
−
±0.3
±0.5
±0.7
LSB
LSB
ADNL
AC differential non-linearity
full-scale input sine
wave; note 4
±0.75
50% full-scale input sine
wave; note 4
−
−
±0.3
±1
±0.5
LSB
LSB
OFER
GER
offset error
middle code;
−
V
RB = 1.3 V;
VRT = 3.43 V
gain error (from
device to device)
VRB = 1.3 V;
−
±0.1
−
%
VRT = 3.43 V; note 5
1998 Nov 03
7
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BANDWIDTH (fclk = 30 MHZ)
B
analog bandwidth
full-scale sine wave;
note 6
−
−
−
15
−
−
−
MHz
75% full-scale sine wave;
note 6
20
MHz
MHz
small signal at mid-scale;
VI = ±10 LSB at
350
code 256; note 6
tSTLH
tSTHL
analog input settling time
LOW-to-HIGH
full-scale square wave;
Fig.6; note 7
−
−
1.5
1.5
3.0
3.0
ns
ns
analog input settling time
HIGH-to-LOW
full-scale square wave;
Fig.6; note 7
HARMONICS (fclk = 30 MHZ); see Figs 7 and 8
THD total harmonic distortion
fi = 10 MHz
−
−56
−
−
dB
dB
SIGNAL-TO-NOISE RATIO; see Figs 7 and 8; note 8
SNR signal-to-noise ratio (full scale) without harmonics;
clk = 30 MHz;
fi = 10 MHz
53
55
f
EFFECTIVE BITS; see Figs 7 and 8; note 8
ENOB effective bits
f
clk = 30 MHz
fi = 4.43 MHz
fi = 10 MHz
−
−
8.8
8.2
−
−
bits
bits
TWO-TONE; note 9
TTIR two-tone intermodulation
rejection
f
clk = 30 MHz
−
−
−56
−
−
dB
BIT ERROR RATE
BER
bit error rate
fclk = 30 MHz;
fi = 10 MHz;
VI = ±16 LSB at
code 256
10−13
times/
sample
DIFFERENTIAL GAIN; note 10
Gdiff
differential gain
fclk = 30 MHz;
PAL modulated ramp
−
−
0.5
0.3
−
−
%
DIFFERENTIAL PHASE; note 10
ϕdiff
differential phase
fclk = 30 MHz;
°C
PAL modulated ramp
1998 Nov 03
8
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing (fclk = 30 MHz; CL = 15 pF); see Fig.4; note 11
tds
th
sampling delay time
output hold time
−
4
−
−
−
3
−
ns
−
−
ns
ns
ns
pF
td
output delay time
VCCO = 4.75 V
CCO = 3.15 V
10
12
−
13
15
15
V
CL
digital output load
3-state output delay times; see Fig.5
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
−
−
−
5.5
12
19
12
8.5
15
24
15
ns
ns
ns
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 511:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb = 25 °C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to code 511 at Tamb = 25 °C.
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.
V
RT – VRB
a) The current flowing into the resistor ladder is IL
=
and the full-scale input range at the converter,
˙
-----------------------------------------
R
OB + RL + ROT
R L
to cover code 0 to code 511, is V = R × I =
× (V
– VRB ) = 0.852 × (V RT – VRB )
RT
-----------------------------------------
I
L
L
R
OB + RL + ROT
b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
RL
will be kept reasonably constant from device to device. Consequently variation of the output
-----------------------------------------
OB + RL + ROT
R
codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.
4. fi = 10 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz.
(V511 – V0) – V
5. GER =
i(p-p) × 100
---------------------------------------------------
Vi(p-p)
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data.
1998 Nov 03
9
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = ENOB × 6.02 + 1.76 dB.
9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 and 10.10 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.
10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
11. Output data acquisition: the output data is available after the maximum delay time of td.
handbook, halfpage
9
V
RT
R
OT
code 511
R
L
7
V
I
RM
L
R
LAD
code 0
R
OB
6
V
RB
MGD233
Fig.3 Explanation of note 3.
1998 Nov 03
10
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.43 V)
BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
STEP VI(p-p) IR
U/F
0
<1.46
0
1
1
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
1
1
1
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
1.46
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
510
511
O/F
.
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
3.27
>3.27
Table 2 Mode selection
TC OE
D8 to D0
IR
X
0
1
1
0
0
high impedance
high impedance
active
active; two’s complement
active; binary
active
t
CPL
t
CPH
V
CCD
50%
0 V
CLK
sample N
sample N + 1
sample N + 2
V
l
t
t
ds
h
V
CCO
DATA
D0 to D8
DATA
N - 2
DATA
N - 1
DATA
N
DATA
N + 1
50%
0 V
t
d
MBG908
Fig.4 Timing diagram.
11
1998 Nov 03
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
V
CCD
n
OE
50 %
dZH
t
t
dHZ
HIGH
90 %
output
data
50 %
LOW
t
t
dZL
dLZ
HIGH
output
data
50 %
LOW
10 %
TEST
S1
V
CCD
t
t
t
t
V
CCD
dLZ
dZL
dHZ
dZH
3.3 kΩ
15 pF
V
CCD
DGND
DGND
S1
TDA8761A
OE
MBG907
fOE = 100 kHz.
Fig.5 Timing diagram and test conditions of 3-state output delay time.
t
t
STLH
STHL
50 %
code 511
V
I
50 %
code 0
2 ns
2 ns
CLK
50 %
50 %
MGC359
0.5 ns
0.5 ns
Fig.6 Analog input settling-time diagram.
12
1998 Nov 03
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
MBG912
0
amplitude
(dB)
20
40
60
80
100
120
0
1.25
2.50
3.76
5.01
6.26
7.51
8.77
10.0
f (MHz)
Effective bits: 8.70; THD = −68.68 dB.
Harmonic levels (dB): 2nd = −78.40; 3rd = −72.08; 4th = −75.85 dB; 5th = −76.26; 6th = −80.23.
Fig.7 Typical Fast Fourier Transform (fclk = 30 MHz; fi = 4.43 MHz).
MBG911
0
amplitude
(dB)
20
40
60
80
100
120
0
1.87
3.75
5.62
7.50
9.37
11.2
13.1
15.0
f (MHz)
Effective bits: 8.25; THD = −56.72 dB.
Harmonic levels (dB): 2nd = −62.21; 3rd = −58.58; 4th = −80.29; 5th = −71.71; 6th = −72.04.
Fig.8 Typical Fast Fourier Transform (fclk = 30 MHz; fi = 10 MHz).
13
1998 Nov 03
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
FCE166
1
LSB
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
100
200
300
400
500
Code
Fig.9 Typical AC INL (fclk = 30 MHz; fi = 10 MHz).
FCE165
1
LSB
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
100
200
300
400
500
Code
Fig.10 Typical AC DNL (fclk = 30 MHz; fi = 10 MHz).
1998 Nov 03
14
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
handbook, halfpage
V
V
CCO
CCA
D8 to D0
IR
V
I
OGND
AGND
MGD231
MGC040 - 1
Fig.11 CMOS data and in range outputs.
Fig.12 Analog inputs.
handbook, halfpage
V
handbook, halfpage
CCA
V
CCO
V
V
RT
R
LAD
RM
OE
V
RB
(TC)
OGND
AGND
MBE557
MGD232
Fig.13 OE (TC) input.
Fig.14 VRB, VRM and VRT inputs.
1998 Nov 03
15
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
handbook, halfpage
V
CCD
1.5 V
CLK
DGND
MBE559 - 1
Fig.15 CLK input.
1998 Nov 03
16
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
APPLICATION INFORMATION
V
handbook, halfpage
CLK
TC
CCD1
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DGND1
IR
V
CCA
3
AGND
D8
4
n.c.
(1)
D7
5
V
RB
D6
6
(1)
100 nF
V
RM
D5
7
AGND
100 nF
TDA8761A
V
I
D4
8
(1)
V
RT
D3
9
AGND
100 nF
OE
D2
10
11
12
13
14
AGND
V
D1
CCD2
DGND2
D0
(2)
V
n.c.
CCO
(2)
OGND
n.c.
MBG906
The analog and digital supplies should be separated and decoupled.
The external voltage regulator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the
reference ladder voltages can be derived from a well regulated VCCA supply through a resistor bridge and a decoupled capacitor.
(1) VRB, VRM and VRT are decoupled to AGND.
(2) Pins 15 and 16 may be connected to DGND in order to prevent noise influence.
Fig.16 Application diagram.
1998 Nov 03
17
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
PACKAGE OUTLINE
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
D
E
A
X
c
H
v
M
A
y
E
Z
28
15
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
14
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.1
0.7
mm
2.0
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-09-08
95-02-04
SOT341-1
MO-150AH
1998 Nov 03
18
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SSOP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1998 Nov 03
19
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Nov 03
20
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
NOTES
1998 Nov 03
21
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
NOTES
1998 Nov 03
22
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
NOTES
1998 Nov 03
23
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/750/03/pp24
Date of release: 1998 Nov 03
Document order number: 9397 750 04668
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