TDA8764HL/4 [NXP]
10-bit high-speed low-power ADC with internal reference regulator; 10位高速低功耗ADC，内置电压基准稳压器
| 型号： | TDA8764HL/4 |
| 厂家： | 
NXP |
| 描述： | 10-bit high-speed low-power ADC with internal reference regulator |
| 文件： | 总28页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8764
10-bit high-speed low-power ADC
with internal reference regulator
1999 Jan 12
Preliminary specification
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
FEATURES
APPLICATIONS
High-speed analog-to-digital conversion for:
• 10-bit resolution (binary or gray code)
• Sampling rate up to 40 MHz (/4 version)
Sampling rate up to 80 MHz (/8 version)
• DC sampling allowed
• Video data digitizing
• Radar pulse analysis
• Transient signal analysis
• High energy physics research
• Σ∆ modulators
• One clock cycle conversion only
• High signal-to-noise ratio over a large analog input
frequency range (9.5 effective bits at 5 MHz; full-scale
input at fclk = 40 MHz)
• Medical imaging.
• No missing codes guaranteed
GENERAL DESCRIPTION
• In-Range (IR) CMOS output
The TDA8764 is a 10-bit high-speed low-power
Analog-to-Digital Converter (ADC) for professional video
and other applications. It converts the analog input signal
into 10-bit binary or gray coded digital words at a maximum
sampling rate of 40 MHz (/4 version) and 80 MHz
(/8 version). All digital inputs and outputs are TTL
compatible, although a low-level sine wave clock input
signal is allowed.
• TTL and CMOS levels compatible digital inputs
• 2.7 to 3.6 V CMOS digital outputs
• Low-level AC clock input signal allowed
• Internal reference voltage regulator
• Power dissipation only 250 mW (typical for /4 version)
Power dissipation only 375 mW (typical for /8 version)
• Low analog input capacitance, no buffer amplifier
required
The device includes an internal voltage reference
regulator.
• No sample-and-hold circuit required.
ORDERING INFORMATION
PACKAGE
DESCRIPTION
TYPE
NUMBER
SAMPLING
FREQUENCY (MHz)
NAME
VERSION
TDA8764TS/4
TDA8764TS/8
TDA8764HL/4
TDA8764HL/8
SSOP28 plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1
40
80
40
80
LQFP32 plastic low profile quad flat package; 32 leads;
SOT401-1
body 5 × 5 × 1.4 mm
1999 Jan 12
2
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
CONDITIONS
MIN.
4.75
TYP.
5.0
MAX.
5.25
UNIT
analog supply voltage
V
VCCD
VCCO
ICCA
digital supply voltage
4.75
2.7
5.0
3.3
5.25
3.6
V
V
output stages supply voltage
analog supply current
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
digital supply current
−
−
25
45
tbf
tbf
mA
mA
ICCD
ICCO
INL
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
output stages supply current
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
integral non-linearity
−
−
25
30
tbf
tbf
mA
mA
f
clk = 40 MHz; ramp input
clk = 80 MHz; ramp input
−
−
0
0
tbf
tbf
mA
mA
f
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
differential non-linearity
fclk = 40 MHz; ramp input
fclk = 80 MHz; ramp input
−
−
±0.8
±0.8
tbf
tbf
LSB
LSB
DNL
fclk(max)
Ptot
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
maximum clock frequency
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
total power dissipation
fclk = 40 MHz; ramp input
−
−
±0.25
±0.25
tbf
tbf
LSB
LSB
fclk = 80 MHz; ramp input
40
80
−
−
−
−
MHz
MHz
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
f
clk = 40 MHz; ramp input
clk = 80 MHz; ramp input
−
−
250
375
tbf
tbf
mW
mW
f
1999 Jan 12
3
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
BLOCK DIAGRAM
V
V
CCD2
DEC
5 (10)
CLK
1 (5)
OE GRAY
CCA
3 (7)
11 (17) 10
(16)
15 (21)
REFERENCE
VOLTAGE
REGULATOR
CLOCK DRIVER
2 (6)
TC
9 (15)
V
RT
25 (31)
24 (30)
D9
MSB
D8
D7
D6
23 (29)
22 (28)
21 (27)
20 (26)
19 (25)
18 (24)
17 (23)
16 (22)
V
8 (14)
7 (13)
analog
voltage input
I
ANALOG-TO-DIGITAL
CONVERTER
D5
CMOS
OUTPUTS
data outputs
LATCHES
D4
D3
D2
V
RM
R
LAD
D1
LSB
D0
13 (19)
6 (12)
V
V
CCO
RB
26 (2)
28 (4)
CMOS
OUTPUT
IR output
IN-RANGE LATCH
TDA8764
V
CCD1
4 (8)
12 (18)
14 (20)
OGND
27 (3)
DGND1
FCE099
AGND
DGND2
analog ground
digital ground
output ground
digital ground
The pin numbers given in parenthesis refer to the LQFP32 package.
Fig.1 Block diagram.
1999 Jan 12
4
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
PINNING
PINS
SYMBOL
DESCRIPTION
SSOP28
LQFP32
CLK
TC
1
5
clock input
2
6
twos complement input (input active LOW)
analog supply voltage (+5 V)
analog ground
VCCA
AGND
DEC
VRB
VRM
VI
3
7
4
8
5
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2
decoupling input
6
reference voltage BOTTOM input
reference voltage MIDDLE input
analog input voltage
7
8
VRT
9
reference voltage TOP input
output enable input (input active LOW)
digital supply voltage 2 (+5 V)
digital ground 2
OE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
−
VCCD2
DGND2
VCCO
OGND
GRAY
D0
supply voltage for output stages (2.7 to 3.6 V)
output ground
gray code input (input active HIGH)
data output; bit 0 (LSB)
data output; bit 1
D1
D2
data output; bit 2
D3
data output; bit 3
D4
data output; bit 4
D5
data output; bit 5
D6
data output; bit 6
D7
data output; bit 7
D8
data output; bit 8
D9
data output; bit 9 (MSB)
in-range data output
digital ground 1
IR
DGND1
VCCD1
n.c.
3
4
digital supply voltage 1 (+5 V)
1, 9, 11 and 32 not connected
1999 Jan 12
5
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
handbook, halfpage
V
CLK
TC
1
2
28
27
26
25
24
23
22
CCD1
DGND1
IR
V
3
CCA
AGND
DEC
D9
4
D8
5
V
6
D7
RB
V
D6
7
RM
TDA8764TS
V
I
8
21 D5
V
D4
D3
D2
D1
D0
9
20
19
18
17
16
RT
OE
10
11
12
13
14
V
CCD2
DGND2
V
CCO
OGND
15 GRAY
FCE100
Fig.2 Pin configuration (SSOP28).
D2
D1
n.c.
IR
1
2
3
4
5
6
7
8
24
23
DGND1
22 D0
V
21 GRAY
20 OGND
CCD1
TDA8764HL
CLK
TC
V
19
18
17
CCO
V
DGND2
CCA
V
AGND
CCD2
FCE125
Fig.3 Pin configuration (LQFP32).
6
1999 Jan 12
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
analog supply voltage
CONDITIONS
note 1
MIN.
−0.3
MAX.
+7.0
UNIT
VCCA
VCCD
VCCO
∆VCC
V
V
V
digital supply voltage
note 1
note 1
−0.3
−0.3
+7.0
+7.0
output stages supply voltage
supply voltage difference
V
V
V
CCA − VCCD
CCA − VCCO
CCD − VCCO
−1.0
−1.0
−1.0
+1.0
+4.0
+4.0
+7.0
VCCD
10
V
V
V
V
V
VI
input voltage
referenced to AGND −0.3
Vi(sw)(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND
−
IO
output current
−
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
−40
−
+150
+85
150
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply
voltage differences ∆VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
SSOP28
LQFP32
110
90
K/W
K/W
1999 Jan 12
7
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
CHARACTERISTICS
The characteristics given refer to the SSOP28 package. VCCA = V3 to V4 = 4.75 to 5.25 V;
VCCD = V11 to V12 and V28 to V27 = 4.75 to 5.25 V; VCCO = V13 to V14 = 2.7 to 3.6 V; AGND and DGND shorted
together; Tamb = 0 to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 10 pF and
Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
Supplies
VCCA
analog supply voltage
4.75
5.0
5.25
5.25
5.25
3.6
V
VCCD1
VCCD2
VCCO
digital supply voltage 1
digital supply voltage 2
output stages supply voltage
supply voltage difference
4.75
4.75
2.7
5.0
5.0
3.3
V
V
V
∆VCC
VCCA − VCCD
VCCA − VCCO
VCCD − VCCO
−0.20
−0.20
−0.20
−
−
−
+0.20
+2.55
+2.55
V
V
V
ICCA
ICCD
ICCO
analog supply current
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
digital supply current
−
−
25
45
tbf
tbf
mA
mA
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
output stages supply current
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
−
−
25
30
tbf
tbf
mA
mA
f
clk = 40 MHz; ramp input
−
−
0
0
tbf
tbf
mA
mA
fclk = 80 MHz; ramp input
Inputs
CLOCK INPUT; CLK (REFERENCED TO DGND); note 1
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input capacitance
0
−
−
0
2
2
0.8
VCCD
+1
V
2
V
VCLK = 0.8 V
VCLK = 2 V
−1
−
µA
µA
pF
IIH
Ci
10
−
−
INPUTS OE, TC AND GRAY (REFERENCED TO DGND); see Tables 3 and 4
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
0
−
−
−
−
0.8
VCCD
−
V
2
V
VIL = 0.8 V
VIH = 2 V
−1
−
µA
µA
IIH
1
1999 Jan 12
8
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND)
IIL
IIH
Yi
LOW-level input current
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
HIGH-level input current
VI = VRB
−
−
0
−
−
µA
VI = VRB
0
µA
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
VI = VRT
−
−
45
85
−
−
µA
µA
VI = VRT
input admittance
fi = 5 MHz; note 2
TDA8764TS/4; TDA8764HL/4
input resistance
−
70
5
−
kΩ
input capacitance
3
7
pF
input admittance
fi = 5 MHz; note 2
TDA8764TS/8; TDA8764HL/8
input resistance
−
45
5
−
kΩ
input capacitance
3
7
pF
Reference voltages for the resistor ladder using the internal voltage regulator; see Table 1
VRB
reference voltage BOTTOM
reference voltage TOP
tbf
tbf
tbf
1.3
3.7
2.4
tbf
tbf
tbf
V
V
V
VRT
Vdiff(ref)
differential reference voltage
VRT − VRB
TCVdiff
temperature coefficient of
−
tbf
−
mV/K
differential reference voltage
Voffset(B)
Voffset(T)
VI(p-p)
offset voltage BOTTOM
offset voltage TOP
note 3
note 3
note 4
−
161
161
2.08
−
mV
mV
V
−
−
analog input voltage
(peak-to-peak value)
tbf
tbf
Outputs
DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)
VOL
VOH
IOZ
LOW-level output voltage
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
HIGH-level output voltage
I
OL = 1 mA
OL = 2 mA
0
0
−
−
0.5
0.5
V
V
I
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
output current in 3-state mode
IOH = −1 mA
OH = −2 mA
0.5 V < Vo < VCCO
V
CCO − 0.5 −
VCCO
VCCO
+20
V
I
V
CCO − 0.5 −
V
−20
−
µA
1999 Jan 12
9
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
Switching characteristics
CLOCK INPUT; CLK; see Fig.5; note 1
fclk(max)
maximum clock frequency
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
clock pulse width HIGH
40
80
−
−
−
MHz
−
MHz
tCPH
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
clock pulse width LOW
7
5
−
−
−
−
ns
ns
tCPL
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
7
5
−
−
−
−
ns
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
differential non-linearity
TDA8764TS/4; TDA8764HL/4
TDA8764TS/8; TDA8764HL/8
offset error
f
clk = 40 MHz; ramp input
−
−
±0.8
±0.8
tbf
tbf
LSB
LSB
fclk = 80 MHz; ramp input
DNL
fclk = 40 MHz; ramp input
−
−
−
−
±0.25 tbf
±0.25 tbf
LSB
LSB
LSB
%
fclk = 80 MHz; ramp input
middle code
Eoffset
EG
±1
−
−
gain error (from device to device)
using internal reference voltage
note 5
tbf
BANDWIDTH (fclk = 40 MHZ)/4 VERSION;
B
analog bandwidth
full-scale sine wave; note 6
−
−
20
30
−
−
MHz
MHz
75% full-scale sine wave;
note 6
small signal at mid-scale;
VI = ±10 LSB at code 512;
note 6
−
350
−
MHz
tstLH
tstHL
analog input settling time
LOW-to-HIGH
full-scale square wave;
see Fig.7 and note 7
−
−
tbf
tbf
tbf
tbf
ns
ns
analog input settling time
HIGH-to-LOW
full-scale square wave;
see Fig.7 and note 7
1999 Jan 12
10
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
BANDWIDTH (fclk = 80 MHZ) /8 VERSION;
B
analog bandwidth
full-scale sine wave; note 6
−
−
40
−
−
MHz
75% full-scale sine wave;
note 6
60
MHz
small signal at mid-scale;
Vi = ±10 LSB at code 512;
note 6
−
700
−
MHz
tstLH
tstHL
analog input settling time
LOW-to-HIGH
full-scale square wave;
see Fig.7 and note 7
−
−
tbf
tbf
tbf
tbf
ns
ns
analog input settling time
HIGH-to-LOW
full-scale square wave;
see Fig.7 and note 7
HARMONICS (fclk = 40 MHZ) /4 VERSION;
Hall(FS)
harmonics (full-scale);
all components
fi = 5 MHz
second harmonics
third harmonics
−
−
−
−
−70
−90
tbf
tbf
tbf
−
dBc
dBc
dBc
dB
SFDR
THD
spurious free dynamic range
total harmonic distortion
fi = 5 MHz
fi = 5 MHz
−70
−
HARMONICS (fclk = 80 MHZ)/8 VERSION;
Hall(FS)
harmonics (full-scale);
all components
fi = 5 MHz
second harmonics
third harmonics
−
−
−
−
−71
−87
tbf
tbf
tbf
−
dBc
dBc
dBc
dB
SFDR
THD
spurious free dynamic range
total harmonic distortion
fi = 5 MHz
fi = 5 MHz
−70
−
SIGNAL-TO-NOISE RATIO; note 8
SNR(FS)
signal-to-noise ratio (full-scale)
without harmonics;
fi = 5 MHz
f
clk = 40 MHz; /4 version
clk = 80 MHz; /8 version
tbf
tbf
58
58
−
−
dB
dB
f
EFFECTIVE BITS; note 8
EB
effective bits
fclk = 40 MHz
TDA8764TS/4; TDA8764HL/4
fi = 5 MHz
tbf
tbf
tbf
tbf
9.5
9.2
9.0
tbf
tbf
tbf
tbf
tbf
bits
bits
bits
bits
fi = 7.5 MHz
fi = 10 MHz
fi = 20 MHz
effective bits
TDA8764TS/8; TDA8764HL/8
fclk = 80 MHz
fi = 5 MHz
tbf
tbf
tbf
tbf
9.5
tbf
tbf
tbf
tbf
tbf
tbf
tbf
bits
bits
bits
bits
fi = 10 MHz
fi = 20 MHz
fi = 40 MHz
1999 Jan 12
11
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
TWO-TONE; note 9
TTID
two-tone intermodulation distortion fclk = 40 MHz
clk = 80 MHz
−
−
tbf
−
−
dB
f
tbf
dB
BIT ERROR RATE
BER
bit error rate
fi = 5 MHz; Vi = ±16 LSB at
code 512
f
clk = 40 MHz
−
−
10−13
10−13
−
−
times/
sample
fclk = 80 MHz
times/
sample
Timing (fclk = 40 MHz; CL = 10 pF) /4 version; see Fig.5 and note 10
tds
th
sampling delay time
output hold time
−
−
2
ns
5
−
−
ns
td
output delay time
VCCO = 2.7 V
tbf
tbf
−
12
11
−
tbf
tbf
10
tbf
ns
VCCO = 3.3 V
ns
CL
digital output load capacitance
slew rate
pF
V/µs
SR
VCCO = 2.7 V; CL = 10 pF
−
−
Timing (fclk = 80 MHz; CL = 10 pF) /8 version; see Fig.5 and note 10
tds
th
sampling delay time
output hold time
−
−
−
8
7
−
−
2
ns
4
−
ns
td
output delay time
VCCO = 2.7 V
VCCO = 3.3 V
tbf
tbf
−
tbf
tbf
10
tbf
ns
ns
CL
digital output load capacitance
slew rate
pF
V/µs
SR
VCCO = 2.7 V; CL = 10 pF
−
3-state output delay times (fclk = 40 MHz) /4 version; see Fig.6
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
−
−
−
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
ns
ns
ns
ns
3-state output delay times (fclk = 80 MHz) /8 version; see Fig.6
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
−
−
−
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
ns
ns
ns
ns
1999 Jan 12
12
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
1
Ri
2. The input admittance is Vi=
+ Cijw
----
3. Analog input voltages producing code 0 up to and including code 1023:
a) Voffset(B) (offset voltage BOTTOM) is the difference between the analog input which produces data equal to 00
and the reference voltage BOTTOM (VRB) at Tamb = 25 °C.
b) Voffset(T) (offset voltage TOP) is the difference between reference voltage TOP (VRT) and the analog input which
produces data outputs equal to code 1023 at Tamb = 25 °C.
4. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.4.
V
RT – VRB
a) The current flowing into the resistor ladder is IL=
to cover code 0 to code 1023, is V I = R L × I L =
and the full-scale input range at the converter,
-----------------------------------------
R
OB + RL + ROT
R L
× (V RT – VRB) = 0.866 × (VRT – VRB
)
-----------------------------------------
R
OB + RL + ROT
b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
RL
will be kept reasonably constant from device to device. Consequently variation of the output
-----------------------------------------
OB + RL + ROT
R
codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.
(V 1023 – V0) – Vi (p – p)
5.
E G
=
× 100
-----------------------------------------------------------
Vi (p – p)
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, nor any significant attenuation are observed in the reconstructed signal.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data.
8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = EB × 6.02 + 1.76 dB.
9. Intermodulation measured relative to either tone with analog input frequencies of 5 and 5.1 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.
10. Output data acquisition: the output data is available after the maximum delay time of td(max). For the 80 MHz version
it is recommended to have the lowest possible output load.
1999 Jan 12
13
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
handbook, halfpage
V
RT
R
OT
code 1023
code 0
R
L
V
I
RM
L
R
LAD
R
OB
V
RB
MGD281
Fig.4 Explanation of note 4.
Table 1 Output coding and input voltage (typical values; referenced to AGND); binary and gray codes
BINARY OUTPUT BITS GRAY OUTPUT BITS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
STEP Vi(p-p) IR
U/F
0
<tbf
tbf
...
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
...
...
...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
...
1022 ...
1023 tbf
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
O/F
>tbf
Table 2 Output coding and input voltage (typical values; referenced to AGND); binary and twos complement codes
BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
STEP Vi(p-p) IR
U/F
0
<tbf
tbf
...
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
...
...
...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
...
1022 ...
1023 tbf
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
O/F
>tbf
1999 Jan 12
14
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
Table 3 Mode selection
TC
OE
D9 TO D0
high impedance
IR
IR
X
0
1
1
0
0
high impedance
active
active; two complement
active; binary
active
Table 4 Mode selection
GRAY
OE
1
D9 TO D0
high impedance
active; binary
X
0
1
high impedance
active
0
0
active; gray
active
t
CPL
t
CPH
V
CCO
50%
CLK
0 V
sample N
sample N + 1
sample N + 2
V
l
t
t
ds
h
V
CCO
DATA
D0 to D9
DATA
N - 2
DATA
N - 1
DATA
N
DATA
N + 1
50%
0 V
t
d
MBG916
Fig.5 Timing diagram.
1999 Jan 12
15
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
V
CCD
50%
OE
t
t
dHZ
HIGH
dZH
90%
output
data
50%
t
t
dLZ
dZL
LOW
HIGH
output
data
50%
LOW
10%
TEST
S1
V
t
t
V
CCD
dLZ
dZL
CCD
S1
V
3.3 kΩ
CCD
TDA8764
t
t
DGND
dHZ
dZH
15 pF
DGND
FCE101
OE
fOE = 100 kHz.
Fig.6 Timing diagram and test conditions of 3-state output delay time.
t
t
STLH
STHL
50%
code 1023
V
I
50%
code 0
2 ns
2 ns
CLK
50%
50%
MBE566
0.5 ns
0.5 ns
Fig.7 Analog input settling time diagram.
16
1999 Jan 12
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
handbook, halfpage
V
V
CCO
CCA
D9 to D0
IR
V
I
OGND
AGND
MBG915
MGC040 - 1
Fig.8 CMOS data and in range outputs.
Fig.9 Analog inputs.
DEC
handbook, halfpage
V
CCA
handbook, halfpage
V
CCO
V
RT
OE
R
LAD
V
REGULATOR
RM
TC
GRAY
V
RB
OGND
FCE102
AGND
MBE558 - 1
Fig.10 OE, GRAY and TC inputs.
Fig.11 VRB, VRM and VRT.
1999 Jan 12
17
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
handbook, halfpage
V
CCD
1.5 V
CLK
DGND
FCE103
Fig.12 CLK input.
1999 Jan 12
18
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
APPLICATION INFORMATION
V
CCD1
CLK
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(2)
100 nF
DGND1
IR
TC
2
V
CCA
3
(2)
100 nF
D9
AGND
4
D8
DEC
5
4.7 nF
AGND
(1)
V
V
RB
D7
6
7
8
9
(1)
1 nF
AGND
RM
D6
TDA8764TS
V
I
D5
(1)
1 nF
AGND
V
D4
RT
1 nF
AGND
D3
OE
10
11
V
D2
CCD2
(2)
100 nF
100 nF
D1
DGND2
12
13
14
V
D0
CCO
(2)
GRAY
OGND
FCE104
The analog and digital supplies should be separated and well decoupled.
An application note is available which describes the design and the realization of a demonstration board
that uses TDA8764HL in an application environment.
(1) VRB, VRM and VRT are decoupled to AGND.
(2) Decoupling capacitor for supplies; it must be placed close to the device.
Fig.13 Application diagram (SSOP28).
1999 Jan 12
19
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
n.c.
32
D9
31
D8
30
D7
29
D6
28
D5
27
D4
26
D3
25
n.c.
IR
D2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
D1
DGND1
D0
(2)
100 nF
V
CCD1
GRAY
OGND
TDA8764HL
CLK
TC
(2)
100 nF
V
CCO
V
CCA
DGND2
(2)
(2)
100 nF
100 nF
V
AGND
CCD2
9
10
DEC
11
n.c.
12
13
14
15
16
OE
n.c.
4.7 nF
AGND
V
V
V
V
RT
RB
RM
I
(1)
(1)
(1)
1 nF
1 nF
AGND AGND
1 nF
AGND
FCE126
The analog and digital supplies should be separated and well decoupled.
An application note is available which describes the design and the realization of a demonstration board
that uses TDA8764HL in an application environment.
(1) VRB, VRM and VRT are decoupled to AGND.
(2) Decoupling capacitor for supplies; it must be placed close to the device.
Fig.14 Application diagram (LQFP32).
1999 Jan 12
20
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
PACKAGE OUTLINES
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
D
E
A
X
c
H
v
M
A
y
E
Z
28
15
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
14
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.1
0.7
mm
2.0
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-09-08
95-02-04
SOT341-1
MO-150AH
1999 Jan 12
21
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm
SOT401-1
c
y
X
A
E
17
24
Z
16
25
E
e
A
H
2
E
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
32
9
L
1
8
detail X
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.5
0.05 1.3
0.27 0.18 5.1
0.17 0.12 4.9
5.1
4.9
7.15 7.15
6.85 6.85
0.75
0.45
0.95 0.95
0.55 0.55
mm
1.60
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-04
SOT401-1
1999 Jan 12
22
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Jan 12
23
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
not suitable(2)
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, SMS
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Jan 12
24
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
NOTES
1999 Jan 12
25
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
NOTES
1999 Jan 12
26
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
NOTES
1999 Jan 12
27
Philips Semiconductors – a worldwide company
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Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
295002/750/01/pp28
Date of release: 1999 Jan 12
Document order number: 9397 750 04632
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