TDA8765H/4 [NXP]
10-bit high-speed Analog-to-Digital Converter ADC; 10位高速模拟数字转换器ADC
| 型号： | TDA8765H/4 |
| 厂家： | 
NXP |
| 描述： | 10-bit high-speed Analog-to-Digital Converter ADC |
| 文件： | 总20页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8765
10-bit high-speed Analog-to-Digital
Converter (ADC)
1999 Jan 06
Preliminary specification
Supersedes data of 1998 May 08
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
FEATURES
APPLICATIONS
• 10-bit resolution
• High-speed analog-to-digital conversion for
– Video signal digitizing
• Sampling rate up to 55 MHz
• −3 dB bandwidth of 200 MHz
• 5 V power supplies
– High Definition TV (HDTV)
– Imaging (camera scanner)
– Medical imaging
• Binary or twos-complement CMOS outputs
• In-range CMOS-compatible output
• TLL- CMOS-compatible static digital inputs
• 3 to 5 V CMOS-compatible digital outputs
– Telecommunication
– Base-station receiver.
GENERAL DESCRIPTION
• Differential clock input; Positive Emitter Coupled Logic
(PECL) compatible
The TDA8765 is a bipolar 10-bit Analog-to-Digital
Converter (ADC) optimized for telecommunications and
professional imaging. It converts the analog input signal
into 10-bit binary coded digital words at a maximum
sampling rate of 55 MHz. All static digital inputs (SH, CE
and OTC) are TTL and CMOS compatible and all outputs
are CMOS compatible. A sine wave clock input signal can
also be used.
• Power dissipation 325 mW (typical)
• Low analog input capacitance (typical 2 pF), no buffer
amplifier required
• Integrated sample-and-hold amplifier
• Differential analog input
• External amplitude range control
• Voltage controlled regulator included.
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
CONDITIONS
MIN.
4.75
TYP.
5.0
MAX.
5.25
UNIT
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
integral non-linearity
differential non-linearity
maximum clock frequency
TDA8765H/4
V
VCCD
VCCO
ICCA
4.75
3.0
−
5.0
3.3
33
5.25
5.25
tbf
V
V
mA
mA
mA
LSB
LSB
ICCD
−
30
tbf
ICCO
fCLK = 4 MHz; fi = 400 kHz
fCLK = 4 MHz; fi = 400 kHz
fCLK = 4 MHz; fi = 400 kHz
−
3.2
±0.5
±0.3
tbf
INL
−
±1.75
±0.5
DNL
fCLK(max)
−
40
55
−
−
−
MHz
MHz
mW
TDA8765H/5
−
−
Ptot
total power dissipation
325
tbf
ORDERING INFORMATION
TYPE
PACKAGE
SAMPLING
NUMBER
FREQUENCY (MHz)
NAME
DESCRIPTION
VERSION
SOT307-2
TDA8765H/4
QFP44
plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10 × 10 × 1.75 mm
40
55
TDA8765H/5
1999 Jan 06
2
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
BLOCK DIAGRAM
V
V
V
V
V
V
CLK
35
CLK
36
OTC
18
CE
19
CCA1 CCA2
CCA3 CCA4
CCD1 CCD2
2
9
3
41
37 15
D9
21
MSB
TDA8765
CLOCK DRIVER
22 D8
23 D7
24 D6
11
V
ref
D5
25
26 D4
27
CMOS
OUTPUTS
data outputs
43
42
V
I
D3
28 D2
D1
ANALOG-TO-DIGITAL
CONVERTER
AMP
LATCHES
V
I
29
sample-
and-hold
30 D0
LSB
39
SH
33
V
CCO
1, 5 to 8,
12 to 14, 16, 31 and 32
OVERFLOW/
UNDERFLOW
LATCH
20
CMOS
OUTPUT
IR
n.c.
44
10
4
40
38
17
34
MGK801
AGND1 AGND2 AGND3 AGND4
DGND1 DGND2
OGND
Fig.1 Block diagram.
1999 Jan 06
3
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
PINNING
SYMBOL PIN
DESCRIPTION
not connected
SYMBOL PIN
DESCRIPTION
n.c.
1
2
3
4
5
6
7
8
9
D7
23 data output; bit 7
24 data output; bit 6
VCCA1
VCCA3
AGND3
n.c.
analog supply voltage 1 (+5 V)
analog supply voltage 3 (+5 V)
analog ground 3
D6
D5
25 data output; bit 5
26 data output; bit 4
27 data output; bit 3
28 data output; bit 2
29 data output; bit 1
30 data output; bit 0 (LSB)
31 not connected
D4
not connected
D3
n.c.
not connected
D2
n.c.
not connected
D1
n.c.
not connected
D0
VCCA2
AGND2
Vref
analog supply voltage 2 (+5 V)
n.c.
n.c.
VCCO
OGND
CLK
10 analog ground 2
11 reference voltage input
12 not connected
32 not connected
33 output supply voltage (3 to 5.25 V)
34 output ground
n.c.
n.c.
13 not connected
complementary clock input; active
35
LOW
n.c.
14 not connected
CLK
36 clock input
VCCD2
n.c.
15 digital supply voltage 2 (+5 V)
16 not connected
VCCD1
DGND1
SH
37 digital supply voltage 1 (+5 V)
38 digital ground 1
DGND2
OTC
17 digital ground 2
39 sample-and-hold enable input
(CMOS level; active HIGH)
control input twos complement
output; active HIGH
18
AGND4
VCCA4
VI
40 analog ground 4
CE
chip enable input
19
(CMOS level; active LOW)
41 analog supply voltage 4 (+5 V)
42 positive analog input voltage
43 negative analog input voltage
44 analog ground 1
IR
20 in-range output
D9
D8
21 data output; bit 9 (MSB)
22 data output; bit 8
VI
AGND1
1999 Jan 06
4
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
V
33
n.c.
1
2
CCO
V
V
32 n.c.
31 n.c.
CCA1
CCA3
3
D0
4
30
29 D1
28
AGND3
n.c.
5
TDA8765H
n.c.
6
D2
7
27 D3
26 D4
25 D5
24 D6
23 D7
n.c.
n.c.
8
V
9
CCA2
10
11
AGND2
V
ref
MGK800
Fig.2 Pin configuration.
1999 Jan 06
5
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN.
−0.3
MAX.
+7.0
UNIT
note 1
note 1
note 1
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
output supply voltage
supply voltage difference
−0.3
−0.3
+7.0
+7.0
V
V
V
CCA − VCCD
CCD − VCCO
CCA − VCCO
−1.0
−1.0
−1.0
0.3
+1.0
+4.0
+4.0
VCCA
VCCD
V
V
V
V
V
VI
input voltage at pins 42 and 43
referenced to AGND
Vi(p-p)
input voltage at pins 35 and 36 for
differential clock drive (peak-to-peak
value)
−
IO
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
0
+150
+85
150
−
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply
voltage differences ∆VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITION
in free air
VALUE
UNIT
thermal resistance from junction to ambient
75
K/W
1999 Jan 06
6
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
CHARACTERISTICS
V
V
CCA = V2 to V44, V9 to V10, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V;
CCO = V33 to V34 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to 85 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C, VI(p-p) − VI(p-p) = 2.0 V and CL = 10 pF; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
VCCD
VCCO
ICCA
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
4.75
5.0
5.25
5.25
5.25
45
V
4.75
3.0
−
5.0
3.3
33
V
V
mA
mA
mA
mA
ICCD
−
30
37
ICCO
fCLK = 4 MHz; fi = 400 kHz
−
3.2
11
tbf
fCLK = 40 MHz;
fi = 4.43 MHz
−
tbf
Inputs
CLK AND CLK (REFERENCED TO DGND)
VIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input impedance
VCCD = 5 V; note 1
VCCD = 5 V; note 1
VCLK or VCLK = 3.19 V
VCLK or VCLK = 3.83 V
fCLK = 40 MHz
3.19
3.83
−10
−
−
−
−
−
−
−
−
3.52
4.12
−
V
VIH
V
IIL
µA
µA
kΩ
pF
V
IIH
10
−
Zi
2
Ci
input capacitance
fCLK = 40 MHz
−
2
∆VCLK(p-p)
differential AC input voltage
DC voltage level = 2.5 V
0.5
2.0
for switching (VCLK − VCLK
;
peak-to-peak value)
OTC, SH AND CE (REFERENCED TO DGND); see Tables 2 and 3
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
0
−
−
−
−
0.8
VCCD
−
V
2.0
−20
−
V
VIL = 0.8 V
VIH = 2.0 V
µA
µA
IIH
20
VI AND VI (REFERENCED TO AGND; see Table 1); VREF = VCCA − 1.825 V
IIL
LOW-level input current
HIGH-level input current
input resistance
−
10
10
−
−
−
−
2
µA
µA
kΩ
pF
IIH
−
Ri
fi = 4.43 MHz
fi = 4.43 MHz
100
−
Ci
input capacitance
−
VI(CM)
common mode input voltage VI = VI; output code 511
V
V
CCA = 5 V
tbf
tbf
tbf
3.6
tbf
tbf
tbf
V
V
V
CCA = 4.75 V
3.35
3.85
VCCA = 5.25 V
1999 Jan 06
7
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Voltage controlled regulator input Vref (referenced to AGND); note 2
Vref
full-scale fixed voltage
VCCA = 5 V
−
−
3.175
2.0
−
V
VI(p-p) − VI(p-p) input voltage amplitude
Vref = VCCA − 1.825 V
−
V
(peak-to-peak value)
Iref
input current at Vref
−
0.5
10
µA
Outputs (referenced to OGND)
DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND)
VOL
VOH
Io
LOW-level output voltage
HIGH-level output voltage
output current in 3-state
IOL = 2 mA
0
−
−
−
0.5
V
IOH = −0.4 mA
V
CCO − 0.5
VCCO
+20
V
output level between 0.5 V −20
µA
and VCCO
Switching characteristics
CLOCK FREQUENCY fCLK; see Fig.5
fCLK(min)
minimum clock frequency
SH = HIGH
SH = LOW
−
−
−
−
1
1
MHz
kHz
fCLK(max)
maximum clock frequency
TDA8765H/4
40
−
−
−
−
−
−
−
−
MHz
MHz
ns
TDA8765H/5
55
tCLKH
tCLKL
clock pulse width HIGH
clock pulse width LOW
8.5
8.5
ns
Analog signal processing; 50% clock duty factor; VI − VI = 2.0 V; Vref = VCCA− 1.825 V; see Table 1
LINEARITY
INL
integral non-linearity
fCLK = 4 MHz; fi = 400 kHz
CLK = 4 MHz; fi = 400 kHz;
no missing code
VCCA = VCCD = VCCO = 5 V; tbf
amb = 25 °C; VI = VI;
output code = 511
gain error amplitude; spread VCCA = VCCD = VCCO = 5 V; −5
from device to device Tamb = 25 °C;
I(p-p) − VI(p-p) = 2.0 V
−
±0.5
±0.3
±1.75
±0.5
LSB
LSB
DNL
differential non-linearity
f
−
Eoffset
offset error
−11
tbf
+5
mV
T
EG
−
%FS
V
BANDWIDTH (fCLK = 55 MHz); note 3
B
analog bandwidth
−3 dB; full-scale input
tbf
200
−
MHz
1999 Jan 06
8
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
SYMBOL
HARMONICS (fCLK = 40 MHz)
Hfund(FS) fundamental harmonics
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fi = 4.43 MHz
−
−
0
dB
(full scale)
Htot(FS)
harmonics (full scale);
all components
fi = 4.43 MHz
second harmonic
third harmonic
−
−
−
−75
−70
−66
−
−
−
dB
dB
dB
THD
total harmonic distortion
fi = 4.43 MHz; note 4
grounded input;
THERMAL NOISE
Nth(rms)
thermal noise (RMS value)
−
0.2
tbf
LSB
fCLK = 40 MHz
SPURIOUS FREE DYNAMIC RANGE
DRsf
spurious free dynamic range fi = 4.43 MHz
tbf
tbf
tbf
71
68
67
−
−
−
dB
dB
dB
fi = 10 MHz
fi = 20 MHz
SIGNAL-TO-NOISE RATIO; note 5
S/N
signal-to-noise ratio
without harmonics;
fCLK = 40 MHz;
fi = 4.43 MHz
−
59
−
dB
EFFECTIVE NUMBER OF BITS; see Figs 3 and 4 and note 5
Nbit
effective number of bits
TDA8765H/4
(fCLK = 40 MHz)
fi = 4.43 MHz
fi = 10 MHz
fi = 15 MHz
fi = 4.43 MHz
fi = 10 MHz
fi = 15 MHz
fi = 20 MHz
9.0
−
9.6
9.6
9.5
9.6
9.4
9.3
9.1
−
−
−
−
−
−
−
bits
bits
bits
bits
bits
bits
bits
−
effective number of bits
TDA8765H/5
(fCLK = 55 MHz)
−
−
−
−
INTERMODULATION; note 6
TTIR
two-tone intermodulation
rejection
f
CLK = 40 MHz
tbf
tbf
66
67
−
−
dB
dB
d3
third-order intermodulation
distortion
fCLK = 40 MHz
BIT ERROR RATE
BER
bit error rate
fCLK = 40 MHz;
−
10−15
tbf
times/
fi = 4.43 MHz;
sample
VI = ±16 LSB at code 511
1999 Jan 06
9
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing (CL = 10 pF); see Fig.5 and note 7
td(s)
th
sampling delay time
output hold time
−
4
−
−
−
−
2
ns
−
ns
ns
ns
td
output delay time
VCCO = 5.25 V
CCO = 3.0 V
10
13
15
18
V
3-state output delay times; see Fig.6
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
−
−
−
14
16
16
14
18
20
20
18
ns
ns
ns
ns
Notes
1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:
a) PECL mode 1 (DC level varies equal to DC level of VCCD): CLK and CLK inputs are at differential PECL levels.
b) PECL mode 2 (DC level varies equal to DC level of VCCD): CLK input is at PECL level and sampling is taken on
the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
c) PECL mode 3 (DC level varies equal to DC level of VCCD): CLK input is at PECL level and sampling is taken on
the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with
a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.
2. It is possible with an external reference connected to pin Vref to adjust the ADC input range. This voltage has to be
referenced to VCCA. For VCCA − 1.825 V, the differential input voltage amplitude is 2 V (p-p).
3. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
full-scale sine wave.
4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
F
THD = 20 log---------------------------------------------------------------------------------------------------------------
2
2
2
2
2
(2nd) + (3rd) + (4th) + (5th) + (6th)
where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all
harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:
SNR = Nbit × 6.02 + 1.76 dB.
6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB
below full scale for each input signal).
d3 is the ratio of the RMS-value of either input tone to the RMS-value of the worst case third order intermodulation
product.
7. Output data acquisition: the output data is available after the maximum delay of td.
1999 Jan 06
10
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
Table 1 Output coding with differential inputs (typical values to AGND); Vi(p-p) − Vi(p-p) = 2.0 V; Vref = VCCA − 1.825 V
TWOS COMPLEMENT
BINARY OUTPUTS
OUTPUTS
CODE
Vi(p-p)
Vi(p-p)
IR
D9 TO D0
D9 TO D0
Underflow
<3.1
3.1
−
>4.1
4.1
−
0
1
1
↓
1
↓
1
1
0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1
↓
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 00
1 0 0 0 0 0 0 0 0 1
↓
0
1
↓
−
−
511
↓
3.6
−
3.6
−
0 1 1 1 1 1 1 1 1 1
↓
1 1 1 1 1 1 1 1 1 1
↓
1022
1023
Overflow
−
−
1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1
4.1
>4.1
3.1
<3.1
Table 2 Mode selection
OTC
CE
D0 TO D9 AND IR
0
1
X(1)
0
0
1
binary; active
twos complement; active
high impedance
Note
1. X = don’t care.
Table 3 Sample-and-hold selection
SH
SAMPLE-AND-HOLD
1
0
active
inactive; tracking mode
1999 Jan 06
11
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
MGL430
0
amplitude
(dB)
−20
−40
−60
−80
−100
−120
−140
−160
0
5
10
15
20
f (MHz)
Effective bits: 9.68; THD = −70.8 dB.
Harmonic levels (dB): 2nd = −80.3; 3rd = −74.5; 4th = −87.7; 5th = −76.4; 6th = −78.6.
Fig.3 Typical fast Fourier transform (fCLK = 40 MHz; fi = 4.43 MHz).
MGL431
0
amplitude
(dB)
−20
−40
−60
−80
−100
−120
−140
−160
0
5
10
15
20
25
f (MHz)
Effective bits: 9.12; THD = −62.5 dB.
Harmonic levels (dB): 2nd = −73.0; 3rd = −63.4; 4th = −80.9; 5th = −78.1; 6th = −74.4.
Fig.4 Typical fast Fourier transform (fCLK = 50 MHz; fi = 21.4 MHz).
1999 Jan 06
12
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
t
CLKL
t
CLKH
HIGH
50%
CLK
LOW
sample N
sample N + 1
sample N + 2
V
I
t
t
h
d(s)
HIGH
50%
DATA
D0 to D9
DATA
N − 2
DATA
N − 1
DATA
N
DATA
N + 1
LOW
t
d
MBH427
Fig.5 Timing diagram.
V
CCD
CE
50 %
0 V
t
t
dHZ
dZH
HIGH
90 %
output
data
50 %
LOW
t
t
dZL
dLZ
HIGH
output
data
50 %
LOW
10 %
TEST
S1
V
CCD
t
t
t
t
V
V
dLZ
dZL
dHZ
dZH
CCD
CCD
3.3 kΩ
15 pF
S1
TDA8765
DGND
DGND
CE
MBH423
fCE = 100 kHz.
Fig.6 Timing diagram and test conditions of 3-state output delay time.
13
1999 Jan 06
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
APPLICATION INFORMATION
220 nF
1 : 1
5 V
SH
mode
5 V
V
V
I
I
IN
100 nF
100 nF
100 Ω
100 Ω
CLK
(1)
CLK
V
CCA
5 V
R1
100 nF
44 43 42 41 40 39 38 37 36 35 34
n.c.
1
2
33
32
31
30
29
28
27
26
25
24
23
n.c
5 V
100 nF
R2
4.7 µF
10 nF
n.c.
D0 (LSB)
D1
3
4
n.c.
n.c.
n.c.
n.c.
5
6
TDA8765
D2
D3
7
D4
8
100 nF
5 V
9
D5
(3)
10
11
D6
100 nF
D7
V
ref
12 13 14 15 16 17 18 19 20 21 22
n.c.
n.c.
n.c.
IR
D8
n.c.
5 V
D9
(MSB)
MGK802
100 nF
chip select input
output format select
The analog, digital and output supplies should be separated and decoupled.
(1) Single-ended clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain a middle voltage of 3.6 V; see common mode input voltage.
In addition, the minimum current into these resistors should be about 1 mA in order to ensure a sufficient analog input stability.
(3) Vref must be decoupled to VCCA
.
Fig.7 Application diagram.
1999 Jan 06
14
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
y
X
A
33
23
34
22
Z
E
e
H
E
E
A
2
A
(A )
3
A
1
w M
θ
b
p
L
p
pin 1 index
L
12
44
detail X
1
11
w M
Z
v
M
A
D
b
p
e
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
10o
0o
0.25 1.85
0.05 1.65
0.40 0.25 10.1 10.1
0.20 0.14 9.9 9.9
12.9 12.9
12.3 12.3
0.95
0.55
1.2
0.8
1.2
0.8
mm
2.10
0.25
0.8
1.3
0.15 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT307-2
1999 Jan 06
15
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
If wave soldering is used the following conditions must be
observed for optimal results:
SOLDERING
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Jan 06
16
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Jan 06
17
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
NOTES
1999 Jan 06
18
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
NOTES
1999 Jan 06
19
Philips Semiconductors – a worldwide company
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/750/02/pp20
Date of release: 1999 Jan 06
Document order number: 9397 750 04716
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