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TDA8786AGB [NXP]

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TDA8786AGB
型号： TDA8786AGB
厂家： NXP    NXP
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INTEGRATED CIRCUITS  
DATA SHEET  
TDA8786; TDA8786A  
10-bit analog-to-digital interface for  
CCD cameras  
1997 Nov 17  
Product specification  
Supersedes data of 1997 May 20  
File under Integrated Circuits, IC02  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
FEATURES  
GENERAL DESCRIPTION  
• Correlated Double Sampling (CDS), AGC, soft clipper,  
pre-blanking, 10-bit ADC and reference regulator  
included  
The TDA8786; TDA8786A is a 10-bit analog-to-digital  
interface for CCD cameras. The device includes a  
correlated double sampling circuit, AGC, a soft clipper  
circuit and a low power 10-bit Analog-to-Digital Converter  
(ADC) together with its reference voltage regulator.  
• Fully programmable via a 3-wire serial interface  
• Sampling frequency up to 18 MHz  
The AGC and soft clipper circuits are controlled by on-chip  
DACs via a serial interface.  
• AGC gain from 3.5 to 33.5 dB (in 0.1 dB steps)  
• Programmable soft clipper for white compression  
A 10-bit DAC controls the ADC input clamp level.  
A pre-blanking function is also included.  
(starting at 40% of the input signal)  
• Standby mode available for each block for power saving  
applications (19 mW)  
An additional DAC is provided for additional system  
controls; its output voltage range is 1.4 V (p-p) which is  
available at pin OFDOUT.  
• 6 dB fixed gain analog output for analog iris control  
• 8-bit and 10-bit DAC included for analog settings  
• Low power consumption of only 475 mW (typ.)  
APPLICATIONS  
• 5 V operation and 2.5 to 5 V operation for the digital  
outputs  
• CCD camera systems.  
• CDS control pulse: TDA8786 = HIGH;  
TDA8786A = LOW  
• TTL compatible inputs, TTL and CMOS compatible  
outputs.  
QUICK REFERENCE DATA  
SYMBOL  
VCCA  
PARAMETER  
analog supply voltage  
CONDITIONS  
MIN.  
4.5  
TYP. MAX. UNIT  
4.75  
4.75  
2.6  
83  
5.5  
5.5  
5.5  
−
V
VCCD  
VCCO  
ICCA  
digital supply voltage  
4.5  
2.5  
−
V
digital outputs supply voltage  
analog supply current  
V
mA  
mA  
mA  
ICCD  
ICCO  
digital supply current  
−
16  
−
digital outputs supply current  
fCLK = 18 MHz;  
CL = 20 pF; ramp input  
−
1
−
ADCres  
Vi(CDS)(p-p)  
GCDS  
ADC resolution  
−
10  
400  
6
−
bits  
CDS input voltage (peak-to-peak value)  
CDS output amplifier gain  
maximum clock frequency  
AGC dynamic range  
−
1200 mV  
−
−
−
−
−
dB  
fCLK(max)  
AGCdyn  
Ntot(rms)  
18  
−
−
MHz  
dB  
30  
0.5  
total noise from CDS input to ADC  
output (RMS value)  
gain = 3.5 dB  
−
LSB  
Ptot  
total power consumption  
−
475  
−
mW  
ORDERING INFORMATION  
TYPE  
PACKAGE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
TDA8786G  
LQFP48  
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm  
SOT313-2  
TDA8786AG  
1997 Nov 17  
2
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
BLOCK DIAGRAM  
V
V
CCA3  
45  
DGND2  
40  
CCO  
V
IN2 IN1 AGND3  
47  
46 48  
CDSP2  
44  
CDSP1  
43  
CLPCDS  
42  
CLK  
41  
CCD2  
39  
OE  
38  
37  
36  
OGND  
TRACK-  
AND-HOLD  
TRACK-  
AND-HOLD  
TRACK-  
AND-HOLD  
CLOCK  
GENERATOR  
35  
34  
33  
32  
31  
30  
29  
28  
27  
TRACK-  
AND-HOLD  
TRACK-  
AND-HOLD  
D9  
D8  
19  
5
STGE  
CLAMP  
CLAMP  
AGND1  
ref2  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
TDA8786  
TDA8786A  
4
2
+
6 dB  
AMPOUT  
PBK  
OUTPUTS  
BUFFER  
10-BIT ADC  
7
1
SOFT  
CLIPPER  
AGCOUT  
CLPOPB  
1
AGC  
ref1  
OPTICAL  
BLACK  
CLAMP  
8
6
9-BIT DAC  
4-BIT DAC  
PBIN  
V
CCA1  
9
PBOUT  
ADCIN  
1
10  
26  
25  
3
D0  
DGND1  
OFDOUT  
10-BIT DAC  
8-BIT DAC  
SERIAL  
INTERFACE  
REGULATOR  
11  
CLPADC  
CLAMP  
14  
15  
16 17 18  
22  
STDBY SEN  
21  
20  
24  
12  
13  
23  
MGE361  
V
V
DACOUT  
CCA2  
V
SDATA  
SCLK  
CCD1  
RT  
V
AGND2  
V
DEC1  
ref  
RB  
Fig.1 Block diagram.  
3
1997 Nov 17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
PINNING  
SYMBOL  
PIN  
DESCRIPTION  
CLPOPB  
PBK  
1
2
optical black clamp control pulse input (active HIGH for TDA8786, active LOW for TDA8786A)  
pre-blanking control pulse input; if PBK is HIGH (LOW) the signal is replaced by the optical  
black level for TDA8786 (TDA8786A)  
OFDOUT  
AMPOUT  
AGND1  
VCCA1  
3
4
analog output of the additional 8-bit control DAC (controlled via the serial interface)  
CDS amplifier output (fixed gain = +6 dB)  
5
analog ground 1  
6
analog supply voltage 1  
AGCOUT  
PBIN  
7
AGC and soft clipper amplifier signal output  
8
optical black clamp and pre-blanking block signal input (from AGCOUT via a capacitor)  
optical black clamp and pre-blanking block signal output  
ADC analog signal input (from PBOUT or AGCOUT via a capacitor)  
PBOUT  
ADCIN  
9
10  
11  
CLPADC  
clamp control input for ADC analog input signal clamp (active HIGH for TDA8786 and active  
LOW for TDA8786A)  
Vref  
12  
13  
14  
15  
16  
17  
18  
19  
20  
ADC input clamp reference voltage (normally connected to pin VRB or DACOUT)  
DAC output for ADC clamp level  
DACOUT  
AGND2  
VCCA2  
VRB  
analog ground 2  
analog supply voltage 2  
ADC reference voltage (BOTTOM) code 0  
ADC reference voltage (TOP) code 1023  
decoupling 1 (decoupled to ground via a capacitor)  
CDS offset storage  
VRT  
DEC1  
STGE  
SDATA  
serial data input for the 4 control DACs (9-bit DAC for AGC gain, 4-bit DAC for soft clipper;  
additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the stand-by  
mode per block; see Table 1)  
SCLK  
SEN  
STDBY  
VCCD1  
DGND1  
D0  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
serial clock input for the control DACs and their serial interface; see Table 1  
enable input for the serial interface shift register (active when SEN = logic 0); see Table 1  
stand-by control pin (active HIGH); all the output bits are logic 0 when stand-by is enabled  
digital supply voltage 1  
digital ground 1  
ADC digital output 0 (LSB)  
ADC digital output 1  
ADC digital output 2  
ADC digital output 3  
ADC digital output 4  
ADC digital output 5  
ADC digital output 6  
ADC digital output 7  
ADC digital output 8  
ADC digital output 9 (MSB)  
digital output ground  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
OGND  
1997 Nov 17  
4
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
SYMBOL  
VCCO  
PIN  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
DESCRIPTION  
digital output supply voltage  
OE  
output enable (LOW: digital outputs active; HIGH: digital outputs high impedance)  
digital supply voltage 2  
VCCD2  
DGND2  
CLK  
digital ground 2  
ADC clock input  
CLPCDS  
CDSP1  
CDSP2  
VCCA3  
IN1  
CDS clamp control input (active HIGH for TDA8786; active LOW for TDA8786A)  
CDS control pulse input 1 (active HIGH for TDA8786; active LOW for TDA8786A)  
CDS control pulse input 2 (active HIGH for TDA8786; active LOW for TDA8786A)  
analog supply voltage 3  
input signal 1 from CCD (usually black channel)  
input signal 2 from CCD (usually video channel)  
analog ground 3  
IN2  
AGND3  
1
2
36 OGND  
35  
CLPOPB  
PBK  
D9  
34 D8  
33  
OFDOUT  
AMPOUT  
AGND1  
3
4
D7  
5
32 D6  
31 D5  
6
V
CCA1  
TDA8786  
TDA8786A  
AGCOUT  
PBIN  
7
D4  
30  
29 D3  
D2  
8
PBOUT  
ADCIN  
9
28  
27 D1  
26  
10  
11  
12  
CLPADC  
D0  
V
25 DGND1  
ref  
MGE360  
Fig.2 Pin configuration.  
5
1997 Nov 17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
VCCA  
PARAMETER  
analog supply voltage  
CONDITIONS  
note 1  
MIN.  
−0.3  
MAX.  
+7.0  
UNIT  
V
V
V
VCCD  
VCCO  
∆VCC  
digital supply voltage  
output stages supply voltage  
supply voltage difference  
between VCCA and VCCD  
between VCCA and VCCO  
between VCCD and VCCO  
input voltage  
note 1  
note 1  
−0.3  
−0.3  
+7.0  
+7.0  
−1.0  
−1.0  
−1.0  
−0.3  
−
+1.0  
+4.0  
+4.0  
+7.0  
VCCD  
V
V
V
V
V
Vi  
referenced to VSSA  
referenced to VSSD  
VCLK(p-p)  
AC input voltage for switching  
(peak-to peak-value)  
Io  
output current  
−
10  
mA  
°C  
°C  
°C  
Tstg  
Tamb  
Tj  
storage temperature  
operating ambient temperature  
junction temperature  
−55  
−20  
−
+150  
+75  
150  
Note  
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply  
voltage difference ∆VCC remains as indicated.  
HANDLING  
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is  
desirable to take normal precautions appropriate to handling integrated circuits.  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
in free air  
VALUE  
UNIT  
Rth(j-a)  
thermal resistance from junction to ambient  
76  
K/W  
1997 Nov 17  
6
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
CHARACTERISTICS  
VCCA = VCCD = 4.75 V; VCCO = 2.6 V; fCLK = 18 MHz; Tamb = 25 °C; unless otherwise specified.  
SYMBOL  
Supplies  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
VCCA  
VCCD  
VCCO  
analog supply voltage  
digital supply voltage  
4.5  
4.5  
2.5  
4.75  
5.5  
5.5  
5.5  
V
4.75  
2.6  
V
V
digital outputs supply  
voltage  
ICCA  
ICCD  
ICCO  
analog supply current  
digital supply current  
−
−
−
83  
16  
1
−
−
−
mA  
mA  
mA  
digital outputs supply  
current  
CL = 20 pF on all data  
outputs; ramp input  
Digital inputs  
CLOCK INPUT: CLK (REFERENCED TO DGND)  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
input impedance  
0
−
−
−
−
2
2
0.8  
VCCD  
+1  
20  
−
V
2.0  
−1  
−
V
VCLK = 0.8 V  
VCLK = 2.0 V  
fCLK = 18 MHz  
fCLK = 18 MHz  
µA  
µA  
kΩ  
pF  
IIH  
Zi  
−
Ci  
input capacitance  
−
−
INPUTS: CDSP1 AND CDSP2  
VIL  
VIH  
IIL  
LOW-level input voltage  
0
−
0.6  
VCCD  
−
V
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
2.2  
−
−
V
VIL = 0.6 V  
VIH = 2.2 V  
−100  
µA  
µA  
IIH  
−
0
−
INPUTS: SEN, STDBY, CLPCDS, CLPOPB, PBK AND CLPADC  
VIL  
VIH  
Ii  
LOW-level input voltage  
HIGH-level input voltage  
input current  
0
−
−
−
0.6  
V
2.2  
−2  
VCCD  
+2  
V
µA  
INPUTS: SEN, SDATA AND SCLK (see Fig.14)  
tsu1  
SEN set-up time compared  
to SCLK rising edge  
−
−
4
4
−
−
ns  
ns  
tsu2  
SDATA set-up time  
compared to SCLK rising  
edge  
tsu3  
thd3  
thd4  
SEN set-up time compared  
to SCLK falling edge  
−
−
−
4
4
4
−
−
−
ns  
ns  
ns  
SEN hold time compared  
to SCLK rising edge  
SDATA hold time  
compared to SCLK rising  
edge  
1997 Nov 17  
7
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Correlated Double Sampling; CDS  
Vi(CDS)(p-p)  
ISTGE,IN1,IN2  
tCDS(min)  
CDS input amplitude  
(peak-to-peak value)  
−
400  
−
1200  
+2  
mV  
input current pins 19, 46  
and 47  
−2  
12  
µA  
CDS control pulses  
minimum active time  
(HIGH for TDA8786,  
LOW for TDA8786A)  
f
i(CDS1,2) = fCLK(pix)  
−
−
ns  
Vi(CDS)(p-p) = 1200 mV  
black-to-white transition in  
one pixel (±1 LSB typ.)  
thd1  
thd2  
hold time IN1 compared to see Fig.15  
control pulse CDSP1  
−
−
1
−
−
ns  
ns  
hold time of IN2 compared see Fig.15  
to control pulse CDSP2  
−0.5  
Amplifier outputs  
GAMPOUT output amplifier gain  
ZAMPOUT  
−
−
6
−
−
dB  
output amplifier  
impedance  
300  
Ω
VAMPOUT(p-p) output amplifier dynamic  
voltage level  
−
2.4  
−
V
(peak-to-peak value)  
VAMPOUT(bl)  
output amplifier black  
level voltage  
−
−
1.1  
−
−
V
VAGCOUT(p-p) AGC output amplifier  
dynamic voltage level  
1800  
mV  
(peak-to-peak value)  
VAGCOUT  
ZAGCOUT  
IAGCOUT  
VOPB(p-p)  
AGC output amplifier black  
level voltage  
−
−
−
−
1.1  
5
−
−
1
−
V
AGC output amplifier  
output impedance  
at 10 kHz  
static  
Ω
AGC output static drive  
current  
−
mA  
V
optical black clamp and  
blanking block output  
dynamic voltage  
1.8  
(peak-to-peak value)  
VOPB  
optical black clamp and  
blanking block output black  
level voltage  
−
−
1.4  
−
V
ZOPB  
optical black clamp and  
blanking block output  
impedance  
at 10 kHz  
static  
−
5
Ω
IOPB  
OPB output current drive  
input current pin 8  
−
−
1
mA  
µA  
dB  
IPBIN  
−2  
−
−
+2  
−
GAGC(min)  
minimum gain of AGC  
circuit  
AGC DAC input code = 00  
(9-bit control)  
3.5  
1997 Nov 17  
8
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
SYMBOL  
PARAMETER  
CONDITIONS  
AGC DAC input  
MIN.  
TYP.  
33.5  
MAX.  
UNIT  
dB  
GAGC(max)  
maximum gain of AGC  
circuit  
−
−
−
−
−
code = ≥319 (9-bit control)  
VAGCOUT  
Vinflex(p-p)  
AGC output amplifier black  
level voltage  
1.1  
−
−
−
V
V
V
voltage at soft clipper  
inflexion point  
(peak-to-peak value)  
soft clipper 4-bit control  
DAC input code = 00  
40%  
VAGCOUT(p-p)  
soft clipper 4-bit control  
DAC input code = 15  
100%  
VAGCOUT(p-p)  
CRsc  
soft clipper compression  
ratio  
Vi(sc) < Vinflex  
−
−
1.0  
−
−
Vi(sc) > Vinflex  
0.66  
CLAMPS  
gmADC  
ADC clamps  
transconductance  
at clamp level  
at clamp level  
at clamp level  
−
−
−
−
60  
−
−
−
−
mS  
mS  
mS  
V
gmPBK  
PBK clamp  
transconductance  
60  
gmCDS  
CDS clamps  
transconductance  
5.5  
1.4  
VPBIN(clamp)  
clamp voltage  
at PBIN input  
Analog-to-Digital Converter; ADC  
fCLK(max)  
tCPH  
maximum clock frequency  
clock pulse width HIGH  
clock pulse width LOW  
18  
15  
15  
0.5  
−
−
−
−
−
−
−
−
MHz  
ns  
tCPL  
ns  
SRCLK  
clock input slew rate  
10 to 90%  
V/ns  
(rising and falling edge)  
Vi(ADC)(p-p)  
VRB  
ADC input voltage level  
(peak-to-peak value)  
−
−
−
1.8  
1.4  
3.2  
−
−
−
V
V
V
ADC reference voltage  
output code 0  
VRT  
ADC reference voltage  
output code 1023  
IADCIN  
ILE  
input current pin 10  
integral linearity error  
differential linearity error  
sampling delay time  
−2  
−
−
+2  
µA  
f
CLK = 18 MHz; ramp input  
CLK = 18 MHz; ramp input  
±1.0  
±0.4  
−
±2.0  
LSB  
DLE  
td(s)  
f
−
±0.75 LSB  
5 ns  
−
1997 Nov 17  
9
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Total chain timing (CDS + ADC + SOFT CLIPPER + PRE BLANKING + ADC)  
td  
time delay between  
CDSP1 and CLK  
50% at rising edges of  
CLK and CDSP1:  
−
40  
−
ns  
transition full-scale code 0  
to code 1023;  
Vi(CDS)(p-p) = 1200 mV  
N(rms)  
noise (RMS value)  
gain = 3.5 dB  
−
−
0.5  
1.4  
−
−
LSB  
V
Digital-to-Analog Converters (OFDOUT DAC)  
VOFDOUT(p-p) additional 8-bit control  
DAC (OFD) output voltage  
(peak-to-peak value)  
VOFDOUT(0)  
DC output voltage for  
code 0  
−
−
−
2.0  
3.4  
−
−
−
V
V
Ω
VOFDOUT(255) DC output voltage for  
code 255  
ZOFDOUT  
additional 8-bit control  
DAC (OFD) output  
impedance  
2000  
IOFDOUT  
OFD output current drive  
static  
−
−
−
50  
µA  
ADC clamp control DAC (see Fig.5)  
VDACOUT(p-p) ADC clamp 10-bit control  
DAC output voltage  
0.9  
−
V
(peak-to-peak value)  
VDACOUT  
DC output voltage  
code 0  
−
−
−
1.4  
2.3  
−
−
V
V
Ω
code 1023  
−
ZDACOUT  
ADC clamp control DAC  
output impedance  
250  
IDACOUT  
DAC output current drive  
static  
−
−
−
−
50  
−
µA  
OFELOOP  
maximum offset error of  
DAC + ADC clamp loop  
code 0  
± 5  
± 5  
LSB  
LSB  
code 1023  
−
1997 Nov 17  
10  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Digital outputs (fCLK = 18 MHz; CL = 20 pF)  
VOH  
VOL  
IOZ  
HIGH-level output voltage IOH = −1 mA  
LOW-level output voltage IOL = 1 mA  
V
0
CCO − 0.5  
−
−
−
VCCO  
0.5  
V
V
output current in 3-state  
mode  
0.5 V < Vo < VCCO  
−20  
+20  
µA  
to(h)  
to(d)  
output hold time  
output delay  
5
−
−
−
−
−
ns  
ns  
ns  
ns  
Ci = 20 pF; VCCO = 4.75 V  
Ci = 20 pF; VCCO = 3.15 V  
Ci = 20 pF; VCCO = 2.7 V  
12  
17  
21  
15  
20  
24  
Serial interface  
fSCLK(max)  
maximum frequency of  
serial interface  
5
−
−
MHz  
MGE365  
handbook, halfpage  
33.5  
G
AGC  
(dB)  
3.5  
0
319  
511  
AGC control DAC input code  
Fig.3 AGC gain as a function of DAC input code.  
1997 Nov 17  
11  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
AGCOUT  
MGE364  
control DAC  
input code = 15  
100%  
control DAC  
input code = 00  
(1)  
(2)  
40%  
0
0
40%  
100%  
130%  
soft clipper input  
Vo  
(1)  
(2)  
= 1  
------  
Vi  
V o  
= 0.66  
------  
V i  
Fig.4 Soft clipper output voltage as a function of soft clipper input voltage.  
MGE366  
MGD599  
handbook, halfpage  
handbook, halfpage  
2.3  
3.4  
ADC CLAMP DAC  
OFD DAC  
voltage  
output  
(V)  
voltage  
output  
(V)  
2.0  
1.4  
1023  
255  
0
0
ADC CLAMP control DAC input code  
OFD control DAC input code  
Fig.5 DAC voltage output as a function of DAC input code.  
12  
1997 Nov 17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
8 × f  
= 2f  
CLK  
SC  
>12 ns  
CDSP1  
CDSP2  
>12 ns  
MGE370  
Fig.6 CCD high band control signal timing (TDA8786).  
8 × f  
= 3f  
CLK  
SC  
>12 ns  
CDSP1  
>12 ns  
CDSP2  
MGE369  
Fig.7 CCD normal band control signal timing (TDA8786).  
13  
1997 Nov 17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
8 × f  
= 2f  
CLK  
SC  
CDSP1  
CDSP2  
>12 ns  
MGE371  
>12 ns  
Fig.8 CCD high band control signal timing (TDA8786A).  
8 × f  
= 3f  
CLK  
SC  
CDSP1  
>12 ns  
CDSP2  
MGE372  
>12 ns  
Fig.9 CCD normal band control signal timing (TDA8786A).  
14  
1997 Nov 17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
I
I
handbook, halfpage  
handbook, halfpage  
PBIN  
(µA)  
(µA)  
450  
350  
0
0
1.4  
V
(V)  
2.85  
V (V)  
PBIN  
−450  
−350  
MBK058  
MBK057  
30 mV  
200 mV  
Fig.11 Typical clamp currents for pins IN1, IN2 and  
STGE.  
Fig.10 Typical PBK clamp current.  
ADC clamping  
When pin CLPADC is HIGH (TDA8786) (LOW for  
TDA8786A), the ADC input is clamped to voltage level Vref.  
Vref should normally be connected to VRB (ADC reference  
voltage code 0) or to DACOUT (10-bit DAC output).  
The DAC is controlled via the serial interface, its output  
covers the lower half of the ADC input range.  
I
handbook, halfpage  
ADCIN  
(µA)  
slope = 1 kΩ  
450  
V
ref  
0
V
(V)  
ADCIN  
−450  
30 mV  
MBK059  
500 mV  
Fig.12 Typical ADC clamp current.  
1997 Nov 17  
15  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
SDATA  
SCLK  
SHIFT REGISTER  
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 A0 A1 A2  
LSB MSB  
10  
LATCH  
SEN  
SELECTION  
8
9
4
4
10  
(D7 to D0)  
(D8 to D0)  
(D3 to D0)  
(D3 to D0)  
(D9 to D0)  
CLAMP  
REFERENCE  
LATCHES  
PARTIAL  
STANDBY  
OFD  
LATCHES  
SOFT CLIP  
LATCHES  
AGC GAIN  
LATCHES  
8-bit DAC  
AGC control  
soft clip  
control  
standby  
control  
10-bit DAC  
MGD526  
Fig.13 Serial interface block diagram.  
t
SDATA  
su2  
t
hd4  
MSB  
A0  
LSB  
D3  
A2  
A1  
D9  
D8  
D7  
D6  
D5  
D4  
D2  
D1  
D0  
SCLK  
SEN  
MGE373  
t
t
hd3  
su1  
t
su3  
tsu = 4 ns (min.); thd3 = thd4 = 4 ns (min.).  
Fig.14 Loading sequence of control DACs input data via the serial interface.  
16  
1997 Nov 17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
Table 1 Serial interface programming (see note 1)  
ADDRESS BITS  
DATA BITS D9 to D0  
OFDOUT output control (D7 to D0).  
A2  
A1  
A0  
0
0
0
0
0
1
Soft clipper control. Only the 4 LSBs (D3 to D0) are used. Bits D9 to D4 should be set to  
logic 0.  
0
0
1
1
0
1
AGC gain control (D8 to D0).  
Partial standby controls for power consumption optimization. Only the 4 LSBs (D3 to D0)  
are used. Bits D9 to D4 should be set to logic 0:  
D0 = 1: CDS + AGC + soft clipper block in standby; ICCA + ICCD = 48 mA  
D1 = 1: optical black clamp + blanking block in standby; ICCA + ICCD = 92 mA  
D2 = 1: OFD DAC in standby; ICCA + ICCD = 98 mA  
D3 = 1: 6 dB amplifier (output on AMPOUT pin) in standby; ICCA + ICCD = 98.5 mA.  
Clamp reference DAC (D9 to D0).  
1
0
0
Note  
1. At the end of each programming sequence (usually during the video vertical blanking), the soft clipper register must  
be reloaded (for example if the soft clipper is not used, code 15 must be entered in the soft clipper register at the end  
of each TDA8786(A) programming sequence).  
Table 2 Standby selection  
STDBY  
D9 to D0  
ICCA + ICCD  
1
0
LOW  
4 mA (typ.)  
active  
99 mA (typ.)  
1997 Nov 17  
17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
t
hd1  
IN1 and IN2  
PIXEL  
N
PIXEL  
N + 1  
PIXEL  
N + 2  
PIXEL  
N + 3  
PIXEL  
N + 4  
CDSP1  
(active HIGH)  
t
hd2  
sample N  
CDSP2  
(active HIGH)  
t
d
CLK  
t
h
DATA  
PIXEL N − 4  
PIXEL N − 3  
PIXEL N − 2  
PIXEL N − 1  
PIXEL N  
OUTPUT  
D0 to D7  
t
MGE367  
d (OUT)  
The hatched areas represent active video.  
Fig.15 Pixel frequency timing diagram.  
AGCOUT  
VIDEO  
OPTICAL BLACK  
HORIZONTAL FLYBACK  
DUMMY  
VIDEO  
CLPCDS  
(active HIGH)  
CLPOPB  
(active HIGH)  
PBK  
(active HIGH)  
PRE-  
BLANKING  
OUTPUT  
VIDEO  
BLACK LEVEL  
VIDEO  
CLPADC  
(active HIGH)  
MGE368  
Fig.16 Line frequency timing diagram.  
18  
1997 Nov 17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
APPLICATION INFORMATION  
TDA8786 and SAA8110 can be used with Sharp CCDs. TDA8786A and SAA8110 can be used with Sony CCDs. Table 3  
gives as an example some references of ICs which may be used with Philips TDA8786(A)/SAA8110. This overview is  
not restrictive, both devices are compatible with other CCD/V-driver/PPG combinations including the more recent ones.  
Table 3 Possible components for the application of Figs 17 and 18  
NTSC  
PAL  
COMPONENT  
TYPE  
CCD TYPE  
MEDIUM  
HIGH  
MEDIUM  
RESOLUTION  
HIGH  
RESOLUTION  
RESOLUTION  
RESOLUTION  
Sony CCDs  
CCD  
LZ2313H5  
LZ2353A  
LZ2323H5  
LZ2363  
V-driver  
LR36683N  
timing generator  
CCD  
LZ95G55  
LZ95G71  
LZ95G55  
LZ95G71  
Sharp CCDs  
ICX056AK  
ICX068AK  
ICX057AK  
ICXo69AK  
V-driver  
CXD1250MN, CXD1267N  
CXD1265R CXD1257AR  
timing generator  
CXD1257AR  
CXD1265R  
Notes to the application diagram  
1. In the configuration of Figs 17 and 18, the microcontroller reads and writes data from/to the DSP using the  
SNERT-bus (UART mode 0). Optional external control is available via the I2C-bus.  
2. Free I/O pins of the microcontroller can be used to control PGG, or for other purposes.  
3. 83Cxxx processing is synchronized by VD interruption. Depending on VD polarity, it can be necessary to invert VD.  
4. A customized 83Cxxx is available for this application. Please contact your nearest Philips sales office.  
1997 Nov 17  
19  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
P0  
P1  
P0 (optional, PPG setting)  
P1 (optional, PPG settings)  
CDAC  
CDAC (optional, can be used for frequency tuning)  
OUT  
OUT  
CLK1  
CLK1 (to ADC and DSP)  
CLK2 (to DSP, CLK2 = 2 × CLK1)  
CDSPULSE1  
CLK2  
CDSPULSE1  
CDSPULSE2  
CLAMPCDS  
CLAMPOPB  
CLAMPADC  
PreBlank  
CDSPULSE2  
VERTICAL DRIVER  
CLAMPCDS (CLAMP CDS, OPB, ADC can be the same)  
CLAMPOPB  
(PPG)  
digital ground  
CLAMPADC  
analog ground  
PreBlank (optional)  
Horizontal Drive  
Vertical Drive  
Field Id  
HD (to DSP and µC)  
VD (to DSP and µC)  
CLK1  
FI (to DSP and µC)  
CLAMPCDS  
CDSPULSE1  
CDSPULSE2  
Electrical Reset  
Shutter Pulse  
V4  
V3 V2 V1  
VERTICAL  
H1  
H1  
H2  
100 nF  
V
V
DDA1  
DDA1  
100 nF  
DRIVER BUFFER  
OEN (optional)  
(from microcontroller)  
DDD  
1 µF  
Reset  
V4 V3 V2 V1  
H2  
Shutter  
V
CCDout  
CCD  
OFD level  
(optional)  
100 nF  
CLAMPOPB  
PreBlank  
48 47 46 45 44 43 42 41 40 39 38 37  
CLPOPB  
PBK  
OGND  
36  
1
D9  
−xxV  
+xxV  
100 nF  
2
A
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
D8  
OFDOUT  
AMPOUT  
AGND1  
SWITCH MODE  
POWER SUPPLIES  
(optional)  
3
SMP_CLK  
(from DSP)  
B
C
D
E
F
G
H
I
D7  
ANALOG-TO-DIGITAL INTERFACE  
AMPOUT  
100 nF  
4
V
D6  
DDA1  
5
V
D5  
CCA1  
6
V
DDD  
D4  
AGCOUT  
PBIN  
5 V  
5 V  
5 V  
V
V
V
DDA1  
DDA2  
DDA3  
7
TDA8786G  
or  
TDA8786AG  
D3  
8
220 nF  
220 nF  
D2  
PBOUT  
ADCIN  
9
D1  
10  
11  
12  
D0  
CLPADC  
J
V
DGND1  
ref  
13 14 15 16 17 18 19 20 21 22 23 24  
K
10 kΩ  
VD (from PPG)  
BC848C  
CLAMPADC  
(from PPG)  
100 nF  
10 µF  
1 nF  
V
V
V
DDD  
P1.0  
DDD  
DD  
10 kΩ  
2
3
4
5
6
7
8
9
V
DDD  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
P0.0/AD0  
P0.1/AD1  
P0.2/AD2  
P0.3/AD3  
P0.4/AD4  
P0.5/AD5  
P0.6/AD6  
P0.7/AD7  
EA  
P1.1  
P1.2  
V
DDA1  
V
SDA  
5
SS  
MICRO-  
CONTROLLER  
100  
nF  
4
EPROM  
P1.3  
SCL  
A2  
OEN (optional)  
(to ADC)  
6
7
8
3
PCF8598  
PCF8594  
PCF8582  
P1.4  
PTC  
NC  
2
V
DDD  
4.7  
4.7  
kΩ  
L
V
P1.5  
DD  
WP  
kΩ  
1
M
P1.6/SCL  
P1.7/SDA  
1
nF  
1
nF  
2.2  
nF  
200  
nF  
V
V
V
100 nF  
DDD  
DDD DDD  
4.7 µF  
RST  
V
10  
11  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
DDD  
P3.0/RxD  
83C54/  
83C654  
(OM-XXX)  
V
DDD  
P3.1/TxD  
P3.2/INT0  
P3.3/INT1  
P3.4/T0  
ALE  
PSEN  
P2.7/A15  
P2.6/A14  
P2.5/A13  
P2.4/A12  
P2.3/A11  
P2.2/A10  
P2.1/A9  
P2.0/A8  
A0/SN  
DA  
SCL/SN  
RESET_DSP  
(to DSP)  
CL  
P3.5/T1  
HD (opt.)  
P3.6/WR  
FI  
IN  
P3.7/RD  
XTAL2  
XTAL1  
A1/SN  
RES  
18 pF  
V
12 MHz  
SS  
MGK393  
18 pF  
Fig.17 SAA8110G system configuration for camera application (continued in Fig.18).  
20  
1997 Nov 17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
26  
24  
22  
20  
18  
16  
14  
12  
10  
8
25  
23  
21  
19  
17  
15  
13  
11  
9
A1/SN  
RES  
A0/SN  
DA  
SDA  
SCL/SN  
CL  
V
DDD  
100  
nF  
7
V
6
5
DDD  
100 nF  
optional  
4
3
2
1
V
V
DDD  
DDD  
V
DDD  
100 nF  
V
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
DDD(C1)  
CLK1  
UV1  
UV2  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
CLK1  
2
VSYNC  
HSYNC  
IN  
IN  
UV3  
UV4  
UV5  
UV6  
3
VD  
HD  
4
FI  
IN  
FI  
5
V
SSD(C1)  
CCD9  
CCD8  
CCD7  
CCD6  
CCD5  
CCD4  
CCD3  
CCD2  
CCD1  
CCD0  
DIGITAL SIGNAL PROCESSOR  
6
UV7  
V
7
A
SSD(P1)  
8
B
C
D
E
F
G
H
I
LLC  
9
CREF/PXQ  
HREF  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
SAA8110G  
VSYNC  
OUT  
FI  
OUT  
CLK2  
CLK2 (from PPG)  
V
V
DDD(P1)  
V
DDD  
V
DDA(BG)  
J
DDA3  
100 nF  
V
V
47 kΩ  
RBIAS  
SSD(C2)  
SCLK  
100 nF  
DECOUPL  
K
V
SSA(CD)  
SSA(BG)  
100 nF  
V
CDAC  
OUT  
DDA(DC)  
V
DDA3  
100 nF  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
CDAC  
OUT  
3
4
1 6  
5
10 nF  
SVHS  
7
2
L(1)  
L(1)  
Y
68 Ω  
L(1)  
150 kΩ  
V
V
DDA3  
DDA3  
6
100  
nF  
100 nF  
Green  
C
1
11  
7
100 nF  
100 nF  
V
2
3
4
5
12  
13  
14  
15  
DDA2  
8
V
L(1)  
L(1)  
DDD  
L
68 Ω  
L(1)  
9
M
RESET_DSP  
(from µC)  
10  
SMP_CLK (to power supply)  
U, Blue  
V, Red  
P0  
P1  
V
DDD  
L(1)  
L(1)  
68 Ω  
L(1)  
digital ground  
analog ground  
CVBS-RCA  
CVBS  
MGK394  
(1) Values depend on DSP output configuration.  
Fig.18 SAA8110G system configuration for camera application (continued from Fig.17).  
21  
1997 Nov 17  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
PACKAGE OUTLINE  
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm  
SOT313-2  
c
y
X
36  
25  
A
E
37  
24  
Z
E
e
H
E
A
2
A
(A )  
3
A
1
w M  
p
θ
pin 1 index  
b
L
p
L
13  
48  
detail X  
1
12  
Z
v M  
D
A
e
w M  
b
p
D
B
H
v
M
B
D
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.20 1.45  
0.05 1.35  
0.27 0.18 7.1  
0.17 0.12 6.9  
7.1  
6.9  
9.15 9.15  
8.85 8.85  
0.75  
0.45  
0.95 0.95  
0.55 0.55  
1.60  
mm  
0.25  
0.5  
1.0  
0.2 0.12 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
94-12-19  
97-08-01  
SOT313-2  
1997 Nov 17  
22  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
If wave soldering cannot be avoided, for LQFP  
packages with a pitch (e) larger than 0.5 mm, the  
following conditions must be observed:  
SOLDERING  
Introduction  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mounted components are mixed  
on one printed-circuit board. However, wave soldering is  
not always suitable for surface mounted ICs, or for  
printed-circuits with high population densities. In these  
situations reflow soldering is often used.  
• A double-wave (a turbulent wave with high upward  
pressure followed by a smooth laminar wave)  
soldering technique should be used.  
• The footprint must be at an angle of 45° to the board  
direction and must incorporate solder thieves  
downstream and at the side corners.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “IC Package Databook” (order code 9398 652 90011).  
Reflow soldering  
Maximum permissible solder temperature is 260 °C, and  
maximum duration of package immersion in solder is  
10 seconds, if cooled to less than 150 °C within  
Reflow soldering techniques are suitable for all LQFP  
packages.  
6 seconds. Typical dwell time is 4 seconds at 250 °C.  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Several methods exist for reflowing; for example,  
infrared/convection heating in a conveyor type oven.  
Throughput times (preheating, soldering and cooling) vary  
between 50 and 300 seconds depending on heating  
method. Typical reflow peak temperatures range from  
215 to 250 °C.  
Repairing soldered joints  
Fix the component by first soldering two diagonally-  
opposite end leads. Use only a low voltage soldering iron  
(less than 24 V) applied to the flat part of the lead. Contact  
time must be limited to 10 seconds at up to 300 °C. When  
using a dedicated tool, all other leads can be soldered in  
one operation within 2 to 5 seconds between  
270 and 320 °C.  
Wave soldering  
Wave soldering is not recommended for LQFP packages.  
This is because of the likelihood of solder bridging due to  
closely-spaced leads and the possibility of incomplete  
solder penetration in multi-lead devices.  
CAUTION  
Wave soldering is NOT applicable for all LQFP  
packages with a pitch (e) equal or less than 0.5 mm.  
1997 Nov 17  
23  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
1997 Nov 17  
24  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
NOTES  
1997 Nov 17  
25  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
NOTES  
1997 Nov 17  
26  
Philips Semiconductors  
Product specification  
10-bit analog-to-digital interface for  
CCD cameras  
TDA8786; TDA8786A  
NOTES  
1997 Nov 17  
27  
Philips Semiconductors – a worldwide company  
Argentina: see South America  
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,  
Tel. +31 40 27 82785, Fax. +31 40 27 88399  
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Tel. +64 9 849 4160, Fax. +64 9 849 7811  
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,  
Fax. +43 160 101 1210  
Norway: Box 1, Manglerud 0612, OSLO,  
Tel. +47 22 74 8000, Fax. +47 22 74 8341  
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,  
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773  
Philippines: Philips Semiconductors Philippines Inc.,  
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Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474  
Belgium: see The Netherlands  
Brazil: see South America  
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,  
Tel. +48 22 612 2831, Fax. +48 22 612 2327  
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,  
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Tel. +359 2 689 211, Fax. +359 2 689 102  
Portugal: see Spain  
Romania: see Italy  
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,  
Tel. +1 800 234 7381  
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,  
Tel. +7 095 755 6918, Fax. +7 095 755 6919  
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,  
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Tel. +852 2319 7888, Fax. +852 2319 7700  
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,  
Tel. +65 350 2538, Fax. +65 251 6500  
Colombia: see South America  
Czech Republic: see Austria  
Slovakia: see Austria  
Slovenia: see Italy  
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,  
Tel. +45 32 88 2636, Fax. +45 31 57 0044  
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,  
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South America: Al. Vicente Pinzon, 173, 6th floor,  
04547-130 SÃO PAULO, SP, Brazil,  
Tel. +55 11 821 2333, Fax. +55 11 821 2382  
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,  
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427  
Spain: Balmes 22, 08007 BARCELONA,  
Tel. +34 3 301 6312, Fax. +34 3 301 4107  
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,  
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300  
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,  
Tel. +46 8 632 2000, Fax. +46 8 632 2745  
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,  
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2686, Fax. +41 1 481 7730  
Hungary: see Austria  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,  
Tel. +66 2 745 4090, Fax. +66 2 398 0793  
Indonesia: see Singapore  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,  
Tel. +90 212 279 2770, Fax. +90 212 282 6707  
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461  
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,  
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421  
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,  
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077  
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. +1 800 234 7381  
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,  
Tel. +82 2 709 1412, Fax. +82 2 709 1415  
Uruguay: see South America  
Vietnam: see Singapore  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Tel. +381 11 625 344, Fax.+381 11 635 777  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381  
Middle East: see Italy  
For all other countries apply to: Philips Semiconductors,  
Internet: http://www.semiconductors.philips.com  
International Marketing & Sales Communications, Building BE-p,  
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
© Philips Electronics N.V. 1997  
SCA56  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
547047/1200/03/pp28  
Date of release: 1997 Nov 17  
Document order number: 9397 750 02926  

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