TDA8793HL [NXP]
8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter ADC; 8位，低功耗，3V ， 100 Msps的模拟 - 数字转换器ADC的
| 型号： | TDA8793HL |
| 厂家： | 
NXP |
| 描述： | 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter ADC |
| 文件： | 总20页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8793
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
Preliminary specification
1999 Oct 06
Supersedes data of 1998 May 14
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
FEATURES
GENERAL DESCRIPTION
• 8-bit low-power ADC (170 mW typical)
• 2.7 to 3.6 V operation
The TDA8793 is an 8-bit low-power Analog-to-Digital
Converter (ADC) which includes a track-and-hold circuit
and internal references. The device converts an analog
input signal, up to 100 MHz, into 8-bit binary codes at a
maximum sample rate of 100 Msps. All digital inputs and
output are TTL/CMOS compatible. A sine wave clock input
signal can also by used.
• Sampling rate up to 100 Msps
• Track-and-hold circuit
• CMOS/TTL compatible digital inputs and outputs
• Internal references
The Power-down mode enables the device power
consumption to be reduced to 5 mW.
• Adjustable full scale range possibility with external
reference
• Power-down mode; 5 mW.
APPLICATIONS
• Radio communications
• Digital data storage read channels
• Medical imaging
• Digital instrumentation.
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN. TYP. MAX. UNIT
2.7
2.7
2.7
32
0
3.0
3.0
3.0
40
5
3.6
3.6
3.6
48
V
VCCD
VCCO
ICCA
digital supply voltage
V
output stages supply voltage
analog supply current
V
operating
mA
µA
mA
mA
mA
LSB
standby
operating
standby
100
22
ICCD
digital supply current
13
0
16
0.65 1.1
0.1
ICCO
INL
output stages supply current
integral non-linearity
−
−
ramp input; fCLK = 2 MHz;
VCCA = VCCD = 3 V
−
±0.8 tbf
DNL
differential non-linearity
ramp input; fCLK = 2 MHz;
VCCA = VCCD = 3 V
−
±0.25 tbf
LSB
fCLK(max)
Ptot
maximum clock input frequency
total power dissipation
100
−
−
−
MHz
mW
VCC = 3 V
−
170
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8793HL
LQFP32
plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm
SOT401-1
1999 Oct 06
2
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
BLOCK DIAGRAM
V
V
V
V
TEN
12
CCA
7
CCD
10
CCO2
22
CCO1
20
26
25
24
23
18
17
16
15
D7
D6
D5
D4
D3
D2
D1
D0
4
3
INP
INN
TRACK-AND-
HOLD
CMOS
OUTPUTS
LATCHES
ADC
5
2
REFOUT
REFIN
11
CLOCK DRIVER
CLK
V
= 1.85 V
REFOUT
32
8
SDN
REFERENCE
TDA8793
V
= 1.25 V
SDN
STDBY
31
6
9
19
21
AGND
MGR016
DEC
DGND
OGND1 ODGND2
Fig.1 Block diagram.
3
1999 Oct 06
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
PINNING
SYMBOL
D2
PIN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DESCRIPTION
SYMBOL
PIN
DESCRIPTION
not connected
data output bit 2
n.c.
1
2
D3
data output bit 3
output ground 1
output supply voltage 1
output ground 2
output supply voltage 2
data output bit 4
data output bit 5
data output bit 6
data output bit 7 (MSB)
not connected
REFIN
INN
reference input for ADC
negative input
OGND1
VCCO1
OGND2
VCCO2
D4
3
INP
4
positive input
REFOUT
AGND
VCCA
STDBY
DGND
VCCD
CLK
5
reference for AC coupling
analog ground
6
7
analog supply voltage
standby mode input
digital ground
D5
8
D6
9
D7
10
11
12
13
14
15
16
digital supply voltage
clock input
n.c
n.c
not connected
TEN
track enable input (active LOW)
not connected
n.c
not connected
n.c.
n.c
not connected
n.c.
not connected
DEC
SDN
decoupling
D0
data output bit 0 (LSB)
data output bit 1
stabilized decoupling node
D1
n.c.
REFIN
INN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
D5
D4
V
CCO2
INP
OGND2
TDA8793
V
REFOUT
AGND
CCO1
OGND1
D2
V
CCA
STDBY
D3
MGR017
Fig.2 Pin configuration.
4
1999 Oct 06
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN.
−0.3
MAX.
+7.0
UNIT
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
−0.3
−0.3
+7.0
+7.0
output stages supply voltage
supply voltage differences between
V
CCA and VCCD
VCCO and VCCD
CCA and VCCO
−1.0
−1.0
−1.0
−0.3
−
+1.0
+1.0
+1.0
+7.0
10
V
V
V
V
V
VINP, INN
IO
input voltage range
output current
referenced to AGND
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−55
0
+150
70
−
−
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
thermal resistance from junction to ambient
94
K/W
1999 Oct 06
5
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
CHARACTERISTICS
VCCA = V7 to V6 = 2.7 to 3.6 V; VCCD = V10 to V9 = 2.7 to 3.6 V; VCCO = V20 (or V22) to V19 (or V21) = 2.7 to 3.6 V;
AGND to DGND and OGND shorted together; VCCA to VCCD = −0.15 to +0.15 V; VCCD to VCCO = −0.15 to +0.15 V;
VCCA to VCCO = −0.15 to +0.15 V; Tamb = 0 to 70 °C; typical values measured at VCCA = VCCD = VCCO = 3.0 V and
Tamb = 25 °C; single-ended input; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
VCCD
VCCO
ICCA
analog supply voltage
digital supply voltage
2.7
2.7
2.7
32
13
−
3.0
3.6
V
3.0
3.0
40
16
0.1
4
3.6
3.6
48
22
tbf
tbf
V
output stages supply voltage
analog supply current
digital supply current
V
mA
mA
mA
mA
ICCD
ICCO
output stages supply current
fi = ramp input
fi = 20 MHz
−
Internal reference (pin SDN); note 1
Vref
Vreg
TC
IL
reference voltage
line regulation voltage
temperature coefficient
load current
1.21
−
1.25
0.4
18
1.29
V
2.7 < VCCA < 3.6 V
3
−
−
mV
ppm/K
mA
−
−1
−
Internal reference (pin REFOUT)
Vo(ref)
Vo(reg)
TC
reference voltage
line regulation voltage
temperature coefficient
load current
1.76
−
1.82
1.5
18
1.88
V
2.7 < VCCA < 3.6 V
4
−
−
mV
ppm/K
mA
−
IL
−1
−
Adjustable full scale input (pin REFIN); see Figs 3, 4, and 7
Iref
input current
VREFIN = 1.25 V
−
−0.87
−
mA
Clock input (pin CLK); note 2
VIL
VIH
IIL
IIH
tr
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
clock rise time
0
−
0.8
VCCD
+2
5
V
2
−
V
VCLK = 0
−2
−
−
µA
µA
ns
ns
kΩ
pF
VCLK = VCCD
−
0.75
0.75
−
−
tbf
tbf
−
tf
clock fall time
−
Zi
input impedance
fCLK = 100 MHz
fCLK = 100 MHz
32
2
Ci
input capacitance
−
−
Standby input (pin STDBY); see Table 1
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
0
−
−
−
−
0.8
VCCD
−
V
2
V
VSTDBY = 0
−5
−
µA
µA
IIH
VSTDBY = VCCD
5
1999 Oct 06
6
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Track enable input (pin TEN); see Table 2
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
0
−
−
−
−
0.8
V
2
VCCD
V
VTEN = 0
VTEN = VCCD
−5
−
−
µA
µA
IIH
5
Inputs (pins INP and INN); analog input voltage referenced to AGND; VREFIN = 1.27 V; see Table 3
Vi(p-p)
input voltage range
(peak-to-peak value)
Vi = VINP − VINN
;
0.90
0.97
1.040
V
Tamb = 25 °C
∆TCI
Vi(os)
Zi
input voltage range drift
input offset voltage
input impedance
−
0.5
−
−
mV/K
mV
kΩ
output code = 127
fINP = 50 MHz
−25
−
+25
−
90
2
Ci
input capacitance
fINP = 50 MHz
−
−
pF
IIL
LOW-level input current
VINP = VREFOUT + 0.5
−1
−1
−
−
−
µA
VINP = VREFOUT − 0.5
−
−
µA
IIH
HIGH-level input current
VINP = VREFOUT + 0.5
−
40
40
µA
VINP = VREFOUT − 0.5
−
−
µA
Adjustable full scale range; VREFIN = 1.2 to 1.35 V; see Fig.3
VI(p-p)
input voltage range
(peak-to-peak value)
Vi = VINP − VINN
Tamb = 25 °C
;
−
1
−
V
Voltage controlled regulator input pin VREFIN (referenced to AGND); note 3
Vi(ref)
Ii(ref)
reference voltage
tbf
1.25
tbf
tbf
V
input current on pin VREFIN
−
1.1
mA
Outputs; ADC data outputs
VOL
VOH
CL
LOW-level output voltage
IO = 1 mA
−
−
0.5
VCCO
10
V
HIGH-level output voltage
output load capacitance
slew rate
IO = −0.4 mA
V
−
−
CCO − 0.5 −
V
−
pF
V/ns
δv/δt
10% to 90%; CL = 10 pF
track = LOW
1.2
−
Switching characteristics; note 2; see Table 1
fCLK(min)
fCLK(max)
tW(CLKH)
tW(CLKL)
minimum clock frequency
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
−
−
−
−
−
6
−
−
−
MHz
MHz
ns
100
4
4
ns
1999 Oct 06
7
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog signal processing; note 3; see Figs 4, 5, 6 and 7
INL
integral non-linearity
ramp input; fCLK = 2 MHz;
VCCA = VCCD = 3 V
−
−
±0.8
tbf
LSB
DNL
S/N
differential non-linearity
signal-to-noise ratio (full scale)
ramp input; fCLK = 2 MHz;
VCCA = VCCD = 3 V
±0.25
tbf
LSB
without harmonics;
fCLK = 100 MHz
fi = 20 MHz
42
−
45
−
−
−
−
−
dB
fi = 50 MHz
45
dB
BW(−3dB)
THD
−3 dB analog bandwidth
−
350
−56
−52
MHz
dB
total harmonics distortion
fi = 20 MHz
−
fi = 50 MHz
−
dB
Hfund(FS)
full scale fundamental harmonics
fCLK = 100 MHz
fi = 20 MHz
−
−
−
−
0
0
dB
dB
fi = 50 MHz
HD2(FS)
second harmonic distortion (full
scale) all components included
differential inputs;
fCLK = 100 MHz
fi = 20 MHz
−
−
66
57
−
−
dB
dB
fi = 50 MHz
single-ended input;
f
CLK = 100 MHz
fi = 20 MHz
−
−
66
55
−
−
dB
dB
fi = 50 MHz
HD3(FS)
third harmonic distortion (full scale) differential inputs;
all components included
fCLK = 100 MHz
fi = 20 MHz
−
−
64
61
−
−
dB
dB
fi = 50 MHz
single-ended input;
f
f
f
CLK = 100 MHz
fi = 20 MHz
−
−
64
59
−
−
dB
fi = 50 MHz
dB
SFDR
EB
spurious free dynamic range
effective bits
CLK = 100 MHz
fi = 20 MHz
dB
−
−
57
54
−
−
dB
fi = 50 MHz
dB
CLK = 100 MHz; note 4
fi = 20 MHz
bits
bits
bits
7.0
7.4
7.2
−
−
fi = 50 MHz
−
Data timing; fCLK = 100 MHz; CL = 10 pF; see Fig.8
tds
th
sampling delay
output hold time
output delay time
−
3
−
−
−
5
1.5
−
ns
ns
ns
td
8
1999 Oct 06
8
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
Notes
1. It is possible to use the reference output voltage (pin SDN) to drive other analog circuits under the limits indicated.
2. In addition to a good layout of the digital and analog grounds, it is recommended that the rise and fall times of the
clock must be not less than 0.75 ns.
3. It is possible with an external reference voltage connected to REFIN pin to adjust the ADC input range. The input
range variation will be fixed.
4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 k acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(nyquist frequency). Conversion to signal-to-noise ratio: SINAD = 6.02 × EB + 1.76 dB.
Table 1 Standby selection
PIN STDBY
D0 TO D7
ICCA + ICCD
LOW
inactive
56 mA
0.7 mA
HIGH
active; output logic state LOW
Table 2 Track-and-hold selection
PIN TEN
TRACK-AND-HOLD
LOW
active
HIGH
inactive; tracking mode
Table 3 Output coding and input voltage (typical values; referenced to AGND); VREFIN = 1.27 V
BINARY OUTPUT BITS
STEP
VINP (V)
VINN (V)
D7
D6
D5
D4
D3
D2
D1
D0
Underflow
<1.6
1.6
...
>2.1
2.1
...
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
...
...
...
...
...
...
1
...
...
...
1
...
...
...
1
...
...
...
1
...
...
...
1
...
...
...
1
...
...
...
1
...
...
...
0
127
...
1.85
...
1.85
...
254
255
Overflow
...
...
2.1
>2.1
1.6
<1.6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1999 Oct 06
9
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
FCE423
FCE421
1.4
67
handbook, halfpage
SFDR
handbook, halfpage
(1)
V
i(p-p)
(V)
S/N
(dB)
62
1.2
57
52
47
1
0.8
0.6
(2)
42
1.15
1.15
1.25
1.35
1.45
(V)
1.25
1.35
1.45
(V)
V
V
REFIN
REFIN
(1) SFDR
(2) S/N
Typical values measured at VCCA = VCCD = VCCO = 3.0 V,
Typical values measured at VCCA = VCCD = VCCO = 3.0 V,
fCLK = 100 MHz, Tamb = 25 °C and single-ended input.
fCLK = 100 MHz, Tamb = 25 °C and single-ended input.
Fig.3 ADC input voltage as a function of VREFIN
reference input voltage.
Fig.4 Noise and spurious free dynamic range as
a function of VREFIN reference input voltage.
FCE419
FCE420
55
handbook, halfpage
THD
8
handbook, halfpage
EB
(bits)
S/N
(1)
(dB)
(1)
53
7.5
(2)
(2)
51
7
49
6.5
6
(3)
47
45
5.5
2
2
1
10
10
1
10
10
f (MHz)
f (MHz)
i
i
(1) THD for differential inputs
(2) THD for single-ended input
(3) S/N
(1) Differential inputs
(2) Single-ended input
Typical values measured at VCCA = VCCD = VCCO = 3.0 V,
fCLK = 100 MHz and Tamb = 25 °C.
Typical values measured at VCCA = VCCD = VCCO = 3.0 V,
fCLK = 100 MHz and Tamb = 25 °C.
Fig.5 Noise and distortion as a function of input
frequency.
Fig.6 Effective bits as a function of input frequency.
1999 Oct 06
10
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
FCE422
8
handbook, halfpage
EB
(bits)
7
6
5
1.15
1.25
1.35
1.45
V
(V)
REFIN
Typical values measured at VCCA = VCCD = VCCO = 3.0 V,
fCLK = 100 MHz, Tamb = 25 °C and single-ended input.
Fig.7 Effective bits as a function of VREFIN
reference input voltage.
t
CPL
t
CPH
HIGH
50 %
LOW
CLK
sample N
sample N + 1
sample N + 2
V
l
t
t
h
ds
HIGH
DATA
D0 to D7
DATA
N − 2
DATA
N − 1
DATA
N
DATA
N + 1
50 %
LOW
t
d
MGR018
Fig.8 Timing diagram.
11
1999 Oct 06
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
APPLICATION INFORMATION
100 nF
DEC
31
SND
32
100 nF
10 nF
REFIN
2
INN
INP
3
4
220 nF
input
TDA8793
50 Ω 50 Ω
REFOUT
5
100 nF
MGR019
Fig.9 Application diagram for single-ended input mode with internal reference.
EXTERNAL
REFERENCE
100 nF
DEC
31
1.25 V
100 nF
10 nF
REFIN
2
INN
INP
3
4
220 nF
TDA8793
input
50 Ω 50 Ω
REFOUT
5
100 nF
MGR020
Fig.10 Application diagram for single-ended input mode with external reference.
12
1999 Oct 06
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
100 nF
DEC
31
SND
32
100 nF
REFIN
INN
2
3
220 nF
input 2
50 Ω
TDA8793
220 nF
50 Ω
INP
input 1
4
5
REFOUT
100 nF
MGR021
Fig.11 Application diagram for differential input mode with internal reference.
100 nF
SND
32
DEC
31
100 nF
REFIN
INN
2
3
220 nF
1 : 1
input
100 nF
100 Ω
100 Ω
TDA8793
INP
4
5
REFOUT
100 nF
MGR022
Fig.12 Application diagram for differential input mode using a transformer.
13
1999 Oct 06
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm
SOT401-1
c
y
X
A
E
17
24
Z
16
25
E
e
A
H
2
E
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
32
9
L
1
8
detail X
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.5
0.05 1.3
0.27 0.18 5.1
0.17 0.12 4.9
5.1
4.9
7.15 7.15
6.85 6.85
0.75
0.45
0.95 0.95
0.55 0.55
mm
1.60
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-04
SOT401-1
1999 Oct 06
14
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Oct 06
15
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Oct 06
16
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
NOTES
1999 Oct 06
17
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
NOTES
1999 Oct 06
18
Philips Semiconductors
Preliminary specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
NOTES
1999 Oct 06
19
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/02/pp20
Date of release: 1999 Oct 06
Document order number: 9397 750 06028
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