TDA8933T [NXP]
Class-D audio amplifier; D类音频放大器
| 型号： | TDA8933T |
| 厂家： | 
NXP |
| 描述： | Class-D audio amplifier |
| 文件： | 总47页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA8933
Class-D audio amplifier
Rev. 01 — 15 May 2007
Preliminary data sheet
1. General description
The TDA8933 is a high efficiency class-D amplifier with low power dissipation.
The continuous time output power is 2 × 10 W in a stereo half bridge application
(RL = 8 Ω) or 1 × 20 W in a mono full bridge application (RL =16 Ω). Due to the low power
dissipation the device can be used without any external heat sink when playing music.
Due to the implementation of Thermal Foldback (TF), even for high supply voltages and/or
lower load impedances, the device will continue to operate with considerable music output
power without the need for an external heat sink.
The device has two full differential inputs driving two independent outputs. It can be used
in a mono full bridge configuration (Bridge-Tied Load (BTL)) or a stereo half bridge
configuration (Single-Ended (SE)).
2. Features
I High efficiency
I Application without heat sink using thermally enhanced small outline package
I Operating voltage from 10 V to 36 V asymmetrical or ± 5 V to ± 18 V symmetrical
I Thermally protected
I Thermal foldback
I Current limiting to avoid audio holes
I Full short circuit proof to supply lines (using advanced current protection)
I Switchable internal / external oscillator (master-slave setting)
I No pop noise
I Low power dissipation
I Mono bridge-tied load (full bridge) or stereo single-ended (half bridge) application
I Full differential inputs
3. Applications
I Flat panel television sets
I Flat panel monitor sets
I Multimedia systems
I Wireless speakers
I Mini/micro systems
I Home sound sets
TDA8933
NXP Semiconductors
Class-D audio amplifier
4. Quick reference data
Table 1.
Quick reference data
Symbol Parameter
Conditions
Min
Typ
Max
Unit
General; Vp = 25 V, fosc = 320 kHz, Tamb = 25 °C unless specified otherwise
VP
supply voltage
asymmetrical supply
symmetrical supply
Sleep mode
10
5
-
25
36
18
1.0
50
V
12.5
0.6
40
V
IP
supply current
mA
mA
Iq(tot)
total quiescent
current
Operating mode; no load, no
snubbers or filter connected
-
Stereo SE channel
[1]
Po(RMS) RMS output power continuous time output power
per channel
RL = 4 Ω; VP = 17 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
RL = 8 Ω; VP = 25 V
5.9
-
6.5
6.5
8.3
8.3
-
-
-
-
W
W
W
W
7.5
-
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
7.3
-
8.1
-
-
-
-
W
W
W
W
8.1
9.3
-
10.3
10.3
[2]
short time output power per
channel; THD+N = 10 %,
see Figure 23 for details
RL = 8 Ω; VP = 31 V
THD+N = 0.5 %
THD+N = 10 %
11.2
14.1
12.4
15.7
-
-
W
W
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
2 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
Table 1.
Quick reference data …continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Mono BTL channel
[1]
Po(RMS) RMS output power continuous time output power
THD+N = 10 %; fi = 1 kHz
RL = 8 Ω; VP = 17 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
11.9
13.2
13.2
17.1
17.1
-
-
-
-
W
W
W
W
-
15.4
-
THD+N = 10 %, fi = 100 Hz
RL = 16 Ω; VP = 25 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
14.9
16.5
16.5
21
-
-
-
-
W
W
W
W
-
18.9
-
THD+N = 10 %, fi = 100 Hz
21
[2]
short time output power;
THD+N = 10 %, see
Figure 35 for details
RL = 16 Ω; VP = 31 V
THD+N = 0.5 %
THD+N = 10 %
22.8
28.8
25.3
32
-
-
W
W
[1] Output power is measured indirectly, based on RDSon measurement.
[2] 2 layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural
convection.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA8933T
SO32
plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
3 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
6. Block diagram
V
OSCREF
10
OSCIO
31
V
DDA
8
DDP1
29
OSCILLATOR
28
BOOT1
OUT1
2
3
IN1P
IN1N
V
SSD
DRIVER
HIGH
PWM
MODULATOR
27
26
CTRL
DRIVER
LOW
V
SSP1
V
DDA
25
STABI 11V
STAB1
12
INREF
+
V
SSP1
V
DDA
V
SSA
24
MANAGER
STABI 11V
STAB2
BOOT2
V
SSP2
21
20
15
IN2P
V
DDP2
DRIVER
HIGH
PWM
MODULATOR
22
23
OUT2
CTRL
14
7
IN2N
DRIVER
LOW
V
SSP2
PROTECTIONS
OVP, OCP, OTP
UVP, TF, WP
CGND
18
11
REG5V
DREF
V
SSD
4
6
DIAG
V
DDA
HVPREF
POWERUP
30
19
HVP1
HVP2
MODE
5
V
ENGAGE
SSA
HALF SUPPLY VOLTAGE
1, 16, 17, 32
CGND
9
13
010aaa113
V
TEST
V
SSD(HW)
SSA
Fig 1. Block diagram
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
4 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
7. Pinning information
7.1 Pinning
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
SSD(HW)
SSD(HW)
IN1P
OSCIO
HVP1
3
IN1N
DIAG
4
V
DDP1
5
ENGAGE
POWER UP
CGND
BOOT1
OUT1
6
7
V
SSP1
8
V
STAB1
STAB2
DDA
TDA8933T
SO32
9
V
SSA
10
11
12
13
14
15
16
OSCREF
HVPREF
INREF
TEST
V
SSP2
OUT2
BOOT2
V
DDP2
IN2N
HVP2
DREF
IN2P
V
V
SSD(HW)
SSD(HW)
010aaa114
Fig 2. Pin configuration diagram
7.2 Pin description
Table 3.
Symbol
Pinning description
Pin
1
Description
VSSD(HW)
IN1P
negative digital supply voltage and handle wafer connection
positive audio input for channel 1
2
IN1N
3
negative audio input for channel 1
DIAG
4
diagnostic output; open-drain
ENGAGE
POWERUP
CGND
VDDA
5
engage input to switch between Mute mode and Operating mode
power-up input to switch between Sleep mode and Mute mode
control ground; reference for POWERUP, ENGAGE and DIAG
positive analog supply voltage
6
7
8
VSSA
9
negative analog supply voltage
OSCREF
HVPREF
INREF
TEST
10
11
12
13
14
15
16
17
18
input internal oscillator setting (only master setting)
decoupling of internal half supply voltage reference
decoupling for input reference voltage
test signal input; for testing purpose only
IN2N
negative audio input for channel 2
IN2P
positive audio input for channel 2
VSSD(HW)
VSSD(HW)
DREF
negative digital supply voltage and handle wafer connection
negative digital supply voltage and handle wafer connection
decoupling of internal (reference) 5 V regulator for logic supply
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
5 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
Table 3.
Pinning description …continued
Symbol
Pin
Description
HVP2
19
half supply output voltage 2 for charging single-ended capacitor for
channel 2
VDDP2
BOOT2
OUT2
VSSP2
STAB2
STAB1
VSSP1
OUT1
BOOT1
VDDP1
HVP1
20
21
22
23
24
25
26
27
28
29
30
positive power supply voltage for channel 2
bootstrap high-side driver channel 2
Pulse Width Modulated (PWM) output channel 2
negative power supply voltage for channel 2
decoupling of internal 11 V regulator for channel 2 drivers
decoupling of internal 11 V regulator for channel 1 drivers
negative power supply voltage for channel 1
PWM output channel 1
bootstrap capacitor for channel 1
positive power supply voltage for channel 1
half supply output voltage 1 for charging single-ended capacitor for
channel 1
OSCIO
31
32
oscillator input in slave configuration or oscillator output in master
configuration
VSSD(HW)
negative digital supply voltage and handle wafer connection
8. Functional description
8.1 General
The TDA8933 is a mono full bridge or stereo half bridge audio power amplifier using
class-D technology. The audio input signal is converted into a Pulse Width Modulated
(PWM) signal via an analog input stage and PWM modulator. To enable the output power
Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM
signal is applied to control and handshake block and driver circuits for both the high side
and low side. A 2nd-order-low-pass filter converts the PWM signal to an analog audio
signal across the loudspeakers.
The TDA8933 contains two independent half bridges with full differential input stages. The
loudspeakers can be connected in the following configurations:
• Mono full bridge: Bridge Tied Load (BTL)
• Stereo half bridge: Single-Ended (SE)
The TDA8933 contains circuits common to both channels, such as: the oscillator, all
reference sources, the mode functionality and a digital timing manager.
The following protections are built-in: thermal foldback, temperature, current and voltage.
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
6 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
8.2 Mode selection and interfacing
The TDA8933 can be switched to one of four operating modes using pins POWERUP and
ENGAGE:
• Sleep mode: with low supply current
• Mute mode: the amplifiers are switching idle (50 % duty cycle), but the audio signal at
the output is suppressed by disabling the Vl-converter input stages. The capacitors on
pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical
supply only)
• Operating mode: the amplifiers are fully operational with an output signal
• Fault mode
Both pins POWERUP and ENGAGE refer to pin CGND.
Table 4 shows the different modes as a function of the voltages on the POWERUP and
ENGAGE pins.
Table 4.
Mode
Mode selection for the TDA8933
Pin
POWERUP[1]
ENGAGE[1]
< 0.8 V
DIAG
Sleep
< 0.8 V
undefined
> 2 V
Mute
2 V to 6 V
2 V to 6 V
2 V to 6 V
< 0.8 V
Operating
Fault
3 V to 6 V
undefined
> 2 V
< 0.8 V
[1] When there are symmetrical supply conditions, the voltage applied to pins POWERUP and ENGAGE must
never exceed the supply voltage (VDDA, VDDP1 or VDDP2).
If the transition between Mute mode and Operating mode is controlled via a time constant,
the start-up will be pop free since the DC output offset voltage is applied gradually to the
output between Mute mode and Operating mode. The bias current setting of the
VI-converters is related to the voltage on pin ENGAGE.
• Mute mode: the bias current setting of the VI-converters is zero (VI-converters
disabled).
• Operating mode: the bias current is at maximum.
The time constant required to apply the DC output offset voltage gradually between Mute
mode and Operating mode can be generated by applying a decoupling capacitor on pin
ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF.
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
7 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
V
P
POWERUP
DREF
HVPREF
HVP1, HVP2
0.43V
ENGAGE
0.3V
ENGAGE
ENGAGE
0.17V
ENGAGE
AUDIO
AUDIO
AUDIO
PWM
audio
OUT1, OUT2
PWM
PWM
DIAG
OSCIO
operating
mute
operating
fault
operating
sleep
001aae788
Fig 3. Start-up sequence
8.3 Pulse width modulation frequency
The output signal of the amplifier is a PWM signal with a carrier frequency of
approximately 320 kHz. Using a 2nd-order-low-pass filter in the application results in an
analog audio signal across the loudspeaker. The PWM switching frequency can be set by
an external resistor Rosc connected between pin OSCREF and VSSD(HW). The carrier
frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 kΩ,
the carrier frequency is set to an optimized value of 320 kHz (see Figure 4).
If two or more TDA8933 devices are used in the same audio application, it is
recommended to synchronize the switching frequency of all devices.This can be done by
connecting all the OSCIO pins together and configuring one of the TDA8933 devices in
the application as the clock master. Configure the other TDA8933 devices as slaves.
Pin OSCIO is a 3-state input or output buffer. Pin OSCIO is configured in master mode as
oscillator output, and in slave mode as oscillator input. Master mode is enabled by
applying a resistor between pin OSCREF and VSSD(HW), while slave mode is enabled by
connecting pin OSCREF directly to VSSD(HW) (without any resistor).
The value of the resistor also sets the frequency of the carrier and can be calculated with
Equation 1:
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
8 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
12.45x109
------------------------
Rosc
f osc
=
(1)
Where:
fosc = oscillator frequency (Hz)
Rosc = oscillator resistor (Ω) (on pin OSCREF)
001aad758
550
f
osc
(kHz)
450
350
250
25
30
35
40
45
Rosc (kΩ)
Fig 4. Oscillation frequency as a function of Rosc
Table 5 summarizes how to configure the TDA8933 in master or slave configuration.
Table 5.
Master/slave configuration
Configuration
Pin
OSCREF
OSCIO
output
input
Master
Slave
Rosc > 25 kΩ to VSSD(HW)
Rosc = 0 Ω; shorted to VSSD(HW)
8.4 Protections
The following protections are implemented in the TDA8933:
• Thermal Foldback (TF)
• OverTemperature Protection (OTP)
• OverCurrent Protection (OCP)
• Window Protection (WP)
• Supply voltage protections
– UnderVoltage Protection (UVP)
– OverVoltage Protection (OVP)
– UnBalance Protection (UBP)
• ElectroStatic Discharge (ESD)
The behavior of the device under the different fault conditions differs according to the
protection activated and is described in the following sections.
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
9 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
8.4.1 Thermal Foldback (TF)
If the junction temperature of the TDA8933 exceeds the threshold level (Tj > 140 °C), the
gain of the amplifier is decreased gradually to a level where the combination of
dissipation (P) and the thermal resistance from junction to ambient (Rth(j-a)) results in a
junction temperature around the threshold level.
This means that the device will not switch off completely, but remains operational at lower
output power levels. With music output signals, this feature enables high peak output
powers while still operating without any external heat sink other than the printed-circuit
board area.
If the junction temperature still increases due to external causes, the OverTemperature
Protection (OTP) shuts down the amplifier completely.
8.4.2 OverTemperature Protection (OTP)
If the junction temperature Tj > 155 °C, the power stage will shut down immediately.
8.4.3 OverCurrent Protection (OCP)
When the output current of the device exceeds 2 A due to a short-circuit across the load
or an impedance drop, the cycle-by-cycle current limitation becomes active. This means
the device will not switch off, but continue to operate while limiting the current without
causing audio holes (interruptions). The maximum output current will not go beyond the
absolute maximum current.
If the current exceeds 2 A due to a low ohmic short from the demodulated output (after the
inductor) to either VSS or VDD both power stages become floating. The DIAG is set low for
50 ms and the internal timer of 100 ms is started. The timer will keep both power stages
disabled for 100 ms. As long as the short remains, this cycle will repeat. The average
power dissipation in the TDA8933 will be low because the short-circuit current will flow
only during a very small part of the timer cycle of 100 ms.
8.4.4 Window Protection (WP)
WP checks the PWM output voltage before switching from Sleep mode to Mute mode
(outputs switching) and is activated:
• During the start-up sequence, when pin POWERUP is switched from Sleep mode to
Mute mode.
In the event of a short-circuit at one of the output terminals to VDDP1, VSSP1, VDDP2 or
VSSP2 the start-up procedure is interrupted and the TDA8933 waits for open-circuit
outputs. Because the check is done before enabling the power stages, no large
currents will flow in the event of a short-circuit.
• When the amplifier is shut down completely, due to activation of the OCP because a
short to one of the supply lines is made, then during restart (after 100 ms) the window
protection will be activated. As a result, the amplifier will not start up until the short to
the supply lines is removed.
8.4.5 Supply voltage protections
If the supply voltage drops below 10 V, the UVP circuit is activated and the system will
shut down directly. This switch-off will be silent and without pop noise. When the supply
voltage rises above the threshold level, the system is restarted again after 100 ms.
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
10 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
If the supply voltage exceeds 36 V, the OVP circuit is activated and the power stages will
shut down. It is re-enabled as soon as the supply voltage drops below the threshold level.
The system is restarted again after 100 ms.
It should be noted that supply voltages > 40 V may damage the TDA8933. Two conditions
should be distinguished:
• If the supply voltage is pumped to higher values by the TDA8933 application itself
(see also Section 14.8), the OVP is triggered and the TDA8933 is shut down. The
supply voltage will decrease and the TDA8933 is protected against any overstress.
• If a supply voltage > 40 V is caused by other or external causes, the TDA8933 will
shut down, but the device can still be damaged since the supply voltage will remain
> 40 V in this case. The OVP protection is not a supply clamp.
An additional UBP circuit compares the positive analog supply voltage (VDDA) and the
negative analog supply voltage (VSSA) and is triggered if the voltage difference between
them exceeds a certain level. This level depends on the sum of both supply voltages. The
unbalance threshold levels can be defined as follows:
• LOW-level threshold: VP(th)(ubp)l < 8/5 × VHVPREF
• HIGH-level threshold: VP(th)(ubp)h > 8/3 × VHVPREF
In a symmetrical supply the UBP is released when the unbalance of the supply voltage is
within 6 % of its starting value.
Table 6 shows an overview of all protections and the effect on the output signal.
Table 6.
Overview of protections for the TDA8933
Protection
Restart
When fault is removed
Every 100 ms
OTP
OCP
WP
no
yes
no
yes
yes
no
no
UVP
OVP
UBP
yes
yes
yes
no
no
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
11 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
8.5 Diagnostic input and output
Whenever one of the protections is triggered, except for TF, pin DIAG is activated to LOW
level (see Table 6). An internal reference supply will pull up the open-drain DIAG output to
approximately 2.4 V. This internal reference supply can deliver approximately 50 µA. The
DIAG pin refers to pin CGND.The diagnostic output signal during different short circuit
conditions is illustrated in Figure 5. Using pin DIAG as input, a voltage < 0.8 V will put the
device into Fault mode.
V
V
o
o
2.4 V
2.4 V
amplifier
restart
no restart
0 V
0 V
≈ 50 ms ≈ 50 ms
short to
shorted load
supply line
001aad759
Fig 5. Diagnostic output for different kinds of short circuit conditions
8.6 Differential inputs
For a high common-mode rejection ratio and for maximum flexibility in the application, the
audio inputs are fully differential. By connecting the inputs anti-parallel, the phase of one
of the two channels can be inverted, so that the amplifier can operate as a mono BTL
amplifier. The input configuration for a mono BTL application is illustrated in Figure 6.
In the single-ended configuration it is also recommended to connect the two differential
inputs in anti-phase. This has advantages for the current handling of the power supply at
low signal frequencies and minimizes supply pumping (see also Section 14.8).
IN1P
OUT1
IN1N
audio
input
IN2P
OUT2
IN2N
001aad760
Fig 6. Input configuration for a mono BTL application
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
12 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
8.7 Output voltage buffers
When pin POWERUP is set HIGH, the half supply output voltage buffers are switched on
in asymmetrical supply configuration. The start-up will be pop free because the device
starts switching when the capacitor on pin HVPREF and the SE capacitors are completely
charged.
Output voltage buffers:
• Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its
value. The half supply voltage output is disabled when the TDA8933 is used in a
symmetrical supply application.
• Pin HVPREF: This output voltage reference buffer charges the capacitor on pin
HVPREF.
• Pin INREF: This output voltage reference buffer charges the input reference capacitor
on pin INREF. Pin INREF applies the bias voltage for the inputs.
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
13 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
9. Internal circuitry
Table 7.
Pin
Internal circuitry
Symbol
Equivalent circuit
1, 16, 17, 32 VSSD(HW)
1, 16,
17, 32
V
V
DDA
SSA
001aad784
2
IN1P
IN1N
INREF
IN2N
IN2P
3
12
14
15
V
V
DDA
13
SSA
001aad795
4
DIAG
V
2.5 V
DDA
50 µA
4
5 kΩ
± 20 %
V
V
CGND 010aaa198
SSA
5
ENGAGE
4.6 V
DDA
I
= 20 µA
ref
5
226 kΩ
± 20 %
V
SSA
CGND
001aad787
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
14 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
Table 7.
Internal circuitry …continued
Pin
Symbol
Equivalent circuit
6
POWERUP
V
DDA
6
V
CGND
001aad788
SSA
7
CGND
V
DDA
7
V
SSA
001aad789
8
VDDA
8
V
V
SSA
SSD
001aad790
9
VSSA
V
DDA
9
V
SSD
001aad791
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
15 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
Table 7.
Internal circuitry …continued
Pin
Symbol
Equivalent circuit
10
OSCREF
V
DDA
I
ref
10
V
001aad792
SSA
11
HVPREF
V
DDA
11
V
SSA
010aaa199
DDA
13
TEST
V
13
V
SSA
001aad795
18
DREF
V
DD
18
V
SSD
010aaa200
19
30
HVP2
HVP1
V
DDA
19, 30
V
SSA
010aaa201
20
23
26
29
VDDP2
VSSP2
VSSP1
VDDP1
20, 29
23, 26
001aad798
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
16 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
Table 7.
Internal circuitry …continued
Pin
21
Symbol
BOOT2
BOOT1
Equivalent circuit
21, 28
28
OUT1, OUT2
001aad799
22
27
OUT2
OUT1
V
V
DDP1,
DDP2
22, 27
V
SSP1,
V
SSP2
010aaa202
24
25
STAB2
STAB1
V
DDA
24, 25
V
SSP1,
V
SSP2
010aaa203
31
OSCIO
DREF
31
V
SSD
010aaa204
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
17 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
10. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VP
Vx
supply voltage
asymmetrical supply
−0.3
+40
V
voltage on pin x
[1]
[2]
[3]
IN1P, IN1N, IN2P, IN2N
OSCREF, OSCIO, TEST
−5
+5
V
V
V
VSSD(HW) - 0.3 5
POWERUP, ENGAGE,
DIAG
VCGND - 0.3
6
[4]
[5]
all other pins
VSS - 0.3
2.3
VDD + 0.3
-
V
A
IORM
repetitive peak output
current
maximum output
current limiting
Tj
junction temperature
storage temperature
ambient temperature
power dissipation
-
150
+150
+85
5
°C
°C
°C
W
Tstg
Tamb
P
−55
−40
-
[1] Measured with respect to pin INREF; Vx < VDD + 0.3 V.
[2] Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V.
[3] Measured with respect to pin CGND; Vx < VDD + 0.3 V.
[4] VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2
.
[5] Current limiting concept.
11. Thermal characteristics
Table 9.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Min
Typ
-
Max
Unit
thermal resistance from
junction to ambient
free air natural convection
JEDEC test board
[1]
[2]
-
-
-
41
44
-
44
-
K/W
K/W
K/W
2 layer application board
Ψj-lead
thermal characterization
parameter from junction to
lead
30
[3]
Ψj-top
thermal characterization
parameter from junction to
top of package
-
-
8
K/W
[1] Measured in a JEDEC high K-factor test board (standard EIA/JESD 51-7) in free air with natural convection.
[2] 2 layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection.
[3] Strongly dependent on where the measurement is taken on the package.
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
18 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
12. Static characteristics
Table 10. Characteristics
VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise.
Symbol
Supply
VP
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
asymmetrical supply
symmetrical supply
Sleep mode
10
±5
-
25
36
V
±12.5
0.6
40
±18
1.0
50
V
IP
supply current
mA
mA
Iq(tot)
total quiescent current
Operating mode; no load,
no snubbers or filter
connected
-
Series resistance output switches
RDSon
drain-source on-state
resistance
Tj = 25 °C
-
-
350
545
-
-
mΩ
mΩ
Tj = 125 °C
Power up input: pin POWERUP[1]
VI
input voltage
0
-
-
6.0
20
V
II
input current
VI = 3 V
1
-
µA
V
VIL
LOW-level input voltage
0
2
0.8
6.0
VIH
HIGH-level input voltage
-
V
Engage input: pin ENGAGE[1]
VO
VI
output voltage
4.2
0
4.6
5.0
6.0
40
V
input voltage
-
V
IO
output current
VI = 3 V
-
20
-
µA
V
VIL
LOW-level input voltage
0
0.8
6.0
VIH
HIGH-level input voltage
3
-
V
Diagnostic output: pin DIAG[1]
VO output voltage
protection activated; see
Table 6
-
-
0.8
3.3
V
V
Operating mode
2
2.5
Bias voltage for inputs: pin INREF
VO(bias) bias output voltage
Reference to VSSA
-
2.1
-
V
Half supply voltage
Pins HVP1 and HVP2
VO
output voltage
half supply voltage to
charge SE capacitor
0.5VP −
0.2 V
0.5VP
50
0.5VP +
0.2 V
V
IO
output current
output voltage
VHVP1 = VHVP2 = VO − 1 V
mA
Pin HVPREF
VO
half supply reference
voltage in Mute mode
0.5VP −
0.2 V
0.5VP
4.8
0.5VP +
0.2 V
V
V
Reference voltage for internal logic: pin DREF
VO
output voltage
4.5
5.1
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
19 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
Table 10. Characteristics …continued
VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise.
Symbol
Amplifier outputs: pins OUT1 and OUT2
VO(offset) output offset voltage
Parameter
Conditions
Min
Typ
Max
Unit
SE; with respect to
HVPREF
Mute mode
Operating mode
BTL
-
-
-
-
15
mV
mV
100
Mute mode
Operating mode
-
-
-
-
20
mV
mV
150
Stabilizer output: pins STAB1, STAB2
VO output voltage
Mute mode and
Operating mode; with
respect to pins VSSP1 and
VSSP2
10
11
12
V
Voltage protections
VP(uvp)
undervoltage protection
supply voltage
8.0
36.1
-
9.5
9.9
40
18
-
V
V
V
V
VP(ovp)
overvoltage protection
supply voltage
38.5
VP(th)(ubp)l
VP(th)(ubp)h
low unbalance protection
threshold supply voltage
VHVPREF = 11 V
VHVPREF = 11 V
-
-
high unbalance protection
threshold supply voltage
29
Current protections
IO(ocp) overcurrent protection
output current
Temperature protection
Tact(th_prot) thermal protection activation
current limiting
2.0
2.3
-
A
155
140
-
-
160
150
°C
°C
temperature
Tact(th_fold)
thermal foldback activation
temperature
Oscillator reference: pin OSCIO[2]
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
4.0
0
-
-
-
-
-
5.0
0.8
5.0
0.8
-
V
V
V
V
-
VIL
VOH
4.0
0
VOL
Nslave(max)
maximum number of slaves driven by one master
12
[1] Measured with respect to pin CGND.
[2] Measured with respect to pin VSSD(HW)
.
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
20 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
13. Dynamic characteristics
Table 11. Switching characteristics
VP = 25 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Internal oscillator
fosc oscillator frequency
Parameter
Conditions
Min
Typ
Max
Unit
Rosc = 39 kΩ
-
320
-
-
kHz
kHz
range
300
500
Timing PWM output: pins OUT1 and OUT2
tr
rise time
IO = 0 A
IO = 0 A
IO = 0 A
-
-
-
10
10
80
-
-
-
ns
ns
ns
tf
fall time
tw(min)
minimum pulse width
Table 12. SE characteristics
VP = 25 V, RL = 2 × 8 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [6] and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
Po(RMS)
RMS output power
continuous time output power
per channel
RL = 4 Ω; VP = 17 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
RL = 8 Ω; VP = 25 V
5.9
-
6.5
6.5
8.3
8.3
-
-
-
-
W
W
W
W
7.5
-
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
7.3
-
8.1
-
-
-
-
W
W
W
W
8.1
9.3
-
10.3
10.3
[2]
short time output power per
channel; THD+N = 10 %,
see Figure 23 for details
RL = 8 Ω; VP = 31 V
THD+N = 0.5 %
THD+N = 10 %
Po = 1 W
11.2
14.1
12.4
15.7
-
-
W
W
[3]
THD+N
total harmonic
distortion-plus-noise
fi = 1 kHz
-
0.011
0.06
30
0.1
0.1
31
1
%
fi = 6 kHz
-
%
Gv(cl)
|∆GV|
αcs
closed-loop voltage gain
voltage gain difference
channel separation
Vi =100 mV; no load
29
-
dB
dB
dB
0.5
Po = 1 W; fi = 1 kHz
Operating mode
fi = 100 Hz
70
80
-
[4]
SVRR
supply voltage ripple
rejection
-
60
-
-
-
dB
dB
kΩ
fi = 1 kHz
40
70
50
|Zi|
input impedance
differential
100
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
21 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
Table 12. SE characteristics …continued
VP = 25 V, RL = 2 × 8 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [6] and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
100
70
Max
150
100
-
Unit
µV
[5]
[5]
Vn(o)
noise output voltage
Operating mode; Rs = 0 Ω
Mute mode
-
-
-
µV
VO(mute)
CMRR
ηpo
mute output voltage
Mute mode; Vi = 1 V (RMS)
and fi = 1 kHz
100
µV
common mode rejection
ratio
Vi(cm) = 1 V (RMS)
-
75
-
dB
output power efficiency
Po = 10 W
VP = 17 V; RL = 4 Ω
VP = 25 V; RL = 8 Ω
86
89
87
90
-
-
%
%
[1] Output power is measured indirectly; based on RDSon measurement.
[2] 2 layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection.
[3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.
[4] Maximum Vripple = 2 V (p-p); RS = 0 Ω.
[5] B = 20 Hz to 20 kHz, AES17 brick wall.
[6] RS is the series resistance of inductor and capacitor of low-pass LC filter in the application.
Table 13. BTL characteristics
VP = 25 V, RL = 16 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [5] and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
Po(RMS)
RMS output power
continuous time output power:
THD+N = 10 %; fi = 1 kHz
RL = 8 Ω; VP = 17 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
RL = 16 Ω; VP = 25 V
11.9
13.2
13.2
17.1
17.1
-
-
-
-
W
W
W
W
-
15.4
-
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
14.9
16.5
16.5
21
-
-
-
-
W
W
W
W
-
18.9
-
21
[2]
short time output power; THD+N
= 10 %, see Figure 35 for details
RL = 16 Ω; VP = 31 V
THD+N = 0.5 %
THD+N = 10 %
Po = 1 W
22.8
28.8
25.3
32
-
-
W
W
[3]
THD+N
total harmonic
distortion-plus-noise
fi = 1 kHz
-
0.04
0.18
36
0.1
0.24
37
-
%
fi = 10 kHz
-
%
Gv(cl)
|Zi|
closed-loop voltage gain
input impedance
35
35
dB
kΩ
differential
50
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
22 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
Table 13. BTL characteristics …continued
VP = 25 V, RL = 16 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [5] and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Rs = 0 Ω
Min
Typ
Max
Unit
Vn(o)
noise output voltage
[4]
[4]
Operating mode
Mute mode
-
-
-
100
70
150
100
-
µV
µV
µV
VO(mute)
CMRR
ηpo
mute output voltage
Mute mode; Vi = 1 V (RMS) and
fi = 1 kHz
100
common mode rejection
ratio
Vi(cm) = 1 V (RMS)
-
75
-
dB
output power efficiency
Po = 17 W; VP = 17 V; RL = 8 Ω
Po = 21 W; VP = 25 V; RL = 16 Ω
87
90
89
92
-
-
%
%
[1] Output power is measured indirectly; based on RDSon measurement.
[2] 2 layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection.
[3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.
[4] B = 22 Hz to 20 kHz, AES17 brick wall.
[5] RS is the series resistance of inductor and capacitor of low-pass LC filter in the application.
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
23 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
14. Application information
14.1 Output power estimation
The output power Po at THD+N = 0.5 %, just before clipping, for the SE and BTL
configurations can be estimated using Equation 2 and Equation 3.
SE configuration:
2
RL
× (1 – tw(min) × f osc) × VP
----------------------------------------------------------
RL + RDSon + Rs + RESR
------------------------------------------------------------------------------------------------------------------------------------------
8 × RL
Po(0.5 %)
=
(2)
(3)
BTL configuration:
2
RL
------------------------------------------------------
RL + 2 × (RDSon + Rs )
--------------------------------------------------------------------------------------------------------------------------------------
2 × RL
× (1 – tw(min) × f osc) × VP
Po(0.5 %)
=
Where:
VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V)
RL = load resistance (Ω)
RDSon = drain-source on-state resistance (Ω)
Rs = series resistance output inductor (Ω)
RESR = equivalent series resistance SE capacitance (Ω)
tw(min) = minimum pulse width (s); 80 ns typical
fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 kΩ
The output power Po at THD+N = 10 % can be estimated by:
Po(10 %) = 1.25 × Po(0.5 %)
(4)
Figure 7 and Figure 8 show the estimated output power at THD+N = 0.5 % and
THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at
different load impedances. The output power is calculated with: RDSon = 0.35 Ω (at
Tj = 25 °C), Rs = 0.05 Ω, RESR = 0.05 Ω and IO(ocp) = 2 A (minimum).
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
24 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
010aaa143
010aaa147
20
20
R
L
= 8 Ω
P
(W)
o
P
(W)
o
R
L
= 8 Ω
16
15
R
= 6 Ω
L
12
8
R = 6 Ω
L
10
5
R
= 4 Ω
L
R
L
= 4 Ω
4
0
0
10
16
22
28
34
10
20
30
36
V
(V)
V (V)
P
P
a. THD+N = 0.5 %
b. THD+N = 10 %
(1) When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP
details.
Fig 7. SE output power as a function of supply voltage
010aaa144
010aaa145
40
40
R
L
= 16 Ω
P
P
o
o
(W)
(W)
R
L
= 16 Ω
30
30
R
L
= 8 Ω
20
10
0
20
10
0
R
L
= 8 Ω
R
L
= 6 Ω
R
= 6 Ω
L
10
20
30
40
10
20
30
40
V
(V)
V (V)
P
P
a. THD+N = 0.5 %
b. THD+N = 10 %
(1) When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP
details.
Fig 8. BTL output power as a function of supply voltage
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
25 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
14.2 Output current limiting
The peak output current IOM is internally limited to 2 A (minimum). During normal
operation the output current should not exceed this threshold level, otherwise the signal is
distorted. The peak output current in SE or BTL configurations can be calculated using
Equation 5 and Equation 6.
SE configuration:
0.5 × VP
IO(max)
≤
≤ 2 A
(5)
(6)
----------------------------------------------------------
RL + RDSon + Rs + RESR
BTL configuration:
VP
IO(max)
≤
≤ 2 A
-----------------------------------------------------
RL + 2 × (RDSon + Rs)
Where:
VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V)
RL = load resistance (Ω)
RDSon = drain-source on-state resistance (Ω)
Rs = series resistance (Ω)
RESR = equivalent series resistance SE capacitance (Ω)
Example:
An 8 Ω speaker in the BTL configuration can be used up to a supply voltage of 18 V
without running into current limiting. Current limiting (clipping) will avoid audio holes but
produces a similar distortion to voltage clipping.
14.3 Speaker configuration and impedance
For a flat frequency response (second order Butterworth filter) it is necessary to change
the low-pass filter components LLC and CLC according to the speaker configuration and
impedance. Table 14 shows the required values in practice.
Table 14. Filter component values
Configuration
RL (Ω)
LLC (µH)
CLC (nF)
680
SE
4
22
33
47
22
47
6
470
8
330
BTL
8
680
16
330
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
26 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
14.4 Single-ended capacitor
The SE capacitor forms a high-pass filter with the speaker impedance. So the frequency
response will roll off with 20 dB per decade below f−3dB (3 dB cut-off frequency).
The 3 dB cut-off frequency is equal to:
1
f –3dB
=
(7)
-----------------------------------
2π × RL × CSE
Where:
−3dB = 3 dB cut-off frequency (Hz)
f
RL = load resistance (Ω)
CSE = single-ended capacitance (F); see Figure 37.
Table 15 shows an overview of the required SE capacitor values in the case of 60 Hz,
40 Hz or 20 Hz 3 dB cut-off frequency.
Table 15. SE capacitor values
Impedance (Ω)
CSE (µF)
−3dB = 60 Hz
f
f
−3dB = 40 Hz
f−3dB = 20 Hz
4
6
8
680
470
330
1000
680
2200
1500
1000
470
14.5 Gain reduction
The gain of the TDA8933 is internally fixed at 30 dB for SE, and 36 dB for BTL. The gain
can be reduced by a resistive voltage divider at the input (see Figure 9).
R1
R2
470 nF
470 nF
100
kΩ
R3
audio in
010aaa137
Fig 9. Input configuration for reducing gain
When applying a resistive divider, the total voltage gain Gv(tot) can be calculated using
Equation 8 and Equation 9:
REQ
Gv(tot) = Gv(cl) + 20log
(8)
-----------------------------------------
REQ + (R1 + R2)
Where:
Gv(tot) = total voltage gain (dB)
Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE (dB)
REQ = equivalent resistance, R3 and Zi (Ω)
TDA8933_1
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Preliminary data sheet
Rev. 01 — 15 May 2007
27 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
R1 = series resistors (Ω)
R2 = series resistors (Ω)
R3 × Zi
REQ
=
(9)
------------------
R3 + Zi
Where:
REQ = equivalent resistance (Ω)
R3 = parallel resistor (Ω)
Zi = internal input impedance (Ω)
Example:
Substituting R1 = R2 = 4.7 kΩ, Zi = 100 kΩ and R3 = 22 kΩ in Equation 8 and Equation 9
results in a gain of Gv(tot) = 26.3 dB.
14.6 Device synchronization
If two or more TDA8933 devices are used in one application it is recommended that all
devices are synchronized at the same switching frequency to avoid beat tones.
Synchronization can be realized by connecting all OSCIO pins together and configuring
one of the TDA8933 devices as master, while the other TDA8933 devices are configured
as slaves (see Figure 10).
A device is configured as master when a resistor Rosc is connected between pin OSCREF
and pin VSSD(HW), setting the carrier frequency. Pin OSCIO of the master is then
configured as an oscillator output for synchronization. The OSCREF pins of the slave
devices should be shorted to pin VSSD(HW), configuring pin OSCIO as an input.
master
slave
IC1
IC2
TDA8933
TDA8933
V
V
SSD(HW) OSCREF
OSCREF SSD(HW) OSCIO
OSCIO
C
R
osc
39 kΩ
osc
100 nF
010aaa138
Fig 10. Master/slave concept in two-chip application
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
28 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
14.7 Thermal behavior (printed-circuit board considerations)
The heat sink in an application with a TDA8933 is made using the copper on the
printed-circuit board. The TDA8933 uses the four corner leads (pins 1, 16, 17 and 32) for
heat transfer from the die to the PCB. The thermal foldback will limit the maximum junction
temperature to 140 °C.
Equation 10 shows the relation between the maximum allowable power dissipation P and
the thermal resistance from junction to ambient.
T j(max) – Tamb
Rth( j – a)
=
(10)
-----------------------------------
P
Where:
Rth(j-a) = thermal resistance from junction to ambient (K/W)
Tj(max) = maximum junction temperature (°C)
Tamb = ambient temperature (°C)
P = power dissipation (W), which is determined by the efficiency of the TDA8933
The power dissipation is shown in Figure 21 (SE) and Figure 33 (BTL).
The thermal resistance, Rth(j-a), of a 2 layer application board (55 mm × 45 mm), 35 µm
copper, FR4 base material in free air with natural convection, is 44 K/W (typ.).
14.8 Pumping effects
When the amplifier is used in an SE configuration, a so-called ‘pumping effect’ can occur.
During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of
that energy is delivered back to the other supply line (e.g. VSSP1), and vice versa. When
the power supply cannot sink energy, the voltage across the output capacitors of that
power supply will increase.
The voltage increase caused by the pumping effect depends on:
• Speaker impedance
• Supply voltage
• Audio signal frequency
• Value of decoupling capacitors on supply lines
• Source and sink currents of other channels
The pumping effect should not cause a malfunction of either the audio amplifier or the
power supply. For instance, this malfunction can be caused by triggering of the
undervoltage or overvoltage protection of the amplifier.
Pumping effects in an SE configuration can be minimized by connecting audio inputs in
anti-phase and changing the polarity of one speaker, as shown in Figure 11.
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
29 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
IN1P
IN1N
OUT1
OUT2
audio
in1
IN2N
IN2P
audio
in2
010aaa140
Fig 11. SE application for reducing pumping effect
14.9 SE curves measured in the reference design
010aaa158
2
10
THD+N
(%)
10
1
−1
(1)
(3)
(2)
10
10
10
−2
−3
−2
−1
2
10
10
1
10
10
P
(W/channel)
o
(1) fi = 6 kHz
(2) fi = 1 kHz
(3) fi = 100 Hz
a. VP = 25 V; RL = 2 × 8 Ω
Fig 12. Total harmonic distortion-plus-noise as a function of output power
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
30 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
010aaa156
2
10
THD+N
(%)
10
1
(1)
(3)
−1
10
(2)
−2
10
−3
10
−2
−1
2
10
10
1
10
10
P
(W/channel)
o
(1) fi = 6 kHz
(2) fi = 1 kHz
(3) fi = 100 Hz
a. VP = 17 V; RL = 2 × 4 Ω
Fig 13. Total harmonic distortion-plus-noise as a function of output power
010aaa159
2
10
THD+N
(%)
10
1
(1)
(2)
−1
10
−2
10
−3
10
2
3
4
5
10
10
10
10
10
f (Hz)
i
(1) Po = 7 W
(2) Po = 1 W
a. VP = 25 V; RL = 2 × 8 Ω
Fig 14. Total harmonic distortion-plus-noise as a function of frequency
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
31 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
010aaa160
2
10
THD+N
(%)
10
1
(1)
(2)
−1
10
−2
10
−3
10
2
3
4
5
10
10
10
10
10
f (Hz)
i
(1) Po = 5 W
(2) Po = 1 W
a. VP = 17 V; RL = 2 × 4 Ω
Fig 15. Total harmonic distortion-plus-noise as a function of frequency
010aaa146
010aaa155
35
0
G
(dB)
v
SVRR
(dB)
30
−20
(2)
(1)
25
20
15
10
−40
(2)
(1)
−60
−80
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
i
f (Hz)
i
Po = 1 W (RMS)
Vripple = 500 mV (RMS) referenced to ground;
Ri = 0 Ω (shorted input)
(1) VP = 17 V; RL = 2 × 4 Ω; CSE = 1000 µF
(2) VP = 25 V; RL = 2 × 8 Ω; CSE = 1000 µF
(1) VP = 17 V; RL = 2 × 4 Ω
(2) VP = 25 V; RL = 2 × 8 Ω
Fig 16. Gain as a function of frequency
Fig 17. Supply voltage ripple rejection as a function of
frequency
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
32 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
010aaa148
010aaa153
120
−20
α
(dB)
cs
S/N
(dB)
−40
80
40
0
−60
−80
(1)
(2)
−100
−2
−1
2
2
3
4
5
10
10
1
10
o
10
(W/channel)
10
10
10
10
10
P
f (Hz)
i
Ri = 0 Ω; 20 kHz brick wall filter AES17
(1) RL = 2 × 4 Ω; VP = 17 V
Po = 1 W; CHVPREF = 47 µF
(1) VP = 17 V; RL = 2 × 4 Ω
(2) VP = 25 V; RL = 2 × 8 Ω
(2) RL = 2 × 8 Ω; VP = 25 V
Fig 18. Signal-to-noise ratio as a function of output
power
Fig 19. Channel separation as a function of frequency
010aaa152
010aaa149
3.0
100
(1)
(2)
P
(W)
η
po
(%)
(1)
(2)
2.0
1.0
0.0
75
50
25
0
−2
−1
2
10
10
1
10
o
10
(W/channel)
P
0
5
10
P
15
(W/channel)
o
ηpo = (2 × Po) / (2 × Po + P)
Power dissipation in junction only.
(1) VP = 17 V; RL = 2 × 4 Ω; fi = 1 kHz
(2) VP = 25 V; RL = 2 × 8 Ω; fi = 1 kHz
(1) VP = 17 V; RL = 2 × 4 Ω; fi = 1 kHz
(2) VP = 25 V; RL = 2 × 8 Ω; fi = 1 kHz
Fig 20. Output power efficiency as a function of output
power
Fig 21. Power dissipation as a function of output power
per channel (two channels driven)
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
33 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
010aaa206
010aaa207
(2)
20
5.0
P
(W)
P
o
(W)
4.0
15
(1)
(1)
3.0
2.0
1.0
0.0
(2)
(3)
(4)
10
5
0
10
20
30
40
10
18
26
34
42
V
(V)
V (V)
P
P
fi = 1 kHz
fi = 1 kHz; power dissipation in junction only; short
time PO at THD+N = 10 %
(1) RL = 2 × 8 Ω SE; THD = 10 %
(2) RL = 2 × 8 Ω SE; THD = 0.5 %
(3) RL = 2 × 4 Ω SE; THD = 10 %
(4) RL = 2 × 4 Ω SE; THD = 0.5 %
(1) RL = 2 × 4 Ω SE
(2) RL = 2 × 8 Ω SE
Fig 22. Output power per channel as a function of
supply voltage
Fig 23. Power dissipation as a function of supply
voltage
010aaa205
010aaa229
20
10
P
o
P
o
(W/channel)
(W/channel)
(1)
16
8
(2)
(1)
12
8
6
4
2
4
0
0
0
0
150
300
450
600
150
300
450
600
time (s)
time (s)
(1) VP = 25 V
(2) VP = 31 V
(1) VP = 17 V
2 layer application board (55 mm × 45 mm), 35 µ
copper, FR4 base material in free air with natural
convection.
a. R = 2 × 8 Ω SE; f = 1 kHz
b. R = 2 × 4 Ω SE; f = 1 kHz
L i
L
i
Fig 24. Output power as a function of time
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
34 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
010aaa227
4
3
2
1
0
V
o
(V)
OPERATING
SLEEP
0.5
0
1
1.5
2
2.5
V
3
(V)
POWERUP
fi = 1 kHz; Vi = 100 mV; VENGAGE > 3 V
Fig 25. Output voltage as a function of voltage on pin POWERUP
010aaa228
4
V
o
(V)
OPERATING
3
2
1
0
MUTE
0
0.5
1
1.5
2
2.5
3
V
V)
ENGAGE (
fi = 1 kHz; Vi = 100 mV
Fig 26. Output voltage as a function of voltage on pin ENGAGE
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
35 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
14.10 BTL curves measured in the reference design
010aaa157
2
10
THD+N
(%)
10
1
−1
10
(1)
−2
(2)
(3)
10
−3
10
−2
−1
2
10
10
1
10
10
P
(W)
o
(1) fi = 6 kHz
(2) fi = 1 kHz
(3) fi = 100 Hz
a. VP = 17 V; RL = 8 Ω
Fig 27. Total harmonic distortion-plus-noise as a function of output power
010aaa161
2
10
THD+N
(%)
10
1
(1)
(2)
−1
10
−2
10
(3)
−3
10
−2
−1
2
10
10
1
10
10
P
(W)
o
(1) fi = 6 kHz
(2) fi = 1 kHz
(3) fi = 100 Hz
a. VP = 25 V; RL = 16 Ω
Fig 28. Total harmonic distortion-plus-noise as a function of output power
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
36 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
010aaa162
2
10
THD+N
(%)
10
1
−1
10
(1)
(2)
−2
10
−3
10
2
3
4
5
10
10
10
10
10
f (Hz)
i
(1) Po = 10 W
(2) Po = 1 W
a. VP = 17 V; RL = 8 Ω
Fig 29. Total harmonic distortion-plus-noise as a function of frequency
010aaa163
2
10
THD+N
(%)
10
1
−1
10
(1)
−2
10
(2)
−3
10
2
3
4
5
10
10
10
10
10
f (Hz)
i
(1) Po = 10 W
(2) Po = 1 W
a. VP = 25 V; RL = 16 Ω
Fig 30. Total harmonic distortion-plus-noise as a function of frequency
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
37 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
010aaa154
45
G
v
(dB)
(1)
(2)
35
25
15
2
3
4
5
10
10
10
10
10
f (Hz)
i
Po = 1 W (RMS)
(1) VP = 17 V; RL = 8 Ω
(2) VP = 25 V; RL = 16 Ω
Fig 31. Gain as a function of frequency
010aaa150
(2)
010aaa151
100
3.0
η
po
(%)
P
(W)
(1)
(1)
75
2.0
(2)
50
25
0
1.0
0.0
−2
−1
2
0
10
20
30
10
10
1
10
10
P (W/channel)
o
P
(W)
o
ηpo = Po / (Po + P)
Power dissipation in junction only.
(1) VP = 17 V; RL = 8 Ω; fi = 1 kHz
(2) VP = 25 V; RL = 16 Ω; fi = 1 kHz
(1) VP = 17 V; RL = 8 Ω; fi = 1 kHz
(2) VP = 25 V; RL = 16 Ω; fi = 1 kHz
Fig 32. Output power efficiency as a function of output
power
Fig 33. Power dissipation as a function of output power
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
38 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
010aaa208
010aaa210
40
5.0
P
(W)
P
(W)
o
4.0
30
(2)
(1)
3.0
2.0
1.0
0.0
(2)
(1)
(3)
(4)
20
10
0
10
15
20
25
30
35
10
18
26
34
42
V
(P)
V (V)
P
P
fi = 1 kHz
fi = 1 kHz; power dissipation in junction only; short
time PO at THD+N = 10 %
(1) RL = 16 Ω BTL; THD = 10 %
(2) RL = 16 Ω BTL; THD = 0.5 %
(3) RL = 8 Ω BTL; THD = 10 %
(4) RL = 8 Ω BTL; THD = 0.5 %
(1) RL = 8 Ω BTL
(2) RL = 16 Ω BTL
Fig 34. Output power as a function of supply voltage
Fig 35. Power dissipation as a function of supply
voltage
010aaa209
010aaa230
32
(2)
20
(1)
P
(W)
o
P
(W)
o
16
24
(1)
12
8
16
8
4
0
0
0
120
240
360
480
600
0
150
300
450
600
time (s)
time (s)
(1) VP = 25 V
(2) VP = 31 V
(1) VP = 17 V
2 layer application board (55 mm × 45 mm), 35 µ
copper, FR4 base material in free air with natural
convection.
a. R = 16 Ω BTL; f = 1 kHz
b. R = 8 Ω BTL; f = 1 kHz
L i
L
i
Fig 36. Output power as a function of time
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
39 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
14.11 Typical application schematics (simplified)
V
V
SSD(HW)
SSD(HW)
IN1P
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
SSA
SSA
Cin
470 nF
OSCIO
HVP1
+
2
IN1N
DIAG
−
3
Csn
470 pF
Cvddp
100 nF
Cvssp
100 nF
Cin
V
DDP1
470 nF
4
V
V
SS
DD
Rsn
10 Ω
Rbo
ENGAGE
POWERUP
CGND
BOOT1
OUT1
MUTE
5
CONTROL
Cen
470 nF
1 M
Cbo
15 nF
LIc
+
6
SLEEP
CONTROL
−
V
SSP1
CIc
7
V
STAB1
STAB2
DDA
8
V
V
DDA
SSA
Cosc
100 nF
U1
TDA8933
V
SSA
9
Cstab
100 nF
Rosc
V
OSCREF
HVPREF
INREF
TEST
SSP2
10
11
12
13
14
15
16
V
V
SSA
SS
SS
39 Ω
LIc
−
OUT2
Cbo
15 nF Rbo
+
Rsn
CIc
BOOT2
10 Ω
1 M
Cinref
100 nF
V
DDP2
V
V
Cvssp
100 nF
DD
Cin
470 nF
Cvddp
100 nF
Csn
470 pF
HVP2
DREF
IN2N
+
IN2P
−
Cdref
100 nF
Cin
470 nF
V
V
SSD(HW)
SSD(HW)
V
V
SSA
SSA
V
DD
Rvdda
Cvddp
220 µF/25 V
V
V
DD
DDA
SSA
10 Ω
Cvdda
100 nF
GND
Cvssa
100 nF
Rvssa
Cvssp
220 µF/25 V
V
V
SS
10 Ω
V
010aaa142
SS
Fig 37. Typical simplified application diagram for 2 × SE (symmetrical supply)
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
40 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
V
V
SSD(HW)
SSD(HW)
IN1P
1
2
3
4
5
6
32
31
30
29
28
27
V
V
SSA
Cin
470 nF
SSA
OSCIO
HVP1
+
IN1N
DIAG
Cvddp
100 nF
Cvssp
100 nF
Csn
470 pF
−
Cin
V
DDP1
470 nF
V
V
DD
SS
Rbo
Rsn
10 Ω
ENGAGE
BOOT1
OUT1
MUTE
CONTROL
Cen
470 nF
Cbo
15 nF
1 M
LIc
POWERUP
CGND
V
SSP1
SLEEP
CIc
7
8
26
25
CONTROL
V
STAB1
STAB2
DDA
+
V
V
DDA
Cosc
100 nF
U1
TDA8933
V
SSA
−
9
24
23
22
21
20
19
18
17
SSA
Cstab
100 nF
Rosc
V
OSCREF
HVPREF
SSP2
CIc
V
V
10
11
12
13
14
15
16
SS
SSA
39 Ω
LIc
OUT2
Cbo
15 nF Rbo
Rsn
10 Ω
INREF
TEST
IN2N
BOOT2
Cinref
100 nF
1 M
V
DDP2
V
V
DD
SS
HVP2
DREF
Cvddp
100 nF
Cvssp
Csn
100 nF
470 pF
IN2P
Cdref
V
V
V
SSD(HW)
SSD(HW)
V
SSA
SSA
V
DD
Rvdda
Cvddp
220 µF/25 V
V
V
Cvdda
100 nF
DD
DDA
10 Ω
GND
Cvssa
100 nF
Rvssa
Cvssp
V
V
220 µF/25 V
SSA
SS
10 Ω
010aaa141
V
SS
Fig 38. Typical simplified application diagram for 1 × BTL (symmetrical supply)
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
41 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
VP
Rvdda
VP
VPA
10 Ω
Cvdda
100 nF
Cvddp
220 µF/35 V
GND
V
V
SSD(HW)
SSD(HW)
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Cin
470 nF
IN1P
IN1N
OSCIO
HVP1
Chvp
2
+
100 nF
Csn
470pF
−
3
Cvddp
100 nF
HVP1
Cin
V
DDP1
DIAG
470 nF
4
VP
Rsn
10 Ω
Rbo
1 M
BOOT1
OUT1
ENGAGE
POWERUP
CGND
MUTE
CONTROL
5
Cbo
15 nF
Cen
470 nF
LIc
+
6
SLEEP
−
V
SSP1
CONTROL
7
HVP1
Cse
CIc
V
DDA
STAB1
STAB2
8
VPA
Cosc
U1
TDA8933
V
SSA
100 nF
9
Cstab
V
100 nF
SSP2
Rosc
OSCREF
HVPREF
10
11
12
13
14
15
16
39 Ω
LIc
−
OUT2
Cbo
15 nF Rbo
+
Chvpref
47 µF/25 V
Chvp
100 nF
Rsn
10 Ω
INREF
TEST
IN2N
BOOT2
HVP2
1 M
Cse
Cinref
CIc
V
DDP2
100 nF
VP
Cvddp
100 nF
Cin
470 nF
Csn
HVP2
DREF
470 pF
+
IN2P
HVP2
−
Cdref
100 nF
Chvp
100 nF
Cin
470 nF
V
V
SSD(HW)
SSD(HW)
010aaa193
Fig 39. Typical simplified application diagram for 2 × SE (asymmetrical supply)
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
42 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
VP
Rvdda
VP
VPA
10 Ω
Cvdda
100 nF
Cvddp
220 µF/35 V
GND
V
V
SSD(HW)
SSD(HW)
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Cin
470 nF
Chvp
100 nF
IN1P
IN1N
OSCIO
HVP1
HVPREF
2
+
Rhvp
Csn
470 pF
−
3
Cvddp
100 nF
470 Ω
Cin
V
DDP1
DIAG
470 nF
4
VP
Rsn
10 Ω
Rbo
1 M
BOOT1
OUT1
ENGAGE
MUTE
CONTROL
5
Cbo
15 nF
Cen
LIc
470 nF POWERUP
6
SLEEP
CONTROL
V
CGND
SSP1
7
Clc
Clc
V
DDA
STAB1
STAB2
+
8
VPA
Cosc
100 nF
U1
TDA8933
V
SSA
−
9
Cstab
100 nF
Rosc
V
SSP2
OSCREF
HVPREF
10
11
12
13
14
15
16
39 Ω
LIc
OUT2
HVPREF
Cbo
15 nF Rbo
Chvp
100 nF
Rsn
10 Ω
INREF
TEST
IN2N
BOOT2
1 M
Cinref
100 nF
V
DDP2
VP
Cvddp
100 nF
Csn
470 pF
HVP2
DREF
Rhvp
470 Ω
IN2P
HVPREF
Cdref
100 nF
Chvp
100 nF
V
V
SSD(HW)
SSD(HW)
010aaa194
Fig 40. Typical simplified application diagram for 1 × BTL (asymmetrical supply)
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
43 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
15. Package outline
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
H
v
M
A
E
Z
17
32
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
16
1
w
M
detail X
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
0.3
0.1
2.45
2.25
0.49
0.36
0.27 20.7
0.18 20.3
7.6
7.4
10.65
10.00
1.1
0.4
1.2
1.0
0.95
0.55
mm
2.65
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.02 0.011 0.81
0.01 0.007 0.80
0.30
0.29
0.419
0.394
0.043 0.047
0.016 0.039
0.037
0.022
inches
0.1
0.004
0.055
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-08-17
03-02-19
SOT287-1
MO-119
Fig 41. Package outline SOT287-1 (SO32)
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
44 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
16. Revision history
Table 16. Revision history
Document ID
Release date
20070515
Data sheet status
Change notice
Supersedes
TDA8933_1
Preliminary data sheet
-
-
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
45 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
17.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
TDA8933_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 May 2007
46 of 47
TDA8933
NXP Semiconductors
Class-D audio amplifier
19. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
17.3
17.4
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 46
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
8.1
8.2
8.3
Functional description . . . . . . . . . . . . . . . . . . . 6
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mode selection and interfacing. . . . . . . . . . . . . 7
Pulse width modulation frequency . . . . . . . . . . 8
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Foldback (TF) . . . . . . . . . . . . . . . . . . 10
OverTemperature Protection (OTP) . . . . . . . . 10
OverCurrent Protection (OCP) . . . . . . . . . . . . 10
Window Protection (WP). . . . . . . . . . . . . . . . . 10
Supply voltage protections . . . . . . . . . . . . . . . 10
Diagnostic input and output . . . . . . . . . . . . . . 12
Differential inputs . . . . . . . . . . . . . . . . . . . . . . 12
Output voltage buffers. . . . . . . . . . . . . . . . . . . 13
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.6
8.7
9
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 14
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal characteristics. . . . . . . . . . . . . . . . . . 18
Static characteristics. . . . . . . . . . . . . . . . . . . . 19
Dynamic characteristics . . . . . . . . . . . . . . . . . 21
10
11
12
13
14
Application information. . . . . . . . . . . . . . . . . . 24
Output power estimation. . . . . . . . . . . . . . . . . 24
Output current limiting. . . . . . . . . . . . . . . . . . . 26
Speaker configuration and impedance . . . . . . 26
Single-ended capacitor. . . . . . . . . . . . . . . . . . 27
Gain reduction . . . . . . . . . . . . . . . . . . . . . . . . 27
Device synchronization. . . . . . . . . . . . . . . . . . 28
Thermal behavior (printed-circuit board
14.1
14.2
14.3
14.4
14.5
14.6
14.7
considerations) . . . . . . . . . . . . . . . . . . . . . . . . 29
Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 29
SE curves measured in the reference design. 30
BTL curves measured in the reference design 36
Typical application schematics (simplified) . . . 40
14.8
14.9
14.10
14.11
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 45
17
17.1
17.2
Legal information. . . . . . . . . . . . . . . . . . . . . . . 46
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 May 2007
Document identifier: TDA8933_1
相关型号：
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IC 1.5 W, 2 CHANNEL, AUDIO AMPLIFIER, PDIP16, 0.300 INCH, PLASTIC, SOT-38-1, MO-001, DIP-16, Audio/Video Amplifier
NXP
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