TDA9875AH [NXP]
Digital TV Sound Processor DTVSP; 数字电视音频处理器DTVSP型号: | TDA9875AH |
厂家: | NXP |
描述: | Digital TV Sound Processor DTVSP |
文件: | 总96页 (文件大小:319K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA9875A
Digital TV Sound Processor
(DTVSP)
Product specification
1999 Dec 20
Supersedes data of 1998 Aug 13
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
CONTENTS
10
I2C-BUS CONTROL
10.1
10.2
10.3
10.4
10.5
Introduction
Power-up state
Slave receiver mode
Slave transmitter mode
Expert mode
1
FEATURES
1.1
1.2
1.3
Demodulator and decoder section
DSP section
Analog audio section
2
GENERAL DESCRIPTION
Supported standards
ORDERING INFORMATION
BLOCK DIAGRAM
11
12
13
14
I2S-BUS DESCRIPTION
2.1
3
APPLICATION INFORMATION
PACKAGE OUTLINES
SOLDERING
4
5
PINNING
14.1
14.2
14.3
14.4
Introduction
Through-hole mount packages
Surface mount packages
Suitability of IC packages for wave, reflow and
dipping soldering methods
6
FUNCTIONAL DESCRIPTION
6.1
6.2
6.3
Demodulator and decoder section
Digital signal processing
Analog audio section
15
16
17
DEFINITIONS
7
8
9
LIMITING VALUES
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
THERMAL CHARACTERISTICS
CHARACTERISTICS
1999 Dec 20
2
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
1
FEATURES
1.1
Demodulator and decoder section
• Sound IF (SIF) input switch e.g. to select between
terrestrial TV SIF and SAT SIF sources
• SIF AGC with 24 dB control range
• Dual audio Digital-to-Analog Converter (DAC) from DSP
to analog crossbar switch, bandwidth 15 kHz
• SIF 8-bit Analog-to-Digital Converter (ADC)
• Differential Quadrature Phase Shift Keying (DQPSK)
demodulation for different standards, simultaneously
with 1-channel FM demodulation
• Dual audio ADC from analog inputs to DSP
• Two dual audio DACs for loudspeaker (Main) and
headphone (Auxiliary) outputs; also applicable for
L, R, C and S in the Dolby Pro Logic mode with feature
extension.
• Near Instantaneous Companded Audio Multiplex
(NICAM) decoding (B/G, I and L standard)
• Two-carrier multistandard FM demodulation
(B/G, D/K and M standard)
2
GENERAL DESCRIPTION
• Decoding for three analog multi-channel systems
(A2, A2+ and A2*) and satellite sound
The TDA9875A is a single-chip Digital TV Sound
Processor (DTVSP) for analog and digital multi-channel
sound systems in TV sets and satellite receivers.
• Optional AM demodulation for system L, simultaneously
with NICAM
• Programmable identification (B/G, D/K and M standard)
and different identification times.
2.1
Supported standards
The multistandard/multi-stereo capability of the
TDA9875A is mainly of interest in Europe, but also in
Hong Kong/Peoples Republic of China and
South East Asia. This includes B/G, D/K, I, M and L
standards. In other application areas there exists only
subsets of these standard combinations otherwise only
single standards are transmitted.
1.2
DSP section
• Digital crossbar switch for all digital signal sources and
destinations
• Control of volume, balance, contour, bass, treble,
pseudo stereo, spatial, bass boost and soft mute
• Plop-free volume control
M standard is transmitted in Europe by the American
Forces Network (AFN) with European channel spacing
(7 MHz VHF and 8 MHz UHF) and monaural sound.
• Automatic Volume Level (AVL) control
• Adaptive de-emphasis for satellite
• Programmable beeper
The AM sound of L/L accent standard is normally
demodulated in the first sound IF. The resulting AF signal
has to be entered into the mono audio input of the
TDA9875A. A second possibility is to use the internal
AM demodulator stage, however this gives limited
performance.
• Monitor selection for FM/AM DC values and signals,
with peak detection option
• I2S-bus interface for a feature extension (e.g. Dolby Pro
Logic) with matrix, level adjust and mute.
Korea has a stereo sound system similar to Europe and is
supported by the TDA9875A. The differences include
deviation, modulation contents and identification. It is
based on M standard.
1.3
Analog audio section
• Analog crossbar switch with inputs for mono and stereo
(also applicable as SCART 3 input), SCART 1
input/output, SCART 2 input/output and line output
An overview of the supported standards and sound
systems and their key parameters is given in Table 1.
• User defined full-level/−3 dB scaling for SCART outputs
• Output selection of mono, stereo, dual A/B, dual A or
dual B
The analog multi-channel sound systems (A2, A2+ and
A2*) are 2-Carrier Systems (2CS).
• 20 kHz bandwidth for SCART-to-SCART copies
• Standby mode with function for SCART copies
1999 Dec 20
3
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
2.1.1
ANALOG 2-CARRIER SYSTEMS
Table 1 Frequency modulation
CARRIER
FREQUENCY
(MHz)
FM DEVIATION (kHz)
NOM. MAX. OVER
MODULATION
BANDWIDTH/
DE-EMPHASIS
(kHz/µs)
SOUND
SYSTEM
STANDARD
SC1
mono
1⁄2(L + R) 1⁄2(L − R) 15/75 (Korea)
SC2
M
mono
4.5
15
15
27
27
27
27
25
25
50
50
50
50
50
50
80
80
80
80
−
15/75
M
A2+
A2
4.5/4.724
5.5/5.742
6.0
B/G
I
1⁄2(L + R)
R
−
15/50
15/50
15/50
15/50
mono
A2
mono
D/K
D/K
6.5/6.742
6.5/6.258
1⁄2(L + R)
1⁄2(L + R)
R
R
A2*
Table 2 Identification for A2 systems
PARAMETER
A2/A2*
A2+ (KOREA)
Pilot frequency
54.6875 kHz = 3.5 × line frequency 55.0699 kHz = 3.5 × line frequency
Stereo identification frequency
line frequency
------------------------------------
133
line frequency
------------------------------------
105
117.5 Hz =
149.9 Hz =
Dual identification frequency
AM modulation depth
line frequency
------------------------------------
57
line frequency
------------------------------------
57
274.1 Hz =
276.0 Hz =
50%
50%
2.1.2
2-CARRIER SYSTEMS WITH NICAM
Table 3 NICAM
SC1
MODULATION
SC2
NICAM
(MHz)
DE-
ROLL-
NICAM
STANDARD
FREQUENCY
INDEX
(%)
DEVIATION
(kHz)
EMPHASIS OFF (%) CODING
TYPE
(MHz)
NOM. MAX. NOM. MAX.
B/G
I
5.5
6.0
6.5
6.5
FM
FM
FM
AM
−
−
−
−
27
27
27
−
50
50
50
−
5.85
6.552
5.85
J17
J17
J17
J17
40
100
40
note 1
note 1
note 2
note 1
D/K
L
−
−
54
100
5.85
40
Notes
1. See “EBU specification” or equivalent specification.
2. Not yet defined.
1999 Dec 20
4
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
2.1.3
SATELLITE SYSTEMS
An important specification for satellite TV reception is the ‘Astra specification’. The TDA9875A is suited for the reception
of Astra and other satellite signals.
Table 4 FM satellite sound
CARRIER
FREQUENCY
(MHz)
MAXIMUM
FM DEVIATION
(kHz)
BANDWIDTH/
DE-EMPHASIS
(kHz/µs)
MODULATION
INDEX
CARRIER TYPE
MODULATION
Main
Sub
Sub
Sub
Sub
6.50(1)
0.26
0.15
85
50
mono
m/st/d(3)
15/50(2)
15/adaptive(4)
7.02/7.20
7.38/7.56
7.74/7.92
8.10/8.28
Notes
1. For other satellite systems, frequencies of e.g. 5.80, 6.60 or 6.65 MHz can also be received.
2. A de-emphasis of 60 µs, or in accordance with J17, is available.
3. m/st/d = mono, stereo or dual language sound.
4. Adaptive de-emphasis is compatible to transmitter specification.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TDA9875A
TDA9875AH
SDIP64
QFP64
plastic shrink dual in-line package; 64 leads (750 mil)
SOT274-1
SOT393-1
plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14 × 14 × 2.7 mm
1999 Dec 20
5
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
4
BLOCK DIAGRAM
SIF2
SIF1
12 (4)
10 (2)
9 (1)
P1
P2
(63) 7
(62) 6
(3) 11
(64) 8
20 (12)
3 (59)
13 (5)
4 (60)
5 (61)
V
DEC1
SUPPLY
SOUND IF
(SIF)
ADDR1
ADDR2
SCL
V
2
SSA1
I C-BUS
INPUT SWITCH
AGC, ADC
INTERFACE
V
ref1
I
ref
SDA
(58) 2
(57) 1
NICAM
PCLK
FM (AM)
DEMODULATION
NICAM
DEMODULATION
IDENTIFICATION
(25) 33
(26) 34
SCIR1
SCIL1
SCIR2
SCIL2
EXTIR
EXTIL
18 (10)
19 (11)
21 (13)
XTALI
(28) 36
(29) 37
A2/SATELLITE
DECODER
NICAM
DECODER
CLOCK
XTALO
SYSCLK
(23) 31
(24) 32
(21) 29
ANALOG
CROSSBAR
SWITCH
MONOIN
(39) 47
SCOR1
SCOL1
SCOR2
SCOL2
LOR
(40) 48
(43) 51
(44) 52
(55) 63
(54) 62
LEVEL
ADJUST
LEVEL
ADJUST
PEAK
DETECTION
LOL
27 (19)
26 (18)
25 (17)
24 (16)
22 (14)
23 (15)
SDI1
SDI2
SDO1
SDO2
SCK
(33) 41
(34) 42
(36) 44
(37) 45
i.c.
i.c.
i.c.
i.c.
ADC (2)
2
I S-BUS
INTERFACE
DIGITAL
SELECT
WS
15 (7)
64 (56)
14 (6)
49 (41)
35 (27)
17 (9)
16 (8)
V
DDD1
DAC (2)
(46) 54
(47) 55
V
PCAPR
PCAPL
DDD2
V
SSD1
DIGITAL
SUPPLY
V
SSD2
V
SSD3
(51) 59
(30) 38
V
V
SSD4
DDA
AUDIO PROCESSING
V
CRESET
DEC2
(31) 39
(32) 40
V
ref(p)
TDA9875A
TDA9875AH
V
ref(n)
SUPPLY
SCART,
DAC,
(
)
(38) 46
(45) 53
V
ref2
DAC (2)
DAC (2)
ADC
28 (20)
30 (22)
V
ref3
TEST1
TEST2
TEST
(35) 43
(48) 56
(42) 50
V
SSA2
V
SSA3
V
SSA4
(53)
61
(52)
60
(50)
58
(49)
57
MHB598
MOL MOR
AUXOL AUXOR
The pin numbers given in parenthesis refer to the TDA9875AH version.
Fig.1 Block diagram.
6
1999 Dec 20
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
5
PINNING
PIN
PIN
SYMBOL
DESCRIPTION
NICAM clock output at 728 kHz
TYPE(1)
TDA9875A TDA9875AH
PCLK
NICAM
ADDR1
SCL
1
57
58
59
60
61
62
63
64
1
O
O
I
2
serial NICAM data output at 728 kHz
I2C-bus slave address input 1
I2C-bus clock input
3
4
I
SDA
5
I/O
S
−
−
I/O
I
I2C-bus data input/output
VSSA1
VDEC1
Iref
6
supply ground 1; analog front-end circuitry
7
supply voltage decoupling 1; analog front-end circuitry
resistor for reference current generator; analog front-end circuitry
general purpose input/output pin 1
sound IF input 2
8
P1
9
SIF2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
2
Vref1
3
−
I
reference voltage 1; analog front-end circuitry
sound IF input 1
I2C-bus slave address input 2
SIF1
4
ADDR2
VSSD1
VDDD1
CRESET
VSSD4
XTALI
XTALO
P2
5
I
6
S
S
−
S
I
supply ground 1; digital circuitry
digital supply voltage 1; digital circuitry
capacitor for Power-on reset
7
8
9
supply ground 4; digital circuitry
crystal oscillator input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
O
I/O
O
I/O
I/O
O
O
I
crystal oscillator output
general purpose input/output pin 2
SYSCLK
SCK
system clock output
I2S-bus clock input/output
WS
I2S-bus word select input/output
I2S-bus data output 2 (I2S2 output)
I2S-bus data output 1 (I2S1 output)
I2S-bus data input 2 (I2S2 input)
I2S-bus data input 1 (I2S1 input)
test pin 1; connected to VSSD1 for normal operating mode
audio mono input
SDO2
SDO1
SDI2
SDI1
I
TEST1
MONOIN
TEST2
EXTIR
EXTIL
SCIR1
SCIL1
VSSD3
SCIR2
SCIL2
VDEC2
I
I
I
test pin 2; connected to VSSD1 for normal operating mode
external audio input right channel
external audio input left channel
SCART 1 input right channel
I
I
I
I
SCART 1 input left channel
S
I
supply ground 3; digital circuitry
SCART 2 input right channel
I
SCART 2 input left channel
−
supply voltage decoupling 2; audio analog-to-digital converter
circuitry
1999 Dec 20
7
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
PIN
PIN
SYMBOL
DESCRIPTION
TYPE(1)
TDA9875A TDA9875AH
Vref(p)
Vref(n)
39
31
−
−
positive reference voltage; audio analog-to-digital converter
circuitry
40
32
reference voltage ground; audio analog-to-digital converter
circuitry
i.c.
41
42
43
44
45
46
47
48
49
50
51
52
53
33
34
35
36
37
38
39
40
41
42
43
44
45
−
−
internally connected; note 2
i.c.
internally connected; note 3
VSSA2
i.c.
S
−
supply ground 2; audio analog-to-digital converter circuitry
internally connected; note 3
i.c.
−
internally connected; note 2
Vref2
−
reference voltage 2; audio analog-to-digital converter circuitry
SCART 1 output right channel
SCOR1
SCOL1
VSSD2
VSSA4
SCOR2
SCOL2
Vref3
O
O
S
S
O
O
−
SCART 1 output left channel
supply ground 2; digital circuitry
supply ground 4; audio operational amplifier circuitry
SCART 2 output right channel
SCART 2 output left channel
reference voltage 3; audio digital-to-analog converter and
operational amplifier circuitry
PCAPR
PCAPL
54
55
46
47
−
−
post-filter capacitor pin right channel; audio digital-to-analog
converter
post-filter capacitor pin left channel; audio digital-to-analog
converter
VSSA3
AUXOR
AUXOL
VDDA
56
57
58
59
60
61
62
63
64
48
49
50
51
52
53
54
55
56
S
O
O
S
supply ground 3; audio digital-to-analog converter circuitry
headphone (Auxiliary) output right channel
headphone (Auxiliary) output left channel
analog supply voltage; analog circuitry
loudspeaker (Main) output right channel
loudspeaker (Main) output left channel
line output left channel
MOR
MOL
O
O
O
O
S
LOL
LOR
line output right channel
VDDD2
digital supply voltage 2; digital circuitry
Notes
1. Pin type: I = input, O = output, S = supply.
2. Test pin: CMOS level input; pull-up resistor; can be connected to VSS
3. Test pin: CMOS 3-state stage; can be connected to VSS
.
.
1999 Dec 20
8
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
handbook, halfpage
PCLK
NICAM
ADDR1
SCL
1
2
3
4
5
6
7
8
9
64 V
DDD2
63 LOR
62 LOL
61 MOL
60 MOR
SDA
V
59 V
DDA
SSA1
V
58 AUXOL
57 AUXOR
DEC1
I
ref
P1
56 V
SSA3
SIF2 10
11
55 PCAPL
54 PCAPR
V
ref1
SIF1 12
53 V
ref3
ADDR2 13
52 SCOL2
51 SCOR2
V
V
14
15
SSD1
50
49
V
V
DDD1
SSA4
SSD2
CRESET 16
17
TDA9875A
V
48 SCOL1
47 SCOR1
SSD4
XTALI 18
XTALO 19
P2 20
46
V
ref2
45 i.c.
44 i.c.
SYSCLK 21
SCK 22
43
V
SSA2
WS 23
42 i.c.
41 i.c.
SDO2 24
SDO1 25
SDI2 26
40
39
38
V
V
V
ref(n)
ref(p)
DEC2
SDI1 27
TEST1 28
MONOIN 29
TEST2 30
EXTIR 31
EXTIL 32
37 SCIL2
36 SCIR2
35
V
SSD3
34 SCIL1
33 SCIR1
MHB071
Fig.2 Pin configuration (TDA9875A).
9
1999 Dec 20
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
V
P1
1
2
3
4
5
6
7
8
9
48
47
46
45
44
SSA3
PCAPL
PCAPR
SIF2
V
ref1
V
SIF1
ref3
ADDR2
SCOL2
V
43 SCOR2
SSD1
V
V
V
42
41
DDD1
SSA4
SSD2
CRESET
TDA9875AH
V
40 SCOL1
39 SCOR1
SSD4
XTALI 10
XTALO 11
P2 12
V
38
ref2
37 i.c.
36 i.c.
V
SYSCLK 13
SCK 14
35
34
SSA2
WS
i.c.
15
16
SDO2
33 i.c.
MHB599
Fig.3 Pin configuration (TDA9875AH).
10
1999 Dec 20
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
6
FUNCTIONAL DESCRIPTION
6.1.5
FM IDENTIFICATION
6.1
Demodulator and decoder section
The identification of the FM sound mode is performed by
AM synchronous demodulation of the pilot signal and
narrow-band detection of the identification frequencies.
The result is available via the I2C-bus interface. A selection
can be made via the I2C-bus for B/G, D/K and M standard
and for three different modes that represent different
trade-offs between speed and reliability of identification.
6.1.1
SIF INPUT
Two input pins are provided: SIF1 e.g. for terrestrial TV
and SIF2 e.g. for a satellite tuner. For higher SIF signal
levels the SIF input can be attenuated with an internal
switchable −10 dB resistor divider. As no specific filters are
integrated, both inputs have the same specification giving
flexibility in application. The selected signal is passed
through an AGC circuit and then digitized by an 8-bit ADC
operating at 24.576 MHz.
6.1.6
NICAM DEMODULATION
The NICAM signal is transmitted in a DQPSK code at a bit
rate of 728 kbit/s. The NICAM demodulator performs
DQPSK demodulation and feeds the resulting bitstream
and clock signal onto the NICAM decoder and, for
evaluation purposes, to pins PCLK and NICAM.
6.1.2
AGC
The gain of the AGC amplifier is controlled from the ADC
output by means of a digital control loop employing
hysteresis. The AGC has a fast attack behaviour to
prevent ADC overloads and a slow decay behaviour to
prevent AGC oscillations. For AM demodulation the AGC
must be switched off. When switched off, the control loop
is reset and fixed gain settings can be chosen
(see Table 15).
A timing loop controls the frequency of the crystal oscillator
to lock the sampling rate to the symbol timing of the
NICAM data.
6.1.7
NICAM DECODER
The device performs all decoding functions in accordance
with the “EBU NICAM 728 specification”. After locking to
the frame alignment word, the data is descrambled by
applying the defined pseudo-random binary sequence and
the device will then synchronize to the periodic frame flag
bit C0.
The AGC can be controlled via the I2C-bus. Details can be
found in the I2C-bus register definitions (see Chapter 10).
6.1.3
MIXER
The digitized input signal is fed to the mixers, which mix
one or both input sound carriers down to zero IF. A 24-bit
control word for each carrier sets the required frequency.
Access to the mixer control word registers is via the
I2C-bus. When receiving NICAM programs, a feedback
signal is added to the control word of the second carrier
mixer to establish a carrier-frequency loop.
Bit VDSP (see Section 10.4.1) indicates that the decoder
has locked to the NICAM data and that the data is valid
sound data.
The status of the NICAM decoder can be read out from the
NICAM status register by the user (see Section 10.4.2).
Bit OSB indicates that the decoder has locked to the
NICAM data. Bit C4 indicates that the sound conveyed by
the FM mono channel is identical to the sound signal
conveyed by the NICAM channel.
6.1.4
FM AND AM DEMODULATION
An FM or AM input signal is fed via a band-limiting filter to
a demodulator that can be used for either FM or AM
demodulation. Apart from the standard (fixed)
de-emphasis characteristic, an adaptive de-emphasis is
available for encoded satellite programs. A stereo decoder
recovers the left and right signal channels from the
demodulated sound carriers. Both the European and
Korean stereo systems are supported.
The error byte contains the number of sound sample
errors, resulting from parity checking, that occurred in the
past 128 ms period. The Bit Error Rate (BER) can be
calculated using the following equation:
bit errors
total bits
BER =
≈ error byte × 1.74 × 10–5
-----------------------
1999 Dec 20
11
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
6.1.8
NICAM AUTO-MUTE
Bit CLRPOR (see Section 10.3.2) resets the Power-on
reset flip-flop to LOW. If this is detected, an initialization of
the TDA9875A has to be carried out to ensure reliable
operation.
This function is enabled by setting bit AMUTE to logic 0
(see Section 10.3.11).
Upper and lower error limits may be defined by writing
appropriate values to two registers in the I2C-bus section
(see Sections 10.3.13 and 10.3.14). When the number of
errors in a 128 ms period exceeds the upper error limit the
auto-mute function will switch the output sound from
NICAM to whatever sound is on the first sound carrier
(FM or AM). When the error count is smaller than the lower
error limit the NICAM sound is restored.
6.1.12 POWER-ON RESET
The reset is active LOW. In order to perform a reset at
power-up, a simple RC circuit may be used which consists
of the integrated passive pull-up resistor and an external
capacitor connected to ground. The pull-up resistor has a
nominal value of 50 kΩ, which can easily be measured
between pins CRESET and VDDD2. Before the supply
voltage has reached a certain minimum, the state of the
circuit is completely undefined, and it remains in this
undefined state unless a reset is applied.
The auto-mute function can be disabled by setting
bit AMUTE to logic 1. In this condition clicks become
audible when the error count increases; the user will hear
a signal of degrading quality.
The reset is guaranteed to be active when:
A decision to enable/disable the auto-muting is taken by
the microcontroller based on an interpretation of the
application control bits C1, C2, C3 and C4 and, possibly,
any additional strategy implemented by the set maker in
the microcontroller software.
• The power supply is within the specified limits
(4.75 and 5.5 V)
• The crystal oscillator is functioning
• The voltage at pin CRESET is below 0.3VDDD (1.5 V if
VDDD = 5.0 V, typically below 1.8 V).
For NICAM L applications, it is recommended to
demodulate AM sound in the first sound IF and connect
the audio signal to the mono input of the TDA9875A.
By setting bit AMSEL (see Section 10.3.11), the
auto-mute function will switch to the audio ADC instead of
switching to the first sound carrier. The ADC source
selector (see Section 10.3.20) should be set to mono
input, where the AM sound signal should be connected.
The required capacitor value depends on the gradient of
the rising power supply voltage. The time constant of the
RC circuit should be clearly larger than the rise time of the
power supply, to make sure that the reset condition is
always satisfied (see Fig.4), even considering the
tolerance spread. To avoid problems with a too slow
discharging of the capacitor at power-down, it may be
helpful to add a diode from pin CRESET to VDDD. It should
be noted that the internal ESD protection diode does not
help here as it only conducts at higher voltages. Under
difficult power supply conditions (e.g. very slow or
non-monotonic ramp-up), it is recommended to drive the
reset line from a microcontroller port or the like.
6.1.9
CRYSTAL OSCILLATOR
The circuitry of the crystal oscillator is fully integrated, only
the external 24.576 MHz crystal is needed (see Fig.10).
6.1.10 TEST PINS
Test pins TEST1 and TEST2 are active HIGH and in the
normal operating mode of the device they are connected
to VSSD1. Test functions are for manufacturing tests only
and are not available to customers. Without external
circuitry these pins are pulled down to a LOW level with
internal resistors.
MHB595
handbook, halfpage
V
> 4.75 V
DDD
5
voltage
(V)
V
< 0.3V
DDD
CRESET
1.5
6.1.11 POWER FAIL DETECTOR
reset active
guaranteed
The power fail detector monitors the internal power supply
for the digital part of the device. If the supply has
temporarily been lower than the specified lower limit, the
Power-on reset bit POR (see Section 10.4.1), will be set to
logic 1.
t
Fig.4 Reset at power-on.
1999 Dec 20
12
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2
2
2
SPATIAL
PSEUDO
VOLUME
BASS/TREBLE
BASS BOOST
CONTOUR
SOFT-MUTE
BEEPER
LEVEL ADJUST
2
2
4
AUTOMATIC
VOLUME
LEVEL
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DC
FILTER
from ADC
MATRIX
MATRIX
MATRIX
MATRIX
MATRIX
Main
LEVEL ADJUST
LEVEL ADJUST
LEVEL ADJUST
LEVEL ADJUST
VOLUME
SOFT-MUTE
BASS/TREBLE
BEEPER
2
I S1
Auxiliary
DIGITAL
CROSSBAR
SELECT
6
8
LEVEL ADJUST AND MUTE
2
2
I S2
I S1
LEVEL ADJUST AND MUTE
LEVEL ADJUST
FIXED
DE-EMPHASIS
2
NICAM
I S2
10
FM
2
DC
FILTER
ADAPTIVE
DE-EMPHASIS
FIXED
MATRIX
DAC
DE-EMPHASIS
12
MONITOR
SELECT
PEAK
1
16
2
4
2
I C-bus
DETECTION
MGK108
Fig.5 DSP data flow diagram.
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
6.2.1
LEVEL SCALING
Optionally, the peak value can be measured instead of
simply taking samples. The internally stored peak value is
reset to zero when the data is read via the I2C-bus.
The monitor function may be used, for example, for signal
level measurements or carrier detection.
All input channels to the digital crossbar switch (except for
the loudspeaker feedback path) are equipped with a level
adjust facility to change the signal level in a range from
+15 to −15 dB (see Fig.5). It is recommended to scale all
input channels to be 15 dB below full-scale (−15 dB
full-scale) under nominal conditions.
6.2.6
LOUDSPEAKER (MAIN) CHANNEL
The matrix provides the following functions: forced mono,
stereo, channel swap, channel 1, channel 2 and spatial
effects.
6.2.2
NICAM PATH
The NICAM path has a switchable J17 de-emphasis.
There are fixed coefficient sets for spatial settings of 30%,
40% and 52%.
6.2.3
FM (AM) PATH
A high-pass filter suppresses DC offsets from the
FM demodulator due to carrier frequency offsets and
supplies the monitor/peak function with DC values and an
unfiltered signal, e.g. for the purpose of carrier detection.
The Automatic Volume Level (AVL) function provides a
constant output level of −23 dB (full-scale) for input levels
between 0 and −29 dB (full-scale). There are some fixed
decay time constants to choose from, i.e. 2, 4 and 8 s.
The de-emphasis function offers fixed settings for the
supported standards (50, 60 or 75 µs and J17).
Pseudo stereo is based on a phase shift in one channel via
a second-order all-pass filter. There are fixed coefficient
sets to provide 90 degrees phase shift at frequencies of
150, 200 and 300 Hz.
An adaptive de-emphasis is available for
Wegener-Panda 1 encoded programs.
Volume is controlled individually for each channel ranging
from +24 to −83 dB with 1 dB resolution. There is also a
mute position. For the purpose of a simple control software
in the microcontroller, the decimal number that is sent as
an I2C-bus data byte for volume control is identical to the
volume setting in dB (e.g. the I2C-bus data byte +10 sets
the new volume value to +10 dB).
A matrix performs the dematrixing of the A2 stereo, dual
and mono signals.
6.2.4
NICAM AUTO-MUTE
If NICAM B/G, I or D/K is received, the auto-mute is
enabled and the signal quality becomes poor, the digital
crossbar switch switches automatically to FM and
switches the matrix to channel 1. The automatic switching
depends on the NICAM bit error rate.
Balance can be realized by independent control of the left
and right channel volume settings.
Contour is adjustable between 0 and +18 dB with 1 dB
resolution. This function is linked to the volume setting by
means of microcontroller software.
The auto-mute function can be disabled via the I2C-bus.
For NICAM L applications, it is recommended to
demodulate AM sound in the first sound IF and connect the
audio signal to the mono input of the TDA9875A.
By setting bit AMSEL (see Section 10.3.11), the
auto-mute function will switch to the audio ADC instead of
switching to the first sound carrier. The ADC source
selector bits (see Section 10.3.20) should be set to mono
input, where the AM sound signal should be connected.
Bass is adjustable between +15 and −12 dB with 1 dB
resolution and treble is adjustable between
+12 and −12 dB with 1 dB resolution.
For the purpose of a simple control software in the
microcontroller, the decimal number that is sent as an
I2C-bus data byte for contour, bass or treble is identical to
the new contour, bass or treble setting in dB (e.g. the
I2C-bus data byte +8 sets the new value to +8 dB).
6.2.5
MONITOR
This function provides data words from a number of
locations in the signal processing paths to the I2C-bus
interface (2 data bytes). Signal sources include the
FM demodulator outputs, most inputs to the digital
crossbar switch and the outputs of the ADC. Source
selection and data read-out is performed via the I2C-bus.
Extra bass boost is provided up to 20 dB with 2 dB
resolution. The implemented coefficient set serves merely
as an example on how to use this filter.
The beeper provides tones in a range from approximately
400 Hz to 30 kHz. The frequency can be selected via the
I2C-bus. The beeper output signal is added to the
loudspeaker and headphone channel signals.
1999 Dec 20
14
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
The beeper volume is adjustable with respect to full-scale
between 0 and −93 dB with 3 dB resolution. The beeper is
not effected by mute.
The I2S-bus output matrix provides the following functions:
forced mono, stereo, channel swap, channel 1 and
channel 2.
Soft mute provides a mute ability in addition to volume
control with a well defined time (32 ms) after which the soft
mute is completed. A smooth fading is achieved by a
cosine masking.
One example of how the feature interface can be used in
a TV set is to connect an external Dolby Surround Pro
Logic DSP, such as the SAA7710, to the I2S-bus ports.
Outputs must be enabled and a suitable master clock
signal for the DSP can be taken from pin SYSCLK.
A stereo signal from any source will be output on one of
the I2S-bus serial data outputs and the four processed
signal channels will be entered at both I2S-bus serial data
inputs. Left and right could then be output to the power
amplifiers via the Main channel, centre and surround via
the Auxiliary channel.
6.2.7
HEADPHONE (AUXILIARY) CHANNEL
The matrix provides the following functions: forced mono,
stereo, channel swap, channel 1 and channel 2
(or C and S in Dolby Surround Pro Logic mode).
Volume is controlled individually for each channel in a
range from +24 to −83 dB with 1 dB resolution. There is
also a mute position. For the purpose of a simple control
software in the microcontroller, the decimal number that is
sent as an I2C-bus data byte for volume control is identical
to the volume setting in dB (e.g. the I2C-bus data byte +10
sets the new volume value to +10 dB).
6.2.9
CHANNEL FROM THE AUDIO ADC
The signal level at the output of the ADC can be adjusted
in a range from +15 to −15 dB with 1 dB resolution.
The audio ADC itself is scaled to a gain of −6 dB.
Balance can be realized by independent control of the left
and right channel volume settings.
6.2.10 CHANNEL TO THE ANALOG CROSSBAR PATH
Level adjust with control positions 0, +3, +6 and +9 dB.
Bass is adjustable between +15 and −12 dB with 1 dB
resolution and treble is adjustable between
6.2.11 DIGITAL CROSSBAR SWITCH
+12 and −12 dB with 1 dB resolution. For the purpose of a
simple control software in the microcontroller, the decimal
number that is sent as an I2C-bus data byte for bass or
treble is identical to the new bass or treble setting in dB
(e.g. the I2C-bus data byte +8 sets the new value
to +8 dB).
Input channels to the crossbar switch are from the audio
ADC, I2S1, I2S2, FM path, NICAM path and from the
loudspeaker channel path after matrix and AVL
(see Fig.8).
Output channels comprise loudspeaker, headphone, I2S1,
I2S2 and audio DACs for line output and SCART. I2S1 and
I2S2 outputs also provide digital outputs from the
loudspeaker and headphone channels, but without the
beeper signals.
The beeper provides tones in a range from approximately
400 Hz to 30 kHz. The frequency can be selected via the
I2C-bus. The beeper output signal is added to the
loudspeaker and headphone channel signals. The beeper
volume is adjustable with respect to full-scale between
0 and −93 dB with 3 dB resolution. The beeper is not
effected by mute.
6.2.12 SIGNAL GAIN
There are a number of functions that can provide signal
gain, e.g. volume, bass and treble control. Great care has
to be taken when using gain with large input signals in
order not to exceed the maximum possible signal swing,
which would cause severe signal distortion. The nominal
signal level of the various signal sources to the digital
crossbar switch should be 15 dB below digital full-scale
(−15 dB full-scale). This means that a volume setting of,
say, +15 dB would just produce a full-scale output signal
and not cause clipping, if the signal level is nominal.
Soft mute provides a mute ability in addition to volume
control with a well defined time (32 ms) after which the soft
mute is completed. A smooth fading is achieved by a
cosine masking.
6.2.8
FEATURE INTERFACE
The feature interface comprises two I2S-bus input/output
ports and a system clock output. Each I2S-bus port is
equipped with level adjust facilities that can change the
signal level in a range from +15 to −15 dB with 1 dB
resolution. Outputs can be disabled to improve EMC
performance.
Sending illegal data patterns via the I2C-bus will not cause
any changes of the current setting for the volume, bass,
treble, bass boost and level adjust functions.
1999 Dec 20
15
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
6.2.13 EXPERT MODE
More information on the functions of this device, such as
the number of coefficients per function, their default
values, memory addresses, etc., can be made available
on request.
The TDA9875A provides a special expert mode that gives
direct write access to the internal Coefficient RAM (CRAM)
of the DSP. It can be used to create user-defined
characteristics, such as a tone control with different corner
frequencies or special boost/cut characteristics to correct
the low-frequency loudspeaker and/or cabinet frequency
responses by means of the bass boost filter. However, this
mode must be used with great care.
6.2.14 DSP FUNCTIONS
Table 5 Overview of DSP functions
EXPERT
FUNCTION
MODE
PARAMETER
control range
VALUE
−12 to +15
UNIT
dB
Bass control for loudspeaker and
headphone output
yes
yes
yes
yes
resolution
1
dB
Hz
dB
dB
kHz
dB
dB
Hz
dB
dB
Hz
Hz
dB
dB
resolution at frequency
control range
40
Treble control for loudspeaker and
headphone output
−12 to +12
resolution
1
resolution at frequency
control range
14
Contour for loudspeaker output
0 to +18
resolution
1
resolution at frequency
control range
40
Bass boost for loudspeaker output
0 to +20
resolution
2
resolution at frequency
corner frequency
control range
20
350
Volume control for each separate
channel in loudspeaker and
headphone output
no
no
−83 to +24
resolution
1
mute position at step
processing time
1010 1100
32
Soft mute for loudspeaker and
headphone output
ms
Spatial effects
Pseudo stereo
yes
yes
yes
anti-phase crosstalk positions
30, 40 and 52
%
90 degrees phase shift at frequency 150, 200 and 300
Hz
Beeper additional to the signal in
the loudspeaker and headphone
channel
beep frequencies
control range
resolution
see Section 10.3.38
0 to −93
dB
dB
3
mute position at step
step width
0010 0000
quasi continuously
−23
Automatic Volume Level (AVL)
yes
AVL output level for an input level
dB
between 0 and −29 dB (full-scale)
attack time
10
ms
s
decay time constant
2, 4 and 8
1999 Dec 20
16
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
EXPERT
FUNCTION
MODE
PARAMETER
−3 dB lower corner frequency of DSP 10
VALUE
UNIT
Hz
General
no
−1 dB bandwidth of DSP
control range
resolution
14.5
kHz
dB
dB
dB
dB
Level adjust I2S1 and I2S2 inputs
Level adjust I2S1 and I2S2 outputs
yes
yes
−15 to +15
1
control range
resolution
−15 to +15
1
mute position at step
control positions
control range
resolution
0001 0000
0, 3, 6 and 9
+15 to −15
1
Level adjust analog crossbar path
Level adjust audio ADC outputs
no
dB
dB
dB
dB
dB
dB
dB
yes
Level adjust NICAM path
Level adjust FM path
yes
yes
control range
resolution
+15 to −15
1
control range
resolution
+15 to −15
1
6.3
Analog audio section
3 dB
0 dB
2
2
2
2
2
2
2
2
2
2
2
2
ANALOG
MATRIX
SCART 1
SCART 1
−3 dB
−3 dB
3 dB
0 dB
2
2
ANALOG
MATRIX
SCART 2
2
2
ANALOG
CROSSBAR
SWITCH
SCART 2
3 dB
0 dB
ANALOG
MATRIX
external
mono
Line output
2
2
D
A
D
A
2
2
2
2
2
2
NICAM
FM
DSP
AND
DIGITAL
CROSSBAR
SWITCH
2
2
2
2
D
A
Main
2
I S1
2
I S2
D
A
2
I S1
Auxiliary
2
I S2
MGK109
Fig.6 Block diagram for the audio section.
1999 Dec 20
17
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
6.3.1
ANALOG CROSSBAR SWITCH AND ANALOG MATRIX
6.3.2
SCART INPUTS
There are a number of analog input and output ports with
the TDA9875A (see Figs 6 and 8). Analog source selector
switches are employed to provide the desired analog
signal routing capability. The analog signal routing is
performed by the analog crossbar switch section. A dual
audio ADC provides the connection to the DSP section
and a dual audio DAC provides the connection from the
DSP section to the analog crossbar switch. The digital
signal routing is performed by a digital crossbar switch.
The SCART specification allows for a signal level of up to
2 V (RMS). Because of signal handling limitations, due to
the 5 V supply voltage of the TDA9875A, it is necessary to
have fixed 3 dB attenuators at the SCART inputs to obtain
a 2 V input. This results in a −3 dB SCART-to-SCART
copy gain. If 0 dB copy gain is preferred (with a maximum
input of 1.4 V), there are 0/3 dB amplifiers at the outputs of
SCART 1 and SCART 2 and at the line output.
The input attenuator is realized by an external series
resistor in combination with the input impedance, both of
which form a voltage divider. With this voltage divider the
maximum SCART signal level of 2 V (RMS) is scaled
down to 1.4 V (RMS) at the input pin.
The basic signal routing philosophy of the TDA9875A is
that each switch handles two signal channels at the same
time, e.g. left and right, language A and B, directly at the
source.
Each source selector switch is followed by an analog
matrix to perform further selection tasks, such as putting a
signal from one input channel, say language A, to both
output channels or for swapping left and right channels
(see Fig.7).
6.3.3
EXTERNAL AND MONO INPUTS
The 3 dB input attenuators are not required for the external
and mono inputs, because those signal levels are under
control of the TV designer. The maximum allowed input
level is 1.4 V (RMS). By adding external series resistors,
the external inputs can be used as an additional SCART
input.
6.3.4
SCART OUTPUTS
handbook, halfpage
left input
left output
ANALOG
MATRIX
The SCART outputs employ amplifiers with two gain
settings. The gain can be set to 3 or 0 dB via the I2C-bus.
The 3 dB position is needed to compensate for the 3 dB
attenuation at the SCART inputs should
right input
right output
MGK110
SCART-to-SCART copies with 0 dB gain be preferred
[under the condition of 1.4 V (RMS) maximum input level].
The 0 dB position is needed, for example, for an
external-to-SCART copy with 0 dB gain.
Fig.7 Analog matrix.
The analog matrix provides the functions given in Table 6.
Table 6 Analog matrix functions
MATRIX OUTPUT
MODE
LEFT OUTPUT RIGHT OUTPUT
1
2
3
4
left input
right input
left input
right input
right input
left input
left input
right input
All switches and matrices are controlled via the I2C-bus.
1999 Dec 20
18
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
6.3.5
LINE OUTPUT
6.3.8
DUAL AUDIO ADC
The line output can provide an unprocessed copy of the
audio signal in the loudspeaker channels. This can be
either an external signal that comes from the dual audio
ADC, or a signal from an internal digital audio source that
comes from the dual audio DAC. The line output employs
amplifiers with two gain settings. The 3 dB position is
needed to compensate for the attenuation at the SCART
inputs, while the 0 dB position is needed, for example, for
non-attenuated external or internal digital signals
(see Section 6.3.4).
There is one dual audio ADC in the TDA9875A for the
connection of the analog crossbar switch section to the
DSP. The dual audio ADC consists of two bitstream
third-order sigma-delta audio ADCs and a high-order
decimation filter.
6.3.9
STANDBY MODE
The standby mode, selected by setting bit STDBY to
logic 1 (see Section 10.3.2) disables most functions and
reduces power dissipation. The analog crossbar switch
and the SCART section remain operational and can be
controlled by the I2C-bus to support copying of analog
signals from SCART-to-SCART.
6.3.6
LOUDSPEAKER (MAIN) AND HEADPHONE
(AUXILIARY) OUTPUTS
Signals from any audio source can be applied to the
loudspeaker and to the headphone output channels via the
digital crossbar switch and the DSP.
Unused internal registers may lose their information in the
standby mode. Therefore, the device needs to be
initialized on returning to the normal operating mode. This
can be accomplished in the same way as after a Power-on
reset.
6.3.7
DUAL AUDIO DAC
The TDA9875A contains three dual audio DACs, one for
the connection from the DSP to the analog crossbar switch
section and two for the loudspeaker and headphone
outputs. Each of the three dual low-noise high-dynamic
range DACs consists of two 15-bit DACs with current
outputs, followed by a buffer operational amplifier.
The audio DACs operate with four-fold oversampling and
noise shaping.
6.3.10 SUPPLY GROUND
The different supply grounds VSS are internally connected
via the substrate. It is recommended to connect all ground
pins by means of a copper plane close to the pins.
1999 Dec 20
19
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SCART 1
AUTOMATIC
VOLUME
LEVEL
LOUDSPEAKER
CHANNEL
PROCESSING
Main
DIGITAL
MATRIX
DAC
DAC
SCART 2
ADC
LEVEL
ADJUST
ADC
−6 dB
external
mono
HEADPHONE
CHANNEL
PROCESSING
Auxiliary
DIGITAL
MATRIX
2
I S1
2
I S1
DIGITAL
MATRIX
OUTPUT
LEVEL
ADJUST
2
I S2
FM
FM/AM
part
FM/AM
DEMODULATOR
ADAPTIVE
DE-EMPHASIS
FIXED
DE-EMPHASIS
STEREO
DECODER
LEVEL
ADJUST
2
I S2
DIGITAL
MATRIX
OUTPUT
LEVEL
ADJUST
Line
ANALOG
MATRIX
BUFFER
0/+3 dB
NICAM
LEVEL
ADJUST
NICAM
part
NICAM
DECODER
DE-EMPHASIS
SCART 1
BUFFER
0/+3 dB
ANALOG
MATRIX
2
I S1
INPUT
LEVEL
ADJUST
2
I S1
DAC
GAIN
DIGITAL
MATRIX
DAC
SCART 2
ANALOG
MATRIX
BUFFER
0/+3 dB
2
I S2
INPUT
LEVEL
2
I S2
ADJUST
MHB600
Fig.8 Audio signal flow diagram.
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
7
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.0
UNIT
V
∆VDD
voltage differences between two VDD pins
voltage on any other pin
−
550
mV
V
Vn
−0.5
−
VDD + 0.5
±180
−
I
DDD, ISSD
Ilu(prot)
Ptot
DC current per digital supply pin
latch-up protection current
total power dissipation
mA
mA
W
100
−
1.0
Tstg
storage temperature
−55
−20
−2000
−200
+125
+70
°C
°C
V
Tamb
Ves
ambient temperature
electrostatic handling voltage
note 1
note 2
+2000
+200
V
Notes
1. Human body model: C = 100 pF; R = 1.5 kΩ.
2. Machine model: C = 200 pF; L = 0.75 µH; R = 0 Ω.
8
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
VALUE
UNIT
thermal resistance from junction to ambient
TDA9875A (SDIP64)
in free air
40
50
K/W
K/W
TDA9875AH (QFP64)
1999 Dec 20
21
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
9
CHARACTERISTICS
VSIF(p-p) = 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain settings in accordance with note 1;
DD = 5 V; Tamb = 25 °C; settings in accordance with B/G standard; FM deviation ±50 kHz; fmod = 1 kHz; FM sound
V
parameters in accordance with system A2; NICAM in accordance with “EBU specification”; 1 kΩ measurement source
resistance for AF inputs; with external components of Fig.10; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD1
VSSD1
IDDD1
VDDD2
VSSD2
IDDD2
digital supply voltage 1
digital supply ground 1
digital supply current 1
digital supply voltage 2
digital supply ground 2
digital supply current 2
4.75
5.0
5.5
V
note 2
−
0.0
73
−
V
VDDD1 = 5.0 V
58
4.75
−
88
5.5
−
mA
V
5.0
0.0
0.4
note 2
V
VDDD2 = 5.0 V; system clock 0.1
output disabled
2
mA
VSSD3
VSSD4
VDDA
IDDA
digital supply ground 3
digital supply ground 4
analog supply voltage
note 2
note 2
−
0.0
0.0
5.0
56
−
V
−
−
V
4.75
5.5
68
V
analog supply current for
DAC part
VDDA = 5.0 V; digital silence 44
mA
VSSA1
VSSA2
VSSA3
VSSA4
analog ground for analog
front-end
note 2
−
−
−
−
0.0
0.0
0.0
0.0
−
−
−
−
V
V
V
V
analog ground for audio ADC note 2
part
analog ground for audio DAC note 2
part
analog ground for SCART
Demodulator supply decoupling and references
VDEC1
analog supply decoupling
voltage for demodulator part
3.0
−
3.3
2
3.6
−
V
Vref1
analog reference voltage for
demodulator part
V
Iref1(sink)
sink current at pin Vref1
−
200
−
µA
Audio supply decoupling and references
VDEC2
analog supply decoupling
voltage for audio ADC part
3.0
3.3
50
3.6
V
Vref2
reference voltage ratio for
audio ADCs
referenced to VDEC2 and
VSSA2
−
−
%
ZVref2-VDEC2 impedance pins Vref2 to VDEC2
−
−
−
20
20
50
−
−
−
kΩ
kΩ
%
ZVref2-VSSA2
Vref3
impedance pins Vref2 to VSSA2
reference voltage ratio for
audio DAC and operational
amplifier
referenced to VDDA and
VSSA3
ZVref3-VDDA
ZVref3-VSSA3
impedance pins Vref3 to VDDA
impedance pins Vref3 to VSSA3
−
−
20
20
−
−
kΩ
kΩ
1999 Dec 20
22
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Power fail detector
Vth(pf)
power fail threshold voltage
−
−
3.9
−
V
Digital inputs and outputs
INPUTS
CMOS level input, pull-down (pins TEST1 and TEST2)
VIL
VIH
Ci
LOW-level input voltage
HIGH-level input voltage
input capacitance
−
0.3VDDD
V
0.7VDDD
−
−
V
−
−
−
10
−
pF
kΩ
Zi
input impedance
50
CMOS level input, hysteresis, pull-up (pin CRESET)
VIL
VIH
Vhys
Ci
LOW-level input voltage
HIGH-level input voltage
hysteresis voltage
−
−
0.3VDDD
V
0.7VDDD
−
−
V
−
1.3
−
−
V
input capacitance
−
10
−
pF
kΩ
Zi
input impedance
30
50
INPUTS/OUTPUTS
I2C-bus level input with Schmitt trigger, open-drain output stage, 400 kHz I2C-bus operation (pins SCL and SDA)
VIL
VIH
Vhys
ILI
LOW-level input voltage
HIGH-level input voltage
hysteresis voltage
−
−
0.3VDDD
−
V
0.7VDDD
−
V
−
−
−
−
−
0.05VDDD
−
V
input leakage current
input capacitance
−
−
−
−
±10
10
µA
pF
V
Ci
VOL
CL
LOW-level output voltage
load capacitance
0.6
400
pF
TTL/CMOS level, 4 mA 3-state output stage, pull-up (pins PCLK, NICAM, ADDR1, ADDR2, P1, P2, SCK, WS, SDO1,
SDO2, SDI1 and SDI2)
VIL
VIH
Ci
LOW-level input voltage
HIGH-level input voltage
input capacitance
−
−
0.8
−
V
2.0
−
−
V
−
10
0.4
−
pF
V
VOL
VOH
CL
LOW-level output voltage
HIGH-level output voltage
load capacitance
−
−
2.4
−
−
V
−
100
−
pF
kΩ
Zi
input impedance
−
50
OUTPUTS
CMOS level output, 4 mA 3-state output stage, slew rate controlled (pin SYSCLK)
VOL
VOH
CL
LOW-level output voltage
HIGH-level output voltage
load capacitance
−
−
−
−
−
0.3VDDD
−
V
0.7VDDD
V
−
−
100
pF
µA
ILIZ
3-state leakage current
Vi = 0 to VDDD
23
±10
1999 Dec 20
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SIF1 and SIF2 analog inputs
VSIF(max)(p-p) maximum composite SIF input SIF input level adjust 0 dB
voltage for clipping
−
941
−
−
mV
SIF input level adjust −10 dB −
2976
mV
(peak-to-peak value)
VSIF(min)(p-p)
minimum composite SIF input SIF input level adjust 0 dB
−
59
−
−
mV
mV
voltage for lower limit of AGC
(peak-to-peak value)
SIF input level adjust −10 dB −
188
AGC
fi
AGC range
−
24
−
−
dB
input frequency
input resistance
input capacitance
FM deviation
4
9.2
−
MHz
kΩ
Ri
AGCLEV = 0
10
−
Ci
−
7.5
−
11
−
pF
∆fFM
∆fFM(FS)
B/G standard; THD < 1%
±100
±150
kHz
kHz
FM deviation full-scale level
terrestrial FM;
−
−
level adjust 0 dB
C/NFM
C/NN
αct
FM carrier-to-noise ratio
NFM bandwidth = 6 MHz;
white noise for S/N = 40 dB;
“CCIR468”; quasi peak
−
77
66
−
−
−
−
dB
------
Hz
NICAM carrier-to-noise ratio
NN bandwidth = 6 MHz;
bit error rate = 10−3;
white noise
−
dB
------
Hz
crosstalk attenuation
SIF1 to SIF2
fi = 4 to 9.2 MHz; note 3
50
dB
Demodulator performance
THD + N total harmonic distortion plus from FM source to any
−
−
0.3
0.1
70
0.5
0.3
−
%
noise
output; Vo = 1 V (RMS) with
low-pass filter
from NICAM source to any
output; Vo = 1 V (RMS) with
low-pass filter
%
S/N
signal-to-noise ratio
SC1 from FM source to any 64
output; Vo = 1 V (RMS);
dB
dB
“CCIR468”; quasi peak
SC2 from FM source to any 60
output; Vo = 1 V (RMS);
66
−
“CCIR468”; quasi peak
NICAM source;
Vo = 1 V (RMS); note 4
−
−
−
−
−
−
B−3dB
−3 dB bandwidth
from FM source to any
output
14.5
14.5
−
15
15
±2
kHz
kHz
dB
from NICAM source to any
output
fres
frequency response
20 Hz to 14 kHz
from FM or NICAM to any
output; fref = 1 kHz;
inclusive pre-emphasis and
de-emphasis
1999 Dec 20
24
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
SYMBOL
PARAMETER
CONDITIONS
MIN.
65
40
TYP.
MAX.
UNIT
dB
αcs(dual)
αcs(stereo)
αAM
dual signal channel separation note 5
70
45
−
−
−
−
stereo channel separation
AM suppression for FM
note 6
dB
dB
AM: 1 kHz, 30% modulation; 50
reference: 1 kHz,
50 kHz deviation
S/NAM
AM demodulation
SIF level 100 mV (RMS);
54% AM; 1 kHz AF;
36
45
−
dB
“CCIR468”; quasi peak
IDENTIFICATION FOR FM SYSTEMS
modp
pilot modulation for
identification
25
50
27
75
%
C/Np
pilot sideband carrier-to-noise
ratio for identification start
−
−
dB
------
Hz
fident
identification window
B/G stereo
slow mode
medium mode
fast mode
116.85
116.11
114.65
−
−
−
118.12 Hz
118.89 Hz
120.46 Hz
B/G dual
slow mode
medium mode
fast mode
273.44
−
−
−
−
−
−
−
−
−
274.81 Hz
276.20 Hz
277.60 Hz
272.07
270.73
tident(on)
total identification time ON
total identification time OFF
slow mode
medium mode
fast mode
−
−
−
−
−
−
2
s
s
s
s
s
s
1
0.5
2
tident(off)
slow mode
medium mode
fast mode
1
0.5
Analog audio inputs
MONO INPUT AND EXTERNAL INPUT
Vi(nom)(rms)
nominal level input voltage
(RMS value)
−
500
1400
35
−
mV
mV
kΩ
Vi(clip)(rms)
clipping level input voltage
(RMS value)
THD < 3%; note 7
note 7
1250
28
−
Ri
input resistance
42
SCART INPUTS
Vi(nom)(rms)
nominal level input voltage at −3 dB divider with external
−
350
−
−
mV
mV
input pin (RMS value)
15 kΩ resistor; note 8
Vi(clip)(rms)
clipping level input voltage at
input pin (RMS value)
−3 dB divider with external
15 kΩ resistor; THD < 3%;
notes 7 and 8
1250
1400
Ri
input resistance
note 7
28
35
42
kΩ
1999 Dec 20
25
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog audio outputs
LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS
Vo(clip)(rms)
clipping level output voltage
(RMS value)
THD < 3%
1250
1400
−
mV
Ro
output resistance
AC load resistance
DC load resistance
load capacitance
150
10
10
−
250
−
375
−
Ω
RL(AC)
RL(DC)
CL
kΩ
kΩ
nF
mV
dB
−
−
10
30
−
12
70
−
Voffset(DC)
αmute
static DC offset voltage
mute suppression
−
nominal input signal from
any source; fi = 1 kHz
80
Gro(main,aux)
roll-off gain at 14.5 kHz for
Main and Auxiliary channels
from any source
−3
−2
−
−
dB
dB
PSRRmain,aux power supply ripple rejection
for Main and Auxiliary
fripple = 70 Hz;
40
45
Vripple = 100 mV (peak);
CVref = 47 µF;
signal from I2S-bus
channels
SCART OUTPUTS AND LINE OUTPUT
Vo(nom)(rms)
nominal level output voltage
(RMS value)
3 dB amplification
THD < 3%
−
500
−
−
mV
mV
Vo(clip)(rms)
clipping level output voltage
(RMS value)
1250
1400
Ro
output resistance
150
10
10
−
250
−
375
−
Ω
RL(AC)
RL(DC)
CL
AC load resistance
DC load resistance
load capacitance
kΩ
kΩ
nF
mV
−
−
−
2.5
50
Voffset(DC)
static DC offset voltage
output amplifiers at 3 dB
position
−
30
αmute
mute suppression
bandwidth
nominal input signal from
any source; fi = 1 kHz
80
20
−
−
−
−
dB
B
from SCART, external and
mono sources;
kHz
−3 dB bandwidth
from DSP sources;
−3 dB bandwidth
14.5
40
−
−
−
kHz
dB
PSRR
power supply ripple rejection
fripple = 70 Hz;
45
Vripple = 100 mV (peak);
CVref = 47 µF;
signal from I2S-bus
1999 Dec 20
26
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Audio performance
THD + N
total harmonic distortion plus Vi = Vo = 1 V (RMS);
noise
fi = 1 kHz; bandwidth
20 Hz to 15 kHz; note 9
from any analog audio
input to I2S-bus
from I2S-bus to any analog
audio output
−
−
0.1
0.3
%
0.1
0.3
%
SCART-to-SCART copy
SCART-to-Main copy
−
−
0.1
0.2
0.3
0.5
%
%
S/N
signal-to-noise ratio
reference voltage
Vo = 1.4 V (RMS);fi = 1 kHz;
“CCIR468”; quasi peak;
note 9
from any analog audio
input to I2S-bus
from I2S-bus to any analog 78
audio output
73
77
85
−
−
dB
dB
SCART-to-SCART copy
SCART-to-Main copy
78
73
70
85
77
−
−
−
−
dB
dB
dB
αct
αcs
GA
crosstalk attenuation
channel separation
between any analog input
pairs; fi = 1 kHz
between any analog output
pairs; fi = 10 kHz
65
−
−
dB
dB
dB
dB
dB
between left and right of any 65
input pair
−
−
between left and right of any 60
output pair
−
−
gain from SCART-to-SCART
with −3 dB input voltage
divider
output amplifier in 3 dB
position; Rext = 15 kΩ ±10%
−1.5
0
+1.1
−1.9
output amplifier in 0 dB
−4.5
−3.0
position; Rext = 15 kΩ ±10%
Crystal specification (fundamental mode)
fxtal
CL
crystal frequency
load capacitance
series capacitance
parallel capacitance
pulling sensitivity
−
−
−
−
−
24.576
20
−
−
−
7
−
MHz
pF
C1
20
fF
C0
−
pF
Φpull
CL changed from
18 to 16 pF
25
10–6
-----------
pF
RR
RN
equivalent series resistance
at nominal frequency
−
−
−
30
Ω
Ω
equivalent series resistance of
unwanted mode
2RR
−
∆T
temperature range
−20
+25
+70
°C
1999 Dec 20
27
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
SYMBOL
XJ
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
±30
UNIT
10−6
10−6
adjustment tolerance
−
−
−
−
−
−
XD
XA
drift
across temperature range
±30
±5
ageing
10–6
-----------
year
Notes
1. Definitions of levels and level setting:
a) The full-scale level for analog audio signals is 1.4 V (RMS).
b) The nominal level at the digital crossbar switch is defined at −15 dB (full-scale).
c) Nominal audio input levels for external and mono: 500 mV (RMS) at −9 dB (full-scale).
d) See also Tables 7 and 8.
2. All analog and digital supply ground pins are connected internally.
3. Set demodulator to AM mode. Apply an AM carrier (with 1 kHz and 100%) to one channel. Check AGC step. Switch
AGC off and set AGC to the gain step found. Measure the 1 kHz signal level of this channel and take it as a reference.
Switch to the other SIF input to which no signal is connected and which is terminated with 50 Ω. Now measure the
1 kHz crosstalk signal level. The SIF source resistance should be low (50 Ω).
4. NICAM in accordance with “EBU specification”. Audio performance is limited by the dynamic range of the NICAM728
system. Due to compansion, the quantization noise is never lower than −62 dB (unweighted RMS) with respect to
the input level.
5. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output;
Vo = 1 V (RMS) of modulated channel.
6. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output;
Vo = 1 V (RMS) of modulated channel. The stereo channel separation may be limited by adjustment tolerances of
the transmitter.
7. If the supply voltage for the TDA9875A is switched off, because of the ESD protection circuitry, all audio input pins
are short-circuited. To avoid a short-circuit at the SCART inputs a 15 kΩ resistor (−3 dB divider) has to be used.
8. The SCART specification allows a signal level of up to 2 V (RMS). Because of signal handling limitations due to the
5 V supply voltage for the TDA9875A, there is a need for fixed 3 dB attenuators at the SCART inputs. To achieve
SCART-to-SCART copies with 0 dB gain, there are 3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2
and at the line output. The attenuator is realized by an internal resistor that works together with an external series
resistor as a voltage divider. With this voltage divider the maximum SCART input signal level of 2 V (RMS) is scaled
down to 1.4 V (RMS) at the input pin. To avoid clipping, the 3 dB gain must not be used if the SCART input signal is
larger than 1.4 V (RMS).
9. ADC level adjust is 6 dB, all other level adjusts are 0 dB. If an external −3 dB divider is used set output buffer gain
to 3 dB, tone control to 0 dB, AVL off and volume control to 0 dB.
1999 Dec 20
28
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Table 7 Level setting FM, AM and NICAM at 0 dB (full-scale) = 1.4 V (RMS); note 1
TRANSMITTER
NOMINAL LEVEL AT
DEMODULATOR
OUTPUT
FM/NICAM
CARRIER FREQUENCY MODE IDENT DE-EMPHASIS LEVEL
NOMINAL
MODULATION
DEPTH
STANDARD MODE
ADJUST
M
2 channel 15 kHz deviation
−24 dB (full-scale);
note 2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4.5 MHz
FM
FM
FM
FM
FM
−
75 µs
75 µs
50 µs
50 µs
50 µs
J17
+9 dB
+9 dB
+4 dB
+4 dB
+4 dB
+3 dB
+4 dB
+8 dB
+4 dB
+4 dB
+4 dB
+4 dB
+4 dB
+4 dB
+4 dB
+3 dB
+5 dB
+3 dB
4.724 MHz
5.5 MHz
on
−
B/G
2 channel 27 kHz deviation
−19 dB (full-scale)
5.742 MHz
5.5 MHz
on
−
NICAM
NICAM
−11.2 dB (full-scale) −18 dB (full-scale)
−15.8 dB (full-scale) −23 dB (full-scale)
5.85 MHz
6.0 MHz
NICAM off
FM
NICAM off
I
−
50 µs
J17
6.552 MHz
6.5 MHz
D/K
2 channel 27 kHz deviation
2 channel 27 kHz deviation
2 channel 27 kHz deviation
−19 dB (full-scale)
−19 dB (full-scale)
−19 dB (full-scale)
FM
FM
FM
FM
FM
FM
FM
−
50 µs
50 µs
50 µs
50 µs
50 µs
50 µs
50 µs
J17
6.742 MHz
6.5 MHz
on
−
6.25 MHz
6.5 MHz
on
−
5.742 MHz
6.5 MHz
on
−
NICAM
NICAM
−11.2 dB (full-scale) −18 dB (full-scale)
5.85 MHz
6.5 MHz
NICAM off
AM
NICAM off
L/L accent
54% AM
−19 dB (full-scale)
−
50 µs
J17
5.85 MHz
Notes
1. Nominal level at digital crossbar is defined at −15 dB (full-scale). DAC gain setting 6 dB. Output buffer setting 0 dB. Nominal SCART output level
500 mV (RMS).
2. For stereo signals the output level is 6 dB lower. The level adjust has to be increased by 6 dB.
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Table 8 Level setting SAT FM at 0 dB (full-scale) = 1.4 V (RMS)
TRANSMITTER
NOMINAL LEVEL AT FM LEVEL
MAXIMUM
LEVEL AT
CROSSBAR
MAXIMUM
MODULATION
DEPTH
DAC GAIN OUTPUT
SETTING BUFFER
NOMINAL SCART
OUTPUT VOLTAGE
SOURCE
DEMODULATOR
OUTPUT
ADJUST
SETTING
SAT FM, stereo
SAT FM, mono
50 kHz deviation
85 kHz deviation
−13 dB (full-scale)
−9 dB (full-scale)
+4 dB
0 dB
−9 dB (full-scale) +6 dB
0 dB
1 V (RMS)
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10 I2C-BUS CONTROL
10.1 Introduction
10.2 Power-up state
At power-up the device is in the following state:
• All outputs muted
The TDA9875A is fully controlled via the I2C-bus. Control
is exercised by writing data to one or more internal
registers. Status information can be read from an array of
registers to enable the controlling microcontroller to
determine whether any action is required.
• No sound carrier frequency loaded
• General-purpose I/O pins ready for input (HIGH)
• Input SIF1 selected with:
– AGC on
The device has an I2C-bus slave transceiver, in
accordance with the fast-mode specification, with a
maximum speed of 400 kbits/s. Information concerning the
I2C-bus can be found in brochure “I2C-bus and how to use
it” (order number 9398 393 40011). To avoid conflicts in a
real application with other ICs providing similar or
complementary functions, there are four possible slave
addresses available which can be selected by pins
ADDR1 and ADDR2 (see Table 9).
– Small hysteresis
– SIF input level shift 0 dB.
• Demodulators for both sound carriers set to FM with:
– Identification for B/G and D/K, response time 1 s
– Level adjust set to 0 dB
– De-emphasis 50 µs
– Matrix set to mono.
• Main channel set to FM input with:
– Spatial off
Table 9 Possible slave addresses
SLAVE ADDRESS
ADDR2 ADDR1
– Pseudo off
A6 A5 A4 A3 A2 A1 A0
– AVL off
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
– Volume mute
– Bass flat
– Treble flat
– Contour off
– Bass boost flat.
The I2C-bus interface remains operational in the standby
mode of the TDA9875A to allow control of the analog
source selectors with regard to SCART-to-SCART
copying.
• Auxiliary channel set to FM input with:
– Volume mute
– Bass flat
The device will not respond to a ‘general call’ on the
I2C-bus, i.e. when a slave address of 0000000 is sent by a
master.
– Treble flat.
• Feature interface all outputs off
• Beeper off
The data transmission between the microcontroller and
the other I2C-bus controlled ICs is not disturbed when the
supply voltage of the TDA9875A is not connected.
• Monitoring of carrier 1 FM demodulator DC output.
After power-up a device initialization has to be performed
via the I2C-bus to put the TDA9875A into the proper mode
of operation, in accordance with the desired TV standard,
audio control settings, etc.
1999 Dec 20
31
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3 Slave receiver mode
As a slave receiver, the TDA9875A provides 46 registers for storing commands and data. These registers are accessed
via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location.
Table 10 I2C-bus; slave address, subaddress and data format
S
SLAVE ADDRESS
0
ACK
SUBADDRESS
ACK
DATA
ACK
P
Table 11 Explanation of Table 10
BIT
FUNCTION
S
START condition
SLAVE ADDRESS
7-bit device address
0
data direction bit (write to device)
acknowledge by slave
ACK
SUBADDRESS
address of register to write to
data byte to be written into register
STOP condition
DATA
P
It is allowed to send more than one data byte per transmission to the TDA9875A. In this event, the subaddress is
automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register
locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with
ACK (acknowledge).
There is no ‘wrap-around’ of subaddresses.
Commands and data are processed as soon as they have been completely received. Functions requiring more than one
byte will, thus, be executed only after all bytes for that function have been received. If the transmission is terminated
(STOP condition) before all bytes have been received, the incomplete data for that function are ignored.
Table 12 Format for a transmission employing auto-increment of subaddresses
S
SLAVE ADDRESS
0
ACK
SUBADDRESS
ACK
DATA
BYTE A(1)
DATA ACK
P
Note
1. n data bytes with auto-increment of subaddresses.
Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the
functions of volume, bass, treble control, bass boost and level adjust.
Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will
then not be executed.
1999 Dec 20
32
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
Table 13 Overview of the slave receiver registers
DATA
SUBADDRESS
(DECIMAL)
FUNCTION
MSB
LSB
0
0
c
p
f
0
c
0
f
s
c
g
c
m
f
g
c
m
f
g
c
s
f
g
c
s
f
g
c
s
f
AGC level shift, AGC gain selection
general configuration
1
2
0
f
monitor select, peak detector on/off
carrier 1 frequency; most significant part
carrier 1 frequency
3
4
f
f
f
f
f
f
f
f
5
f
f
f
f
f
f
f
f
carrier 1 frequency; least significant part
carrier 2 frequency; most significant part
carrier 2 frequency
6
f
f
f
f
f
f
f
f
7
f
f
f
f
f
f
f
f
8
f
f
f
f
f
f
f
f
carrier 2 frequency; least significant part
demodulator configuration
FM de-emphasis
9
c
d
0
0
0
t
c
d
0
0
0
t
c
c
d
0
l
c
d
0
l
c
d
m
l
c
d
m
l
c
d
m
l
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
d
0
0
0
0
0
l
FM matrix
channel 1 output level adjust
channel 2 output level adjust
NICAM configuration
l
l
l
l
l
c
l
0
l
c
l
c
l
c
l
0
l
0
l
NICAM output level adjust
NICAM lower error limit
NICAM upper error limit
audio mute control
l
l
l
l
l
u
m
g
0
0
0
s
0
0
v
v
0
0
0
0
v
v
0
0
0
0
u
m
m
g
g
g
s
m
0
v
v
0
0
0
m
v
v
0
0
0
m
u
m
m
m
m
m
s
u
m
m
m
m
m
l
u
m
g
0
0
0
l
u
m
s
s
s
0
l
u
m
s
s
s
0
l
u
m
s
s
s
s
l
DAC output select
SCART 1 output select
SCART 2 output select
line output select
ADC output select
m
s
m
s
v
v
c
b
t
0
p
v
v
c
b
t
s
p
v
v
c
b
t
s
a
v
v
c
b
t
s
a
v
v
c
b
t
Main channel select
audio effects (AVL, pseudo and spatial)
volume control, Main left
volume control, Main right
contour control, Main
v
v
0
0
0
m
v
bass control, Main
treble control, Main
m
v
v
b
t
0
v
v
b
t
s
v
v
b
t
s
v
v
b
t
s
v
v
b
t
Auxiliary channel select
volume control, Auxiliary left
volume control, Auxiliary right
bass control, Auxiliary
v
0
0
0
m
treble control, Auxiliary
feature interface configuration
I2S1 output select
c
m
c
0
c
s
c
s
c
s
1999 Dec 20
33
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
DATA
SUBADDRESS
(DECIMAL)
FUNCTION
I2S1 input level adjust
I2S1 output level adjust
I2S2 output select
I2S2 input level adjust
I2S2 output level adjust
MSB
LSB
38
39
40
41
42
43
44
45
0
0
0
0
0
0
0
b
0
0
m
0
0
0
0
b
0
0
m
0
0
0
v
i
o
m
i
i
i
i
i
o
0
i
o
s
i
o
s
i
o
s
i
o
0
v
b
o
0
v
b
o
f
o
f
o
f
beeper frequency
v
b
v
b
v
b
beeper volume, Main and Auxiliary
bass boost, Main left and right
b
The following sub-sections provide a detailed description of the slave receiver registers.
10.3.1 AGC GAIN REGISTER
If the automatic gain control function is switched off in the general configuration register, the contents of this register will
define a fixed gain of the AGC stage. The input voltages given are meant to generate a full-scale output from the SIF
ADC. If automatic gain control is on, the AGCGAIN setting is ignored. After switching off the automatic gain control
function, the latest gain control setting is copied to the AGC gain register.
If the AGC input level shift bit AGCLEV is set to logic 1 the input signal is scaled with −10 dB. The AGCLEV bit is also
active if the automatic gain function is enabled.
It should be noted that the input voltages should be considered as approximate target values.
Table 14 Subaddress 0 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
B6
0
0
1
0
−
set to logic 0
6
5
set to logic 0
AGCLEV
input signal scaled with −10 dB
input signal not scaled
gain control bits (see Table 15)
4
AGCGAIN
3
2
1
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
34
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
Table 15 Gain control bits
MSB
LSB
B0
AGC GAIN SIF INPUT VOLTAGE
(dB)
[mV (p-p)]
B7
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.0
0.8
941/2976
861/2723
788/2490
720/2278
659/2084
603/1906
551/1744
504/1595
461/1459
422/1334
386/1221
353/1117
323/1021
295/934
270/855
247/782
226/715
207/654
189/598
173/547
158/501
145/458
132/419
121/383
111/350
101/321
93/293
1.5
2.3
3.1
3.9
4.6
5.4
6.2
7.0
7.7
8.5
9.3
10.1
10.8
11.6
12.4
13.2
13.9
14.7
15.5
16.3
17.0
17.8
18.6
19.4
20.1
20.9
21.7
22.5
23.2
24.0
85/268
78/245
71/224
65/205
59/188 (note 1)
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
35
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.2 GENERAL CONFIGURATION REGISTER
Table 16 Subaddress 1 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
P2OUT
−
This bit controls the general purpose input/output pin P2. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1).
6
P1OUT
−
This bit controls the general purpose input/output pin P1. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1). P1OUT is recommended to be
used for switching an SIF trap for the adjacent picture carrier in designs that
employ such a trap.
5
4
STDBY
INIT
1
The IC is in the standby mode. Most functions are disabled and power dissipation
is somewhat reduced, but the analog selectors/matrices remain operational to
support analog copying from SCART-to-SCART.
0
1
The IC is in the normal operating mode. On return from standby mode, the device
is in its Power-on reset mode and needs to be re-initialized.
Causes initialization of the TDA9875A to its default settings. This has the same
effect as a Power-on reset. If there is a conflict between the default settings and
any bit set to logic 1 in this register, the bits of this register have priority over the
corresponding default setting.
0
Automatically reset to logic 0 after initialization. When set to logic 0, the
TDA9875A is in its normal operating mode.
3
CLRPOR
AGCSLOW
AGCOFF
SIFSEL
1
0
Resets the power fail detector to LOW.
This bit is automatically reset to logic 0 after bit POR in the device status register
has been reset.
2
1
1
A longer decay time is selected for input signals with strong video modulation
(intercarrier). This bit only has an effect when bit AGCOFF = 0.
0
1
0
Selects normal attack and decay times for the AGC.
Forces the AGC block to a fixed gain as defined in the AGC gain register.
The automatic gain control function is enabled and the contents of the AGC gain
register is ignored.
0 (LSB)
1
0
Selects pin SIF2 for input (recommended for satellite tuner).
Selects pin SIF1 for input (terrestrial TV).
Note
1. The default setting at power-up is 1100 0000.
1999 Dec 20
36
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.3 MONITOR SELECT REGISTER
This register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be
monitored. Peak level refers to the magnitude of the maximum excursion of a signal.
Audio magnitude/phase is related to the FM demodulator output. Phase information is provided, when it operates in
FM mode, while magnitude is supplied in AM mode.
Data can be read-out in the I2C-bus slave transmitter mode. By reading out level read-out registers (see Section 10.4)
the current peak level will be reset.
Table 17 Subaddress 2 (note 1)
BIT
NAME
VALUE
DESCRIPTION
selects the peak level of a source to be monitored
the last sample will be supplied
default value
7 (MSB)
PEAKMON
1
0
0
0
−
6
B6
B5
B4
B3
B2
B1
B0
5
default value
4
monitor output (see Table 18)
3
2
1
−
signal source (see Table 19)
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
Table 18 Monitor output
B4
B3
MONITOR OUTPUT
0
0
L input + R input
------------------------------------------
2
0
1
1
0
L input (channel 1, respectively)
R input (channel 2, respectively)
Table 19 Signal source (note 1)
B2
B1
B0
SIGNAL SOURCE
DC output of FM demodulator
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
audio magnitude/phase, FM demodulator output
crossbar input from FM/AM channel
crossbar input from NICAM channel
crossbar input from I2S1 channel
crossbar input from I2S2 channel
crossbar input from audio ADC channel
input to Main channel DAC (without beeper)
Note
1. The term ‘crossbar’ refers to the digital selector, where level-adjusted signals from various sources are available.
1999 Dec 20
37
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.4 CARRIER 1 FREQUENCY REGISTER
Table 20 Subaddresses 3 to 5
The three bytes together constitute a 24-bit frequency
control word to represent the sound carrier (i.e. mixer)
frequency in accordance with the following formula:
SUB-
BIT
DESCRIPTION
ADDRESS
3
4
5
7 (MSB)
carrier 1 frequency;
most significant part
f
data = mix × 2 24
6
--------
fclk
5
where:
4
data = 24-bit frequency control word
fmix = desired sound carrier frequency
fclk = 12.288 MHz (clock frequency of mixer)
3
2
1
24 = 16777216 (number of steps in a 24-bit word size).
0
2
7
carrier 1 frequency
Example: A 5.5 MHz sound carrier frequency will be
generated by sending the following sequence of data
bytes to the TDA9875A (data = 7509333 in decimal
notation or 72555 in hexadecimal):
6
5
4
01110010 10010101 01010101.
3
As three bytes are required to define a carrier frequency,
execution of this command starts only after all bytes have
been received. If an error occurs, e.g. a premature STOP
condition, partial data for this function is ignored.
2
1
0
7
carrier 1 frequency;
least significant part
The default setting at power-up is 0000 0000 for all three
bytes.
6
5
Most significant part at subaddress 3 and least significant
part at subaddress 5 (see Table 20).
4
3
2
1
0 (LSB)
1999 Dec 20
38
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.5 CARRIER 2 FREQUENCY REGISTER
Same as for sound carrier 1, except for subaddresses (subaddresses 6 to 8). If the carrier 2 frequency register is used,
it will be for either the second FM sound carrier of a terrestrial or satellite FM program or the NICAM sound carrier.
10.3.6 DEMODULATOR CONFIGURATION REGISTER
It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial
2-carrier sound. Switching the identification off will reset the associated hardware to a defined state.
Table 21 Subaddress 9 (note 1)
BIT
7 (MSB)
6
NAME
IDMOD1
IDMOD0
VALUE
DESCRIPTION
−
these bits define the response time after which a FM sound mode identification
result may be expected; the longer the time, the more reliable the identification
(see Table 22)
5
IDAREA
1
selects FM identification frequencies in accordance with the specification for
Korea
0
−
−
selects frequencies for Europe (B/G and D/K standard)
selects filter bandwidth (see Table 23)
4
3
2
FILTBW1
CH2MOD1
CH2MOD0
channel 2 receive mode: these bits control the hardware for the second sound
carrier (see Table 24); the NICAM mode employs a wider bandwidth of the
decimation filters than the FM mode
1
FILTBW0
−
1
0
selects the filter bandwidth (see Table 23)
0 (LSB)
CH1MODE
selects the hardware for the first sound carrier to operate in AM mode
FM mode is assumed; this applies to both terrestrial and satellite FM reception
Notes
1. The default setting at power-up is 0000 0000.
Table 22 Identification mode
B7
B6
IDENT MODE
0
0
1
1
0
1
0
1
slow
medium
fast
off/reset
Table 23 Filter bandwidth channel 1 and channel 2
FILTER
BANDWIDTH
B4
B1
FILTER MODES
CH1
CH2
0
0
0
1
narrow
narrow recommended for nominal terrestrial broadcast conditions and
SAT with 2 carriers
extra wide narrow recommended only for high-deviation SAT mono carriers
(e.g. obsolete Main channel on Astra)
1
1
0
1
medium
wide
medium recommended for moderately overmodulated broadcast conditions
wide
recommended for strongly overmodulated broadcast conditions
1999 Dec 20
39
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
Table 24 Channel 2 receive mode
B3
B2
CHANNEL 2
0
0
1
0
1
0
FM
AM
NICAM
10.3.7 FM DE-EMPHASIS REGISTER
This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received
carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2.
In the event of A2 reception, both groups must be set to the same characteristics.
Table 25 Subaddress 10 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB) ADEEM2
1
Activates the adaptive de-emphasis function, which is required for certain satellite
FM channels. The standard FM de-emphasis must then be set to 75 µs (note 2).
0
The adaptive de-emphasis is off.
6
5
4
3
B6
B5
−
Time constant selection for FM de-emphasis (see Table 26).
B4
ADEEM1
1
Activates the adaptive de-emphasis function, which is required for certain satellite
FM channels. The standard FM de-emphasis must then be set to 75 µs (note 2).
0
The adaptive de-emphasis is off.
2
1
B2
B1
B0
−
Time constant selection for FM de-emphasis (see Table 27).
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
2. The FM de-emphasis gain is 0 dB at 40 Hz.
Table 26 De-emphasis sound carrier 2
B6
B5
B4
DE-EMPHASIS
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
50 µs (Europe)
60 µs
75 µs (M standard)
J17
off
Table 27 De-emphasis sound carrier 1
B2
B1
B0
DE-EMPHASIS
0
0
0
0
0
1
50 µs (Europe)
60 µs
1999 Dec 20
40
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
B2
B1
B0
DE-EMPHASIS
0
0
1
1
1
0
0
1
0
75 µs (M standard)
J17
off
10.3.8 FM MATRIX REGISTER
This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received
carrier and the related sound mode identification.
Table 28 Subaddress 11 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
−
default value
default value
default value
default value
default value
6
5
4
3
2
1
dematrixing characteristics (see Table 29)
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
Table 29 Dematrixing characteristics
B2
B1
B0
L OUTPUT
R OUTPUT
MODE
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
CH1 input; note 1
CH2 input; note 2
CH1 input; note 1
CH2 input; note 2
2CH1 input − CH2 input
CH1 input; note 1
CH2 input; note 2
CH2 input; note 2
CH1 input; note 1
CH2 input; note 2
mono 1
mono 2
dual
dual swapped
stereo Europe
stereo Korea; note 3
CH1 input + CH2 input
-----------------------------------------------------------
2
CH1 input – CH2 input
----------------------------------------------------------
2
Notes
1. CH1 input: audio signal from FM channel 1.
2. CH2 input: audio signal from FM channel 2.
3. For stereo Korea the dematrix applies 6 dB attenuation (see Table 7).
1999 Dec 20
41
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.9 FM CHANNEL 1 LEVEL ADJUST REGISTER
This register is used to correct for standard and station-dependent differences of signal levels.
Table 30 applies to sound carrier 1.
Table 30 Subaddress 12
MSB
B7
LSB
B0
GAIN SETTING (dB)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
mute
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
42
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.10 FM CHANNEL 2 LEVEL ADJUST REGISTER
This register is used to correct for standard and station-dependent differences of signal levels. Table 31 applies to sound
carrier 2 in its FM and AM modes. In the event of A2, channels 1 and 2 should be adjusted to the same level.
Table 31 Subaddress 13
MSB
B7
LSB
B0
GAIN SETTING (dB)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
mute
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
43
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.11 NICAM CONFIGURATION REGISTER
The decision of whether auto-muting is permitted shall be taken by the controlling microcontroller based on information
contained in the TDA9875A’s status registers. Thus, it depends on the strategy implemented in the software whether the
auto-mute function is in accordance with “NICAM 728 ETS Revised for Data Applications” or any other preference.
The NICAM de-emphasis gain is 0 dB at 40 Hz.
Table 32 Subaddress 14 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
DCXOPULL
1
0
1
0
0
1
Set to lower DCXO frequency during DCXO test mode.
Set to higher DCXO frequency during DCXO test mode.
DCXO test mode on (available only during FM mode); note 2
DCXO normal mode on
6
DCXOTEST
5
4
B5
Set logic to 0.
DOUTEN
Enables the output of the NICAM serial data stream from the DQPSK
demodulator on pin NICAM and of the associated clock on pin PCLK
0
0
1
Both outputs will be 3-stated.
Set logic to 0.
3
2
AMSEL
The auto-mute function will switch the output sound from NICAM L to the
ADC output select register. With the ADC output select register the wanted
signal source, e.g. the mono input, can be pre-set (see Section 10.3.20).
This is useful, if the AM sound NICAM L system is demodulated externally.
0
The auto-mute function will switch the output sound from NICAM L to the
AM program on the internal first sound carrier.
1
NDEEM
AMUTE
1
0
1
Switches the NICAM J17 de-emphasis off.
Switches the NICAM J17 de-emphasis on.
0 (LSB)
Automatic muting is disabled. This bit has only an effect when the second
sound carrier is set to NICAM.
0
Enables the automatic switching between NICAM and the program on the
first sound carrier (i.e. FM mono or AM), dependent on the NICAM bit error
rate.
Notes
1. The default setting at power-up is 0000 0000.
2. The DCXO test mode is intended for checking the DCXO control range with the actually used PCB layout and crystal
type. During the normal operating mode, the DCXO test mode should not be used.
1999 Dec 20
44
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.12 NICAM LEVEL ADJUST REGISTER
This register is used to correct for standard and station-dependent differences of signal levels.
Table 33 applies to both NICAM sound outputs.
Table 33 Subaddress 15 (note 1)
MSB
B7
LSB
B0
GAIN SETTING (dB)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
mute
Note
1. The default setting at power-up is 000 00000.
1999 Dec 20
45
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.13 NICAM LOWER ERROR LIMIT REGISTER
Table 35 Subaddress 17 (notes 1 and 2)
When the auto-mute function is enabled (bit AMUTE in the
NICAM configuration register) and the NICAM bit error
count is lower than the value contained in this register, the
NICAM signal is selected (again) for reproduction
(see Section 10.3.14).
BIT
NAME VALUE
DESCRIPTION
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
−
upper error limit value
6
5
4
Table 34 Subaddress 16 (notes 1 and 2)
3
BIT
NAME VALUE
DESCRIPTION
2
1
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
−
lower error limit value
6
0 (LSB)
5
Notes
4
1. The default setting at power-up is 0101 0000.
3
2. The upper bit error rate
2
1
limit subaddress 17 × 1.74 × 10−5.
0 (LSB)
Notes
1. The default setting at power-up is 0001 0100.
2. The lower bit error rate
limit subaddress 16 × 1.74 × 10−5.
10.3.14 NICAM UPPER ERROR LIMIT REGISTER
When the auto-mute function is enabled (bit AMUTE in the
NICAM configuration register) and the NICAM bit error
count is higher than the value contained in this register, the
signal of the first sound carrier (i.e. FM mono or AM sound)
or the external mono input (depending on bit AMSEL and
ADC output selection) is selected for reproduction.
The difference between upper and lower error limit
constitutes a hysteresis to avoid frequent switching
between NICAM and the program on the first sound
carrier.
1999 Dec 20
46
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.15 AUDIO MUTE CONTROL REGISTER
When any of these bits are set to logic 1, the corresponding pair of output channels will be muted. A bit set to logic 0
allows normal signal output.
There is a soft mute facility for the Main and Auxiliary output channels to provide click-free muting independent of the
volume control. This is switched on/off by bits MUTMAIN and MUTAUX.
Table 36 Subaddress 18 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
MUTI2S2
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
mute I2S2 output
normal I2S2 output
mute I2S1 output
6
MUTI2S1
MUTDAC
MUTLINE
MUTSC2
MUTSC1
MUTAUX
MUTMAIN
normal I2S1 output
5
mute internal DAC
normal internal DAC
mute line outputs
4
normal line outputs
mute SCART 2 outputs
normal SCART 2 outputs
mute SCART 1 outputs
normal SCART 1 outputs
mute Auxiliary outputs
normal Auxiliary outputs
mute Main outputs
3
2
1
0 (LSB)
normal Main outputs
Note
1. The default setting at power-up is 1111 1111.
10.3.16 DAC OUTPUT SELECT REGISTER
This register is used to define both the signal source to be entered into the DAC and the mode of the digital matrix for
signal selection. The DAC is used for signal output from digital sources at analog outputs.
The bits DACGAIN1 and DACGAIN2 can introduce some extra gain at the input to the DAC; DACGAIN1 adds 3 dB and
DACGAIN2 adds 6 dB of gain, respectively.
The two combinations of FM and NICAM apply to the (rare) condition that three different languages are being broadcast
in an FM + NICAM system. They allow for a two-out-of-three selection for external use, such as recording.
1999 Dec 20
47
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
Table 37 Subaddress 19 (note 1)
BIT
NAME
VALUE
DESCRIPTION
extra gain setting (see Table 38)
7 (MSB)
DACGAIN2
−
−
6
B6
DAC output selection (see Table 39)
5
B5
4
B4
DACGAIN1
B2
3
−
−
extra gain setting (see Table 38)
2
1
signal source selection (see Table 40)
B1
0 (LSB)
B0
Note
1. The default setting at power-up is 0000 0000.
Table 38 Extra gain setting
B7
B3
GAIN (dB)
0
0
1
1
0
1
0
1
0
3
6
9
Table 39 DAC output selection
B6
B5
B4
L OUTPUT
R OUTPUT
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
L input
L input
R input
R input
R input
L input
R input
L input
L + R
-------------
2
L + R
-------------
2
Table 40 Signal source selection
SIGNAL SOURCE
B2
B1
B0
LEFT
RIGHT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FM left
NICAM left
I2S1 left
FM right
NICAM right
I2S1 right
I2S2 right
ADC right
AVL right
I2S2 left
ADC left
AVL left
FM mono
FM mono
NICAM M1
NICAM M2
1999 Dec 20
48
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.17 SCART 1 OUTPUT SELECT REGISTER
This register is used to define both the signal source to be output at SCART 1 and the output channel selector mode.
Table 41 Subaddress 20 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
6
B7
0
1
default value
SC1GAIN
Activates the 3 dB gain stage at the SCART 1 output buffers. As any SCART input
passes a 3 dB attenuator, this gain stage can be used to compensate that
attenuation, resulting in a 0 dB insertion loss when copying from SCART 2 input to
SCART 1 output. However, that gain must be used with great care, as it will cause
signal clipping at high input levels.
0
the audio signal output will be unchanged (0 dB gain)
output channel selection (see Table 42)
5
B5
B4
B3
B2
B1
B0
−
4
3
0
default value
2
1
−
signal source selection (see Table 43)
0 (LSB)
Note
1. The default setting at power-up is 0000 0001.
Table 42 Output channel selection
B5
B4
L OUTPUT
R OUTPUT
0
0
1
1
0
1
0
1
L input
L input
R input
R input
R input
L input
R input
L input
Table 43 Signal source selection
B2
0
B1
0
B0
0
SIGNAL SOURCE
SCART 1 input
SCART 2 input
external input
mono input
0
0
1
0
1
0
0
1
1
1
0
0
DAC input
1999 Dec 20
49
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.18 SCART 2 OUTPUT SELECT REGISTER
This register is used to define both the signal source to be output at SCART 2 and the output channel selector mode.
Table 44 Subaddress 21 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
6
B7
0
1
SC2GAIN
Activates the 3 dB gain stage at the SCART 2 output buffers. As any SCART input
passes a 3 dB attenuator, this gain stage can be used to compensate that
attenuation, resulting in a 0 dB insertion loss when copying from SCART 1 input to
SCART 2 output. However, that gain must be used with great care, as it will cause
signal clipping at high input levels.
0
the audio signal output will be output (0 dB gain)
output channel selection (see Table 45)
5
B5
B4
B3
B2
B1
B0
−
4
3
0
default value
2
1
−
signal source selection (see Table 46)
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
Table 45 Output channel selection
B5
B4
L OUTPUT
R OUTPUT
0
0
1
1
0
1
0
1
L input
L input
R input
R input
R input
L input
R input
L input
Table 46 Signal source selection
B2
0
B1
0
B0
0
SIGNAL SOURCE
SCART 1 input
SCART 2 input
external input
mono input
0
0
1
0
1
0
0
1
1
1
0
0
DAC input
1999 Dec 20
50
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.19 LINE OUTPUT SELECT REGISTER
By definition, the line output conveys the same signal as the Main (loudspeaker) channel, but in a non-processed form.
This register is used to characterize the signal to be output at the line output and define the output channel selector mode.
Table 47 Subaddress 22 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
6
B7
0
1
0
−
set to logic 0
LINGAIN
activates the 3 dB gain stage at the line output buffers
audio signal will be output unchanged (0 dB gain)
output channel selection (see Table 48)
5
B5
B4
4
3
B3
0
0
0
1
set to logic 0
set to logic 0
set to logic 0
2
1
B2
B1
0 (LSB)
LINSEL
A signal from an analog source is being processed in the Main channel for line
output. Analog signal sources comprise SCART 1 input, SCART 2 input,
external input and mono input, i.e. any input to the ADC.
0
A signal from a digital source is being processed in the Main channel for line
output. Digital signal sources comprise FM, NICAM, I2S1 input and I2S2 input.
Note
1. The default setting at power-up is 0000 0000.
Table 48 Output channel selection
B5
B4
L OUTPUT
R OUTPUT
0
0
1
1
0
1
0
1
L input
L input
R input
R input
R input
L input
R input
L input
1999 Dec 20
51
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.20 ADC OUTPUT SELECT REGISTER
This register is used to define the signal source for the ADC. There is no output channel selector, because all digital
signal sinks of the ADC have their own matrix. Instead, a level adjustment facility for the ADC output is provided.
Table 49 Subaddress 23 (note 1)
BIT
NAME
VALUE
DESCRIPTION
signal source selection (see Table 50)
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
−
6
5
4
−
ADC level adjust (see Table 51)
3
2
1
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
Table 50 Signal source selection
B7
B6
B5
SIGNAL SOURCE
0
0
0
0
0
0
1
1
0
1
0
1
SCART 1 input
SCART 2 input
external input
mono input
1999 Dec 20
52
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
Table 51 ADC level adjust (note 1)
B4
B3
B2
B1
B0
GAIN SETTING (dB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
mute
Note
1. If the ADC level adjust is set to 0 dB a full-scale input signal to the ADC results into a full-scale level of −6 dB at the
digital crossbar.
1999 Dec 20
53
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.21 MAIN CHANNEL SELECT REGISTER
This register is used to define both the signal source to be processed in the Main (loudspeaker) channel and the mode
of the digital matrix for signal selection.
Table 52 Subaddress 24 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
0
default value
6
−
output channel selection (see Table 53)
5
4
3
0
default value
2
1
−
signal source selection (see Table 54)
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
Table 53 Output channel selection
B6
B5
B4
L OUTPUT
R OUTPUT
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
L input
L input
R input
R input
R input
L input
R input
L input
L + R
-------------
2
L + R
-------------
2
Table 54 Signal source selection
B2
B1
B0
SIGNAL SOURCE
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
FM input
NICAM input
I2S1 input
I2S2 input
ADC input
1999 Dec 20
54
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.22 AUDIO EFFECTS REGISTER (MAIN)
Switching the AVL off will reset the associated hardware to a defined state. When the signal source for the Main channel
is changed while the AVL is on, the AVL needs to be reset in order to avoid excessive settling times. This can be achieved
by switching the AVL off and on again.
The pseudo stereo function is based on an all-pass filter. A 90 degrees phase shift occurs at the frequencies stated in
Table 57. There is a gain of 3 dB in the left audio channel.
Table 55 Subaddress 25 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
0
0
−
Default value.
Default value.
6
5
4
B6
SPATIAL1
SPATIAL0
These bits set the amount of the effect function (stereo base width expansion)
for stereo signals in the Main channel (see Table 56). This function should be
activated only in accordance with the result of the sound mode identification.
3
2
PSEUDO1
PSEUDO0
−
−
These bits set the amount of the effect function (pseudo stereo) for mono
signals in the Main channel (see Table 57). This function should be activated
only in accordance with the result of the sound mode identification.
1
AVL1
AVL0
These bits set the mode of operation of the automatic volume level control
function at the entrance to the Main (loudspeaker) channel (see Table 58).
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
Table 56 Spatial control setting
B5
B4
SPATIAL SETTING (%)
0
0
1
1
0
1
0
1
off
30
40
52
Table 57 Pseudo control setting
B3
0
B2
0
PSEUDO SETTING (Hz)
off
0
1
300
200
150
1
0
1
1
Table 58 AVL control mode
B1
0
B0
AVL MODE
off/reset
0
1
0
1
0
short decay
medium decay
long decay
1
1
1999 Dec 20
55
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.23 VOLUME CONTROL REGISTERS (MAIN)
These two registers control the volume setting of the Main (loudspeaker) channel. The register at subaddress 26 applies
to the left channel signal, while the register at subaddress 27 applies to the right channel signal.
Balance control is exercised by offsetting the left and right channel volume settings.
Table 59 Subaddresses 26 and 27
MSB
B7
LSB
B0
VOLUME SETTING (dB)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+24
+23
+22
+21
+20
+19
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
1999 Dec 20
56
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
MSB
LSB
B0
VOLUME SETTING (dB)
B7
B6
B5
B4
B3
B2
B1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
−10
−11
−12
−13
−14
−15
−16
−17
−18
−19
−20
−21
−22
−23
−24
−25
−26
−27
−28
−29
−30
−31
−32
−33
−34
−35
−36
−37
−38
−39
−40
−41
−42
−43
−44
−45
−46
−47
−48
1999 Dec 20
57
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
MSB
LSB
B0
VOLUME SETTING (dB)
B7
B6
B5
B4
B3
B2
B1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
−49
−50
−51
−52
−53
−54
−55
−56
−57
−58
−59
−60
−61
−62
−63
−64
−65
−66
−67
−68
−69
−70
−71
−72
−73
−74
−75
−76
−77
−78
−79
−80
−81
−82
−83
mute (note 1)
Note
1. The default setting at power-up is 1010 1100.
1999 Dec 20
58
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.24 CONTOUR CONTROL REGISTER (MAIN)
This register is used to apply the contour or loudness function (physiological volume control) to the left and right signal
channels of the Main channel by means of an extra bass boost. The gain setting must be chosen in accordance with the
volume control setting for the Main channel. For example, the contour gain could be incremented for every 5 dB, or so,
of decrease of the volume setting. This needs to be done by the microcontroller. The 0 dB contour setting is equal to
contour off.
Table 60 Subaddress 28
MSB
B7
LSB
B0
CONTOUR GAIN (dB)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 (note 1)
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
59
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.25 BASS CONTROL REGISTER (MAIN)
This register is used to apply bass control to the left and right signal channels of the Main channel.
Table 61 Subaddress 29
MSB
B7
LSB
B0
BASS SETTING (dB)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
60
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.26 TREBLE CONTROL REGISTER (MAIN)
This register is used to apply treble control to the left and right signal channels of the Main channel.
Table 62 Subaddress 30
MSB
B7
LSB
B0
TREBLE SETTING (dB)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
61
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.27 AUXILIARY CHANNEL SELECT REGISTER
This register is used to define both the signal source to be processed in the Auxiliary (headphone) channel and the mode
of the digital matrix for signal selection.
Table 63 Subaddress 31 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
0
default value
6
−
output channel selection (see Table 64)
5
4
3
0
default value
2
1
−
signal source selection (see Table 65)
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
Table 64 Output channel selection
B6
B5
B4
L OUTPUT
R OUTPUT
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
L input
L input
R input
R input
R input
L input
R input
L input
L + R
-------------
2
L + R
-------------
2
Table 65 Signal source selection
B2
B1
B0
SIGNAL SOURCE
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
FM input
NICAM input
I2S1 input
I2S2 input
ADC input
AVL input
1999 Dec 20
62
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.28 VOLUME CONTROL REGISTERS (AUXILIARY)
These two registers control the volume setting of the Auxiliary (headphone) channel. The register at subaddress 32
applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal.
Balance control is exercised by offsetting the left and right channel volume settings.
Table 66 Subaddresses 32 and 33
MSB
B7
LSB
B0
VOLUME SETTING (dB)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+24
+23
+22
+21
+20
+19
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
1999 Dec 20
63
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
MSB
LSB
B0
VOLUME SETTING (dB)
B7
B6
B5
B4
B3
B2
B1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
−11
−12
−13
−14
−15
−16
−17
−18
−19
−20
−21
−22
−23
−24
−25
−26
−27
−28
−29
−30
−31
−32
−33
−34
−35
−36
−37
−38
−39
−40
−41
−42
−43
−44
−45
−46
−47
−48
−49
−50
−51
1999 Dec 20
64
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
MSB
LSB
B0
VOLUME SETTING (dB)
B7
B6
B5
B4
B3
B2
B1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
−52
−53
−54
−55
−56
−57
−58
−59
−60
−61
−62
−63
−64
−65
−66
−67
−68
−69
−70
−71
−72
−73
−74
−75
−76
−77
−78
−79
−80
−81
−82
−83
mute (note 1)
Note
1. The default setting at power-up is 1010 1100.
1999 Dec 20
65
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.29 BASS CONTROL REGISTER (AUXILIARY)
This register is used to apply bass control to the left and right signal channels of the Auxiliary channel.
Table 67 Subaddress 34
MSB
B7
LSB
B0
BASS SETTING (dB)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
66
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.30 TREBLE CONTROL REGISTER (AUXILIARY)
This register is used to apply treble control to the left and right signal channels of the Auxiliary channel.
Table 68 Subaddress 35
MSB
B7
LSB
B0
TREBLE SETTING (dB)
B6
B5
B4
B3
B2
B1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
67
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER
Table 69 Subaddress 36 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
B6
0
0
0
−
default value
default value
default value
6
5
4
3
2
B5
SYSCL1
SYSCL0
SYSOUT
system clock frequency selection (see Table 70)
1
0
1
enables the output of a system (or master) clock signal at pin SYSCLK
the output will be off, thereby improving the EMC performance
1
I2SFORM
I2SOUT
an MSB-aligned (MSB-first) serial output format is selected, i.e. a level change at
pin WS indicates the beginning of a new audio sample
the standard I2S-bus output format is selected
enables the I2S-bus outputs (both serial data outputs plus serial bit clock and word
select) in a format determined by bit I2SFORM; the TDA9875A is then an I2S-bus
master
0
1
0 (LSB)
0
the outputs mentioned will be 3-stated, thereby improving the EMC performance
Note
1. The default setting at power-up is 0000 0000.
Table 70 System clock frequency selection
B4
B3
SYSCLK OUTPUT
FREQUENCY (MHz)
0
0
1
1
0
1
0
1
256fs
384fs
512fs
768fs
8.192
12.288
16.384(1)
24.576
Note
1. With 16.384 MHz the duty cycle is 33%.
1999 Dec 20
68
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.32 I2S1 OUTPUT SELECT REGISTER
This register is used to define both the signal source to be output at I2S1 and the mode of the digital matrix for signal
selection.
Table 71 Subaddress 37 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
0
default value
6
−
output selection (see Table 72)
5
4
3
0
default value
2
1
−
signal source selection (see Table 73)
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
Table 72 Output selection
B6
B5
B4
L OUTPUT
R OUTPUT
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
L input
L input
R input
R input
R input
L input
R input
L input
L + R
-------------
2
L + R
-------------
2
Table 73 Signal source selection (note 1)
B2
B1
B0
SIGNAL SOURCE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FM output
NICAM output
I2S1 input
I2S2 input
ADC output
AVL output
Auxiliary output
Main output
Note
1. The Main and Auxiliary channel outputs will not contain the beeper signal.
1999 Dec 20
69
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.33 I2S1 INPUT LEVEL ADJUST REGISTER
This register is used to adjust the input level at the I2S1 interface. Left and right signal channel are treated identically.
Table 74 Subaddress 38
MSB
LSB
GAIN SETTING (dB)
B7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
B2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
B1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
B0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
mute
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
70
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.34 I2S1 OUTPUT LEVEL ADJUST REGISTER
This register is used to adjust the output level at the I2S1 interface. Left and right signal channel are treated identically.
Table 75 Subaddress 39
MSB
LSB
GAIN SETTING (dB)
B7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
B2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
B1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
B0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
mute
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
71
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.35 I2S2 OUTPUT SELECT REGISTER
This register is used to define both the signal source to be output at I2S2 and the mode of the digital matrix for signal
selection.
Table 76 Subaddress 40 (note 1)
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
0
default value
6
−
output selection (see Table 77)
5
4
3
0
default value
2
1
−
signal source selection (see Table 78)
0 (LSB)
Note
1. The default setting at power-up is 0000 0000.
Table 77 Output selection
B6
B5
B4
L OUTPUT
R OUTPUT
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
L input
L input
R input
R input
R input
L input
R input
L input
L + R
-------------
2
L + R
-------------
2
Table 78 Signal source selection (note 1)
B2
B1
B0
SIGNAL SOURCE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FM output
NICAM output
I2S1 input
I2S2 input
ADC output
AVL output
Auxiliary output
Main output
Note
1. The Main and Auxiliary channel outputs will not contain the beeper signal.
1999 Dec 20
72
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.36 I2S2 INPUT LEVEL ADJUST REGISTER
This register is used to adjust the input level at the I2S2 interface. Left and right signal channel are treated identically.
Table 79 Subaddress 41
MSB
LSB
GAIN SETTING (dB)
B7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
B2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
B1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
B0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
mute
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
73
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.37 I2S2 OUTPUT LEVEL ADJUST REGISTER
This register is used to adjust the output level at the I2S2 interface. Left and right signal channel are treated identically.
Table 80 Subaddress 42
MSB
LSB
GAIN SETTING (dB)
B7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
B2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
B1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
B0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0 (note 1)
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
mute
Note
1. The default setting at power-up is 0000 0000.
1999 Dec 20
74
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.38 BEEPER FREQUENCY CONTROL REGISTER
This register is used to select from sample beeper oscillator frequencies. The beeper output signal is added to the Main
and Auxiliary channel output DAC.
Due to the frequency response of the audio DACs upsampling filters, the 25 kHz beep is approximately 5 dB louder than
the 390 Hz beep.
Table 81 Subaddress 43 (note 1)
MSB
B7
LSB
B0
GENERATED FREQUENCY (Hz)
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
25000
7040
3580
1770
1270
900
640
390
Note
1. The default setting at power-up is 0000 0000.
10.3.39 BEEPER VOLUME CONTROL REGISTER
This register is used to set the beeper volume. The gain setting is relative to digital full-scale at the input to the Main and
Auxiliary channel output DACs. The beeper volume is independent of any other volume setting.
The beeper signal is added to the Main and Auxiliary channel output signals in the 2 × fs domain. The beeper volume
should be set with great care, when the audio signals in the Main and Auxiliary channels are close to digital full-scale, to
avoid output signal distortion due to overload.
1999 Dec 20
75
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
Table 82 Subaddress 44
MSB
LSB
B0
GAIN SETTING (dB)
B7
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
−3
−6
−9
−12
−15
−18
−21
−24
−27
−30
−33
−36
−39
−42
−45
−48
−51
−54
−57
−60
−63
−66
−69
−72
−75
−78
−81
−84
−87
−90
−93
mute (note 1)
Note
1. The default setting at power-up is 0010 0000.
1999 Dec 20
76
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.40 BASS BOOST CONTROL REGISTER
This register is used to select from a few sample bass boost settings to modify the frequency characteristics of the Main
channel (shelving filter). Bits B3 to B0 apply to the left channel, bits B7 to B4 apply to the right channel. This function
must be used with care in order to avoid clipping distortion at high volume settings.
More sophisticated control of the bass boost filter can be exercised in the expert mode (see Section 10.5). The user then
has full control over this second-order filter and can, within limits, realize bass equalizers with arbitrary centre
frequencies, Q factors and boost/cut settings.
Table 83 Subaddress 45 (note 1)
BIT
NAME
B7
VALUE
DESCRIPTION
7 (MSB)
−
gain setting of right channel (see Table 84)
6
B6
5
B5
4
B4
3
B3
−
gain setting of left channel (see Table 85)
2
1
B2
B1
0 (LSB)
B0
Note
1. The default setting at power-up is 0000 0000.
Table 84 Gain setting right channel
B7
B6
B5
B4
GAIN SETTING (dB)
CORNER FREQUENCY (Hz)
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
20
18
16
14
12
10
8
350
350
350
350
350
350
350
350
350
350
350
6
4
2
0
1999 Dec 20
77
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
Table 85 Gain setting left channel
B3
B2
B1
B0
GAIN SETTING (dB)
CORNER FREQUENCY (Hz)
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
20
18
16
14
12
10
8
350
350
350
350
350
350
350
350
350
350
350
6
4
2
0
1999 Dec 20
78
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.4 Slave transmitter mode
As a slave transmitter, the TDA9875A provides 13 registers with status information and data, a part of which is for Philips
internal purposes only. These registers can be accessed by means of subaddresses.
Table 86 General format for reading data from the TDA9875A
S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS
1
ACK
DATA NAm P
Table 87 Explanation of Tables 86 and 88
BIT
FUNCTION
S
START condition
SLAVE ADDRESS
7-bit device address
0
data direction bit (write to device)
acknowledge (by the slave)
address of register to read from
repeated START condition
data direction bit (read from device)
data byte read from register
not acknowledge (by the master)
acknowledge (by the master)
STOP condition
ACK
SUBADDRESS
Sr
1
DATA
NAm
Am
P
Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the
TDA9875A. In this situation, the subaddress is automatically incremented after each data byte, which results in reading
the sequence of data bytes from successive register locations, starting at SUBADDRESS.
Table 88 Format of a transmission using automatic incrementing of subaddresses
S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr
SLAVE
ADDRESS
1 ACK
DATA BYTE
Am(1)
DATA NAm P
Note
1. n data bytes with auto-increment of subaddresses.
Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master).
The subaddresses ‘wrap around’ from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress,
the device will send a data pattern of all ones, i.e. FF in hexadecimal notation.
1999 Dec 20
79
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
Table 89 Overview of the slave transmitter registers (note 1)
DATA
SUBADDRESS
(DECIMAL)
FUNCTION
MSB
LSB
0
1
s
s
e
d
c
l
s
s
e
d
c
l
s
s
e
d
X
l
s
s
e
d
c
l
s
s
e
d
c
l
s
s
e
d
d
l
s
s
e
d
d
l
s
s
e
d
d
l
device status (power-on, identification, etc.)
NICAM status
2
NICAM error count
3
additional data (LSB)
additional data (MSB)
level read-out (MSB)
level read-out (LSB)
SIF level
4
5
6
l
l
l
l
l
l
l
l
7
X
a
a
a
d
s
X
a
a
a
d
s
X
a
a
a
d
s
c
a
a
a
d
s
c
a
a
a
d
s
c
a
a
a
d
s
c
a
a
a
d
s
c
a
a
a
d
s
251
252
253
254
255
test register 3; note 2
test register 2; note 2
test register 1; note 2
device identification code
software identification code
Notes
1. X indicates a bit that has not been assigned to a function. This bit is reserved for future extensions.
2. Registers from subaddress 251 to 255 are for Philips internal purposes only. They are considered as a set of
registers for the identification of individual members and some key parameters in a family of devices.
The following sub-sections provide a detailed description of the slave transmitter registers.
1999 Dec 20
80
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.4.1 DEVICE STATUS REGISTER
Table 90 Subaddress 0
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
P2IN
−
This bit reflects the status of the corresponding general purpose port of pin P2
(see Section 10.3.2).
6
5
P1IN
−
This bit reflects the status of the corresponding general purpose port of pin P1
(see Section 10.3.2).
RSSF
1
Reserve sound switching flag: this bit is a copy of the C4 bit in the NICAM status
register. It indicates that the FM (or AM for standard L) sound matches the
digital transmission and auto-muting should be enabled.
0
1
Auto-muting should be disabled, as analog and digital sound are different.
4
AMSTAT
Auto-mute status: it indicates that the auto-muting function has switched from
NICAM to the program of the first sound carrier (i.e. FM mono or AM in the
NICAM L system) or to the ADC (depending on bit AMSEL).
0
1
0
−
Auto-muting function has not switched.
3
2
VDSP
Indicates that digital transmission is a sound source (NICAM).
The transmission is either data or currently undefined format (NICAM).
IDDUA
This bit is logic 1 if an FM dual-language signal has been identified. When
neither IDSTE nor IDDUA are set, the received signal has to be assumed to be
FM mono.
1
IDSTE
POR
−
−
This bit is logic 1 if an FM stereo signal has been identified.
0 (LSB)
Power fail bit: the power supply for the digital part of the device, VDDD2, has
temporarily been lower than the specified lower limit. If this is detected an
initialization of the TDA9875A has to be carried out to ensure a reliable
operation.
1999 Dec 20
81
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.4.2 NICAM STATUS REGISTER
The TDA9875A does not support the Extended Control Modes. Therefore, the program of the first sound carrier
(i.e. FM mono or AM) is selected for reproduction in case bit C3 is set to logic 1, independent of bit AMUTE in the NICAM
configuration register being set or not.
When a NICAM transmitter is switched off, the device will lose synchronization. In this situation the program of the first
sound carrier is selected for reproduction, independent of bit AMUTE being set or not.
Table 91 Subaddress 1
BIT
NAME
C4
VALUE
DESCRIPTION
7 (MSB)
−
application control bits (C1 to C4 in the NICAM transmission)
6
5
4
3
C3
C2
C1
OSB
1
0
1
0
1
0
1
0
indication that the device has both frame and C0 (16 frame) synchronization
the audio output from the NICAM part should be digital silence
indication of a configuration change at the 16 frame (C0) boundary
no configuration change
2
1
CFC
S/MB
D/SB
indication of NICAM stereo mode
no NICAM stereo mode
0 (LSB)
indication NICAM dual mono mode
no NICAM dual mono mode
10.4.3 NICAN ERROR COUNT REGISTER
Bits B7 to B0 contain the number of errors occurring in the previous 128 ms period. The register is updated every 128 ms.
Table 92 Subaddress 2
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
−
number of errors
6
5
4
3
2
1
0 (LSB)
1999 Dec 20
82
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.4.4 ADDITIONAL DATA REGISTERS
These two bytes provide information on the additional data bits.
Table 93 Subaddress 3
BIT
NAME
VALUE
DESCRIPTION
comprise the additional data word
7 (MSB)
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
−
6
5
4
3
2
1
0 (LSB)
Table 94 Subaddress 4
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
OVW
1
new additional data bits are written to the IC without the previous bits being
read
0
1
0
−
−
no bits are written
6
SAD
new additional data is written into the IC
this bit is set to logic 0 when the additional data bits are read
don’t care
5
X
4
CI1
these are CI bits decoded by majority logic from the parity checks of the last
ten samples in a frame
3
CI2
2
1
AD10
AD9
AD8
−
comprise the additional data word
0 (LSB)
1999 Dec 20
83
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.4.5 LEVEL READ-OUT REGISTERS
Table 96 Subaddress 7
These two bytes constitute a word that provides data from
a location that has been specified with the monitor select
register. The most significant byte of the data is stored at
subaddress 5.
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
−
bit not assigned
bit not assigned
bit not assigned
6
5
If peak-level monitoring has been selected, the peak-level
monitoring register is cleared and monitoring resumes
after its contents has been transferred to these two bytes.
4
indication of SIF
input level
3
2
1
Table 95 Subaddresses 5 and 6
SUB-
ADDRESS
0 (LSB)
BIT
DESCRIPTION
10.4.7 TEST REGISTER 3
5
7 (MSB) most significant bit or sign bit
6
This register contains, as a binary number, the highest
memory address used for the Coefficient RAM (CRAM,
expert mode).
5
4
3
Table 97 Subaddress 251
2
MSB
LSB
1
B7
B6
B5
B4
B3
B2
B1
B0
0 (LSB)
0
1
1
1
1
1
1
1
6
7 (MSB)
6
10.4.8 TEST REGISTER 2
5
This register contains, as a binary number, the highest
subaddress used for slave receiver registers.
4
3
2
Table 98 Subaddress 252
1
MSB
LSB
0 (LSB) least significant bit
B7
B6
B5
B4
B3
B2
B1
B0
10.4.6 SIF LEVEL REGISTER
0
0
1
0
1
1
0
1
When the SIF AGC is on, bits B4 to B0 of this register
contain a number that gives an indication of the SIF input
level. That number corresponds to the AGC gain register
setting (see Section 10.3.1).
When the SIF AGC is off, this register returns the contents
of the AGC gain register.
1999 Dec 20
84
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.4.9 TEST REGISTER 1
As the coefficients do not fit into one data byte, they have
to be split and arranged (see Table 104). The most
significant bit is transferred first.
This register contains, as a binary number, the highest
subaddress used for slave transmitter (status) registers.
The general format described in Table 104 shows the
minimum number of data bytes required, i.e. two bytes for
the transfer of a single coefficient.
Table 99 Subaddress 253
MSB
LSB
Should more than one coefficient be sent, then the CRAM
address will be automatically incremented after each
coefficient, resulting in writing the sequence of coefficients
into successive memory locations, starting at
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
1
1
1
CRAM ADDRESS. A transmission can start with any valid
CRAM address. If two coefficients are to be transferred,
they are arranged as shown in Table 105.
10.4.10 DEVICE IDENTIFICATION CODE
There will be several devices in the digital TV sound
processor family. This byte is used to identify the individual
family members.
With any odd number of coefficients to be transferred, the
least significant nibble of the last byte is regarded as
containing don’t care data.
Table 100 Subaddress 254
As the transfer of coefficients cannot be accomplished
within one audio sample period, it is necessary that
received coefficients be buffered and made active all at the
same time to avoid audio signal transients. The receive
buffer is designed to store up to 8 coefficients in addition
to the CRAM address. Each byte that fits into the buffer is
acknowledged with ACK (acknowledge). If an attempt is
made to write more coefficients than the buffer can store,
the device acknowledges with NACK (not acknowledge)
and any further coefficients are ignored. Coefficients that
are already in the receive buffer remain intact.
MSB
LSB
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
1
0
10.4.11 SOFTWARE IDENTIFICATION CODE
It is likely that during the life time of this family of devices
several versions of the DSP software will be made, e.g., to
accommodate new application concepts, respond to
customer wishes, etc. This byte is used to identify the
different releases.
An expert mode transfer ends when the I2C-bus STOP
condition or a repeated START condition has been
detected. Only those coefficients that have been received
during the last transmission will then be copied from the
buffer to the CRAM.
Table 101 Subaddress 255
MSB
LSB
B7
B6
B5
B4
B3
B2
B1
B0
To make efficient and correct use of the expert mode, it is
recommended to transfer all coefficients for any one
function in a single transmission.
0
0
0
0
0
0
1
0
10.5 Expert mode
There is no checking of memory addresses and the
automatic incrementing of addresses does not stop at the
highest used CRAM address. The user of this expert mode
must be fully acquainted with the relevant procedures.
In addition to the slave receiver and slave transmitter
modes previously described, there is a special ‘expert’
mode that gives direct write access to the internal CRAM
of the DSP.
More information concerning the functions of this device,
such as the number of coefficients per function, their
default values, memory addresses, etc., can be supplied
on request at a later date.
In this mode, transferred data contain 12-bit coefficients.
As these coefficients bypass on-chip coefficient look-up
tables for many functions, they directly influence the
processing of signals within the DSP.
This mode must be used with great care. It can be used to
create user-defined characteristics, such as a tone control
with different corner frequencies or special boost/cut
characteristics to correct the low-frequency loudspeaker
and/or cabinet frequency responses.
1999 Dec 20
85
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
Table 102 General format for entering the expert mode and writing coefficients into the TDA9875A
S
SLAVE
0
ACK 10000000
ACK
CRAM
ACK DATA ACK DATA
ACK
P
ADDRESS
ADDRESS
Table 103 Explanation of Table 102
BIT
FUNCTION
S
START condition
7-bit device address
SLAVE ADDRESS
0
data direction bit (write to device)
acknowledge
ACK
10000000
pattern to enter the expert mode
CRAM ADDRESS
start address of coefficient RAM to write to
data byte containing part of a coefficient
STOP condition
DATA
P
Table 104 General format (notes 1, 2 and 3)
BYTE
DATA
DESCRIPTION
2 MST of 1st coefficient
1 LST of 1st coefficient
1 data byte
2 data byte
a
a
a
a
a
a
a
a
a
a
a
a
X
X
X
X
Notes
1. X = don’t care.
2. MST = most significant third.
3. LST = least significant third.
Table 105 Transfer of two coefficients
BYTE
DATA
DESCRIPTION
2 MST of 1st coefficient
1 data byte
2 data byte
3 data byte
a
a
b
a
a
b
a
a
b
a
a
b
a
b
b
a
b
b
a
b
b
a
b
b
1 LST of 1st coefficient + 1 MST of 2nd coefficient
2 LST of 2nd coefficient
1999 Dec 20
86
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
11 I2S-BUS DESCRIPTION
Apart from just feeding a digital audio device, such as a
DAC or an AES/EBU transmitter, the serial data outputs
can be connected directly to the serial inputs (loop-back
connection) or first to an external device, e.g. a feature
DSP such as the SAA7710 and then back to the serial
inputs. In all of these configurations, the SCK and WS
clocks will be generated by the TDA9875A, which then is
the I2S-bus master.
The feature interface of the TDA9875A contains two serial
audio inputs and outputs and associated clock signals.
It can be used to supply, for example, audio signals from
received TV programs to a digital audio output device
(AES/EBU format), or import serial audio signals from
other sources for reproduction through the TV set’s
loudspeaker and/or headphone channels. Apart from such
simple data input or output, it is also possible to run audio
signals through an external DSP, which performs some
additional functions, such as room simulation, Dolby
Surround Pro Logic etc. and feed those signals back into
the loudspeaker and/or headphone channels of the
TDA9875A.
The serial data inputs, SDI1 and SDI2, are active at all
times, independent of the serial data outputs being on or
off. When the serial data outputs are off (either after
power-up or via the appropriate I2C-bus command) serial
data and clocks WS and SCK from a separate digital audio
source can be fed into the TDA9875A, be processed and
output in accordance with internal selector positions,
provided that the following criteria are met:
Two serial audio formats are supported at the feature
interface, i.e. the I2S-bus format and a very similar
MSB-aligned format. The difference is illustrated in Fig.9.
• 32 kHz audio sample frequency
• 32 clock bits per sample
In both formats the left audio channel of a stereo sample
pair is output first and is placed on the serial data line (SDI
for input, SDO for output) when the Word Select line (WS)
is LOW. Data is written at the trailing edge of SCK and
read at the leading edge of SCK. The most significant bit
is sent first.
• External timing and data synchronized to TDA9875A.
In such cases, the external source is the I2S-bus master
and the TDA9875A is the I2S-bus slave.
To support synchronization of external devices or as a
master clock for them, a system clock output, SYSCLK, is
available from the TDA9875A. At power-up it is off. It can
be enabled and the output frequency set via an I2C-bus
command. Available output frequencies are
At power-up, the outputs of the feature interface are
3-stated to reduce EMC and allow for combinations with
other ICs. If output is desired, it has to be activated by
means of an I2C-bus command.
8.192, 12.288, 16.384 and 24.576 MHz.
When the output is enabled, the serial audio data can be
taken from pins SDO1 and SDO2. Depending on the
signal source, switch and matrix positions, the output can
be either mono, stereo or dual language sound on either
output.
The word select output is clocked with the audio sample
frequency at 32 kHz. The serial clock output (SCK) is
clocked at a frequency of 2.048 MHz. This means, that
there are 64 clock pulses per pair of stereo output
samples, or 32 clock pulses per sample. Depending again
on the signal source, the number of significant bits on the
serial data outputs, SDO1 and SDO2, is between
14 and 18.
1999 Dec 20
87
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
SCK
WS
SD
LSB MSB
LSB MSB
MGK112
one sample
a. I2S-bus format.
SCK
WS
SD
LSB MSB
LSB MSB
MGK113
one sample
b. MSB-aligned format.
Fig.9 Serial audio interface formats.
1999 Dec 20
88
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
12 APPLICATION INFORMATION
V
R19
PCLK
1 (57)
DDD2
(56) 64
(55) 63
(54) 62
(53) 61
(52) 60
(51) 59
(50) 58
(49) 57
(48) 56
(47) 55
(46) 54
(45) 53
(44) 52
(43) 51
(42) 50
(41) 49
(40) 48
(39) 47
(38) 46
(37) 45
(36) 44
(35) 43
(34) 42
(33) 41
(32) 40
(31) 39
(30) 38
(29) 37
(28) 36
(27) 35
(26) 34
+5 V
C35
47 µF 1.5 Ω
C34
NICAM
2 (58)
LOR
LOL
2.2 µF
C33
ADDR1
3 (59)
2.2 µF
C32
SCL
MOL
MOR
4 (60)
10 nF
C30
C31
C29
2.2 µF
SDA
5 (61)
10 nF
2.2 µF
R8
V
V
SSA1
DDA
6 (62)
+5 V
47 µF
C28
C26
2.2 Ω
C27
V
DEC1
AUXOL
AUXOR
7 (63)
10 nF
C1
4.7 µF
2.2 µF
C25
R1
I
ref
8 (64)
C24
10 nF
10 kΩ
2.2 µF
V
P1
SSA3
9 (1)
C23
C2
SIF2
PCAPL
PCAPR
10 (2)
SIFSAT
SIFTV
47 pF
10 nF
C3
C22
V
ref1
11 (3)
100 nF
10 nF
C21
C4
V
SIF1
ref3
12 (4)
47 pF
47 µF
C20
SCOL2
SCOR2
ADDR2
13 (5)
2.2 µF
C19
V
SSD1
14 (6)
2.2 µF
V
R2
1.5 Ω
V
SSA4
DDD1
15 (7)
+5 V
C5
47 µF
C6
V
SSD2
CRESET
16 (8)
TDA9875A
(TDA9875AH)
1 µF
C18
V
SCOL1
SCOR1
SSD4
17 (9)
2.2 µF
C17
XTALI
18 (10)
19 (11)
20 (12)
21 (13)
22 (14)
23 (15)
24 (16)
25 (17)
26 (18)
27 (19)
28 (20)
29 (21)
30 (22)
31 (23)
32 (24)
2.2 µF
C16
24.576 MHz
V
ref2
XTALO
P2
47 µF
i.c.
i.c.
SYSCLK
SCK
V
SSA2
i.c.
i.c.
WS
SDO2
SDO1
SDI2
V
ref(n)
C15
47 µF
V
R7
ref(p)
C14
4.7 µF
270 Ω
V
DEC2
SDI1
C13
R6
15 kΩ
SCIL2
TEST1
MONOIN
TEST2
EXTIR
EXTIL
330 nF
C7
C12
R5
SCIR2
15 kΩ
330 nF
470 nF
V
SSD3
C8
C11
330 nF
R4
SCIL1
SCIR1
15 kΩ
470 nF
C9
470 nF
C10
R3
(25) 33
15 kΩ
330 nF
MHB601
The pin numbers given in parenthesis refer to the TDA9875AH version.
Fig.10 Schematic for measurements.
89
1999 Dec 20
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
L9
C42
+5 V
POWER
0 V
V
R13
PCLK
NICAM
ADDR1
SCL
DDD2
1 (57)
2 (58)
3 (59)
4 (60)
5 (61)
6 (62)
7 (63)
8 (64)
9 (1)
(56) 64
(55) 63
(54) 62
(53) 61
(52) 60
(51) 59
(50) 58
(49) 57
(48) 56
(47) 55
(46) 54
(45) 53
(44) 52
(43) 51
(42) 50
(41) 49
(40) 48
(39) 47
(38) 46
(37) 45
(36) 44
(35) 43
(34) 42
(33) 41
(32) 40
(31) 39
(30) 38
(29) 37
(28) 36
(27) 35
(26) 34
+5 V
C1
47 µF
470
nF
1 Ω
C41
LOR
LOL
470 pF
C40
2.2 µF
C39
470 pF
10 nF
10 nF
470 nF
10 nF
10 nF
C38
C36
C34
2.2 µF
L1
L2
C37
R1
MOL
MOR
100 Ω
2.2 µF
C35
R2
SDA
100 Ω
2.2 µF
R12
V
V
SSA1
DDA
+5 V
C32
C31
2.2 Ω
C33
V
DEC1
AUXOL
AUXOR
C2
470 nF
2.2 µF
C29
R3
10 kΩ
I
ref
R4
2.2 kΩ
C30
2.2 µF
V
P1
SSA3
L3
C28
C3
SIF2
PCAPL
PCAPR
10 (2)
11 (3)
12 (4)
13 (5)
14 (6)
15 (7)
16 (8)
17 (9)
18 (10)
19 (11)
20 (12)
21 (13)
22 (14)
23 (15)
24 (16)
25 (17)
26 (18)
27 (19)
28 (20)
29 (21)
30 (22)
31 (23)
32 (24)
SIFSAT
SIFTV
10 nF
47 pF
C4
C27
V
ref1
100 nF
10 nF
L4
C26
C5
V
SIF1
ref3
47 pF
47 µF
C25
SCOL2
SCOR2
ADDR2
C24
470 pF
470 pF
2.2 µF
C23
V
SSD1
C22
2.2 µF
L5
V
R5
V
SSA4
DDD1
+5 V
C6
470 nF
1 Ω
C7
V
SSD2
CRESET
TDA9875A
(TDA9875AH)
1 µF
C21
V
SCOL1
SCOR1
SSD4
C20
C18
470 pF
470 pF
2.2 µF
C19
XTALI
2.2 µF
C17
24.576 MHz
V
ref2
XTALO
P2
47 µF
R6
i.c.
i.c.
2.2 kΩ
SYSCLK
SCK
V
SSA2
i.c.
i.c.
WS
SDO2
SDO1
SDI2
V
ref(n)
C16
47 µF
V
R11
ref(p)
C15
470 nF
270 Ω
V
DEC2
SDI1
C14
330 nF
R10
SCIL2
TEST1
MONOIN
TEST2
EXTIR
EXTIL
15 kΩ
L6
C8
C13
R9
SCIR2
15 kΩ
330 nF
470 nF
V
SSD3
L7
C9
C12
330 nF
R8
SCIL1
SCIR1
15 kΩ
L8
470 nF
C10
470 nF
C11
R7
(25) 33
15 kΩ
330 nF
MHB602
L1 to L9 are ferrite beads.
The pin numbers given in parenthesis refer to the TDA9875AH version.
Fig.11 Schematic for application.
90
1999 Dec 20
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
13 PACKAGE OUTLINES
SDIP64: plastic shrink dual in-line package; 64 leads (750 mil)
SOT274-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w
M
Z
b
1
M
H
b
64
33
pin 1 index
E
1
32
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
58.67
57.70
17.2
16.9
3.2
2.8
19.61
19.05
20.96
19.71
mm
0.51
4.57
5.84
1.778
19.05
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
99-12-27
SOT274-1
MS-021
1999 Dec 20
91
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
y
X
A
48
33
32
49
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
L
p
b
pin 1 index
L
17
64
detail X
16
1
w M
v
M
A
b
p
Z
e
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.75
0.10 2.55
0.45 0.23 14.1 14.1
0.30 0.13 13.9 13.9
17.45 17.45
16.95 16.95
1.03
0.73
1.2
0.8
1.2
0.8
mm
3.00
0.25
0.8
1.60
0.16 0.16 0.10
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-08-04
99-12-27
SOT393-1
MS-022
1999 Dec 20
92
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
14 SOLDERING
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
14.1 Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
14.3.2 WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
14.2 Through-hole mount packages
14.2.1 SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
14.2.2 MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
300 and 400 °C, contact may be up to 5 seconds.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
14.3 Surface mount packages
14.3.1 REFLOW SOLDERING
14.3.3 MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Dec 20
93
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
14.4 Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
WAVE
REFLOW(1) DIPPING
suitable(2)
MOUNTING
PACKAGE
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
−
suitable
Surface mount
BGA, SQFP
not suitable
not suitable(3)
suitable
suitable
−
−
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP,
SMS
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
−
−
−
not recommended(4)(5) suitable
not recommended(6)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Dec 20
94
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
15 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
16 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Dec 20
95
Philips Semiconductors – a worldwide company
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Brazil: see South America
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Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/02/pp96
Date of release: 1999 Dec 20
Document order number: 9397 750 06065
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