TDA9898HN [NXP]
Multistandard hybrid IF processing; 多标准混合型中频处理
| 型号： | TDA9898HN |
| 厂家： | 
NXP |
| 描述： | Multistandard hybrid IF processing |
| 文件： | 总103页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA9897; TDA9898
Multistandard hybrid IF processing
Rev. 03 — 11 January 2008
Product data sheet
1. General description
The Integrated Circuit (IC) is suitable for Intermediate Frequency (IF) processing including
global multistandard Analog TV (ATV), Digital Video Broadcast (DVB) and mono FM radio
using only 1 IC and 1 to 3 fixed Surface Acoustic Waves (SAWs) (application dependent).
TDA9898 including L and L-accent standard. TDA9897 without L and L-accent standard.
2. Features
2.1 General
I 5 V supply voltage
I I2C-bus control over all functions
I Four I2C-bus addresses provided; selection by programmable Module Address (MAD)
I Three I2C-bus voltage level supported; selection via pin BVS
I Separate gain controlled amplifiers with input selector and conversion for incoming IF
[analog Vision IF (VIF) or Sound IF (SIF) or Digital TV (DTV)] allows the use of
different filter shapes and bandwidths
I All conventional ATV standards applicable by using DTV bandwidth window
[Band-Pass (BP)] filter
I Easy to use default settings for almost every standard provided, selectable via I2C-bus
I Two 4 MHz reference frequency stages; the first one operates as crystal oscillator, the
second one as external signal input
I Stabilizer circuit for ripple rejection and to achieve constant output signals
I Smallest size, simplest application
I ElectroStatic Discharge (ESD) protection for all pins
2.2 Analog TV processing
I Gain controlled wide-band VIF amplifier; AC-coupled
I Multistandard true synchronous demodulation with active carrier regeneration: very
linear demodulation, good intermodulation figures, reduced harmonics and excellent
pulse response
I Internal Nyquist slope processing; switch-off able for alternative use of inexpensive
Nyquist slope SAW filter with additive video noise improvement
I Gated phase detector for L and L-accent standards
I Fully integrated VIF Voltage-Controlled Oscillator (VCO), alignment-free, frequencies
switchable for all negative and positive modulated standards via I2C-bus
I VIF Automatic Gain Control (AGC) detector for gain control; operating as a peak sync
detector for negative modulated signals and as a peak white detector for positive
modulated signals
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
I Optimized AGC modes for negative modulation; e.g. very fast reaction time for VIF and
SIF
I Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit
Digital-to-Analog Converter (DAC); AFC bits can be read-out via I2C-bus
I High precise Tuner AGC (TAGC) TakeOver Point (TOP) for negative modulated
standards; TOP adjust via I2C-bus
I TAGC TOP for positive standards and Received Signal Strength Indication (RSSI);
adjustable via I2C-bus or alternatively by potentiometer
I Fully integrated Sound Carrier (SC) trap for any ATV standard (SC at 4.5 MHz,
5.5 MHz, 6.0 MHz and 6.5 MHz)
I SIF AGC for gain controlled SIF amplifier and high-performance single-reference
Quasi Split Sound (QSS) mixer
I Fully integrated sound BP filter supporting any ATV standard
I Optional use of external FM sound BP filter
I AM sound demodulation for L and L-accent standard
I Alignment-free selective FM Phase-Locked Loop (PLL) demodulator with high linearity
and low noise; external FM input
I VIF AGC voltage monitor output or port function
I VIF AFC current or tuner, SIF or FM AGC voltage monitor output
I 2nd SIF output, gain controlled by internal SIF AGC or by internal FM carrier AGC for
Digital Signal Processor (DSP)
I Fully integrated BP filter for 2nd SIF at 4.5 MHz, 5.5 MHz, 6.0 MHz or 6.5 MHz
2.3 Digital TV processing
I Applicable for terrestrial and cable TV reception
I 70 dB variable gain wide-band IF amplifier (AC-coupled)
I Gain control via external control voltage (0 V to 3 V)
I 2 V (p-p) differential low IF (downconverted) output or 1 V (p-p) 1st IF output for direct
Analog-to-Digital Converter (ADC) interfacing
I DVB downconversion with integrated selectivity for Low IF (LIF)/Zero IF (ZIF)
I Integrated anti-aliasing tracking low-pass filter
I Fully integrated synthesizer controlled oscillator with excellent phase noise
performance
I Synthesizer frequencies for a wide range of world wide DVB standards (for IF center
frequencies of 34.5 MHz, 36 MHz, 44 MHz and 57 MHz)
I All DVB bandwidth ranges supported (including ZIF I/Q)
I TAGC detector for independent tuner gain control loop applications
I TAGC operating as peak detector, fast reaction time due to additional speed-up
detector
I Port function
I TAGC voltage monitor output
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
2 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
2.4 Dual mode
I Fully performed DTV processing and additional ATV video signal processing in
parallel, but with reduced performance, for very fast channel scan
I VIF AGC voltage monitor output or port function
I VIF AFC current monitor output or TAGC voltage output
2.5 FM radio mode
I Gain controlled wide-band Radio IF (RIF) amplifier; AC-coupled
I Buffered RIF amplifier wide-band output, gain controlled by internal RIF AGC
I Fully integrated BP filter for 2nd RIF at 4.5 MHz, 5.5 MHz, 6.0 MHz, 6.5 MHz or
10.7 MHz
I 2nd RIF output, gain controlled by internal RIF AGC or by internal FM carrier AGC for
DSP
I Alignment-free selective FM PLL demodulator with high linearity and low noise
I Precise fully digital AFC detector with 4-bit DAC; AFC bits read-out via I2C-bus
I Port function
I Radio AFC current or tuner, RIF or FM AGC voltage monitor output
3. Applications
I Analog and digital TV front-end applications for TV sets, recording applications and
personal computer cards
4. Quick reference data
Table 1.
Quick reference data
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
4.5
-
Typ
5.0
-
Max
5.5
Unit
V
[1]
VP
IP
supply voltage
supply current
190
mA
Analog TV signal processing
Video part
Vi(IF)(RMS)
RMS IF input voltage
lower limit at −1 dB video
-
60
100
µV
output signal
GVIF(cr)
fVIF
control range VIF gain
VIF frequency
60
-
66
-
-
-
dB
see Table 25
MHz
∆fVIF(dah)
digital acquisition help VIF
frequency window
related to fVIF
all standards except M/N
M/N standard
-
-
±2.3
±1.8
-
-
MHz
MHz
Vo(video)(p-p) peak-to-peak video output voltage see Figure 10
[2]
[3]
positive or negative
modulation; normal mode
and sound carrier on
1.7
-
2.0
1.1
2.3
-
V
V
trap bypass mode and
sound carrier off
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
3 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 1.
Quick reference data …continued
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2][4]
[2][4]
Gdif
differential gain
“ITU-T J.63 line 330”
B/G standard
L standard
-
-
-
-
5
7
%
%
ϕdif
differential phase
“ITU-T J.63 line 330”
B/G standard
L standard
-
2
2
8
4
4
-
deg
deg
MHz
-
[3]
[3]
Bvideo(−3dB) −3 dB video bandwidth
trap bypass mode and
sound carrier off; AC load:
CL < 20 pF, RL > 1 kΩ
6
αSC1
first sound carrier attenuation
M/N standard;
f = fSC1 = 4.5 MHz;
see Figure 21
38
35
53
-
-
-
-
dB
dB
dB
[3]
B/G standard;
f = fSC1 = 5.5 MHz;
see Figure 23
-
[2][5]
(S/N)w
weighted signal-to-noise ratio
normal mode and sound
carrier on; B/G standard;
50 % grey video signal;
unified weighting filter
(“ITU-T J.61”);
57
see Figure 20
[2]
[6]
PSRRCVBS power supply ripple rejection on
pin CVBS
normal mode and sound
carrier on; fripple = 70 Hz;
video signal; grey level;
positive and negative
14
20
-
dB
modulation; see Figure 11
∆IAFC/∆fVIF change of AFC current with VIF
AFC TV mode
0.85
430
1.05
540
1.25
650
µA/kHz
frequency
Audio part
Vo(AF)(RMS) RMS AF output voltage
FM: QSS mode;
mV
27 kHz FM deviation;
50 µs de-emphasis
AM: 54 % modulation
400
-
500
600
mV
%
THD
total harmonic distortion
AF cut-off frequency
FM: 50 µs de-emphasis;
FM deviation: for TV mode
27 kHz and for radio mode
22.5 kHz
0.15
0.50
AM: 54 % modulation;
BP on; see Figure 33
-
0.5
1.0
-
%
f−3dB(AF)
W3[2] = 0; W3[4] = 0;
without de-emphasis;
FM window
80
100
kHz
width = 237.5 kHz
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
4 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 1.
Quick reference data …continued
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(S/N)w(AF)
AF weighted signal-to-noise ratio
“ITU-R BS.468-4”
FM: 27 kHz FM deviation;
50 µs de-emphasis; vision
carrier unmodulated;
FM PLL only
48
56
-
dB
AM: BP off
44
14
90
50
-
dB
dB
mV
PSRR
power supply ripple rejection
RMS output voltage
f
ripple = 70 Hz; see Figure 11
20
-
Vo(RMS)
IF intercarrier single-ended
to GND; SC1 on; SC2 off
140
180
IF intercarrier single-ended
to GND; L standard;
without modulation; BP on;
W7[5] = 0
45
70
90
mV
FM sound part
Vi(FM)(RMS)
RMS FM input voltage
gain controlled operation;
W1[1:0] = 10 or
2
-
300
mV
W1[1:0] = 11 or
W1[1:0] = 01; see Figure 15
[6]
∆IAFC/∆fRIF change of AFC current with RIF
AFC radio mode
0.85
35
1.05
46
1.25
-
µA/kHz
frequency
αAM
AM suppression
referenced to 27 kHz
FM deviation;
dB
50 µs de-emphasis;
AM: f = 1 kHz; m = 54 %
Digital TV signal processing
Digital direct IF
[7]
[8]
Vo(dif)(p-p)
peak-to-peak differential output
voltage
between pin OUT2A and
pin OUT2B
W4[7] = 0
W4[7] = 1
-
-
-
1.0
0.50
83
1.1
0.55
-
V
V
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
dB
[8]
[8]
GIF(cr)
PSRR
control range IF gain
60
66
-
dB
power supply ripple rejection
residual spurious at nominal
differential output voltage
dependent on power supply
ripple
fripple = 70 Hz
fripple = 20 kHz
-
-
60
60
-
-
dB
dB
Digital low IF
Vo(dif)(p-p)
[7]
[8]
[8]
peak-to-peak differential output
voltage
between pin OUT1A and
pin OUT1B; W4[7] = 0
-
-
2
-
-
V
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
89
dB
GIF(cr)
fsynth
control range IF gain
synthesizer frequency
60
-
66
-
-
-
dB
see Table 35 and Table 36
MHz
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
5 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 1.
Quick reference data …continued
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ϕn(synth)
synthesizer phase noise
with 4 MHz crystal oscillator
reference; fsynth = 31 MHz;
fIF = 36 MHz
[8]
[8]
[8]
[8]
at 1 kHz
89
89
98
115
-
99
99
102
119
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dB
at 10 kHz
at 100 kHz
at 1.4 MHz
-
-
-
αripple(pb)LIF low IF pass-band ripple
6 MHz bandwidth
2.7
2.7
2.7
-
7 MHz bandwidth
-
-
dB
8 MHz bandwidth
-
-
dB
αstpb
αimage
C/N
stop-band attenuation
image rejection
8 MHz band; f = 15.75 MHz
−10 MHz to 0 MHz; BP on
at fo = 4.9 MHz;
30
30
112
40
34
118
dB
-
dB
[8][9][10]
carrier-to-noise ratio
-
dBc/Hz
Vi(IF) = 10 mV (RMS);
see Figure 37
Digital zero IF
Vo(dif)(p-p)
[7]
peak-to-peak differential output
voltage
between pin OUT1A and
pin OUT1B or between
pin OUT2A and pin OUT2B;
W4[7] = 0
-
-
2
-
-
V
[8]
[8]
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
89
dB
GIF(cr)
fsynth
control range IF gain
synthesizer frequency
synthesizer phase noise
60
-
66
-
-
-
dB
see Table 35 and Table 36
MHz
ϕn(synth)
with 4 MHz crystal oscillator
reference; fsynth = 31 MHz;
fIF = 36 MHz
[8]
[8]
[8]
[8]
at 1 kHz
89
99
-
-
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
at 10 kHz
at 100 kHz
at 1.4 MHz
89
99
98
102
119
115
Reference frequency input from external source
[11]
fref
reference frequency
W7[7] = 0
-
4
-
MHz
mV
Vref(RMS)
RMS reference voltage
W7[7] = 0; see Figure 34
and Figure 46
15
150
500
[1] Values of video and sound parameters can be decreased at VP = 4.5 V.
[2] AC load; CL < 20 pF and RL > 1 kΩ. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound
carrier traps.
[3] The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 24. In this way the full composite video
spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p).
[4] Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps.
[5] Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter (“ITU-T J.64”).
[6] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The
AFC steepness can be changed by resistors R1 and R2.
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
6 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
[7] With single-ended load for fIF < 45 MHz RL ≥ 1 kΩ and CL ≤ 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 kΩ and CL ≤ 3 pF to
ground.
[8] This parameter is not tested during production and is only given as application information.
[9] Noise level is measured without input signal but AGC adjusted corresponding to the given input level.
[10] Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off.
[11] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum
FM deviation, sound trap frequency, LIF band-pass cut-off frequency and ZIF low-pass cut-off frequency as well as the accuracy of the
synthesizer.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA9897HL/V2/S1 LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
SOT619-1
TDA9897HN/V2
HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 × 7 × 0.85 mm
TDA9898HL/V2/S1 LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
SOT619-1
TDA9898HN/V2
HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 × 7 × 0.85 mm
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
7 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
6. Block diagram
SDA
SCL
i.c.
ADRSEL BVS
GNDD
22
LFSYN2
1
23
24
14
25
32
2
SYNTHESIZER
AND VCO
I C-BUS
A
B
TDA9898
AM average
FM peak
36
SIF AGC
AGCDIN
sideband
3
4
IF3A
IF3B
C
D
Q
I
SIDEBAND
FILTER
6
7
IF1A
IF1B
VIF AGC
sideband (L-accent)
2 ×
I
9
NYQUIST
FILTER
IF2A
E
F
Q
10
IF2B
CIFAGC
5
SOUND
CARRIER
TRAP
GROUP
DELAY
EQUALIZER
2
VIF
AFC
I C-BUS
TOPNEG
45
DECODER
i.c.
VIF PLL
AND
ACQUISITION
HELP
trap reference
PEAK
AGC
TUNER
RSSI
DETECTOR
AND
standard
SYNTHESIZER
AND VCO
L STANDARD
TUNER
G
H
2
I C-BUS TOP2
AND RSSI
47
TAGC
AGC
48
2, 18, 37
8
11
TOP2
optional tuner
13
38
GND
CTAGC
LFVIF
LFSYN1
n.c.
AGC TOP for
positive
008aaa090
modulation and
radio signal
strength detector
onset
Fig 1. Block diagram of TDA9898 (continued in Figure 2)
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
8 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
(2)
R
4 MHz reference
input
(2)
R
EXTERNAL SOUND
(1)
BAND-PASS FILTER
V
GNDA
40, 41
EXTFILO
15
EXTFILI
FREF
46
OPTXTAL
39
P
43, 44
17
4 MHz FREQUENCY
REFERENCE
SUPPLY
+3 dB
A
B
29
30
OUT2A
OUT2B
TDA9898
BP on/off
OUTPUT
SWITCH
C
D
26
27
BAND-PASS
FILTER
OUT1A
OUT1B
21
EXTFMI
34 CAF2
20 CDEEM
FM SWITCH
E
F
31
FM
AMPLIFIER
AUD
28 CAF1
FM CARRIER AGC
AM
AM DEMODULATOR
AND
FM NARROW-BAND PLL
FM
AM
16
MPP2
TAGC
SIF AGC
FM AGC
AFC
33
12
CVBS
MPP1
G
H
VIF AGC
port
2
I C-bus
35, 42
n.c.
19
LFFM
008aaa055
(1) Optional.
(2) Connect resistor if input or crystal is not used.
Fig 2. Block diagram of TDA9898 (continued from Figure 1)
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
9 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
SDA
SCL
i.c.
ADRSEL BVS
GNDD
22
LFSYN2
1
23
24
14
25
32
2
SYNTHESIZER
AND VCO
I C-BUS
A
TDA9897
36
FM peak
SIF AGC
AGCDIN
sideband
3
4
IF3A
IF3B
B
C
Q
I
SIDEBAND
FILTER
6
7
IF1A
IF1B
VIF AGC
sideband
2 ×
I
9
NYQUIST
FILTER
IF2A
IF2B
D
E
Q
10
SOUND
CARRIER
TRAP
GROUP
DELAY
EQUALIZER
2
VIF
AFC
I C-BUS
TOPNEG
DECODER
VIF PLL
AND
45
i.c.
ACQUISITION
HELP
trap reference
PEAK
AGC
TUNER
RSSI
DETECTOR
AND
standard
SYNTHESIZER
AND VCO
IF BASED
TUNER
AGC
F
2
I C-BUS TOP2
AND RSSI
47
G
TAGC
48
GND
2, 5, 18, 37
8
11
TOP2
optional tuner
13
LFVIF
38
LFSYN1
CTAGC
n.c.
AGC TOP for
IF based tuner
AGC and
008aaa091
radio signal
strength detector
onset
Fig 3. Block diagram of TDA9897 (continued in Figure 4)
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
10 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
(2)
R
4 MHz reference
input
(2)
R
EXTERNAL SOUND
(1)
BAND-PASS FILTER
V
GNDA
40, 41
EXTFILO
15
EXTFILI
FREF
46
OPTXTAL
39
P
43, 44
17
4 MHz FREQUENCY
REFERENCE
SUPPLY
+3 dB
A
29
30
OUT2A
OUT2B
TDA9897
BP on/off
OUTPUT
SWITCH
B
C
26
27
BAND-PASS
FILTER
OUT1A
OUT1B
21
EXTFMI
34 CAF2
20 CDEEM
FM SWITCH
D
E
31
FM
AMPLIFIER
AUD
28 CAF1
FM CARRIER AGC
DEMODULATOR
AND
FM
16
MPP2
TAGC
SIF AGC
FM AGC
AFC
FM NARROW-BAND PLL
33
12
CVBS
MPP1
F
VIF AGC
G
port
2
I C-bus
35, 42
n.c.
19
LFFM
008aaa056
(1) Optional.
(2) Connect resistor if input or crystal is not used.
Fig 4. Block diagram of TDA9897 (continued from Figure 3)
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
11 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
7. Pinning information
7.1 Pinning
1
2
36
35
34
33
32
31
30
29
28
27
26
25
LFSYN2
n.c.
AGCDIN
n.c.
3
IF3A
CAF2
4
IF3B
(1)
CVBS
BVS
5
CIFAGC
6
IF1A
IF1B
AUD
TDA9897HL
TDA9898HL
7
OUT2B
OUT2A
CAF1
8
CTAGC
IF2A
9
10
11
12
IF2B
OUT1B
OUT1A
ADRSEL
TOP2
MPP1
008aaa040
(1) Not connected for TDA9897HL.
Fig 5. Pin configuration for LQFP48
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
12 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
terminal 1
index area
1
2
36
35
34
33
32
31
30
29
28
27
26
25
LFSYN2
n.c.
AGCDIN
n.c.
3
IF3A
CAF2
4
IF3B
CVBS
BVS
(1)
5
CIFAGC
6
IF1A
IF1B
AUD
TDA9897HN
TDA9898HN
7
OUT2B
OUT2A
CAF1
8
CTAGC
IF2A
9
10
11
12
IF2B
OUT1B
OUT1A
ADRSEL
TOP2
MPP1
008aaa041
Transparent top view
(1) Not connected for TDA9897HN.
Fig 6. Pin configuration for HVQFN48
7.2 Pin description
Table 3.
Pin description
Pin Description
Symbol
LFSYN2
n.c.
1
2
3
4
5
loop filter synthesizer 2 (conversion synthesizer)
not connected
IF3A
IF symmetrical input 3 for sound
IF3B
CIFAGC
TDA9898: IF AGC capacitor; L standard
TDA9897: not connected
IF1A
6
IF symmetrical input 1 for vision or digital
IF1B
7
CTAGC
IF2A
8
TAGC capacitor
9
IF symmetrical input 2 for vision or digital
IF2B
10
11
12
13
14
15
TOP2
MPP1
LFVIF
i.c.
TOP potentiometer for positive modulated standards and RSSI reference
multipurpose pin 1: VIF AGC monitor output or port function
loop filter VIF PLL
internally connected; connect to ground
output to external filter
EXTFILO
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Multistandard hybrid IF processing
Table 3.
Pin description …continued
Symbol
Pin Description
MPP2
16
multipurpose pin 2: SIF AGC or FM AGC or TAGC or VIF AFC or FM AFC
monitor output
EXTFILI
n.c.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
input from external filter
not connected
LFFM
CDEEM
EXTFMI
GNDD
SDA
loop filter FM PLL
de-emphasis capacitor
external FM input
digital ground
I2C-bus data input and output
I2C-bus clock input
SCL
ADRSEL
OUT1A
OUT1B
CAF1
address select
zero IF I or low IF or 2nd sound intercarrier symmetrical output
Direct Current (DC) decoupling capacitor 1
OUT2A
OUT2B
AUD
zero IF Q or 1st Digital IF (DIF) symmetrical output
audio signal output
I2C-bus voltage select
BVS
CVBS
CAF2
composite video signal output
DC decoupling capacitor 2
not connected
n.c.
AGCDIN
n.c.
AGC input for DIF amplifier for e.g. input from channel decoder AGC
not connected
LFSYN1
loop filter synthesizer 1 (filter control synthesizer)
optional quartz input
OPTXTAL 39
GNDA
GNDA
n.c.
40
41
42
43
44
45
46
47
48
analog ground
analog ground
not connected
VP
supply voltage
VP
supply voltage
i.c.
internally connected; connect to ground
4 MHz reference input
TAGC output
FREF
TAGC
GND
ground; plateau connection
8. Functional description
8.1 IF input switch
Different signal bandwidth can be handled by using two signal processing chains with
individual gain control.
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Multistandard hybrid IF processing
Switch configuration allows independent selection of filter for analog VIF and for analog
SIF (used at same time) or DIF.
The switch takes into account correct signal selection for TAGC in the event of VIF and
DIF signal processing.
8.2 VIF demodulator
ATV demodulation using 6 MHz DVB window (band-pass) filter (for 6 MHz, 7 MHz or
8 MHz channel width).
IF frequencies adapted to enable the use of different filter configurations. The Nyquist
processing is integrated.
For optional use of standard Nyquist filter the integrated Nyquist processing can be
switched off.
Sideband switch supplies selection of lower or upper sideband (e.g. for L-accent).
Equalizer provides optimum pulse response at different standards [e.g. to cope with
higher demands for Liquid Crystal Display (LCD) TV].
Integrated sound traps.
Sound trap reference independent from received 2nd sound IF (reference taken from
integrated reference synthesizer).
IF level selection provides an optimum adaptation of the demodulator to high linearity or
low noise.
8.3 VIF AGC and tuner AGC
8.3.1 Mode selection of VIF AGC
Peak white AGC for positive modulation mode with adaptation for speed up and black level
AGC (using proven system from TDA9886).
For negative modulation mode equal response times for increasing or decreasing input
level (optimum for amplitude fading) or normal peak AGC or ultra fast peak AGC.
8.3.2 VIF AGC monitor
VIF AGC DC voltage monitor output (with expanded internal characteristic).
VIF AGC read out via I2C-bus (for IF level indication) with zero-calibration via TOP setting
(TOP setting either via I2C-bus or via TOP potentiometer).
8.3.3 Tuner AGC
Independent integral tuner gain control loop (not nested with VIF AGC). Integral
characteristic provides high control accuracy.
Accurate setting of tuner control onset (TOP) for integral tuner gain control loop via
I2C-bus.
For L standard, TAGC remains VIF AGC nested, as from field experience in the past this
narrow-band TAGC gives best performance.
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Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Thus two switchable TAGC systems for negative/DIF and positive modulation
implemented.
L standard TAGC output changed from current output to voltage output, as it is not
necessary to adapt for other than 5 V tuner.
L standard tuner time constant switching integrated (= speed up function in the event of
step into high input levels), to minimize external application.
For high TOP accuracy at L standard, additional adjustment via optional potentiometer or
I2C-bus is provided.
Tuner AGC status bit provided. This function enables TOP alignment without need for
TAGC voltage measurement (e.g. for TOP alignment in a complete set, where access to
internal signals is not possible).
8.4 DIF/SIF FM and AM sound AGC
External AGC control input for DIF. DIF includes 1st IF, zero IF and low IF.
Integrated gain control loop for SIF.
Bandwidth of AGC control for FM SIF related to used SAW bandwidth.
Peak AGC control in the event of FM SIF.
Ultra fast SIF AGC time constant when VIF AGC set to ultra fast mode.
Slow average AGC control in the event of AM sound.
AM sound AGC related to AM sound carrier level.
Fast AM sound AGC in the event of fast VIF AGC (speed up).
SIF AGC DC voltage monitor output with expanded internal characteristic.
8.5 Frequency phase-locked loop for VIF
Basic function as previous TDA9887 design.
PLL gating mode for positive and negative modulation, optional.
PLL optimized for either overmodulation or strong multipath.
8.6 DIF/SIF converter stage
Frequency conversion with sideband suppression.
Selection mode of upper or lower sideband for pass or suppression.
Suppression around zero for frequency conversion.
I/Q output mode for zero IF conversion.
Conversion mode selection via synthesizer for DIF and radio mode or via VIF Frequency
Phase-Locked Loop (FPLL) for TV QSS sound (FM/AM).
TDA9897_TDA9898_3
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NXP Semiconductors
Multistandard hybrid IF processing
External BP filter (e.g. for 4.5 MHz) for additional filtering, optional.
Bypass mode selection for use of external filter.
Integrated SIF BP tracking filter for chroma suppression.
Integrated tracking filters for LIF and ZIF.
Symmetrical output stages for DIF, ZIF and 2nd SIF.
Second narrow-band gain control loop for 2nd SIF via FM PLL.
8.7 Mono sound demodulator
8.7.1 Narrow-band FM PLL demodulation
Additional external input for either TV or radio intercarrier signal.
FM carrier selection independent from VIF trap, because VIF trap uses reference via
synthesizer.
FM wide and ultra wide mode with adapted loop bandwidth and different selectable
FM acquisition window widths to cope with FM overmodulation conditions.
8.7.2 AM sound demodulation
Passive AM sound detector.
L and L-accent standard without SAW switching (done by sideband selection of SIF
converter).
8.8 Audio amplifier
Different gain settings for FM sound to adapt to different FM deviation.
Switchable de-emphasis for FM sound.
Automatic mute function when FM PLL is unlocked.
Forced mute function.
Output amplifier for AM sound.
8.9 Synthesizer
In DIF mode, the synthesizer supports low and zero IF input frequencies for 34.5 MHz,
36 MHz, 44 MHz and 57 MHz center frequencies.
In radio mode, the synthesizer supports 2nd sound intercarrier conversion. A large set of
synthesizer frequencies in steps of 0.5 MHz enables flexible combination of filter and 2nd
IF frequencies.
Synthesizer loop internally adapted to divider ratio range for optimum phase noise
requirement (loop bandwidth).
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Multistandard hybrid IF processing
Synthesizer reference either via 4 MHz crystal or via an external source. Individual pins
for crystal and external reference allows optimum interface definition and supports use of
custom reference frequency offset.
8.10 I2C-bus transceiver and slave address
Four different I2C-bus device addresses to enable application with multi-IC use.
I2C-bus transceiver input ports can handle three different I2C-bus voltages.
Read-out functions as TDA9887 plus additional read out of VIF AGC and TAGC status.
Table 4.
Slave address detection
Slave address
Selectable address bit
Pin ADRSEL
A3
0
A0
1
MAD1
MAD2
MAD3
MAD4
GND
0
0
VP
1
1
resistor to GND
resistor to VP
1
0
9. I2C-bus control
Table 5.
Slave addresses[1]
Slave address
Bit
A6
1
Name
MAD1
MAD2
MAD3
MAD4
Value
A5
0
A4
0
A3
0
A2
0
A1
1
A0
1
43h
42h
4Bh
4Ah
1
0
0
0
0
1
0
1
0
0
1
0
1
1
1
0
0
1
0
1
0
[1] For MAD activation via pin ADRSEL: see Table 4.
TDA9897_TDA9898_3
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Product data sheet
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18 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
9.1 Read format
S
BYTE 1
A6 to A0
slave address
A
BYTE 2
D7 to D0
data (R1)
A
BYTE 3
D7 to D0
data (R2)
NA
P
R/W
1
from master to slave
from slave to master
S = START condition
A = acknowledge
NA = not acknowledge
P = STOP condition
001aad167
Fig 7. I2C-bus read format (slave transmits data)
Table 6.
7
R1 - data read register 1 bit allocation
6
5
4
3
2
1
0
AFCWIN
reserved CARRDET
AFC4
AFC3
AFC2
AFC1
PONR
Table 7.
R1 - data read register 1 bit description
Bit
Symbol
Description
7
AFCWIN
AFC window[1]
1 = VCO in ±1.6 MHz AFC window[2]
1 = VCO in ±0.8 MHz AFC window[3]
0 = VCO out of ±1.6 MHz AFC window[2]
0 = VCO out of ±0.8 MHz AFC window[3]
6
5
-
reserved
FM carrier detection[4]
CARRDET
1 = detection (FM PLL is locked and level is less than 6 dB below
gain controlled range of FM AGC)
0 = no detection
4 to 1
0
AFC[4:1]
PONR
automatic frequency control; see Table 8
power-on reset
1 = after power-on reset or after supply breakdown
0 = after a successful reading of the status register
[1] If no IF input is applied, then bit AFCWIN can be logic 1 due to the fact that the VCO is forced to the AFC
window border for fast lock-in behavior.
[2] All standards except M/N standard.
[3] M/N standard.
[4] Typical time constant of FM carrier detection is 50 ms. The minimal recommended wait time for read out is
80 ms.
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 8.
Automatic frequency control bits[1]
Bit
f[2]
AFC4
AFC3
AFC2
AFC1
R1[1]
R1[4]
R1[3]
R1[2]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
≤ (fnom − 187.5 kHz)
fnom − 162.5 kHz
fnom − 137.5 kHz
fnom − 112.5 kHz
fnom − 87.5 kHz
fnom − 62.5 kHz
fnom − 37.5 kHz
fnom − 12.5 kHz
fnom + 12.5 kHz
fnom + 37.5 kHz
fnom + 62.5 kHz
fnom + 87.5 kHz
fnom + 112.5 kHz
fnom + 137.5 kHz
fnom + 162.5 kHz
≥ (fnom + 187.5 kHz)
[1] fnom is the nominal frequency.
[2] In ATV mode f means vision intermediate frequency; in radio mode f means radio intermediate frequency.
Table 9.
7
R2 - data read register 2 bit allocation
6
5
4
3
2
1
0
reserved
TAGC
VAGC5
VAGC4
VAGC3
VAGC2
VAGC1
VAGC0
Table 10. R2 - data read register 2 bit description
Bit
7
Symbol
-
Description
reserved
6
TAGC
tuner AGC
1 = active
0 = inactive
5 to 0
VAGC[5:0]
AGC level detector; VIF AGC in ATV mode, SIF AGC in radio mode
and DIF AGC in DTV mode; see Table 11
TDA9897_TDA9898_3
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 11. AGC bits (for corresponding AGC characteristic see Figure 12)
Bit
Typical
∆VAGC(VIF)
(V)
VAGC5
VAGC4
VAGC3
VAGC2
VAGC1
VAGC0
R2[5]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
R2[4]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
R2[3]
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
R2[2]
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
R2[1]
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
R2[0]
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (TOP)[1]
−0.04
−0.08
−0.12
−0.16
−0.20
−0.24
−0.28
−0.32
−0.36
−0.40
−0.44
−0.48
−0.52
−0.56
−0.60
−0.64
−0.68
−0.72
−0.76
−0.80
−0.84
−0.88
−0.92
−0.96
−1.00
−1.04
−1.08
−1.12
−1.16
−1.20
−1.24
−1.28
−1.32
−1.36
−1.40
−1.44
−1.48
−1.52
TDA9897_TDA9898_3
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Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 11. AGC bits (for corresponding AGC characteristic see Figure 12) …continued
Bit
Typical
∆VAGC(VIF)
(V)
VAGC5
VAGC4
VAGC3
VAGC2
VAGC1
VAGC0
R2[5]
0
R2[4]
1
R2[3]
1
R2[2]
0
R2[1]
0
R2[0]
0
−1.56
−1.60
−1.64
−1.68
−1.72
−1.76
−1.80
−1.84
−1.88
−1.92
−1.96
−2.00
−2.04
−2.08
−2.12
−2.16
−2.20
−2.24
−2.28
−2.32
−2.36
−2.40
−2.44
−2.48
−2.52
0
1
0
1
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
[1] The reference of 0 (TOP) can be adjusted via TOPPOS[4:0] (register W10; see Table 49 and Table 47) or
via potentiometer at pin TOP2.
9.2 Write format
S
BYTE 1
A6 to A0
slave address
A
BYTE 2
A7 to A0
A
BYTE 3
bits 7 to 0
data 1
A
BYTE n
bits 7 to 0
data n
A
P
R/W
0
subaddress
from master to slave
from slave to master
S = START condition
A = acknowledge
P = STOP condition
001aad166
Fig 8. I2C-bus write format (slave receives data)
TDA9897_TDA9898_3
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Product data sheet
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22 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
9.2.1 Subaddress
Table 12. W0 - subaddress register bit allocation
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Table 13. W0 - subaddress register bit description
Bit
Symbol
A[7:4]
Description
7 to 4
3 to 0
has to be set to logic 0
subaddress; see Table 14
A[3:0]
Table 14. Subaddress control bits
Bit
Mode
A3
0
A2
0
A1
0
A0
0
subaddress for register W1
subaddress for register W2
subaddress for register W3
subaddress for register W4
subaddress for register W5
subaddress for register W6
subaddress for register W7
subaddress for register W8
subaddress for register W9
subaddress for register W10
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
Table 15. I2C-bus write register overview[1]
Register 7
6
5
4
3
2
1
0
W1[2]
W2[3]
W3[4]
W4[5]
W5[6]
W6[7]
W7[8]
W8[9]
W9[10]
W10[11]
RADIO
STD1
STD4
AMUTE
BP
STD0
STD3
FMUTE
MPP2S1
TV2
STD2
TV1
DUAL
PLL
FM
GATE
EXTFIL
TRAP
MOD
SB
RESCAR
VIFLEVEL
FSFREQ1
TAGC1
0
FMWIDE0
MPP2S0
SFREQ4
AGC1
DEEMT
0
DEEM
IFIN1
AGAIN1
IFIN0
SFREQ1
0
AGAIN0
VIFIN
FSFREQ0 SFREQ5
SFREQ3
FMWIDE1
SFREQ2
TWOFLO
PORT
EASY2
SFREQ0
DIRECT
TAGC0
AGC2
0
0
SIFLEVEL VIDLEVEL OPSTATE
FILOUTBP NYQOFF
EASY1 EASY0
0
0
0
EASY3
DAGCSLOPE TAGCIS
TAGCTC
TOPNEG4 TOPNEG3 TOPNEG2 TOPNEG1 TOPNEG0
0
0
XPOTPOS TOPPOS4 TOPPOS3 TOPPOS2 TOPPOS1 TOPPOS0
[1] The register setting after power-on is not specified.
[2] See Table 17 for detailed description of W1.
[3] See Table 24 for detailed description of W2.
[4] See Table 28 for detailed description of W3.
[5] See Table 30 for detailed description of W4.
[6] See Table 34 for detailed description of W5.
[7] See Table 38 for detailed description of W6.
TDA9897_TDA9898_3
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Product data sheet
Rev. 03 — 11 January 2008
23 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
[8] See Table 41 for detailed description of W7.
[9] See Table 43 for detailed description of W8.
[10] See Table 46 for detailed description of W9.
[11] See Table 49 for detailed description of W10.
9.2.2 Description of data bytes
Table 16. W1 - data write register bit allocation
7
6
5
4
3
2
1
0
RADIO
STD1
STD0
TV2
TV1
DUAL
FM
EXTFIL
Table 17. W1 - data write register bit description
Bit
Symbol
Description
FM mode
7
RADIO
1 = radio
0 = ATV/DTV
6 and 5
4 and 3
STD[1:0]
TV[2:1]
2nd sound IF; see Table 18 and Table 19
TV mode
00 = DTV and ZIF
01 = DTV and LIF
10 = not defined
11 = ATV and QSS
2
DUAL
ATV and DTV dual mode for channel search; see Table 22
1 = dual (TV2 = 0)
0 = normal
1 and 0
FM and EXTFIL FM and output switching; see Table 21
Table 18. Intercarrier sound BP and FM PLL frequency select for ATV, QSS mode[1]
Bit
fFMPLL
Sound BP
(MHz)
RADIO
MOD
STD1
STD0
FSFREQ1 FSFREQ0 TV1
W1[7]
W2[7]
W1[6]
W1[5]
W5[7]
W5[6]
W1[3]
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
4.5
5.5
6.0
6.5
off
M/N standard
B/G standard
I standard
D/K standard
L/L-accent standard
[1] For description of bit MOD refer to Table 24 and bits FSFREQ[1:0] are described in Table 34.
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Multistandard hybrid IF processing
Table 19. Intercarrier sound BP and FM PLL frequency select for radio, QSS mode[1]
Bit
fFMPLL
(MHz)
Sound BP
RADIO
MOD
STD1
STD0
FSFREQ1 FSFREQ0 TV1
W1[7]
W2[7]
W1[6]
W1[5]
W5[7]
W5[6]
W1[3]
1
1
1
1
1
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
0
0
1
1
X
0
1
0
1
X
0
0
0
0
0
4.5
5.5
6.0
6.5
10.7
M/N standard
B/G standard
I standard
D/K standard
RADIO
[1] For description of bit MOD refer to Table 24 and bits FSFREQ[1:0] are described in Table 34.
Table 20. Second sound IF selection for 10.7 MHz[1]
Bit
fFMPLL (MHz)
BP
MOD
W2[7]
0
RADIO
W1[7]
1
W4[6]
0
10.7
[1] For description of bit MOD refer to Table 24 and for BP refer to Table 30.
Table 21. 2nd intercarrier and sound input and output switching
MOD FM
EXTFIL Mode
Input signal selection Signal at OUT1A and OUT1B Mono sound
(input switch)
(output switch)
demodulation
W2[7] W1[1] W1[0]
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FM sound internal
internal BP via FM AGC
internal BP
internal BP
external BP
external input
external BP
FM sound EXTFILI
FM sound EXTFMI
FM sound EXTFILI
AM sound not used
AM sound -
internal BP
external BP via FM AGC
internal BP
internal BP
external BP
internal BP
internal BP
internal BP
AM sound -
AM sound EXTFILI
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Multistandard hybrid IF processing
BYPASS
output
switch
OUT1A
OUT1B
BAND-PASS
W7.1 = 0
W7.1 = 1
3 dB
FM
switch
external filter output
external filter input
FM PLL
FM AGC
amplifier
external FM input
EXTFILI
EXTFILO EXTFMI
001aad351
Fig 9. Signal path for intercarrier (2nd SIF) processing
Table 22. Dual mode options
Bit
TV2
W1[4]
X
Output mode
TV1
W1[3]
X
DIRECT DUAL
W6[0]
W1[2]
X
1
0
1
all normal mode functions (ATV OR DTV)
0
X
analog CVBS at pin CVBS AND direct 1st DIF at
pins OUT2A and OUT2B
0
0
0
1
0
0
1
1
analog CVBS at pin CVBS AND digital zero IF I/Q at
pins OUT1A, OUT1B and OUT2A, OUT2B
analog CVBS at pin CVBS AND digital low IF at
pins OUT1A and OUT1B
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Multistandard hybrid IF processing
Table 23. W2 - data write register bit allocation
7
6
5
4
3
2
1
0
MOD
STD4
STD3
STD2
SB
PLL
GATE
TRAP
Table 24. W2 - data write register bit description
Bit
Symbol
Description
7
MOD
modulation
1 = negative; FM mono sound at ATV and dual mode
0 = positive; AM mono sound at ATV and dual mode
6 to 4
3
STD[4:2]
SB
vision IF; see Table 25
sideband for sound IF and digital low IF
1 = upper
0 = lower
2
1
PLL
operating modes; see Table 26
PLL gating
1 = on
GATE
0 = off
0
TRAP
sound trap
1 = on
0 = bypass
Table 25. Vision IF
Bit
fVIF (MHz)
Sideband
NYQOFF
MOD
STD4
STD3
STD2
TV1 = 1 (QSS)
W7[0]
X
W2[7]
W2[6]
W2[5]
W2[4]
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
38.0
low
low
low
low
high
high
-
X
38.375
38.875
39.875
32.25
32.625
33.9
X
X
X
0
1
X
33.125
33.625
38.0
high
high
low
low
low
low
low
low
low
low
X
X
X
38.375
38.875
39.875
45.75
58.75
46.25
59.25
X
X
X
X
X
X
TDA9897_TDA9898_3
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Multistandard hybrid IF processing
Table 26. VIF PLL gating and detector mode
Bit
Gating and detector mode
MOD
PLL
W2[7]
W2[2]
0
0
1
0
1
0
0 % gating in positive modulation mode (W2[1] = 1)
36 % gating in positive modulation mode (W2[1] = 1)
π mode on; optimized for overmodulation in negative modulation mode;
fPC = 0 kHz ± 187.5 kHz
1
1
π mode off; optimized for multipath in negative modulation mode;
fPC = 0 kHz ± 187.5 kHz
Table 27. W3 - data write register bit allocation
7
6
5
4
3
2
1
0
RESCAR
AMUTE
FMUTE FMWIDE0 DEEMT
DEEM
AGAIN1
AGAIN0
Table 28. W3 - data write register bit description
Bit
Symbol
Description
7
RESCAR
video gain correction for residual carrier
1 = 20 % residual carrier
0 = 10 % residual carrier
auto mute
6
AMUTE
FMUTE
1 = on
0 = off
5
forced mute
1 = on
0 = off
4
FMWIDE0
DEEMT
DEEM
FM window (W6[3] = 0)
1 = 475 kHz; normal FM phase detector steepness
0 = 237.5 kHz; high FM phase detector steepness
3
de-emphasis time
1 = 50 µs
0 = 75 µs
2
de-emphasis
1 = on
0 = off
1 and 0
AGAIN[1:0]
audio gain
00 = 0 dB
01 = −6 dB
10 = −12 dB (only for FM mode)
11 = −18 dB (only for FM mode)
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Multistandard hybrid IF processing
Table 29. W4 - data write register bit allocation
7
6
5
4
3
2
1
0
VIFLEVEL
BP
MPP2S1
MPP2S0
0
IFIN1
IFIN0
VIFIN
Table 30. W4 - data write register bit description
Bit
Symbol
Description
7
VIFLEVEL
control of internal VIF mixer input level (W1[4] = 1) and
OUT1/OUT2 output level; see Table 31
1 = reduced
0 = normal
6
BP
SIF/DIF BP
1 = on (bit W6[0] = 0; see Table 38)
0 = bypass
5 and 4
3
MPP2S[1:0]
AGC or AFC output; see Table 32
0 = fixed value
-
2 and 1
IFIN[1:0]
DIF/SIF input
00 = IF1A/B input
01 = IF3A/B input
10 = not used
11 = IF2A/B input
VIF input
0
VIFIN
1 = IF1A/B input
0 = IF2A/B input
Table 31. List of output signals at OUT1 and OUT2
Bit
Output signal at
TV2
TV1
DIRECT
FM
EXTFIL
OUT1A, OUT1B
OUT2A, OUT2B
W1[4]
W1[3]
W6[0]
W1[1]
W1[0]
0
0
0
1
1
1
1
0
0
X
X
X
0
0
1
1
X
X
X
0
1
0
1
zero IF I
zero IF Q
1
0
low IF
off
X
X
X
X
X
1
off
direct IF
off
X
X
X
X
intercarrier[1]
intercarrier[2]
intercarrier[2]
intercarrier[1]
off
off
off
[1] Intercarrier output level based on wide-band AGC of SIF amplifier.
[2] Intercarrier output level based on narrow-band AGC of FM amplifier.
TDA9897_TDA9898_3
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 32. Output mode at pin MPP2 for ATV; dual or radio mode
Bit
Pin MPP2 output mode
RADIO
MPP2S1
MPP2S0
W1[7]
W4[5]
W4[4]
X
X
X
0
0
0
1
1
1
0
1
0
1
1
gain control voltage of FM PLL
gain control voltage of SIF amplifier
TAGC monitor voltage
AFC current output, VIF PLL
AFC current output, radio mode
1
Table 33. W5 - data write register bit allocation
7
6
5
4
3
2
1
0
FSFREQ1 FSFREQ0 SFREQ5 SFREQ4 SFREQ3 SFREQ2 SFREQ1 SFREQ0
Table 34. W5 - data write register bit description[1]
Bit
Symbol
Description
7 and 6
FSFREQ[1:0]
DTV filter or sound trap selection for video
ATV; sound trap; TV2 = 1
00 = M/N standard (4.5 MHz)
01 = B/G standard (5.5 MHz)
10 = I standard (6.0 MHz)
11 = D/K and L/L-accent standard (6.5 MHz)
DTV (zero IF); low-pass cut-off frequency; TV2 = 0 and TV1 = 0
00 = 3.0 MHz
01 = 3.5 MHz
10 = 4.0 MHz
11 = not used
DTV (low IF); upper BP cut-off frequency; TV2 = 0 and TV1 = 1
00 = 7.0 MHz
01 = 8.0 MHz
10 = 9.0 MHz
11 = not used
5 to 0
SFREQ[5:0]
synthesizer frequencies; see Table 35 and Table 36
[1] For bit description of TV1 and TV2 see Table 16 W1[3] and W1[4] and Table 17.
TDA9897_TDA9898_3
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Multistandard hybrid IF processing
Table 35. DIF/SIF synthesizer frequencies (using bit TWOFLO = 0)
Bit
fsynth (MHz)
SFREQ5
SFREQ4
SFREQ3
SFREQ2
SFREQ1
SFREQ0
W5[5]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
W5[4]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
W5[3]
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
W5[2]
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
W5[1]
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
W5[0]
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
22.0
22.5
23.0
23.5
24.0
24.5
25.0
25.5
26.0
26.5
27.0
27.5
28.0
28.5
29.0
29.5
30.0
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
36.5
37.0
37.5
38.0
38.5
39.0
39.5
40.0
40.5
41.0
TDA9897_TDA9898_3
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 35. DIF/SIF synthesizer frequencies (using bit TWOFLO = 0) …continued
Bit
fsynth (MHz)
SFREQ5
SFREQ4
SFREQ3
SFREQ2
SFREQ1
SFREQ0
W5[5]
W5[4]
W5[3]
W5[2]
W5[1]
W5[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
41.5
42.0
42.5
43.0
43.5
44.0
44.5
45.0
45.5
46.0
46.5
47.0
47.5
48.0
48.5
49.0
49.5
50.0
50.5
51.0
51.5
52.0
52.5
53.0
53.5
Table 36. DIF/SIF synthesizer frequency for zero IF Japan (using bit TWOFLO = 1)
Bit
fsynth (MHz)
SFREQ5
W5[5]
1
SFREQ4
W5[4]
1
SFREQ3
W5[3]
0
SFREQ2
W5[2]
0
SFREQ1
W5[1]
1
SFREQ0
W5[0]
0
57
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 37. W6 - data write register bit allocation
7
6
5
4
3
2
1
0
TAGC1
TAGC0
AGC2
AGC1
FMWIDE1 TWOFLO
0
DIRECT
Table 38. W6 - data write register bit description
Bit
Symbol
Description
7 and 6
TAGC[1:0]
tuner AGC mode[1]
00 = TAGC integral loop mode; all currents off
01 = TAGC integral loop mode; source current off
10 = TAGC integral loop mode
11 = TAGC derived from IF AGC; recommended for positive
modulated signals
5 and 4
3
AGC[2:1]
AGC mode and behavior; see Table 39
FM window
FMWIDE1
1 = 1 MHz
0 = see Table 28 bit FMWIDE0
synthesizer frequency selection
1 = zero IF Japan mode (57 MHz)
0 = synthesizer mode
2
TWOFLO
1
0
-
0 = fixed value
direct IF at DTV mode; TV2 = 0[2]
DIRECT
1 = direct IF output
0 = zero IF or low IF output
[1] In integral TAGC loop mode the pin TAGC provides sink and source currents for control. TakeOver Point
(TOP) is set via register W9 TOPNEG[4:0].
[2] For bit description refer to Table 16 and Table 17.
Table 39. AGC mode and behavior
Bit
VIF AGC; MOD = 1[1]
SIF AGC
AGC2
AGC1
W6[5]
W6[4]
0
0
1
1
0
1
0
1
normal
normal
off (minimum gain)
fast
off (minimum gain)
normal
2nd fast
fast
[1] For bit description of MOD refer to Table 23 W2[7] and Table 24.
TDA9897_TDA9898_3
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Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 40. W7 - data write register bit allocation
7
6
5
4
3
2
1
0
0
0
SIFLEVEL VIDLEVEL OPSTATE
PORT
FILOUTBP NYQOFF
Table 41. W7 - data write register bit description
Bit
Symbol
Description
7 and 6
5
-
0 = fixed value
SIFLEVEL SIF level reduction
1 = internal SIF level is reduced by 6 dB (only for AM sound)
0 = internal SIF level is normal
4
3
2
1
0
VIDLEVEL video level reduction
1 = internal video level is reduced by 6 dB
0 = internal video level is normal
OPSTATE output state; PORT = 1
1 = output port is HIGH (external pull-up resistor needed)
0 = output port is LOW
PORT
port or VIF AGC monitor
1 = pin MPP1 is logic output port; level depends on OPSTATE
0 = pin MPP1 is VIF AGC monitor output; independent on OPSTATE
FILOUTBP external filter output signal source; see Figure 9
1 = signal for external filter is obtained behind internal BP filter
0 = signal for external filter is obtained behind SIF mixer
NYQOFF
internal Nyquist processing
1 = internal Nyquist processing off[1]
0 = internal Nyquist processing on
[1] At internal Nyquist processing off (W7[0] = 1) it is mandatory to set the internal video level bit VIDLEVEL to
normal (W7[4] = 0).
Table 42. W8 - data write register bit allocation
7
6
5
4
3
2
1
0
0
0
0
0
EASY3
EASY2
EASY1
EASY0
Table 43. W8 - data write register bit description
Bit
Symbol
Description
7 to 4
3 to 0
-
0 = fixed value
EASY[3:0] easy setting; see Table 44
TDA9897_TDA9898_3
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 44. Easy setting (to be used for fixed bit set-up only)[1]
Bit
Mode or
standard
Name
Bit definition (hexadecimal)
EASY3
EASY2
EASY1
EASY0
W1
W2
W3
W4
W5
W6
W7
W8[3]
W8[2]
W8[1]
W8[0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
off
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I 6.0
ES2
ES3
ES4
ES5
ES6
-
58
38
08
18
28
-
B1
B1
E1
F1
88
-
CC
4C
64
44
60
-
60
60
62
73
61
-
80
40
00
00
AD
-
80
80
81
80
00
-
0C
0C
08
08
0C
-
B/G 5.5
direct IF
M Japan 4.5
LIF 6/36
-
D/K 6.5
radio 5.5
-
ES8
ES9
-
78
BB
-
B1
B8
-
4C
40
-
70
26
-
C0
6B
-
80
00
-
0C
04
-
L 6.5
ES11
-
79
-
33
-
00
-
60
-
C0
-
C0
-
0C
-
-
[1] Access to register W1 to W6 after selection of an easy setting mode would require a transfer of all W1 to W6 register data.
Table 45. W9 - data write register bit allocation
7
6
5
4
3
2
1
0
DAGCSLOPE
TAGCIS
TAGCTC
TOPNEG4
TOPNEG3
TOPNEG2
TOPNEG1
TOPNEG0
Table 46. W9 - data write register bit description
Bit
Symbol
Description
7
DAGCSLOPE
AGCDIN input characteristic; see Figure 45
1 = high voltage for high gain
0 = low voltage for high gain
tuner AGC IF input
6
TAGCIS
1 = inverse to VIF input
0 = aligned to VIF input
tuner AGC time constant
1 = 2nd mode
5
TAGCTC
0 = normal
4 to 0
TOPNEG[4:0]
TOP adjustment for integral loop mode; see Table 47
TDA9897_TDA9898_3
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Product data sheet
Rev. 03 — 11 January 2008
35 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 47. Tuner takeover point adjustment bits W9[4:0]
Bit
TOP adjustment (dBµV)
TOPNEG4
TOPNEG3
TOPNEG2
TOPNEG1
TOPNEG0
W9[4]
W9[3]
W9[2]
W9[1]
W9[0]
1
:
1
:
1
:
1
:
1
:
98.2 typical
see Figure 13
78.7[1]
1
:
0
:
0
:
0
:
0
:
see Figure 13
57.9 typical
0
0
0
0
0
[1] See Table 53 for parameter tuner takeover point accuracy (αacc(set)TOP).
Table 48. W10 - data write register bit allocation
7
6
5
4
3
2
1
0
0
0
XPOTPOS TOPPOS4 TOPPOS3 TOPPOS2 TOPPOS1 TOPPOS0
Table 49. W10 - data write register bit description
Bit
Symbol
-
Description
7 and 6
5
0 = fixed value
XPOTPOS
TOP derived from IF AGC via I2C-bus or potentiometer
1 = TOP adjustment by external potentiometer at pin TOP2
0 = see Table 50
4 to 0
TOPPOS[4:0] TOP adjustment for TAGC derived from IF AGC; see Table 50
Table 50. Tuner takeover point adjustment bits W10[4:0]
Bit
TOP adjustment (dBµV)
TOPPOS4
TOPPOS3
TOPPOS2
TOPPOS1
TOPPOS0
W10[4]
W10[3]
W10[2]
W10[1]
W10[0]
1
:
1
:
1
:
1
:
1
:
99 typical
see Figure 13
81[1]
1
:
0
:
0
:
0
:
0
:
see Figure 13
61 typical
0
0
0
0
0
[1] See Table 53 for parameter tuner takeover point accuracy (αacc(set)TOP2).
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
36 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
10. Limiting values
Table 51. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min Max
Unit
V
VP
supply voltage
-
5.5
VP
10
Vn
voltage on any other pin
short-circuit time
all pins except ground
to ground or VP
0
-
V
tsc
s
Tstg
Tamb
Tcase
storage temperature
ambient temperature
case temperature
−40 +150
−20 +70
°C
°C
°C
°C
°C
°C
V
TDA9898HL (LQFP48)
TDA9898HN (HVQFN48)
TDA9897HL (LQFP48)
TDA9897HN (HVQFN48)
human body model
-
-
-
-
-
-
105
115
105
115
[1]
[2]
Vesd
electrostatic discharge voltage
±3000
±300
machine model
V
[1] Class 2 according to JESD22-A114.
[2] Class B according to EIA/JESD22-A115.
11. Thermal characteristics
Table 52. Thermal characteristics
Symbol Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction in free air; 2 layer board
to ambient
TDA9898HL (LQFP48)
TDA9898HN (HVQFN48)
TDA9897HL (LQFP48)
TDA9897HN (HVQFN48)
67
48
67
48
K/W
K/W
K/W
K/W
Rth(j-c)
thermal resistance from junction
to case
TDA9898HL (LQFP48)
TDA9898HN (HVQFN48)
TDA9897HL (LQFP48)
TDA9897HN (HVQFN48)
19
10
19
10
K/W
K/W
K/W
K/W
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
37 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
12. Characteristics
12.1 Analog TV signal processing
Table 53. Characteristics
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Supply; pin VP
VP
Parameter
Conditions
Min
Typ
Max
Unit
[1]
supply voltage
supply current
4.5
-
5.0
-
5.5
V
IP
190
mA
Power-on reset
VP(POR)
[2]
[2]
power-on reset supply
voltage
for start of reset at
decreasing supply voltage
2.5
-
3.0
3.3
3.5
4.4
V
V
for end of reset at
increasing supply voltage;
I2C-bus transmission
enable
VIF amplifier; pins IF1A, IF1B, IF2A and IF2B
VI
input voltage
-
-
-
-
1.95
2
-
V
[3]
[3]
Ri(dif)
Ci(dif)
Vi(IF)(RMS)
differential input resistance
differential input capacitance
RMS IF input voltage
-
kΩ
pF
µV
3
-
lower limit at −1 dB video
60
100
output signal
upper limit at +1 dB video
output signal
150
190
-
mV
[4]
permissible overload
-
-
-
320
-
mV
dB
∆GIF
IF gain variation
difference between
picture and sound carrier;
within AGC range;
∆f = 5.5 MHz
0.7
GVIF(cr)
control range VIF gain
60
-
66
15
80
-
-
-
dB
f−3dB(VIF)l
f−3dB(VIF)u
lower VIF cut-off frequency
MHz
MHz
upper VIF cut-off frequency
-
FPLL and true synchronous video demodulator[5]
VLFVIF
fVCO(max)
fVIF
voltage on pin LFVIF (DC)
maximum VCO frequency
VIF frequency
0.9
120
-
-
3.6
V
fVCO = 2fPC
140
-
-
-
MHz
MHz
see Table 25
related to fVIF
∆fVIF(dah)
digital acquisition help VIF
frequency window
all standards except
M/N
-
±2.3
-
MHz
M/N standard
-
-
±1.8
-
MHz
ms
[6]
tacq
acquisition time
BLF(−3dB) = 70 kHz
-
30
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
38 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vlock(min)(RMS)
RMS minimum lock-in
voltage
measured on pins IF1A
and IF1B or IF2A and
IF2B; maximum IF gain;
negative modulation
mode W2[7] = 1 and PLL
set to overmodulation
mode W2[2] = 0 and
W2[1] = 0
-
30
70
µV
Tcy(dah)
tw(dah)
digital acquisition help cycle
time
-
64
-
-
-
µs
µs
digital acquisition help pulse
width
64
Ipul(acq)VIF
KO(VIF)
VIF acquisition pulse current sink or source
21
-
-
33
-
µA
VIF VCO steepness
∆fVIF / ∆VLFVIF
26
23
MHz/V
µA/rad
KD(VIF)
VIF phase detector
steepness
∆IVPLL / ∆ϕVCO(VIF)
-
-
Ioffset(VIF)
VIF offset current
−1
0
+1
µA
Video output 2 V; pin CVBS[7]
Normal mode (sound carrier trap active) and sound carrier on
Vo(video)(p-p)
peak-to-peak video output
voltage
positive or negative
modulation; see Figure 10
W4[7] = 0; W7[4] = 0
W4[7] = 1; W7[4] = 0
W4[7] = 0; W7[4] = 1
W4[7] = 1; W7[4] = 1
1.7
1.7
1.7
-
2.0
2.0
2.0
2.0
2.3
2.3
2.3
-
V
V
V
V
∆Vo(CVBS)
CVBS output voltage
difference
difference between
L and B/G standard
W4[7] = 0; W7[4] = 0
W4[7] = 1; W7[4] = 0
W4[7] = 0; W7[4] = 1
−240
−240
−240
2.0
-
+240
+240
+240
2.75
mV
mV
mV
-
-
Vvideo/Vsync
Vsyncl
video voltage to sync voltage
ratio
2.33
sync level voltage
W4[7] = 0; W7[4] = 0
W4[7] = 1; W7[4] = 0
W4[7] = 0; W7[4] = 1
1.0
0.9
0.9
1.2
1.2
1.2
1.4
1.5
1.5
-
V
V
V
Vclip(video)u
Vclip(video)l
RO
upper video clipping voltage
lower video clipping voltage
output resistance
VP − 1.2 VP − 1
V
-
0.4
-
0.9
30
-
V
[3]
-
Ω
Ibias(int)
internal bias current (DC)
for emitter-follower
1.5
1
2.0
-
mA
mA
Isink(o)(max)
maximum output sink current AC and DC
-
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
39 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Isource(o)(max)
maximum output source
current
AC and DC
3.9
-
-
mA
∆Vo(CVBS)
CVBS output voltage
difference
50 dB gain control
30 dB gain control
negative modulation
-
-
-
-
-
-
0.5
0.1
1
dB
dB
%
∆Vblt/VCVBS
black level tilt to CVBS
voltage ratio
∆Vblt(v)/VCVBS
vertical black level tilt to
CVBS voltage ratio
worst case in L standard;
vision carrier modulated
by test line [Vertical
Interval Test Signal
(VITS)] only
-
-
3
%
[8]
[8]
[9]
Gdif
differential gain
“ITU-T J.63 line 330”
B/G standard
-
-
-
-
5
7
%
%
L standard
ϕdif
differential phase
“ITU-T J.63 line 330”
B/G standard
-
2
4
4
-
deg
deg
dB
L standard
-
2
(S/N)w
weighted signal-to-noise ratio B/G standard; 50 % grey
53
57
video signal; unified
weighting filter
(“ITU-T J.61”);
see Figure 20
(S/N)unw
unweighted signal-to-noise
ratio
M/N standard; 50 IRE
grey video signal;
see Figure 20
47
51
-
dB
VPC(rsd)(RMS)
RMS residual picture carrier fundamental wave and
voltage harmonics
-
-
2
-
5
mV
[3]
[3]
∆fPC(p-p)
peak-to-peak picture carrier 3 % residual carrier;
12
kHz
frequency variation
phase difference
50 % serration pulses;
L standard
∆ϕ
0 % residual carrier;
50 % serration pulses;
L standard;
-
-
3
%
L-gating = 0 %
[10]
[11]
αH(video)
video harmonics suppression AC load: CL < 20 pF,
35
40
-
dB
RL > 1 kΩ
αsp
spurious suppression
40
14
-
-
-
dB
dB
PSRRCVBS
power supply ripple rejection fripple = 70 Hz;
20
on pin CVBS
video signal; grey level;
positive and negative
modulation; see Figure 11
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
40 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
M/N standard inclusive Korea; see Figure 21[12]
αripple(resp)f
frequency response ripple
0.5 MHz to 2.5 MHz
2.5 MHz to 3.6 MHz
3.6 MHz to 3.8 MHz
3.8 MHz to 4.2 MHz
−1
-
+1
+2
+2
+2
-
dB
dB
dB
dB
dB
dB
dB
dB
ns
−2
-
−3
-
−16
38
-
αSC1
first sound carrier attenuation f = fSC1 = 4.5 MHz
-
f = fSC1 ± 60 kHz
29
-
-
αSC2
second sound carrier
attenuation
f = fSC2 = 4.724 MHz
25
-
-
f = fSC2 ± 60 kHz
16
-
-
[13]
td(grp)CC
color carrier group delay time f = 3.58 MHz; including
transmitter pre-correction;
−75
−50
+75
see Figure 22
B/G standard; see Figure 23[12]
αripple(resp)f
frequency response ripple
0.5 MHz to 3.2 MHz
3.2 MHz to 4.5 MHz
−1
−2
−4
−12
35
26
25
16
12
-
-
-
-
-
-
-
-
-
+1
+2
+2
+2
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
4.5 MHz to 4.8 MHz
4.8 MHz to 5 MHz
αSC1
first sound carrier attenuation f = fSC1 = 5.5 MHz
f = fSC1 ± 60 kHz
-
αSC2
second sound carrier
attenuation
f = fSC2 = 5.742 MHz
-
f = fSC2 ± 60 kHz
-
αSC(NICAM)
α
NICAM sound carrier
attenuation
fcar(NICAM) = 5.85 MHz;
f = fcar(NICAM) ± 250 kHz
-
attenuation
f = f(N+1)ch = 7 MHz
21
5
-
-
dB
dB
ns
f = f(N+1)ch ± 750 kHz
-
-
[13]
td(grp)CC
color carrier group delay time f = 4.43 MHz; including
transmitter pre-correction;
−75
−10
+75
see Figure 24
I standard; see Figure 25[12]
αripple(resp)f
frequency response ripple
0.5 MHz to 3.2 MHz
3.2 MHz to 4.5 MHz
−1
−2
−4
−12
35
26
12
-
-
-
-
-
-
-
+1
+2
+2
+2
-
dB
dB
dB
dB
dB
dB
dB
4.5 MHz to 5 MHz
5 MHz to 5.5 MHz
αSC1
first sound carrier attenuation f = fSC1 = 6.0 MHz
f = fSC1 ± 60 kHz
-
αSC(NICAM)
NICAM sound carrier
attenuation
fcar(NICAM) = 6.55 MHz;
f = fcar(NICAM) ± 250 kHz
-
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
41 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[13]
td(grp)CC
color carrier group delay time f = 4.43 MHz;
see Figure 26
−75
−15
+75
ns
D/K standard; see Figure 27[12]
αripple(resp)f
frequency response ripple
0.5 MHz to 3.1 MHz
3.1 MHz to 4.5 MHz
−1
−2
−4
−6
35
26
25
16
25
16
6
-
-
-
-
-
-
-
-
-
-
-
+1
+2
+2
+2
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
4.5 MHz to 4.8 MHz
4.8 MHz to 5.1 MHz
αSC1
first sound carrier attenuation f = fSC1 = 6.5 MHz
f = fSC1 ± 60 kHz
-
αSC2(us)
second sound carrier
attenuation (upper side)
f = fSC2 = 6.742 MHz
f = fSC2 ± 60 kHz
-
-
αSC2(ls)
second sound carrier
attenuation (lower side)
f = fSC2 = 6.258 MHz
f = fSC2 ± 60 kHz
-
-
αSC(NICAM)
NICAM sound carrier
attenuation
fcar(NICAM) = 5.85 MHz;
f = fcar(NICAM) ± 250 kHz
-
[13]
td(grp)CC
color carrier group delay time f = 4.28 MHz; including
transmitter pre-correction;
−50
0
+100
ns
see Figure 28
L standard; see Figure 29[12]
αripple(resp)f
frequency response ripple
0.5 MHz to 3.2 MHz
3.2 MHz to 4.5 MHz
4.5 MHz to 4.8 MHz
4.8 MHz to 5.3 MHz
−1
−2
−4
−12
5
-
-
-
-
-
+1
+2
+2
+2
-
dB
dB
dB
dB
dB
αSC(NICAM)
αSC(AM)
NICAM sound carrier
attenuation
fcar(NICAM) = 5.85 MHz;
f = fcar(NICAM) ± 250 kHz
AM sound carrier attenuation f = fSC(AM) = 6.5 MHz
38
-
-
dB
dB
ns
f = fSC(AM) ± 30 kHz
29
-
-
td(grp)CC
color carrier group delay time f = 4.28 MHz; including
transmitter pre-correction;
−75
−5
+75
see Figure 30
Video output 1.1 V; pin CVBS
Trap bypass mode and sound carrier off[12]
Vo(video)(p-p)
peak-to-peak video output
voltage
see Figure 10
-
-
1.1
1.5
-
V
Vsyncl
sync level voltage
-
V
Vclip(video)u
Vclip(video)l
Bvideo(−3dB)
upper video clipping voltage
lower video clipping voltage
−3 dB video bandwidth
VP − 1.1 VP − 1
-
V
-
0.4
8
0.9
-
V
AC load: CL < 20 pF,
6
MHz
RL > 1 kΩ
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
42 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[9]
(S/N)w
weighted signal-to-noise ratio B/G standard; 50 % grey
54
-
-
dB
video signal; unified
weighting filter
(“ITU-T J.61”);
see Figure 20
[9]
(S/N)unw
unweighted signal-to-noise
ratio
M/N standard; 50 IRE
grey video signal;
see Figure 20
47
51
-
dB
Loop filter synthesizer; pin LFSYN1
VLFSYN1
voltage on pin LFSYN1
1.0
-
-
-
3.5
65
V
Isource(o)PD(max)
maximum phase detector
output source current
µA
Isink(o)PD(max)
maximum phase detector
output sink current
-
-
65
µA
KO
KD
VCO steepness
-
-
3.75
9
-
-
MHz/V
phase detector steepness
µA/rad
Pin MPP1 operating as VIF AGC voltage monitor
[3]
Vmonitor(VIFAGC)
VAGC
VIF AGC monitor voltage
AGC voltage
0.5
-
4.5
V
see Figure 12; Vi(IF) set to
1 mV (60 dBµV)
2.2
2.5
3
-
-
-
-
2.6
3.1
4
V
10 mV (80 dBµV)
200 mV (106 dBµV)
sink or source
V
V
Io(max)
maximum output current
10
-
µA
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
43 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[14]
tresp
response time
increasing VIF step;
negative modulation
normal mode
fast mode
-
-
-
4.3
1.5
130
-
-
-
µs/dB
µs/dB
µs/dB
[14]
[14]
increasing VIF step;
positive modulation;
normal mode
decreasing VIF step;
negative modulation
normal mode
fast normal mode
2nd mode
-
-
-
-
1.9
-
-
-
-
ms/dB
ms/dB
ms/dB
ms/dB
0.08
0.25
0.01
fast 2nd mode
[14]
decreasing VIF step;
positive modulation
20 dB
-
890
2.6
143
−6
-
ms
fast mode
-
-
ms/dB
ms/dB
dB
normal mode
L standard
see Table 11
-
-
αth(fast)VIF
VIF fast mode threshold
−10
−2
-
∆VVAGC(step)
VIF AGC voltage difference
(step)
-
40
mV/bit
Pin MPP1 operating as open-collector output port
VOL
LOW-level output voltage
output sink current
I = 2 mA (sink)
W7[3] = 0
-
-
-
-
-
-
-
-
0.4
3
V
Isink(o)
mA
µA
W7[3] = 1
10
VOH
HIGH-level output voltage
VP + 0.5 V
VIF AGC; pin CIFAGC
Ich(max) maximum charge current
Ich(add)
L standard
75
-
100
100
125
-
µA
additional charge current
L standard: in the event of
missing VITS pulses and
no white video content
nA
Idch
discharge current
L standard; normal mode
L standard; fast mode
-
-
35
-
-
nA
1.8
µA
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
44 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tuner AGC; pin TAGC
Integral TAGC loop mode (W6[7:6] = 10); TAGC is current output; applicable for negative modulation only; unmodulated VIF;
see Table 46 and Figure 13
Vi(IF)(RMS)
RMS IF input voltage
at starting point of tuner
AGC takeover;
I
sink(TAGC) = 100 µA
W9[4:0] = 0 0000
W9[4:0] = 1 0000
W9[4:0] = 1 1111
-
57.9
78.7
98.2
-
-
dBµV
dBµV
dBµV
dB
-
-
-
-
αacc(set)TOP
TOP setting accuracy
source current
−2
+2
Isource
TAGC charge current
normal mode;
W9[5] = 0
0.2
1.9
7
0.3
2.3
11
0.4
2.7
15
µA
µA
µA
2nd normal mode;
W9[5] = 1
fast mode activated by
internal level detector;
W9[5] = 0
2nd fast mode activated
by internal level
60
90
120
µA
detector; W9[5] = 1
Isink
sink current
TAGC discharge current;
400
-
500
600
µA
VTAGC = 1 V
∆αacc(set)TOP/∆T TOP setting accuracy
W9[4:0] = 1 0000
-
0.02
dB/K
variation with temperature
[3]
[3]
RL
load resistance
50
-
-
-
MΩ
Vsat(u)
upper saturation voltage
pin operating as current
output
VP − 0.3 -
V
Vsat(l)
lower saturation voltage
AGC fast mode threshold
pin operating as current
output
-
-
0.3
10
V
αth(fast)AGC
activated by internal fast
AGC detector; I2C-bus
setting corresponds to
W9[4:0] = 1 0000
6
8
dB
td
delay time
before activating; Vi(IF)
40
60
80
ms
below αth(fast)AGC
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
45 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TAGC loop based on VIF AGC (W6[7:6] = 11); TAGC is voltage output; applicable for TV mode: positive modulation and
optional for negative modulation); see Table 49; Figure 13 and Figure 14
Vi(IF)(RMS)
RMS IF input voltage
at starting point of tuner
AGC takeover;
VTAGC = 3.5 V
RTOP2 = 22 kΩ or
W10[5:0] = 00 0000
-
-
61
81
-
-
dBµV
dBµV
RTOP2 = 10 kΩ or
W10[5:0] = 01 0000
RTOP2 = 0 kΩ
-
96
99
-
-
dBµV
dBµV
dB
W10[5:0] = 01 1111
-
-
αacc(set)TOP2
TOP2 setting accuracy
−6
-
+6
0.07
∆αacc(set)TOP2/∆T TOP2 setting accuracy
VTAGC = 3.5 V
0.03
dB/K
variation with temperature
VO
output voltage
no tuner gain reduction
4.5
0.2
-
-
VP
V
V
maximum tuner gain
reduction
0.6
∆Gslip(TAGC)
TAGC slip gain offset
tuner gain voltage from
0.6 V to 3.5 V
3
5
8
dB
TOP adjust 2; pin TOP2; IF based TAGC loop mode; see Figure 14
VTOP2
RI
voltage on pin TOP2 (DC)
input resistance
pin open-circuit
-
-
3.5
27
-
-
V
kΩ
RTOP2
resistance on pin TOP2
adjustment of VIF AGC
based TAGC loop
W10[5] = 1; external
resistor operation
0
-
-
22
-
kΩ
kΩ
W10[5] = 0; forced
I2C-bus operation
100
Pin CTAGC
VCTAGC
IL
[3]
[3]
[3]
voltage on pin CTAGC
leakage current
0.2
-
-
-
0.55VP
10
V
sink
-
-
nA
nA
source
10
Control current or voltage monitor output; pin MPP2
General
Vsat(u)
Vsat(l)
upper saturation voltage
lower saturation voltage
VP − 0.8 VP − 0.5 -
0.5 0.8
V
V
-
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
46 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
AFC (current output)
[15][16]
Io
output current
sink or source;
see Figure 17 and
Figure 18
100 kHz VIF deviation
200 kHz VIF deviation
1.5 MHz VIF deviation
80
-
160
240
240
µA
µA
µA
160
160
200
-
AFC TV mode
[16]
[17]
[17]
∆IAFC/∆fVIF
change of AFC current with
VIF frequency
0.85
−20
−20
1.05
1.25
+20
+20
µA/kHz
kHz
fVIFacc(dig)
fVIFacc(a)
digital accuracy of VIF
frequency
read-out via I2C-bus;
R1[4:1] = f0; fref = 4 MHz
-
-
analog accuracy of VIF
frequency
IAFC = 0 A; fref = 4 MHz
kHz
AFC radio mode
[16]
[17]
[17]
∆IAFC/∆fRIF
change of AFC current with
RIF frequency
0.85
−10
−10
1.05
1.25
+10
+10
µA/kHz
kHz
fRIFacc(dig)
fRIFacc(a)
digital accuracy of RIF
frequency
read-out via I2C-bus;
R1[4:1] = f0; fref = 4 MHz
-
-
analog accuracy of RIF
frequency
IAFC = 0 A; fref = 4 MHz
kHz
AGC monitor (voltage output)
Gv
voltage gain
voltage on pin MPP2 to
internal control voltage;
see Table 32
-
0
-
dB
SIF AGC
FM AGC
-
6
6
0
-
-
-
-
-
dB
dB
dB
µA
-
TAGC
-
Io(max)
maximum output current
sink or source
350
SIF amplifier; pins IF3A and IF3B or pins IF1A and IF1B or pins IF2A and IF2B
VI
input voltage
-
-
-
1.95
2
-
-
-
V
Ri(dif)
Ci(dif)
differential input resistance
differential input capacitance
kΩ
pF
3
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
47 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vi(SIF)(RMS)
RMS SIF input voltage
FM mode; −3 dB at
intercarrier output
pins OUT1A and OUT1B;
without FM AGC;
see Table 21
-
60
100
µV
AM mode; −3 dB at
AF output pin AUD
-
40
70
-
µV
FM mode; +1 dB at
intercarrier output
pins OUT1A and OUT1B;
without FM AGC;
see Table 21
150
190
mV
AM mode; +1 dB at
AF output pin AUD
70
140
-
mV
permissible overload
FM and AM mode
-
-
320
mV
GSIF(cr)
control range SIF gain
60
-
66
7
-
-
-
dB
f−3dB(SIF)l
f−3dB(SIF)u
lower SIF cut-off frequency
upper SIF cut-off frequency
MHz
MHz
-
80
SIF AGC detector; pin MPP2; see Figure 16
tresp
response time
increasing or decreasing
SIF step of 20 dB;
AM mode; fast AGC
increasing
decreasing
-
-
8
-
-
ms
ms
25
increasing or decreasing
SIF step of 20 dB;
AM mode; slow AGC
increasing
decreasing
-
-
80
-
-
ms
ms
250
increasing or decreasing
SIF step of 20 dB;
FM mode; normal AGC
increasing
decreasing
-
-
0.3
20
-
-
ms
ms
increasing or decreasing
SIF step of 20 dB;
FM mode; fast AGC
increasing
decreasing
-
-
0.1
4
-
-
ms
ms
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
48 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
FM mode
Min
Typ
Max
Unit
VAGC(SIF)
SIF AGC voltage
VSIF = 100 µV
VSIF = 10 mV
VSIF = 140 mV
AM mode
1.5
2.6
3.3
-
-
-
2.4
3.4
VP
V
V
V
VSIF = 100 µV
VSIF = 10 mV
VSIF = 140 mV
1.5
2.9
3.3
-
-
-
2.4
3.9
VP
V
V
V
Conversion synthesizer PLL; pin LFSYN2 (radio mode)
VLFSYN2
KO
voltage on pin LFSYN2
VCO steepness
1
-
-
3
-
V
∆fVCO / ∆VLFSYN2
31
MHz/V
KD
phase detector steepness
∆ILFSYN2 / ∆ϕVCO;
see Table 57;
fVCO selection:
22 MHz to 29.5 MHz
30 MHz to 37.5 MHz
38 MHz to 45.5 MHz
46 MHz to 53.5 MHz
57 MHz
-
-
-
-
-
32
38
47
61
61
-
-
-
-
-
µA/rad
µA/rad
µA/rad
µA/rad
µA/rad
Io(PD)
phase detector output current sink or source;
fVCO selection:
22 MHz to 29.5 MHz
30 MHz to 37.5 MHz
38 MHz to 45.5 MHz
46 MHz to 53.5 MHz
57 MHz
-
-
-
-
-
200
238
294
384
384
-
-
-
-
-
µA
µA
µA
µA
µA
ϕn(synth)
synthesizer phase noise
with 4 MHz crystal
oscillator reference
[3]
[3]
[3]
[3]
[3]
[3]
at 1 kHz
89
89
98
115
50
-
99
99
102
119
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
at 10 kHz
-
at 100 kHz
-
at 1.4 MHz
-
αsp
spurious suppression
leakage current
multiple of ∆f = 500 kHz
-
IL
synthesizer spurious
performance > 50 dBc
-
10
nA
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
49 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PSRR
power supply ripple rejection residual spurious at
nominal differential output
voltage dependent on
-
50
-
dB
power supply ripple at
70 Hz; see Figure 11
Single reference QSS intercarrier mixer; pins OUT1A and OUT1B
VOUT1A
voltage on pin OUT1A (DC)
voltage on pin OUT1B (DC)
internal bias current (DC)
1.8
1.8
2.0
1.4
3.0
2.0
2.0
2.5
1.7
-
2.2
V
VOUT1B
2.2
V
Ibias(int)
for emitter-follower
-
-
-
mA
mA
mA
Isink(o)(max)
Isource(o)(max)
maximum output sink current DC and AC
maximum output source
current
DC and AC; with external
resistor to GND
RO
output resistance
output active;
single-ended to GND
-
-
25
-
Ω
output inactive; internal
resistance to GND
-
800
140
Ω
Vo(RMS)
RMS output voltage
IF intercarrier
90
180
mV
single-ended to GND;
SC1 on; SC2 off
IF intercarrier
single-ended to GND;
L standard;
without modulation;
BP on
W7[5] = 0
W7[5] = 1
45
20
11
70
35
15
90
45
-
mV
mV
f−3dB(ic)u
αimage
upper intercarrier cut-off
frequency
internal sound band-pass
off
MHz
image rejection
band-pass off;
−8 MHz to 0 MHz
24
-
28
2
-
dB
Vinterf(RMS)
RMS interference voltage
fundamental wave and
harmonics
5
mV
AM intercarrier from pin EXTFILI to pins OUT1A and OUT1B
G
gain
IF intercarrier;L standard;
without modulation
-
5
-
dB
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
50 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Band-pass mode
fc
center frequency
QSS mode;
BP selection for standard
M/N
-
-
-
-
-
4.7
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
B/G
5.75
6.25
6.25
6.05
I
D/K
L/L-accent
radio mode;
BP selection for standard
M/N
B/G
I
-
-
-
-
-
4.7
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
5.75
6.25
6.78
10.7
D/K
RADIO
f−3dB(BP)u
f−3dB(BP)l
αstpb
upper BP cut-off frequency
lower BP cut-off frequency
stop-band attenuation
M/N, B/G, I, D/K or
L/L-accent standard
fc + 0.5 fc + 0.65 fc + 0.8 MHz
RADIO 10.7
fc + 0.25 fc + 0.4 fc + 0.55 MHz
M/N, B/G, I, D/K or
L/L-accent standard
fc − 0.5 fc − 0.65 fc − 0.8 MHz
RADIO 10.7
fc − 0.25 fc − 0.4 fc − 0.55 MHz
at fc ± 1.5 MHz
M/N, B/G, I, D/K or
L/L-accent standard
20
15
30
25
-
-
dB
dB
RADIO 10.7
αCC
color carrier attenuation
QSS mode;
BP selection for standard
M/N; fCC = 3.58 MHz
B/G; fCC = 4.43 MHz
I; fCC = 4.43 MHz
15
22
20
20
20
23
30
28
28
28
-
-
-
-
-
dB
dB
dB
dB
dB
D/K; fCC = 4.28 MHz
L/L-accent;
fCC = 4.28 MHz
External filter output; pin EXTFILO
VEXTFILO
voltage on pin EXTFILO (DC)
1.8
2.0
2.2
V
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
51 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VEXTFILO(p-p)
peak-to-peak voltage on
pin EXTFILO
IF intercarrier; SC1 on;
SC2 off
420
620
820
mV
IF intercarrier;L standard;
without modulation
W7[5] = 0
W7[5] = 1
210
105
1
310
155
-
410
205
-
mV
mV
mA
Io(max)
maximum output current
AC and DC
FM PLL demodulator
fFMPLL
FM PLL frequency
see Table 18 and
Table 20
-
-
-
-
-
4.5
5.5
6.0
6.5
10.7
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
FM PLL filter; pin LFFM
VLFFM
voltage on pin LFFM
fFMPLL = 4.5 MHz
fFMPLL = 5.5 MHz
fFMPLL = 6.0 MHz
fFMPLL = 6.5 MHz
fFMPLL = 10.7 MHz
1.5
1.5
1.5
1.5
1.5
-
1.9
2.2
2.35
2.5
2.4
64
3.3
3.3
3.3
3.3
3.3
-
V
V
V
V
V
Tcy(dah)
tw(dah)
Io(dah)
digital acquisition help cycle
time
µs
digital acquisition help pulse
width
-
16
-
µs
digital acquisition help output sink or source
current
W3[4] = 0; W6[3] = 0;
FM window
width = 237.5 kHz
14
28
14
28
18
36
18
36
22
44
22
44
µA
µA
µA
µA
W3[4] = 1; W6[3] = 0;
FM window
width = 475 kHz
W3[4] = 0; W6[3] = 1;
FM window
width = 1 MHz
W3[4] = 1; W6[3] = 1;
FM window
width = 1 MHz
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
52 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
KD(FM)
FM phase detector
steepness
∆IFMPLL / ∆ϕVCO(FM)
W3[4] = 0; W6[3] = 0;
FM window
-
4
-
µA/rad
width = 237.5 kHz
W3[4] = 1; W6[3] = 0;
FM window
width = 475 kHz
-
-
-
10
4
-
-
-
µA/rad
µA/rad
µA/rad
W3[4] = 0; W6[3] = 1;
FM window
width = 1 MHz
W3[4] = 1; W6[3] = 1;
FM window
10
width = 1 MHz
KO(FM)
FM VCO steepness
FM offset current
∆fFMPLL / ∆VLFFM
f < 10 MHz
-
3.3
5.9
0
-
MHz/V
MHz/V
µA
f = 10.7 MHz
-
-
Ioffset(FM)
W6[3] = 0; W3[4] = 0
W6[3] = 0; W3[4] = 1
−1.5
−2.5
+1.5
+2.5
0
µA
FM intercarrier input; pins EXTFMI and EXTFILI; see Figure 15
|Zi|
input impedance
AC-coupled via 4 pF
-
20
-
-
kΩ
Vi(FM)(RMS)
RMS FM input voltage
gain controlled operation;
W1[1:0] = 10 or
2
300
mV
W1[1:0] = 11 or
W1[1:0] = 01
Vlock(min)(RMS)
RMS minimum lock-in
voltage
W1[1:0] = 10 or
W1[1:0] = 11 or
W1[1:0] = 01
-
-
-
-
1.5
1.8
mV
mV
Vdet(FM)min(RMS) RMS minimum FM carrier
detection voltage
W1[1:0] = 10 or
W1[1:0] = 11 or
W1[1:0] = 01
FM demodulator part; audio output; pin AUD
Vo(AF)(RMS)
RMS AF output voltage
QSS mode;
25 kHz FM deviation;
75 µs de-emphasis
400
430
900
360
500
540
-
600
650
1300
540
mV
mV
mV
mV
QSS mode;
27 kHz FM deviation;
50 µs de-emphasis
QSS mode;
55 kHz FM deviation;
50 µs de-emphasis
radio mode;
450
22.5 kHz FM deviation;
75 µs de-emphasis
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
53 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
∆Vo(AF)/∆T
AF output voltage variation
with temperature
-
3 × 10−3 7 × 10−3 dB/K
THD
total harmonic distortion
50 µs de-emphasis;
FM deviation: for
-
0.15
0.50
%
TV mode 27 kHz and for
radio mode 22.5 kHz
[18]
∆fAF(max)
maximum AF frequency
deviation
THD < 2 %;pre-emphasis
off; fAF = 400 Hz
W3[1:0] = 00 (audio
gain = 0 dB)
±55
-
-
-
-
-
-
-
-
kHz
kHz
kHz
kHz
W3[1:0] = 01 (audio
gain = −6 dB)
±110
±170
±380
W3[1:0] = 10 (audio
gain = −12 dB)
W3[1:0] = 11 (audio
gain = −18 dB) and
W3[4] = 1 (FM window
width = 475 kHz)
[3]
fAF(max)
maximum AF frequency
THD < 2 %;
pre-emphasis off
FM window
15
15
80
48
-
-
-
-
-
kHz
kHz
kHz
dB
width = 237.5 kHz;
−6 dB audio gain;
FM deviation 100 kHz
FM window
-
width = 475 kHz;
−18 dB audio gain;
FM deviation 300 kHz
f−3dB(AF)
AF cut-off frequency
W3[2] = 0; W3[4] = 0;
without de-emphasis;
FM window
100
56
width = 237.5 kHz
(S/N)w(AF)
AF weighted signal-to-noise 27 kHz FM deviation;
ratio
50 µs de-emphasis; vision
carrier unmodulated;
FM PLL only;
“ITU-R BS.468-4”
(S/N)unw(AF)
AF unweighted
signal-to-noise ratio
radio mode (10.7 MHz);
22.5 kHz FM deviation;
75 µs de-emphasis
-
-
58
-
-
dB
VSC(rsd)(RMS)
RMS residual sound carrier
voltage
fundamental wave and
harmonics; without
de-emphasis
2
mV
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
54 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
αAM
AM suppression
referenced to 27 kHz
FM deviation;
35
46
-
dB
50 µs de-emphasis;
AM: f = 1 kHz; m = 54 %
PSRR
power supply ripple rejection
fripple = 70 Hz;
14
20
-
dB
see Figure 11
Audio amplifier
Audio output; pin AUD
[3]
RO
VO
RL
output resistance
-
-
300
Ω
output voltage
load resistance
2.0
10
100
-
2.4
2.7
V
[3]
[3]
[3]
AC-coupled
DC-coupled
-
-
-
-
kΩ
kΩ
nF
-
CL
load capacitance
1
Vo(AF)(RMS)
RMS AF output voltage
25 kHz FM deviation;
75 µs de-emphasis;
see Table 28
0 dB
400
500
250
125
62.5
600
mV
mV
mV
mV
−6 dB
−12 dB
−18 dB
-
-
-
-
-
-
AM; m = 54 %;
see Table 28
0 dB
400
500
250
150
600
mV
mV
kHz
−6 dB
-
-
-
-
[19]
[20]
f−3dB(AF)u
f−3dB(AF)l
upper AF cut-off frequency
lower AF cut-off frequency
mute attenuation
W3[2] = 0 (without
de-emphasis)
W3[2] = 0 (without
de-emphasis)
-
20
-
Hz
αmute
of AF signal
70
-
-
-
dB
∆Vjmp
jump voltage difference (DC) switching AF output to
mute state or vice versa;
activated by digital
±50
±150
mV
acquisition help W3[6] = 1
or via W3[5]
PSRR
power supply ripple rejection
f
ripple = 70 Hz;
14
-
20
-
-
dB
V
see Figure 11
De-emphasis network; pin CDEEM
VO
output voltage
2.4
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
55 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RO
output resistance
W3[3:2] = 11 (50 µs
8.5
-
14
kΩ
de-emphasis)
W3[3:2] = 01 (75 µs
de-emphasis)
13
-
-
21
-
kΩ
VAF(RMS)
RMS AF voltage
fAF = 400 Hz;
170
mV
Vo(AF) = 500 mV (RMS);
0 dB attenuation
AF decoupling
Pin CAF1
Vdec
decoupling voltage (DC)
fFMPLL = 4.5 MHz
fFMPLL = 5.5 MHz
fFMPLL = 6.0 MHz
fFMPLL = 6.5 MHz
fFMPLL = 10.7 MHz
1.5
1.5
1.5
1.5
1.5
-
1.9
2.2
2.35
2.5
2.4
-
3.3
3.3
3.3
3.3
3.3
±25
V
V
V
V
V
IL
leakage current
∆VAUD < ±50 mV (p-p);
nA
0 dB attenuation
Io(max)
Pin CAF2
VO
maximum output current
sink or source
1.15
-
1.5
2.4
1.85
-
µA
output voltage
V
FM operation[21][22]
Single reference QSS AF performance; pin AUD[23]
(S/N)w(SC1)
first sound carrier weighted
signal-to-noise ratio
PC / SC1 > 40 dB at
pins IF1A and IF1B or
IF2A and IF2B;
27 kHz FM deviation;
BP off; “ITU-R BS.468-4”
black picture
white picture
45
45
43
50
50
47
-
-
-
dB
dB
dB
6 kHz sine wave
(black-to-white
modulation)
250 kHz square wave
(black-to-white
modulation)
45
50
-
dB
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
56 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Single reference QSS AF performance with external FM demodulator connected to OUT1A and OUT1B[24]
(S/N)w(SC1)
first sound carrier weighted
signal-to-noise ratio
PC / SC1 > 40 dB at
pins IF1A and IF1B or
IF2A and IF2B;
27 kHz FM deviation;
BP off; “ITU-R BS.468-4”
black picture
white picture
53
50
44
58
53
48
-
-
-
dB
dB
dB
6 kHz sine wave
(black-to-white
modulation)
250 kHz square wave
(black-to-white
modulation)
40
45
46
45
51
52
-
-
-
dB
dB
dB
sound carrier
subharmonics;
f = 2.75 MHz ± 3 kHz
sound carrier
subharmonics;
f = 2.87 MHz ± 3 kHz
(S/N)w(SC2)
second sound carrier
with external reference
weighted signal-to-noise ratio FM demodulator;
PC / SC2 > 40 dB at
pins IF1A and IF1B or
IF2A and IF2B; 27 kHz
(54 % FM deviation);
BP off; “ITU-R BS.468-4”
black picture
white picture
48
46
42
55
51
46
-
-
-
dB
dB
dB
6 kHz sine wave
(black-to-white
modulation)
250 kHz square wave
(black-to-white
modulation)
29
44
45
34
50
51
-
-
-
dB
dB
dB
sound carrier
subharmonics;
f = 2.75 MHz ± 3 kHz
sound carrier
subharmonics;
f = 2.87 MHz ± 3 kHz
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
57 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
AM operation
L standard; pin AUD
Vo(AF)(RMS)
THD
RMS AF output voltage
54 % modulation
400
-
500
0.5
600
1.0
mV
%
total harmonic distortion
54 % modulation; BP on;
see Figure 33
BAF(−3dB)
−3 dB AF bandwidth
12
18
-
kHz
(S/N)w(AF)
AF weighted signal-to-noise “ITU-R BS.468-4”
ratio
BP on
38
44
-
42
50
40
-
-
-
dB
dB
dB
BP off
[3]
composite IF; VIF
modulation = color bar;
“ITU-R BS.468-4”; BP on
Reference frequency
General
[25]
fref
reference frequency
-
4
-
MHz
V
Reference frequency generation with crystal; pin OPTXTAL
VOPTXTAL
voltage on pin OPTXTAL
(DC)
pin open-circuit
2.3
2.6
2.9
[3]
Ri
input resistance
-
2
-
-
kΩ
Ω
Rrsn(xtal)
crystal resonance resistance
pull capacitance
-
200
-
[26]
Cpull
-
-
pF
kΩ
Rswoff(OPTXTAL)
switch-off resistance on pin
OPTXTAL
to switch off crystal input
by external resistor wired
between pin OPTXTAL
and GND
0.22
-
4.7
Iswoff
switch-off current
Rswoff(OPTXTAL) = 0.22 kΩ
Rswoff(OPTXTAL) = 3.3 kΩ
-
-
-
1600
-
µA
µA
500
Reference frequency input from external source; pin OPTXTAL
VOPTXTAL
voltage on pin OPTXTAL
(DC)
pin open-circuit
2.3
2.6
2.9
V
[3]
Ri
input resistance
-
2
-
-
kΩ
mV
kΩ
Vref(RMS)
RO
RMS reference voltage
output resistance
80
-
400
4.7
[3]
[3]
of external reference
signal source
2
Cdec
decoupling capacitance
to external reference
signal source
22
100
-
pF
Reference frequency input from external source; W7[7] = 0; pin FREF
VFREF
Ri
voltage on pin FREF (DC)
input resistance
pin open-circuit
2.2
50
2.5
-
2.8
-
V
[3]
kΩ
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
58 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
fref
Parameter
Conditions
Min
Typ
4
Max
-
Unit
MHz
mV
[25]
reference frequency
RMS reference voltage
output resistance
-
Vref(RMS)
RO
see Figure 34
15
-
150
-
500
4.7
of external reference
signal source;
kΩ
AC-coupled
Cdec
decoupling capacitance
to external reference
signal source
22
100
-
-
pF
Rswoff(FREF)
switch-off resistance on
pin FREF
to switch off reference
signal input by external
resistor wired between
pin FREF and GND
3.9
27
kΩ
Iswoff
switch-off current
Rswoff(FREF) = 3.9 kΩ
Rswoff(FREF) = 22 kΩ
-
-
-
100
-
µA
µA
75
I2C-bus transceiver[27]
Address select; pin ADRSEL
VADRSEL
voltage on pin ADRSEL (DC) pin open-circuit
-
0.5VP
-
V
for address select
MAD1; pin connected
to GND
0
-
-
-
-
0.04VP
0.30VP
0.86VP
VP
V
V
V
V
MAD3; pin connected
to GND via RADRSEL
0.12VP
0.66VP
0.96VP
MAD4; pin connected
to VP via RADRSEL
MAD2; pin connected
to VP
[3]
Ri
input resistance
-
35
47
-
kΩ
kΩ
RADRSEL
resistance on pin ADRSEL
42.3
51.7
I2C-bus voltage select; pin BVS
VBVS
Isink(I)
Isource(I)
VI
voltage on pin BVS (DC)
pin open-circuit
-
0.52VP
-
V
input sink current
input source current
input voltage
pin connected to VP
pin connected to GND
-
-
-
-
10
60
VP
µA
µA
V
-
VCC(I2C-bus) = 5.0 V; pin
connected to VP
0.88VP
VCC(I2C-bus) = 3.3 V; pin
open-circuit
0.46VP
0
-
-
0.58VP
0.12VP
V
V
VCC(I2C-bus) = 2.5 V; pin
connected to GND
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
59 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I2C-bus transceiver; pins SCL and SDA[28]
[29]
[30]
[30]
[29]
[30]
[30]
VIH
HIGH-level input voltage
LOW-level input voltage
VCC(I2C-bus) = 5.0 V
VCC(I2C-bus) = 3.3 V
VCC(I2C-bus) = 2.5 V
VCC(I2C-bus) = 5.0 V
VCC(I2C-bus) = 3.3 V
VCC(I2C-bus) = 2.5 V
0.6VP
2.3
-
-
-
-
-
-
-
-
-
VP
V
VP
V
1.75
−0.3
−0.3
−0.3
−10
−10
-
VP
V
VIL
+0.3VP
+1.0
+0.75
+10
+10
0.4
V
V
V
IIH
HIGH-level input current
LOW-level input current
LOW-level output voltage
µA
µA
V
IIL
VOL
IOL = 3 mA; for data
transmission (SDA)
fSCL
SCL clock frequency
0
-
400
kHz
[1] Values of video and sound parameters can be decreased at VP = 4.5 V.
[2] Condition for secure POR is a rise or fall time greater than 2 µs.
[3] This parameter is not tested during the production and is only given as application information for designing the receiver circuit.
[4] Level headroom for input level jumps during gain control setting.
[5] BLF(−3dB) = 100 kHz (damping factor d = 1.9; calculated with sync level within gain control range). Calculation of the VIF PLL filter can be
done by use of the following formula:
1
2π
BLF(–3dB)
1
=
K K R , valid for d ≥ 1.2
------
O
D
d = R K K C ,
--
O
D
2
where:
rad
-------
sV
Hz
------
V
A
KO is the VCO steepness
or 2π
; KD is the phase detector steepness
;
-------
rad
R is the loop filter serial resistor (Ω); C is the loop filter serial capacitor (F); BLF(−3dB) is the −3 dB LF bandwidth (Hz); d is the damping
factor.
[6] The VCO frequency offset related to the PC frequency is set to 1 MHz with white picture video modulation.
[7] AC load; CL < 20 pF and RL > 1 kΩ. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound
carrier traps.
[8] Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps.
[9] Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter (“ITU-T J.64”).
[10] Modulation VSB; sound carrier off; fvideo > 0.5 MHz.
[11] Sound carrier on; fvideo = 10 kHz to 10 MHz.
[12] The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 24. In this way the full composite video
spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p).
[13] Measurement condition: with transformer, transmitter pre-correction on; reference is at 1 MHz.
[14] The response time is valid for a VIF input level range from 200 µV to 70 mV.
[15] See Figure 19 to smooth current pulses.
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Multistandard hybrid IF processing
[16] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The
AFC steepness can be changed by resistors R1 and R2.
[17] The AFC value of the VIF and RIF frequency is generated by using digital counting methods. The used counter resolution is provided
with an uncertainty of ±1 bit corresponding to ±25 kHz. This uncertainty of ±25 kHz has to be added to the frequency accuracy
parameter.
[18] Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The audio signal processing stage
provides headroom of 6 dB with THD < 1.5 %. The I2C-bus bits W3[0] and W3[1] control the AF output signal amplitude from
0 dB to −18 dB in steps of −6 dB. Reducing the audio gain for handling a frequency deviation of more than 55 kHz avoids AF output
signal clipping.
[19] Amplitude response depends on dimensioning of FM PLL loop filter.
[20] The lower AF cut-off frequency depends on the value of the capacitor at pin CAF1. A value of CAF1 = 470 nF leads to f−3dB(AF)l ≈ 20 Hz
and CAF1 = 220 nF leads to f−3dB(AF)l ≈ 40 Hz.
[21] For all signal-to-noise measurements the used VIF modulator has to meet the following specifications:
a) Incidental phase modulation for black-to-white jump less than 0.5 degrees.
b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted signal-to-noise ratio) better than
60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation.
c) Picture-to-sound carrier ratio PC / SC1 = 13 dB (transmitter).
[22] The PC / SC ratio is calculated as the addition of TV transmitter PC / SC1 ratio and SAW filter PC / SC1 ratio. This PC / SC ratio is
necessary to achieve the weighted signal-to-noise values as noted. A different PC / SC ratio will change these values.
[23] Measurement condition is SC1 / SC2 ≥ 7 dB.
[24] The differential QSS signal output on pins OUT1A and OUT1B is analyzed by a test demodulator TDA9820. The signal-to-noise ratio of
this device is better than 60 dB. The measurement is related to an FM deviation of ±27 kHz and in accordance with “ITU-R BS.468-4”.
[25] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum
FM deviation, sound trap frequency, LIF band-pass cut-off frequency and ZIF low-pass cut-off frequency as well as the accuracy of the
synthesizer.
[26] The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.
[27] The AC characteristics are in accordance with the I2C-bus specification for fast mode (maximum clock frequency is 400 kHz).
Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it” (order number 9398 393 40011).
[28] The SDA and SCL lines will not be pulled down if VP is switched off.
[29] The threshold is dependent on VP.
[30] The threshold is independent of VP.
Table 54. Examples to the FM PLL filter
BLF(−3dB) (kHz)
Cs (nF)
Cpar (pF)
Rs (kΩ)
Comment
210
2.2
100
8.2
recommended for single-carrier-sound,
FM narrow
410
130
210
2.2
2.2
2.2
47
5.6
5.6
8.2
recommended for single-carrier-sound, FM wide
recommended for two-carrier-sound, FM narrow
used for test circuit
470
47
Table 55. Input frequencies and carrier ratios (examples)
Symbol Parameter B/G standard M/N standard L standard L-accent standard Unit
fPC
picture carrier frequency
38.375
32.825
32.583
13
38.375
38.375
33.625
MHz
MHz
MHz
dB
fSC1
fSC2
sound carrier frequency 1
sound carrier frequency 2
33.825
31.825
40.125
-
-
-
PC / SC1 picture to first sound carrier ratio
7
-
10
-
10
-
PC / SC2 picture to second sound carrier ratio 20
dB
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Multistandard hybrid IF processing
trap bypass mode
normal mode
zero carrier level
white level
2.72 V
2.6 V
3.41 V
3.20 V
black level
1.83 V
1.5 V
1.80 V
1.20 V
sync level
mhc115
Fig 10. Typical video signal levels on output pin CVBS (sound carrier off)
V = V + V
P
ripple
TDA9897
TDA9898
V
(V)
P
5.050
5.000
4.950
t (s)
001aae391
Fig 11. Ripple rejection condition
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Multistandard hybrid IF processing
001aad353
5
5
V
V
monitor(VIFAGC)
TAGC
(V)
(V)
4
4
3
2
1
0
3
2
1
(1)
(2)
(3)
(4)
0
30
50
70
90
110
i(VIF)
130
(dBµV)
V
(1) VIF AGC.
(2) TAGC; W10 = 00h.
(3) TAGC; W10 = 10h.
(4) TAGC; W10 = 1Fh.
Fig 12. Typical VIF monitor and TAGC characteristic
001aaf640
100
V
i(IF)
(dBµV)
90
80
70
60
50
bit pattern W9[4:0] or W10[4:0]
Integral TAGC (W9); step width: 1.3 dBµV.
IF based TAGC (W10).
Fig 13. Typical tuner takeover point as a function of I2C-bus register W9 or W10
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Multistandard hybrid IF processing
008aaa034
100
V
i(IF)
(dBµV)
90
80
70
60
(1)
0
5
10
15
20
TOP2
25
(kΩ)
R
(1) IF based TAGC (TOP2).
Fig 14. Typical tuner takeover point as a function of resistor RTOP2
001aad356
001aad357
5
5
V
V
AGC(FM)
(V)
AGC(SIF)
(V)
4
3
2
1
0
4
3
2
1
0
(1)
(2)
40
60
80
100
i(EXTFMI)
120
(dBµV)
20
40
60
80
100
i(SIF)
120
(dBµV)
V
V
(1) AM.
(2) FM.
Fig 15. Typical FM AGC characteristic measured at
pin MPP2
Fig 16. Typical SIF AGC characteristic measured at
pin MPP2
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Multistandard hybrid IF processing
008aaa035
250
250
(6)
(5)
I
∆f
AFC
AFC(VIF)
(kHz)
(1)
(µA)
150
150
50
0
50
(2)
bit AFCWIN (R1[7]) = 1
0
(3)
−50
−50
−150
−250
−150
(4)
−250
40.375
(MHz)
36.375
36.875
37.375
37.875
38.375
38.875
39.375
39.875
f
VIF
(1) VIF AFC via I2C-bus; accuracy is ±1 digit.
(2) Bit AFCWIN via I2C-bus (VCO is in ±1.6 MHz window) for all standards except M/N standard.
(3) Bit AFCWIN via I2C-bus (VCO is in ±0.8 MHz window) for M/N standard.
(4) VIF AFC average current.
(5) Reading via I2C-bus.
(6) Average; RC network at pin MPP2.
Fig 17. Typical analog and digital AFC characteristic for VIF
001aad443
250
250
I
(µA)
(4)
(5)
∆f
AFC(RIF)
AFC
(1)
(kHz)
150
150
(2)
50
50
0
0
−50
−50
−150
−150
(3)
AFC undefined
5.2
bit CARRDET (R1[5]) = 1
5.4 5.6
AFC undefined
5.8
−250
5.0
−250
6.0
f
(MHz)
RIF
Characteristics of digital and analog radio AFC is mirrored with respect to center frequency when lower sideband is used
(W2[3] = 0).
(1) RIF AFC via I2C-bus.
(2) FM carrier detection via I2C-bus.
(3) RIF AFC average current.
(4) Reading via I2C-bus.
(5) Average; RC network at pin MPP2.
Fig 18. Typical analog and digital AFC characteristic for RIF
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Multistandard hybrid IF processing
V
P
R1
22 kΩ
I
AFC
MPP2
TDA9897
TDA9898
R2
100 nF
22 kΩ
001aae392
Fig 19. RC network for measurement of analog AFC characteristic
001aad660
60
S/N
(dB)
(1)
(2)
50
40
30
50
60
70
80
90
i(VIF)
100
(dBµV)
V
(1) B/G standard; weighted video S/N; using 50 % grey picture.
(2) M/N standard; unweighted video S/N; using 50 IRE grey picture.
Fig 20. Typical signal-to-noise ratio as a function of VIF input voltage
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Multistandard hybrid IF processing
001aad487
5
0
(1)
(2)
α
resp(f)
(dB)
(3)
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 21. Typical amplitude frequency response for sound trap at M/N standard (including
Korea)
001aad365
250
200
t
d(grp)
(ns)
150
100
50
(1)
(3)
(2)
0
−50
−100
−150
−200
−250
0
1
2
3
4
5
6
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 22. Typical group delay response for sound trap at M/N standard
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Multistandard hybrid IF processing
001aad488
5
0
(1)
(2)
α
resp(f)
(dB)
(3)
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 23. Typical amplitude frequency response for sound trap at B/G standard
001aad361
250
200
150
100
50
t
d(grp)
(ns)
(1)
(3)
0
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 24. Typical group delay response for sound trap at B/G standard
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Multistandard hybrid IF processing
001aad489
5
0
(1)
(2)
α
resp(f)
(dB)
(3)
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 25. Typical amplitude frequency response for sound trap at I standard
001aad363
250
200
150
100
50
t
d(grp)
(ns)
(1)
(3)
0
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 26. Typical group delay response for sound trap at I standard
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Multistandard hybrid IF processing
001aaf551
5
0
(1)
(2)
α
resp(f)
(dB)
−5
−10
−15
−20
−25
−30
−35
−40
−45
(3)
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 27. Typical amplitude frequency response for sound trap at D/K standard
001aaf552
250
200
150
100
50
t
d(grp)
(ns)
(1)
(3)
(2)
0
−50
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 28. Typical group delay response for sound trap at D/K standard
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Multistandard hybrid IF processing
001aad491
5
0
(1)
(2)
α
resp(f)
(dB)
(3)
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 29. Typical amplitude frequency response for sound trap at L standard
001aad364
250
200
150
100
50
t
d(grp)
(ns)
(1)
(3)
0
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 30. Typical group delay response for sound trap at L standard
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Multistandard hybrid IF processing
001aaf579
10
α
resp(f)
(dB)
(1)
0
−10
−20
−30
−40
−50
(5)
(4)
(3)
(2)
(7)
(6)
−3.0
−2.0
−1.0
0
1.0
2.0
3.0
f − f (MHz)
c
(1) Center frequency.
(2) Minimum upper cut-off frequency.
(3) Minimum lower cut-off frequency.
(4) Maximum upper cut-off frequency.
(5) Maximum lower cut-off frequency.
(6) Minimum upper stop-band attenuation.
(7) Minimum lower stop-band attenuation.
Fig 31. Typical sound BP amplitude frequency response at TV mode, normalized to BP
center frequency
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaf578
10
α
resp(f)
(dB)
(1)
0
−10
−20
−30
−40
−50
(5)
(4)
(3) (2)
(7)
(6)
−3.0
−2.0
−1.0
0
1.0
2.0
3.0
f − f (MHz)
c
(1) Center frequency.
(2) Minimum upper cut-off frequency.
(3) Minimum lower cut-off frequency.
(4) Maximum upper cut-off frequency.
(5) Maximum lower cut-off frequency.
(6) Minimum upper stop-band attenuation.
(7) Minimum lower stop-band attenuation.
Fig 32. Typical sound BP amplitude frequency response at radio 10.7 mode, normalized to
BP center frequency
001aad359
2.0
THD
(%)
1.5
1.0
0.5
0
−2
−1
2
10
10
1
10
10
f
(kHz)
AF
Fig 33. Typical total harmonic distortion as a function of audio frequency at AM standard
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Multistandard hybrid IF processing
001aaf468
55
(S/N)
w
(dB)
45
35
25
0
50
100
150
i(FREF)(RMS)
200
(mV)
V
Reference frequency input signal taken from external quartz circuit.
Fig 34. Weighted FM audio S/N versus reference frequency input level using radio mode
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NXP Semiconductors
Multistandard hybrid IF processing
001aaf639
1
120
antenna
input
level
IF signal
RMS
values
(V)
(5)
(2)
(dBµV)
(4)
−1
100
80
60
40
20
0
10
(6)
(3)
RF
gain
control
range
−2
10
IF gain
control
range
IF gain
control
range limited
by TOP
−3
10
adjustment
−4
10
(1)
−5
10
(7)
−6
10
tuner
band-pass
X3450L
VIF
amplifier
demodulator
video
amplifier
TD1716
IF demodulator, TDA989x
Video signal related peak-to-peak levels are divided by factor 2√2 in order to conform with the
RMS value scale of the secondary y-axis, but disregarding the none sine wave signal content.
(1) Signal levels for −1 dB video output level using maximum RF gain and maximum IF gain.
(2) Signal levels for +1 dB video output level using minimum IF gain.
(3) Signal levels for TOP-adjusted tuner output level using maximum RF gain and
adjustment-related minimum IF gain.
(4) Signal levels for TOP-adjusted tuner output level using minimum RF gain and
adjustment-related minimum IF gain.
(5) TOP-adjusted tuner output level.
(6) TOP-adjusted VIF amplifier input level.
(7) Minimum antenna input level at −1 dB video level.
Fig 35. Front-end level diagram
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Multistandard hybrid IF processing
12.2 Digital TV signal processing
Table 56. Characteristics
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification;
i(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
V
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of
Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IF amplifier; pins IF3A and IF3B or IF1A and IF1B or IF2A and IF2B
VI
input voltage
1.8
-
1.93
2
2.2
-
V
[2]
[2]
[2]
Ri(dif)
differential input
resistance
kΩ
Ci(dif)
differential input
capacitance
-
3
-
-
pF
dB
GIF(cr)
control range IF gain
60
66
DTV differential output; pins OUT1A, OUT1B, OUT2A and OUT2B
VO
output voltage
pin open-circuit
1.8
2.0
2.0
2.5
2.2
-
V
Ibias(int)
internal bias current
(DC)
for emitter-follower
mA
[3]
[3]
Isink(o)(max)
Isource(o)(max)
RO
maximum output sink DC and AC; see Figure 36
current
1.4
6.0
1.7
-
-
-
mA
mA
maximum output
source current
DC and AC; see Figure 36
[2]
[2]
output resistance
differential; output active
-
-
-
50
-
Ω
Ω
output inactive; internal
resistance to GND
800
Vi(IF)(RMS)
RMS IF input voltage minimum input sine wave
level for nominal output level
-
70
170
-
100
-
µV
maximum input sine wave
level for nominal output level
130
-
mV
mV
[2]
permissible overload
320
Direct IF; pins OUT2A and OUT2B
[2]
[4]
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
-
83
-
dB
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
between pin OUT2A and
pin OUT2B
W4[7] = 0
W4[7] = 1
-
-
1.0
1.1
V
V
0.50
0.55
[2][5][6]
C/N
carrier-to-noise ratio
at fo = 33.4 MHz;
see Figure 37
Vi(IF) = 10 mV (RMS)
Vi(IF) = 0.5 mV (RMS)
115
90
124
104
-
-
dBc/Hz
dBc/Hz
[2]
αIM
intermodulation
suppression
input signals: fi = 47.0 MHz
and 57.5 MHz; output
signals: fo = 36.5 MHz or
68.0 MHz; see Figure 38
W4[7] = 0
W4[7] = 1
40
40
-
-
-
-
dB
dB
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Product data sheet
Rev. 03 — 11 January 2008
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of
Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2]
fIF(−1dB)l
lower −1 dB IF cut-off
-
7
-
MHz
frequency
[4]
[7]
[2]
f−3dB(IF)u
PSRR
upper IF cut-off
frequency
W4[7] = 0
W4[7] = 1
60
60
-
-
-
-
MHz
MHz
power supply ripple
rejection
residual spurious at nominal
differential output voltage
dependent on power supply
ripple
fripple = 70 Hz
fripple = 20 kHz
-
-
60
60
-
-
dB
dB
Low or zero IF output signal; pins OUT1A and OUT1B or pins OUT2A and OUT2B; differential
[2]
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
-
89
-
dB
fsynth
synthesizer frequency see Table 35 and Table 36
-
-
-
-
-
-
-
MHz
V
[4]
[4]
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
W4[7] = 0
W4[7] = 1
2
1
V
[2]
PSRR
power supply ripple
rejection
residual spurious at nominal
differential output voltage
dependent on power supply
ripple
fripple = 70 Hz
fripple = 20 kHz
-
-
50
30
-
-
dB
dB
Low IF output signal; pins OUT1A and OUT1B
αripple(pb)LIF
low IF pass-band
ripple
6 MHz bandwidth
7 MHz bandwidth
8 MHz bandwidth
BP off
-
-
2.7
dB
-
-
2.7
dB
-
-
2.7
dB
[4]
[4]
[4]
[4]
B−3dB
−3 dB bandwidth
11
-
15
7.8
8.8
9.8
40
35
40
35
40
35
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
dB
6 MHz bandwidth
7 MHz bandwidth
8 MHz bandwidth
-
-
αstpb
stop-band attenuation 6 MHz band; f = 11.75 MHz
6 MHz band; f = 20 MHz
30
28
30
28
30
28
dB
7 MHz band; f = 13.75 MHz
7 MHz band; f = 20 MHz
dB
dB
8 MHz band; f = 15.75 MHz
8 MHz band; f = 20 MHz
dB
dB
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© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
77 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of
Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2]
[2]
∆td(grp)
group delay time
variation
from 1 MHz to 2 MHz
-
90
200
ns
from 2 MHz to end of band
with a bandwidth of
6 MHz
7 MHz
-
-
-
90
90
90
160
160
160
ns
ns
ns
8 MHz
αimage
image rejection
−10 MHz to 0 MHz
BP on
30
24
34
28
-
-
dB
dB
BP off
[2][5][6]
C/N
carrier-to-noise ratio
at fo = 4.9 MHz;
see Figure 37
Vi(IF) = 10 mV (RMS)
Vi(IF) = 0.5 mV (RMS)
112
90
118
104
-
-
dBc/Hz
dBc/Hz
[2]
αH(ib)
in-band harmonics
suppression
low IF = multiple of
1.31 MHz;
fi = fsynth + 1.31 MHz;
see Figure 41
W4[7] = 0
W4[7] = 1
40
40
-
-
-
-
dB
dB
[2]
αIM
intermodulation
suppression
input signals:
fi = fsynth + 4.7 MHz and
fsynth + 5.3 MHz; output
signals: fo = 4.1 MHz or
5.9 MHz; see Figure 40
W4[7] = 0
W4[7] = 1
40
40
50
-
-
-
-
-
-
dB
dB
dB
[2]
[2]
αsp(ib)
in-band spurious
suppression
single-ended AC load;
RL = 1 kΩ; CL = 5 pF;
1 MHz to end of band;
BP on
αsp(ob)
out-band spurious
suppression
single-ended AC load;
50
-
-
dB
RL = 1 kΩ; CL = 5 pF; BP on
Zero IF output signal; pins OUT1A and OUT1B or pins OUT2A and OUT2B
αripple(pb)ZIF
zero IF pass-band
ripple
3.0 MHz bandwidth
3.5 MHz bandwidth
4.0 MHz bandwidth
BP off
-
-
1.8
dB
-
-
1.8
dB
-
-
1.8
dB
[4]
[4]
[4]
[4]
B−3dB
−3 dB bandwidth
11
-
15
3.7
4.2
4.7
-
-
-
-
MHz
MHz
MHz
MHz
3.0 MHz bandwidth
3.5 MHz bandwidth
4.0 MHz bandwidth
-
-
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
78 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of
Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
30
Typ
40
Max
Unit
dB
αstpb
stop-band attenuation 3.0 MHz band; f = 7.75 MHz
3.5 MHz band; f = 9.25 MHz
-
-
-
30
40
dB
4.0 MHz band;
f = 10.75 MHz
30
40
dB
any band; f = 15 MHz
28
35
-
dB
[2]
∆td(grp)
group delay time
variation
from 0 MHz to end of band
with a bandwidth of
3.0 MHz
3.5 MHz
4.0 MHz
-
-
-
60
50
45
100
100
100
ns
ns
ns
[2][5][6]
C/N
carrier-to-noise ratio
at fo = 1.9 MHz;
see Figure 37
Vi(IF) = 10 mV (RMS)
Vi(IF) = 0.5 mV (RMS)
112
87
121
101
-
-
-
-
dBc/Hz
dBc/Hz
dB
αIM
intermodulation
suppression
input signals:
40
fi = fsynth + 1.7 MHz and
fsynth + 2.3 MHz; output
signals: fo = 1.1 MHz or
2.9 MHz; see Figure 39
[2][4]
[2][4]
[2]
αsp(ib)
αsp(ob)
∆ϕ
in-band spurious
suppression
0.437 MHz to end of band;
BP on
40
50
-
-
-
-
-
-
dB
dB
deg
dB
out-band spurious
suppression
BP on
-
phase difference
mismatch between I and Q
channel
6
2
∆G
gain mismatch
mismatch between I and Q
channel
-
IF AGC control; pin AGCDIN
Isink(i)(max) maximum input sink
[2]
[2]
[2]
-
-
2
µA
V
current
Vi(max)
maximum input
voltage
-
-
VP
3
VAGCDIN
voltage on pin
AGCDIN
0
-
-
V
∆GIF/∆VAGCDIN change of IF gain with VAGCDIN = 0.8 V to 2.2 V
−45
-
dB/V
voltage on
pin AGCDIN
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
79 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of
Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified.
Symbol
Tuner AGC; pin TAGC
Integral TAGC loop mode (W6[7:6] = 10); TAGC is current output; unmodulated IF
Parameter
Conditions
Min
Typ
Max
Unit
Vi(IF)(RMS)
RMS IF input voltage at starting point of tuner
AGC takeover;
I
sink(TAGC) = 100 µA
W9[4:0] = 0 0000
W9[4:0] = 1 0000
W9[4:0] = 1 1111
-
57.9
78.7
98.2
-
-
dBµV
dBµV
dBµV
dB
-
-
-
-
αacc(set)TOP
TOP setting accuracy
source current
−2
+2
Isource
TAGC charge current
normal mode
0.20
7
0.27
10
0.34
13
µA
µA
fast mode activated by
internal level detector
Isink
sink current
TAGC discharge current;
400
-
500
-
600
µA
VTAGC = 1 V
[2]
∆αacc(set)TOP/∆T TOP setting accuracy
variation with
Isink(TAGC) = 100 µA;
0.02
dB/K
W9[4:0] = 1 0000
temperature
[2]
[2]
RL
load resistance
50
-
-
-
-
MΩ
Vsat(u)
upper saturation
voltage
pin operating as current
output
VP − 0.3
V
[2]
[2]
Vsat(l)
lower saturation
voltage
pin operating as current
output
-
-
0.3
10
V
αth(fast)AGC
AGC fast mode
threshold
activated by internal fast
AGC detector; I2C-bus
setting corresponds to
W9[4:0] = 1 0000
6
8
dB
[2]
td
delay time
before activating; Vi(IF)
below αth(fast)AGC
40
60
-
80
ms
V
Filter synthesizer PLL; pin LFSYN1
VLFSYN1
voltage on pin
LFSYN1
1.0
3.5
KO
KD
VCO steepness
∆fVCO / ∆VLFSYN1
∆ILFSYN1 / ∆ϕVCO
-
-
3.75
9
-
-
MHz/V
phase detector
steepness
µA/rad
Isink(o)PD(max)
maximum phase
detector output sink
current
-
-
-
-
65
65
µA
µA
Isource(o)PD(max) maximum phase
detector output
source current
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
80 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of
Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Conversion synthesizer PLL; pin LFSYN2
VLFSYN2
voltage on pin
LFSYN2
1
-
-
3
-
V
KO
KD
VCO steepness
∆fVCO / ∆VLFSYN2
31
MHz/V
phase detector
steepness
∆ILFSYN2 / ∆ϕVCO;
see Table 57;
fVCO selection:
22 MHz to 29.5 MHz
30 MHz to 37.5 MHz
38 MHz to 45.5 MHz
46 MHz to 53.5 MHz
57 MHz
-
-
-
-
-
32
38
47
61
61
-
-
-
-
-
µA/rad
µA/rad
µA/rad
µA/rad
µA/rad
Io(PD)
phase detector output sink or source;
current
fVCO selection:
22 MHz to 29.5 MHz
30 MHz to 37.5 MHz
38 MHz to 45.5 MHz
46 MHz to 53.5 MHz
57 MHz
-
-
-
-
-
200
238
294
384
384
-
-
-
-
-
µA
µA
µA
µA
µA
ϕn(synth)
synthesizer phase
noise
fsynth = 31 MHz;
fIF = 36 MHz
[2]
[2]
[2]
[2]
at 1 kHz
89
99
-
-
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
at 10 kHz
at 100 kHz
at 1.4 MHz
89
99
98
102
119
115
fsynth = 40 MHz;
IF = 44 MHz; external
f
4 MHz reference signal of
265 mV (RMS) and phase
noise better than
120 dBc/Hz; see Figure 46
[2]
[2]
[2]
[2]
[2]
[2]
at 1 kHz
89
89
96
115
50
-
96
100
100
118
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
at 10 kHz
at 100 kHz
at 1.4 MHz
-
-
-
αsp
spurious suppression multiple of ∆f = 500 kHz
-
IL
leakage current
synthesizer spurious
performance > 50 dBc
-
10
nA
Reference frequency
General
[8]
fref
reference frequency
-
4
-
MHz
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
81 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of
Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reference frequency generation with crystal; pin OPTXTAL
VOPTXTAL
voltage on pin
pin open-circuit
2.3
2.6
2.9
V
OPTXTAL (DC)
[2]
[9]
Ri
input resistance
-
-
2
-
-
kΩ
Rrsn(xtal)
crystal resonance
resistance
200
Ω
Cpull
pull capacitance
-
-
-
-
pF
Rswoff(OPTXTAL) switch-off resistance
on pin OPTXTAL
to switch off crystal input by
external resistor wired
between pin OPTXTAL and
GND
0.22
4.7
kΩ
Iswoff
switch-off current
Rswoff(OPTXTAL) = 0.22 kΩ
Rswoff(OPTXTAL) = 3.3 kΩ
-
-
-
1600
-
µA
µA
500
Reference frequency input from external source; pin OPTXTAL
VOPTXTAL
voltage on pin
pin open-circuit
2.3
2.6
2.9
V
OPTXTAL (DC)
[2]
Ri
input resistance
-
2
-
-
kΩ
Vref(RMS)
RMS reference
voltage
80
400
mV
[2]
[2]
RO
output resistance
of external reference signal
source
-
2
4.7
-
kΩ
Cdec
decoupling
capacitance
to external reference signal
source
22
100
pF
Reference frequency input from external source; W7[7] = 0; pin FREF
VFREF
voltage on pin FREF pin open-circuit
(DC)
2.2
2.5
2.8
V
[2]
[8]
Ri
input resistance
50
-
-
-
kΩ
fref
reference frequency
4
-
MHz
mV
Vref(RMS)
RMS reference
voltage
see Figure 46
15
150
500
RO
output resistance
of external reference signal
source; AC-coupled
-
-
4.7
-
kΩ
pF
kΩ
Cdec
decoupling
capacitance
to external reference signal
source
22
3.9
100
-
Rswoff(FREF)
switch-off resistance
on pin FREF
to switch off reference signal
input by external resistor
wired between pin FREF
and GND
27
Iswoff
switch-off current
Rswoff(FREF) = 3.9 kΩ
Rswoff(FREF) = 22 kΩ
-
-
-
100
-
µA
µA
75
[1] Some parameters can be decreased at VP = 4.5 V.
[2] This parameter is not tested during production and is only given as application information.
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
82 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
[3] Output current can be increased by application of single-ended resistor from each output pin to GND. Recommended resistor value is
minimum 1 kΩ.
[4] With single-ended load for fIF < 45 MHz RL ≥ 1 kΩ and CL ≤ 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 kΩ and CL ≤ 3 pF to
ground.
[5] Noise level is measured without input signal but AGC adjusted corresponding to the given input level.
[6] Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off.
[7] With single-ended load RL ≥ 1 kΩ and CL ≤ 5 pF to ground.
[8] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum
FM deviation, sound trap frequency, LIF band-pass cut-off frequency and ZIF low-pass cut-off frequency as well as the accuracy of the
synthesizer.
[9] The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.
Table 57. Conversion synthesizer PLL; loop filter dimensions[1]
fVCO (MHz)
22 to 29.5
30 to 37.5
38 to 45.5
46 to 53.5
57
RLFSYN2 (kΩ)[2]
CLFSYN2 (nF)
1.5
1.8
2.2
2.7
3.3
4.7
4.7
4.7
4.7
4.7
[1] Calculation of the PLL loop filter by using the following formulae, valid under the condition for the damping
K
K
1
--
2
factor d ≥ 1.2. BLF(–3dB)
=
OK R
-------
and d =
R
2π OK C
with the following
LFSYN2
-------
D
LFSYN2
LFSYN2
D
N
N
parameters
KO = VCO steepness (MHz/V),
fVCO
N = divider ratio: N =
,
--------------------
0.5 MHz
KD = phase frequency detector steepness (µA/rad),
RLFSYN2 = synthesizer loop filter serial resistor (Ω),
CLFSYN2 = synthesizer loop filter serial capacitor (F),
BLF(−3dB) = −3 dB LF bandwidth (Hz),
d = damping factor.
[2] If more than one frequency range is used in the application, then the smallest resistor value should be
applied.
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
83 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aah343
(3)
30
C
L(dif)
(pF)
20
(2)
(1)
10
0
0
1
2
3
R
L(dif)
(kΩ)
W4[7] = 0; nominal output level
(1) Direct IF, fmax = 40 MHz, with single-ended resistors of 1 kΩ to GND.
(2) Low IF, fmax = 9 MHz.
(3) Zero IF, fmax = 4 MHz.
Fig 36. Maximum differential load figures at OUT1/OUT2
001aaf467
130
C/N
(dBc/Hz)
120
(1)
110
(2)
(3)
100
90
80
30
50
70
90
i(IF)(RMS)
110
(dBµV)
V
(1) Direct IF.
(2) Low IF.
(3) Zero IF.
Fig 37. Typical C/N ratio as a function of IF input voltage
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
84 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
V
V
i(IF)(RMS)
(dBµV)
o(dif)(p-p)
(V)
74
0.5
(1)
α
IM
0
0
0
47
57.5
0
36.5
47
57.5
68
f
f
o
i
(MHz)
(MHz)
input signal
output signal
008aaa051
(1) 0.25 V for W4[7] = 1.
Fig 38. Direct IF signal conditions for measurement of intermodulation at OUT2
V
V
i(IF)(RMS)
(dBµV)
o(dif)(p-p)
(V)
74
1.0
(1)
α
IM
0
0
36
37.7 38.3
input signal
0
1.1
1.7
2.3
2.9
f
f
o
(MHz)
i
f
synth
(MHz)
output signal
008aaa052
(1) 0.5 V for W4[7] = 1.
Fig 39. Zero IF signal conditions for measurement of intermodulation at OUT1 and OUT2
V
V
i(IF)(RMS)
(dBµV)
o(dif)(p-p)
(V)
74
0.5
(1)
α
IM
0
0
36
40.7 41.3
input signal
0
4.1
4.7
5.3
5.9
f
f
o
(MHz)
i
f
synth
(MHz)
output signal
008aaa053
(1) 0.25 V for W4[7] = 1.
Fig 40. Low IF signal conditions for measurement of intermodulation at OUT1
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
85 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
V
V
i(IF)(RMS)
(dBµV)
o(dif)(p-p)
(V)
80
2.0
(1)
α
H(ib)
0
0
36
37.31
0
1.31 2.62 3.93 5.24 6.55 7.86
output signal
f
f
o
(MHz)
i
f
synth
(MHz)
input signal
008aaa054
(1) 1.0 V for W4[7] = 1.
Fig 41. Low IF signal conditions for measurement of harmonics at OUT1
001aad494
2
t
d(grp)LIF
(ns)
α
resp(f)
(dB)
1
0
−1
−2
(1) (2) (3)
−3
−4
−5
−6
100
0
(3)
−100
−200
−7
−8
−9
−10
0
2
4
6
8
10
12
f (MHz)
tolerance scheme:
(1)
(2)
(3)
(1) Channel bandwidth = 6 MHz.
(2) Channel bandwidth = 7 MHz.
(3) Channel bandwidth = 8 MHz.
Fig 42. Detailed low IF amplitude and group delay pass-band tolerance scheme
TDA9897_TDA9898_3
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Product data sheet
Rev. 03 — 11 January 2008
86 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aad495
10
0
α
resp(f)
(dB)
−10
−20
−30
−40
−50
−60
−70
(3)
(2)
(1)
−30
−25
−20
−15
−10
−5
0
f (MHz)
tolerance scheme:
(1)
(2)
(3)
(1) Channel bandwidth = 6 MHz.
(2) Channel bandwidth = 7 MHz.
(3) Channel bandwidth = 8 MHz.
Fig 43. Low IF amplitude stop-band tolerance scheme
001aad496
10
α
resp(f)
(dB)
0
−10
−20
−30
(1)
(2)
(3)
−40
−50
−60
−70
0
5
10
15
20
25
30
f (MHz)
tolerance scheme:
(1)
(2)
(3)
(1) Channel bandwidth = 6 MHz.
(2) Channel bandwidth = 7 MHz.
(3) Channel bandwidth = 8 MHz.
Fig 44. Low IF amplitude pass-band tolerance scheme
TDA9897_TDA9898_3
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Product data sheet
Rev. 03 — 11 January 2008
87 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
008aaa089
100
(7)
G
(dB)
80
(1)
(2)
(3)
(4)
(5)
(6)
60
40
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
AGCDIN
3.5
(V)
V
(1) 2.0 V (p-p) differential output voltage (LIF or ZIF, W9[7] = 0, W4[7] = 0).
(2) 1.0 V (p-p) differential output voltage (LIF or ZIF, W9[7] = 0, W4[7] = 1; DIF, W9[7] = 0,
W4[7] = 0).
(3) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 0, W4[7] = 1).
(4) 2.0 V (p-p) differential output voltage (LIF or ZIF, W9[7] = 1, W4[7] = 0).
(5) 1.0 V (p-p) differential output voltage (LIF or ZIF, W9[7] = 1, W4[7] = 1; DIF, W9[7] = 1,
W4[7] = 0).
(6) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 1, W4[7] = 1).
(7) Ratio of output peak-to-peak level to input RMS level.
Fig 45. Typical gain characteristic for AGCDIN control voltage
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
88 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aag285
105
ϕ
n(synth)
(dBc/Hz)
(1)
(2)
95
(3)
85
75
0
100
200
300
400
i(FREF)(RMS)
500
(mV)
V
fsynth = 40 MHz; fIF = 44 MHz
(1) ∆f = 100 kHz.
(2) ∆f = 10 kHz.
(3) ∆f = 1 kHz.
Fig 46. Typical synthesizer phase noise at carrier frequency plus ∆f on LIF output versus
input voltage on pin FREF
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
89 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
13. Application information
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
(2)
3.3 kΩ
C
C
TAGC
FREF
100 pF
(1)
(3)
22 kΩ
470 Ω
4 MHz
220 nF
analog
ground
V
P
= 5 V
22 pF
100 nF
i.c.
45
n.c.
n.c.
37
synthesizer
downconverter
(4)
loop filter
22 pF
n.c.
48
1
47
46
44
43 42 41
40
39
38
AGC input for DIF
(from channel decoder)
36
R
LFSYN2
C
LFSYN2
n.c.
2
35
34
33
32
31
30
29
28
27
26
25
C
AF2
3
1.5 nF
2 V CVBS
4
output
C
IFAGC
5
BVS
470 nF
SAW
VIF
X6872
6
AUD
(6)
(5)
TDA9898
IF
(b)
(a)
7 MHz WINDOW
7
(6)
ZIF Q or
1st DIF
C
CTAGC
8
390 nF
C
AF1
SAW
VIF
X6768
9
470 nF
(b)
(a)
digital LIF or
ZIF I or
analog 2nd
sound IF
6 MHz WINDOW
10
11
(6)
(6)
MPP1
12
13
14
15
16
17
18
19
20
21 22 23
24
MPP2
560 Ω
digital
ground
C
4.7 nF
de-em
C
par
C
s
220 nF
(6)
ADRSEL
BP
FM PLL
(7)
R
s
100 Ω
100 Ω
330 Ω
loop filter
560
Ω
VIF
loop filter
external
FM input
SDA
SCL
008aaa092
(1) Connect resistor if external reference signal is not used.
(2) Connect resistor if crystal is not used.
(3) Use of crystal is optional.
(4) Application depends on synthesizer frequency; see Table 57.
(5) Optional single-ended IF input possible.
(6) Optional.
(7) See Table 54.
Fig 47. Application diagram of TDA9898
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
90 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
(2)
3.3 kΩ
C
C
TAGC
FREF
100 pF
(1)
(3)
22 kΩ
470 Ω
4 MHz
220 nF
analog
ground
V
P
= 5 V
22 pF
100 nF
i.c.
45
n.c.
n.c.
37
synthesizer
downconverter
(4)
22 pF
n.c.
48
1
47
46
44 43
42 41 40
39
38
loop filter
AGC input for DIF
(from channel decoder)
36
R
LFSYN2
C
LFSYN2
n.c.
2
35
34
33
32
31
30
29
28
27
26
25
C
AF2
3
1.5 nF
2 V CVBS
4
output
n.c.
5
BVS
SAW
VIF
X6872
6
AUD
(6)
(5)
TDA9897
IF
(b)
(a)
7 MHz WINDOW
7
(6)
ZIF Q or
1st DIF
C
CTAGC
8
390 nF
C
AF1
SAW
VIF
X6768
9
470 nF
(b)
(a)
digital LIF or
ZIF I or
analog 2nd
sound IF
6 MHz WINDOW
10
11
(6)
(6)
MPP1
12
13
14
15
16
MPP2
560 Ω
17
18
19
20
21 22 23
24
digital
ground
C
4.7 nF
de-em
220 nF
C
par
C
s
(6)
ADRSEL
BP
FM PLL
(7)
R
s
100 Ω
100 Ω
330 Ω
loop filter
560
Ω
external
FM input
VIF
loop filter
SDA
SCL
008aaa093
(1) Connect resistor if external reference signal is not used.
(2) Connect resistor if crystal is not used.
(3) Use of crystal is optional.
(4) Application depends on synthesizer frequency; see Table 57.
(5) Optional single-ended IF input possible.
(6) Optional.
(7) See Table 54.
Fig 48. Application diagram of TDA9897
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
91 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
(2)
3.3 kΩ
C
C
TAGC
FREF
100 pF
(1)
(3)
22 kΩ
470 Ω
4 MHz
220 nF
analog
ground
V
P
= 5 V
22 pF
100 nF
i.c.
45
n.c.
n.c.
37
synthesizer
downconverter
(4)
22 pF
n.c.
48
1
47
46
44 43
42 41 40
39
38
loop filter
AGC input for DIF
(from channel decoder)
36
R
LFSYN2
C
LFSYN2
n.c.
2
35
34
33
32
31
30
29
28
27
26
25
C
AF2
3
IF
SAW
SIF
X7550
1.5 nF
2 V CVBS
4
output
n.c.
5
BVS
SAW
VIF
M1980
6
AUD
(6)
TDA9897
(b)
(a)
NYQUIST SLOPE
7
(6)
ZIF Q or
1st DIF
C
CTAGC
8
390 nF
(5)
C
AF1
9
470 nF
(6)
(5)
(b)
(a)
digital LIF or
ZIF I or
analog 2nd
sound IF
10
11
(6)
(6)
MPP1
12
13
14
15
16
MPP2
560 Ω
17
18
19
20
21 22 23
24
digital
ground
C
4.7 nF
de-em
220 nF
C
par
C
s
(6)
ADRSEL
BP
FM PLL
(7)
R
s
100 Ω
100 Ω
1 nF
330 Ω
loop filter
560
Ω
external
FM input
VIF
loop filter
SDA
SCL
008aaa094
(1) Connect resistor if external reference signal is not used.
(2) Connect resistor if crystal is not used.
(3) Use of crystal is optional.
(4) Application depends on synthesizer frequency; see Table 57.
(5) Value depends on application.
(6) Optional.
(7) See Table 54.
Fig 49. Application diagram of TDA9897 using SAW filter with Nyquist slope
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
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92 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
14. Test information
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
(2)
3.3 kΩ
C
C
TAGC
FREF
100 pF
(1)
(3)
22 kΩ
470 Ω
4 MHz
100 nF
analog
ground
V
P
= 5 V
22 pF
100 nF
i.c.
45
n.c.
n.c.
37
synthesizer
downconverter
(4)
loop filter
22 pF
n.c.
48
1
47
46
44 43
42 41 40
39
38
AGC input for DIF
(from channel decoder)
36
R
LFSYN2
C
LFSYN2
n.c.
C
2
35
34
33
32
31
30
29
28
27
26
25
SIF/DIF
1 : 1
AF2
1
2
5
4
3
1.5 nF
2 V CVBS
51 Ω
51 Ω
51 Ω
4
output
3
C
IFAGC
5
BVS
470 nF
5
VIF/SIF/DIF
1 : 1
1
2
6
AUD
TDA9898
4
(b)
7
3
ZIF Q or 1st DIF
C
CTAGC
(a)
C
8
100 nF
5
VIF/SIF/DIF
1 : 1
AF1
1
2
9
470 nF
(b)
4
10
11
digital LIF or ZIF I or
analog 2nd sound IF
3
(a)
TOP potentiometer for
RSSI and positive modulation
22 kΩ
MPP1
+5 V
12
13
14
15
16
17
18
19
20
21 22 23
24
2.7 kΩ only for port
function
MPP2
digital
ground
C
par
C
s
C
de-em
220 nF
ADRSEL
4.7 nF
FM PLL
(5)
R
s
loop filter
330 Ω
100 Ω
100 Ω
008aaa045
SDA
SCL
VIF
loop filter
external
FM input
output to
sound BPF
FM input
from sound BPF
(1) Connect resistor if external reference signal is not used.
(2) Connect resistor if crystal is not used.
(3) Use of crystal is optional.
(4) Application depends on synthesizer frequency; see Table 57.
(5) See Table 54.
Fig 50. Test circuit of TDA9898
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
93 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
(2)
3.3 kΩ
C
C
TAGC
FREF
100 pF
(1)
(3)
22 kΩ
470 Ω
4 MHz
100 nF
analog
ground
V
P
= 5 V
22 pF
100 nF
i.c.
45
n.c.
n.c.
37
synthesizer
downconverter
(4)
22 pF
n.c.
48
1
47
46
44
43 42 41 40
39
38
loop filter
AGC input for DIF
(from channel decoder)
36
R
LFSYN2
C
LFSYN2
n.c.
C
2
35
34
33
32
31
30
29
28
27
26
25
SIF/DIF
1 : 1
AF2
1
2
5
4
3
1.5 nF
2 V CVBS
51 Ω
51 Ω
51 Ω
4
output
3
n.c.
5
BVS
VIF/SIF/DIF
1 : 1
1
2
5
4
6
AUD
TDA9897
(b)
7
3
ZIF Q or 1st DIF
C
CTAGC
(a)
C
8
100 nF
5
VIF/SIF/DIF
1 : 1
AF1
1
2
9
470 nF
(b)
4
10
11
digital LIF or ZIF I or
analog 2nd sound IF
3
(a)
TOP potentiometer for RSSI
and IF based tuner AGC
22 kΩ
MPP1
+5 V
12
13
14
15
16
17
18
19
20
21 22 23
24
2.7 kΩ only for port
function
MPP2
digital
ground
C
par
C
s
C
de-em
220 nF
ADRSEL
4.7 nF
FM PLL
(5)
R
s
loop filter
330 Ω
100 Ω
100 Ω
008aaa044
SDA
SCL
VIF
loop filter
external
FM input
output to
sound BPF
FM input
from sound BPF
(1) Connect resistor if external reference signal is not used.
(2) Connect resistor if crystal is not used.
(3) Use of crystal is optional.
(4) Application depends on synthesizer frequency; see Table 57.
(5) See Table 54.
Fig 51. Test circuit of TDA9897
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
94 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
15. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT313-2
136E05
MS-026
Fig 52. Package outline SOT313-2 (LQFP48)
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
95 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 x 7 x 0.85 mm
SOT619-1
D
B
A
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
y
1/2 e
e
v
M
M
b
C
C
A
B
C
1
w
13
24
L
25
12
e
e
E
2
h
1/2 e
1
36
terminal 1
index area
48
37
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
7.1
6.9
5.25
4.95
7.1
6.9
5.25
4.95
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
5.5
5.5
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-18
SOT619-1
- - -
MO-220
- - -
Fig 53. Package outline SOT619-1 (HVQFN48)
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
96 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
16. Soldering
16.1 Introduction
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
16.2 Through-hole mount packages
16.2.1 Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
16.2.2 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
16.3 Surface mount packages
16.3.1 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 54) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 58 and 59
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
97 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 58. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
220
< 2.5
235
220
≥ 2.5
220
Table 59. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 54.
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 54. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16.3.2 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
98 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
16.3.3 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
16.4 Package related soldering information
Table 60. Suitability of IC packages for wave, reflow and dipping soldering methods
Mounting
Package[1]
Soldering method
Wave
Reflow[2]
Dipping
Through-hole mount
CPGA, HCPGA
suitable
−
−
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable[3]
−
suitable
Through-hole-surface
mount
PMFP[4]
not suitable
not suitable
−
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
99 of 103
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Multistandard hybrid IF processing
Table 60. Suitability of IC packages for wave, reflow and dipping soldering methods …continued
Mounting
Package[1]
Soldering method
Wave
Reflow[2]
Dipping
Surface mount
BGA, HTSSON..T[5], LBGA,
LFBGA, SQFP, SSOP..T[5], TFBGA,
VFBGA, XSON
not suitable
suitable
−
DHVQFN, HBCC, HBGA, HLQFP, not suitable[6]
HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN,
suitable
−
HVSON, SMS
PLCC[7], SO, SOJ
suitable
suitable
−
−
−
−
LQFP, QFP, TQFP
not recommended[7][8]
not recommended[9]
not suitable
suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L[10], WQCCN..L[10]
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your NXP
Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with
respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of
the moisture in them (the so called popcorn effect).
[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
[4] Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed
through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C
measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate
between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the
heatsink surface.
[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint
must incorporate solder thieves downstream and at the side corners.
[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for
packages with a pitch (e) equal to or smaller than 0.65 mm.
[9] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely
not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil.
However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate
soldering profile can be provided on request.
17. Abbreviations
Table 61. Abbreviations
Acronym
ADC
AFC
AGC
ATV
Description
Analog-to-Digital Converter
Automatic Frequency Control
Automatic Gain Control
Analog TV
BP
Band-Pass
CW
Continuous Wave
Digital-to-Analog Converter
Direct Current
DAC
DC
TDA9897_TDA9898_3
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Product data sheet
Rev. 03 — 11 January 2008
100 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 61. Abbreviations …continued
Acronym
DIF
Description
Digital Intermediate Frequency
Digital Signal Processor
Digital TV
DSP
DTV
DVB
ESD
FPLL
IC
Digital Video Broadcast
ElectroStatic Discharge
Frequency Phase-Locked Loop
Integrated Circuit
IF
Intermediate Frequency
Liquid Crystal Display
LCD
LIF
Low Intermediate Frequency
Module Address
MAD
NICAM
PLL
Near Instantaneous Companded Audio Multiplex
Phase-Locked Loop
POR
QSS
RIF
Power-On Reset
Quasi Split Sound
Radio Intermediate Frequency
Received Signal Strength Indication
Surface Acoustic Wave
Sound Carrier
RSSI
SAW
SC
SIF
Sound Intermediate Frequency
Tuner Automatic Gain Control
TakeOver Point
TAGC
TOP
VCO
VIF
Voltage-Controlled Oscillator
Vision Intermediate Frequency
Vertical Interval Test Signal
Zero Intermediate Frequency
VITS
ZIF
18. Revision history
Table 62. Revision history
Document ID
Release date
20080111
Data sheet status
Change notice
Supersedes
TDA9897_TDA9898_3
Modifications:
Product data sheet
-
TDA9897_TDA9898_2
• Additional specification of features for V2/S1 version
TDA9897_TDA9898_2
TDA9897_TDA9898_1
20070411
Product data sheet
-
TDA9897_TDA9898_1
-
20060922
Product data sheet
-
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
101 of 103
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NXP Semiconductors
Multistandard hybrid IF processing
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
to result in personal injury, death or severe property or environmental
19.2 Definitions
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
TDA9897_TDA9898_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 11 January 2008
102 of 103
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NXP Semiconductors
Multistandard hybrid IF processing
21. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
16.2
Through-hole mount packages . . . . . . . . . . . 97
Soldering by dipping or by solder wave . . . . . 97
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 97
Surface mount packages . . . . . . . . . . . . . . . . 97
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 97
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 98
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 99
Package related soldering information. . . . . . 99
16.2.1
16.2.2
16.3
16.3.1
16.3.2
16.3.3
16.4
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Analog TV processing. . . . . . . . . . . . . . . . . . . . 1
Digital TV processing . . . . . . . . . . . . . . . . . . . . 2
Dual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
FM radio mode . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
2.2
2.3
2.4
2.5
3
4
5
6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8
17
18
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 100
Revision history . . . . . . . . . . . . . . . . . . . . . . 101
19
Legal information . . . . . . . . . . . . . . . . . . . . . 102
Data sheet status . . . . . . . . . . . . . . . . . . . . . 102
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 102
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 102
19.1
19.2
19.3
19.4
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . 12
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 13
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.4
8.5
8.6
Functional description . . . . . . . . . . . . . . . . . . 14
IF input switch. . . . . . . . . . . . . . . . . . . . . . . . . 14
VIF demodulator . . . . . . . . . . . . . . . . . . . . . . . 15
VIF AGC and tuner AGC. . . . . . . . . . . . . . . . . 15
Mode selection of VIF AGC . . . . . . . . . . . . . . 15
VIF AGC monitor . . . . . . . . . . . . . . . . . . . . . . 15
Tuner AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DIF/SIF FM and AM sound AGC . . . . . . . . . . 16
Frequency phase-locked loop for VIF . . . . . . . 16
DIF/SIF converter stage . . . . . . . . . . . . . . . . . 16
Mono sound demodulator. . . . . . . . . . . . . . . . 17
Narrow-band FM PLL demodulation. . . . . . . . 17
AM sound demodulation. . . . . . . . . . . . . . . . . 17
Audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . 17
Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I2C-bus transceiver and slave address . . . . . . 18
20
21
Contact information . . . . . . . . . . . . . . . . . . . 102
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.7
8.7.1
8.7.2
8.8
8.9
8.10
9
9.1
9.2
9.2.1
9.2.2
I2C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Description of data bytes . . . . . . . . . . . . . . . . 24
10
11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 37
Thermal characteristics. . . . . . . . . . . . . . . . . . 37
12
12.1
12.2
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 38
Analog TV signal processing . . . . . . . . . . . . . 38
Digital TV signal processing . . . . . . . . . . . . . . 76
13
Application information. . . . . . . . . . . . . . . . . . 90
Test information. . . . . . . . . . . . . . . . . . . . . . . . 93
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 95
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14
15
16
16.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 January 2008
Document identifier: TDA9897_TDA9898_3
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