TDA9962 [NXP]
12-bit, 3.0 V, 20 Msps analog-to-digital interface for CCD cameras; 12位， 3.0V， 20 Msps的模拟 - 数字为CCD相机接口
| 型号： | TDA9962 |
| 厂家： | 
NXP |
| 描述： | 12-bit, 3.0 V, 20 Msps analog-to-digital interface for CCD cameras |
| 文件： | 总24页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA9962
12-bit, 3.0 V, 20 Msps
analog-to-digital interface for CCD
cameras
Objective specification
2000 May 01
File under Integrated Circuits, IC02
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
FEATURES
APPLICATIONS
• Low-power, low-voltage CCD camera systems.
• Correlated Double Sampling (CDS), Programmable
Gain Amplifier (PGA), 12-bit Analog-to-Digital Converter
(ADC) and reference regulator included
GENERAL DESCRIPTION
• Fully programmable via a 3-wire serial interface
• Sampling frequency up to 20 MHz
The TDA9962 is a 12-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, PGA, clamp loops and a low-power 12-bit
ADC together with its reference voltage regulator.
• PGA gain range of 24 dB (in steps of 0.1 dB)
• Low power consumption of only 140 mW at 2.7 V
• Power consumption in standby mode of 4.5 mW (typ.)
The PGA gain and the ADC input clamp level are
controlled via the serial interface.
• 3.0 V operation and 2.2 to 3.6 V operation for the digital
outputs
An additional DAC is provided for additional system
controls; its output voltage range is 1.0 V (p-p) which is
available at pin OFDOUT.
• All digital inputs accept 5 V signals
• Active control pulses polarity selectable via serial
interface
• 8-bit DAC included for analog settings
• TTL compatible inputs, CMOS compatible outputs.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA9962HL
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
2000 May 01
2
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
CONDITIONS
MIN.
2.7
TYP. MAX. UNIT
analog supply voltage
digital supply voltage
digital outputs supply voltage
analog supply current
digital supply current
3.0
3.0
2.5
49
2
3.6
3.6
3.6
−
V
VCCD
VCCO
ICCA
2.7
2.2
−
V
V
all clamps active
mA
mA
mA
ICCD
ICCO
−
−
digital outputs supply current fpix = 20 MHz; CL = 20 pF; input
−
1
−
ramp response time is 800 µs
ADCres
ADC resolution
−
12
−
−
−
−
−
−
−
−
bits
mV
Vi(CDS)(p-p)
maximum CDS input voltage VCC = 2.85 V
(peak-to-peak value)
650
800
20
tbf
−
VCC ≥ 3.0 V
−
mV
fpix(max)
fpix(min)
DRPGA
Ntot(rms)
maximum pixel rate
minimum pixel rate
PGA dynamic range
−
MHz
MHz
dB
−
24
1.2
total noise from CDS input to PGA gain = 0 dB; see Fig.8
ADC output
−
LSB
Ein(rms)
Ptot
equivalent input noise
(RMS value)
gain = 24 dB
−
95
−
µV
total power consumption
VCCA = VCCD = VCCO = 3 V
−
−
155
140
−
−
mW
mW
VCCA = VCCD = VCCO = 2.7 V
2000 May 01
3
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BLK
CLK
OE
V
V
SHP
SHD
AGND1
2
AGND6 CLPOB CLPDM
CCA1
1
CCA4
41
45
46
40
44
48
43
47
39
22
21
DGND1
V
CCD1
CDS CLOCK GENERATOR
37
OGND2
38
36
35
34
33
32
31
30
29
28
V
CCO2
8
9
CPCDS1
CPCDS2
D11
D10
CLAMP
D9
D8
D7
D6
D5
D4
D3
D2
7
3
4
V
CCA2
AGND2
IN
PGA
CORRELATED
DOUBLE
SAMPLING
BLACK
LEVEL
SHIFT
DATA
FLIP-
FLOP
OUTPUT
BUFFER
SHIFT
BLANKING
12-bit ADC
CLAMP
27
26
25
D1
D0
V
14
5
ref
V
CCA3
8-BIT
REGISTER
7-BIT
TDA9962
24
23
REGISTER
OGND1
AGND3
OFD DAC
V
CCO1
11
OFDOUT
10
SERIAL
INTERFACE
8-BIT
REGISTER
REGULATOR
DCLPC
13
16
18
17
20
42
12
6
15
19
FCE504
OPGA
OPGAC
SCLK
VSYNC
TEST
SEN
SDATA
STDBY
AGND5
AGND4
ahdnbok,uflapegwidt
Fig.1 Block diagram.
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
PINNING
SYMBOL
VCCA1
PIN
DESCRIPTION
1
analog supply voltage 1
analog ground 1
AGND1
AGND2
IN
2
3
analog ground 2
4
input signal from CCD
analog ground 3
AGND3
AGND4
VCCA2
CPCDS1
CPCDS2
DCLPC
OFDOUT
TEST
AGND5
VCCA3
OPGA
OPGAC
SDATA
SCLK
SEN
5
6
analog ground 4
7
analog supply voltage 2
clamp storage capacitor pin 1
clamp storage capacitor pin 2
regulator decoupling pin
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
analog output of the additional 8-bit control DAC
test mode input pin (should be connected to AGND5)
analog ground 5
analog supply voltage 3
PGA output (test pin)
PGA complementary output (test pin)
serial data input for serial interface control
serial clock input for serial interface
strobe pin for serial interface
vertical sync pulse input
digital supply voltage 1
VSYNC
VCCD1
DGND1
VCCO1
OGND1
D0
digital ground 1
digital outputs supply voltage 1
digital output ground 1
ADC digital output 0 (LSB)
ADC digital output 1
D1
D2
ADC digital output 2
D3
ADC digital output 3
D4
ADC digital output 4
D5
ADC digital output 5
D6
ADC digital output 6
D7
ADC digital output 7
D8
ADC digital output 8
D9
ADC digital output 9
D10
ADC digital output 10
D11
ADC digital output 11 (MSB)
digital output ground 2
OGND2
VCCO2
OE
digital outputs supply voltage 2
output enable control input (LOW = outputs active; HIGH = outputs in high-impedance)
analog ground 6
AGND6
2000 May 01
5
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
SYMBOL
VCCA4
PIN
DESCRIPTION
41
42
43
44
45
46
47
48
analog supply voltage 4
STDBY
BLK
standby mode control input (LOW = TDA9962 active; HIGH = TDA9962 standby)
blanking control input
CLPOB
SHP
clamp pulse input at optical black
preset sample-and-hold pulse input
data sample-and-hold pulse input
data clock input
SHD
CLK
CLPDM
clamp pulse input at dummy pixel
V
D11
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
CCA1
AGND1
AGND2
IN
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AGND3
AGND4
TDA9962HL
V
CCA2
CPCDS1
CPCDS2
DCPLC 10
OFD 11
TEST 12
FCE505
Fig.2 Pin configuration.
2000 May 01
6
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN. MAX. UNIT
note 1
note 1
note 1
−0.3
−0.3
−0.3
+7.0
+7.0
+7.0
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
digital outputs supply voltage
supply voltage difference
between VCCA and VCCD
between VCCA and VCCO
between VCCD and VCCO
input voltage
−0.5
−0.5
−0.5
−0.3
−
+0.5
+1.2
+1.2
+7.0
±10
V
V
V
Vi
referenced to AGND
V
Io
data output current
mA
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−55
−20
−
+150 °C
+75 °C
+150 °C
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply
voltage difference ∆VCC remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
thermal resistance from junction to ambient
76
K/W
2000 May 01
7
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
CHARACTERISTICS
VCCA = VCCD = 3.0 V; VCCO = 2.5 V; fpix = 20 MHz; Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
VCCD
VCCO
analog supply voltage
digital supply voltage
2.7
2.7
2.2
3.0
3.0
2.5
3.6
3.6
3.6
V
V
V
digital outputs supply
voltage
ICCA
ICCD
ICCO
analog supply current
digital supply current
all clamps active
−
−
−
49
2
−
−
−
mA
mA
mA
digital outputs supply
current
CL = 20 pF on all data
outputs; input ramp
1
response time is 800 µs
Digital inputs
PINS SHP, SHD AND CLK (REFERENCED TO DGND)
VIL
VIH
Ii
LOW-level input voltage
HIGH-level input voltage
input current
0
−
0.6
5.5
+3
−
V
2.2
−3
−
−
V
0 ≤ Vi ≤ 5.5 V
fCLK = 20 MHz
fCLK = 20 MHz
−
µA
kΩ
pF
Zi
input impedance
50
−
Ci
input capacitance
−
2
PINS CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK AND VSYNC
VIL
VIH
Ii
LOW-level input voltage
HIGH-level input voltage
input current
0
−
−
−
0.6
5.5
+2
V
2.2
−2
V
0 ≤ Vi ≤ 5.5 V
µA
Clamps
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp)
clamp active pulse width
in number of pixels
PGA code = 255 for
maximum 4 LSB error
12
−
−
−
pixels
mS
INPUT CLAMP (DRIVEN BY CLPDM)
gm(CDS)
CDS input clamp
transconductance
−
20
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
maximum peak-to-peak
CDS input amplitude
(video signal)
VCC = 2.85 V
650
800
−
−
−
−
mV
mV
VCC ≥ 3.0 V
Vreset(max)
maximum CDS input reset
pulse amplitude
500
−
−
mV
Ii(IN)
input current into pin IN
input capacitance
at floating gate level
tbf
−
−
tbf
−
µA
pF
ns
Ci
2
tCDS(min)
CDS control pulses
minimum active time
Vi(CDS)(p-p) = 800 mV
black-to-white transition in
1 pixel with 99% Vi recovery
11
15
−
2000 May 01
8
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ns
th(IN;SHP)
CDS input hold time
(pin IN) compared to
control pulse SHP
VCCA = VCCD = 3.0 V;
Tamb = 25 °C;
see Figs 3 and 4
−
−
1
1
2
th(IN;SHD)
CDS input hold time
(pin IN) compared to
control pulse SHD
VCCA = VCCD = 3.0 V;
Tamb = 25 °C;
see Figs 3 and 4
2
ns
Amplifier
DRPGA
PGA dynamic range
PGA gain step
−
24
−
dB
dB
∆GPGA
0.08
0.10
0.12
Analog-to-Digital Converter (ADC)
DNL differential non linearity
Total chain characteristics (CDS + PGA + ADC)
fpix = 20 MHz; ramp input
−
±0.5
±0.9
LSB
fpix(max)
fpix(min)
tCLKH
maximum pixel frequency
minimum pixel frequency
CLK pulse width HIGH
CLK pulse width LOW
20
tbf
15
15
10
−
−
−
−
−
−
−
−
−
−
MHz
MHz
ns
tCLKL
ns
td(SHD;CLK)
time delay between
SHD and CLK
see Figs 3 and 4
see Figs 3 and 4
ns
tsu(BLK;SHD)
Vi(IN)(FS)
set-up time of BLK
compared to SHD
5
−
−
ns
video input dynamic signal PGA code = 00
for ADC full-scale output
800
50
−
−
−
−
mV
mV
PGA code = 255
Ntot(rms)
total noise from CDS input see Fig.8
to ADC output
(RMS value)
PGA gain = 0 dB
−
1.2
2.0
95
−
−
−
−
LSB
LSB
µV
PGA gain = 9 dB
−
Ein(rms)
equivalent input noise
voltage (RMS value)
PGA gain = 24 dB
PGA gain = 9 dB
−
−
135
−
µV
OCCD(max)
maximum offset between
CCD floating level and
CCD dark pixel level
−100
+100 mV
Digital-to-analog converter (OFDOUT DAC)
VOFDOUT(p-p) additional 8-bit control
DAC (OFD) output voltage
(peak-to-peak value)
Ri = 1 MΩ
−
1.0
−
V
VOFDOUT(0)
DC output voltage for
code 0
−
−
−
AGND
−
−
−
V
VOFDOUT(255) DC output voltage for
code 255
AGND + 1.0
250
V
TCDAC
DAC output range
ppm/°C
temperature coefficient
ZOFDOUT
IOFDOUT
DAC output impedance
−
−
2000
−
Ω
OFD output current drive static
−
100
µA
2000 May 01
9
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital outputs (fpix = 20 MHz; CL = 10 pF); see Figs 3 and 4
VOH
VOL
IOZ
HIGH-level output voltage IOH = −1 mA
V
CCO − 0.5
−
−
−
VCCO
0.5
V
LOW-level output voltage IOL = 1 mA
0
V
output current in 3-state
mode
0.5 V < Vo < VCCO
−20
+20
µA
th(o)
td(o)
output hold time
output delay time
5
−
−
−
−
−
−
ns
ns
ns
ns
pF
CL = 10 pF; VCCO = 3.0 V
CL = 10 pF; VCCO = 2.7 V
CL = 10 pF; VCCO = 2.2 V
16
18
tbf
−
tbf
tbf
tbf
20
CL
output load capacitance
Serial interface
fSCLK(max)
maximum frequency of
serial clock interface
10
−
−
MHz
2000 May 01
10
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IN
N + 1
N + 2
N + 3
N + 4
N + 5
N
t
CDS(min)
2.2 V
SHP
SHD
0.6 V
t
h(IN;SHP)
t
CDS(min)
2.2 V
2.2 V
0.6 V
0.6 V
t
h(IN;SHD)
t
CLKH
2.2 V
0.6 V
2.2 V
CLK
0.6 V
t
d(SHD;CLK)
ADC CLAMP
CODE
50%
N
DATA
N − 4
N − 3
N − 2
N − 1
t
h(o)
t
d(o)
2.2 V
BLK
FCE506
t
su(BLK;SHD)
ahdnbok,uflapegwidt
Fig.3 Pixel frequency timing diagram; all polarities active HIGH.
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IN
N
N + 1
N + 2
N + 3
N + 4
N + 5
2.2 V
SHP
SHD
0.6 V
t
CDS(min)
2.2 V
t
h(IN;SHP)
2.2 V
0.6 V
0.6 V
t
t
h(IN;SHD)
CDS(min)
2.2 V
2.2 V
0.6 V
CLK
DATA
BLK
0.6 V
CLKL
t
t
d(SHD;CLK)
ADC CLAMP
CODE
50%
N − 4
N − 3
N − 2
N − 1
N
t
h(o)
t
d(o)
0.6 V
FCE507
t
su(BLK;SHD)
ahdnbok,uflapegwidt
Fig.4 Pixel frequency timing diagram; all polarities active LOW.
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
FCE508
1.0
OFDOUT DAC
voltage
output
(V)
0
0
255
OFDOUT control DAC input code
Fig.5 DAC voltage output as a function of DAC input code.
CLPOB
CLPDM
WINDOW
WINDOW
AGCOUT
VIDEO
OPTICAL BLACK
HORIZONTAL FLYBACK
DUMMY
VIDEO
CLPOB
(active HIGH)
CLPDM
(active HIGH)
BLK
(active HIGH)
BLK window
FCE509
Fig.6 Line frequency timing diagram.
13
2000 May 01
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
FCE510
30
handbook, halfpage
TOTAL
gain
(dB)
24
25.9
18
12
6
1.9
0
0
64
128
192
255
PGA input code
Fig.7 Total gain from CDS input to ADC input as a function of PGA input code.
FCE511
8
handbook, halfpage
N
tot(rms)
(LSB)
7
6
5
4
3
2
1
0
0
64
128
192
256
PGA code
Noise measurement at ADC outputs: Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works
at 20 Mpixels with line of 1024 pixels whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during
the other pixels. As a result of this, the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into
account.
Fig.8 Typical total noise performance as a function of PGA gain.
2000 May 01
14
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
SDATA
SHIFT REGISTER
A0
SD0 SD1 SD2 SD3 SD4
A1
A2
A3
SD5 SD6 SD7 SD8 SD9 SD10 SD11
MSB
SCLK
SEN
LSB
12
LATCH
SELECTION
8
10
5
9
CONTROL PULSE
PGA GAIN
LATCHES
ADC CLAMP
LATCHES
OFDOUT DAC
LATCHES
POLARITY
LATCHES
SCLK
VSYNC
FLIP-FLOP
8-bit DAC
FLIP-FLOP
PGA control
FLIP-FLOP
FCE512
ADC clamp
control
control pulses
polarity settings
Fig.9 Serial interface block diagram.
t
su2
SDATA
t
hd4
MSB
LSB
A3
A2
A1
A0
SD10
SD11 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
SCLK
SEN
t
t
su1
su3
t
hd3
FCE513
tsu1 = tsu2 = tsu3 = 10 ns (min.); thd3 = thd4 = 10 ns (min.).
Fig.10 Loading sequence of control input data via the serial interface.
15
2000 May 01
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
Table 1 Serial interface programming
ADDRESS BITS
DATA BITS SD11 TO SD0
PGA gain control (SD7 to SD0)
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
DAC OFDOUT output control (SD7 to SD0)
ADC clamp reference control (SD6 to SD0); from code 0 to 127
control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK) polarity settings; SD2,
SD6, SD7 and SD9 should be set to logic 1; for SD6 and SD7 see Tables 3, 4, 5 and 6
0
1
1
1
0
1
0
1
SD7 = 0 by default; SD7 = 1 PGA gain up to 36 dB but noise and clamp behaviour are
not guaranteed
initialization (SD8 = 1; SD11 to SD9 = 0 and SD7 to SD0 = 0)
test modes
other addresses
Table 2 Polarity settings
SYMBOL
SHP and SHD
CLK
PIN
SERIAL CONTROL BIT
ACTIVE EDGE OR LEVEL
1 = HIGH; 0 = LOW
1 = rising; 0 = falling
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
0 = rising; 1 = falling
45 and 46
SD4
SD5
SD0
SD1
SD3
SD8
47
48
44
43
20
CLPDM
CLPOB
BLK
VSYNC
Table 3 Standby control using pin STDBY
BIT SD7 OF REGISTER
STDBY
0011
ADC DIGITAL OUTPUTS SD11 TO SD0
ICCA + ICCO + ICCD (typ.)
1
0
1
0
1
0
last logic state
active
1.5 mA
51 mA
51 mA
1.5 mA
active
test logic state
2000 May 01
16
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
Table 4 Output enable selection using output enable pin (OE)
BIT SD6 OF REGISTER 0011
OE
ADC DIGITAL OUTPUTS SD9 TO SD0
1
0
1
0
1
active, binary
high-impedance
high-impedance
active binary
0
Table 5 Standby control by serial interface (register address A3 = 0, A2 = 0, A1 = 1, A0 = 1);
pin STDBY connected to ground
SD7
ADC DIGITAL OUTPUTS SD9 TO SD0
ICCA + ICCO + ICCD (typ.)
0
1
last logic state
active
1.5 mA
72 mA
Table 6 Output enable control by serial interface (register address A3 = 0, A2 = 0, A1 = 1, A0 = 1);
output enable pin (OE) connected to ground
SD6
ADC DIGITAL OUTPUTS SD9 TO SD0
0
1
high-impedance
active binary
2000 May 01
17
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
APPLICATION INFORMATION
V
V
n
CCD
CCD
V
V
CCO
CCA
100 nF
100 nF
(2) (2)
(2)
CCD
1 µF
48 47 46 45 44 43 42 41 40 39 38 37
V
CCA1
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
V
1
2
3
4
5
6
36
35
34
33
32
31
30
29
28
27
26
25
CCA
AGND1
AGND2
IN
AGND3
AGND4
V
TDA9962
CCA2
V
7
CCA
CPCDS1
CPCDS2
DCPLC
OFD
100 nF
1 µF
8
9
1 µF
10
11
12
1 µF
TEST
13 14 15 16 17 18 19 20 21 22 23 24
100 nF
100 nF
100 nF
V
(1)
serial
interface
V
V
FCE514
CCD
CCA
CCO
(1) Pins SEN and VSYNC should be interconnected when vertical sync signal is not available.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN;SHP) and th(IN;SHD) (see Chapter “Characteristics”).
Fig.11 Application diagram.
2000 May 01
18
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
Power and grounding recommendations
In a two-ground system, in order to minimize the noise
through package and die parasitics, the following
recommendation must be implemented.
When designing a printed-circuit board for applications
such as PC cameras, surveillance cameras, camcorders
and digital still cameras, care should be taken to minimize
the noise.
All the analog and digital supply pins must be decoupled to
the analog ground plane. Only the ground pin associated
with the digital outputs must be connected to the digital
ground plane. All the other ground pins should be
connected to the analog ground plane. The analog and
digital ground planes must be connected together at one
point as close as possible to the ground pin associated
with the digital outputs.
For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of analog
components (such as classical operational amplifiers)
must be respected, particularly with respect to power and
ground connections.
The following additional recommendation is given for the
CDS input pin(s) which is/are internally connected to the
programmable gain amplifier.
The digital output pins and their associated lines should be
shielded by the digital ground plane which can then be
used as a return path for digital signals.
The connections between the CCD interface and the CDS
input should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analog and digital supplies provide the best
solution. If it is not possible to do this on the board then the
analog supply pins must be decoupled effectively from the
digital supply pins. If the same power supply and ground
are used for all the pins then the decoupling capacitors
must be placed as close as possible to the IC package.
2000 May 01
19
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-12-27
00-01-19
SOT313-2
136E05
MS-026
2000 May 01
20
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2000 May 01
21
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 May 01
22
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
STATUS
DEFINITIONS (1)
Objective specification
Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 May 01
23
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
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220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
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Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
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Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
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Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
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Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
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Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp24
Date of release: 2000 May 01
Document order number: 9397 750 06915
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