TDA9965AHL/C3,118 [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, SOT-313-2, MS-026, PLASTIC, LQFP-48, Consumer IC:Other;
| 型号： | TDA9965AHL/C3,118 |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, SOT-313-2, MS-026, PLASTIC, LQFP-48, Consumer IC:Other 商用集成电路 |
| 文件： | 总22页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA9965A
12-bit, 5.0 V, 40 Msps
analog-to-digital interface for CCD
cameras
Product specification
2004 Jul 05
Supersedes data of 2003 Nov 26
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
FEATURES
• TTL compatible inputs; TTL and CMOS compatible
outputs.
• Clamp and Track/Hold (CTH) circuit with adjustable
bandwidth, Programmable Gain Amplifier (PGA), 12-bit
Analog-to-Digital Converter (ADC) and reference
regulator
APPLICATIONS
• CCD camera systems.
• Fully programmable via a 3-wire serial interface
• Sampling frequency up to 40 MHz
GENERAL DESCRIPTION
• PGA gain from 0 to 36 dB (in 0.05 dB steps)
The TDA9965A is a 12-bit analog-to-digital interface for a
CCD camera. The device includes a CTH circuit, PGA and
a low-power 12-bit ADC, together with its reference
voltage regulator.
• CTH programmable bandwidth from 35 to 284 MHz
typical
• Standby mode (20 mW typical)
• Low power consumption of only 425 mW typical
The CTH has a bandwidth circuit controlled by on-chip
DACs via a serial interface.
• 5 V operation and 3 to 5.25 V operation for the digital
outputs
A 10-bit digital clamp controls the ADC input clamp level.
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
analog supply voltage
digital supply voltage
CONDITIONS
MIN.
4.75
4.75
3.0
−
TYP. MAX. UNIT
5.0
5.0
3.3
65
19
1
5.25
5.25
5.25
−
V
VCCD
VCCO
ICCA
V
digital output supply voltage
analog supply current
digital supply current
V
with internal regulator
with internal regulator
mA
mA
mA
ICCD
ICCO
−
−
digital output supply current
fpix = 40 MHz; CL = 10 pF on all
data outputs; ramp input
−
−
ADCres
ADC resolution
−
−
12
2
−
−
bits
V
Vi(IN)(p-p)
CTH input voltage
(peak-to-peak value)
GCTH
CTH output amplifier gain
PGA dynamic range
−
0
−
−
−
−
dB
PGAdyn
fpix(max)
Ntot(rms)
−
36
−
dB
maximum pixel frequency
code fco(CTH) = 0000
40
−
MHz
LSB
total noise from CTH input to
ADC output (RMS value)
GPGA = 0 dB;
code fco(CTH) = 0000
0.85
Vn(i)(eq)(rms)
equivalent input noise
(RMS value)
GPGA = 30 dB;
code fco(CTH) = 0000; note 1
−
−
90
−
−
µV
Ptot
total power consumption
425
mW
Note
1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB.
ORDERING INFORMATION
PACKAGE
DESCRIPTION
TYPE
NUMBER
NAME
VERSION
TDA9965AHL
2004 Jul 05
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
2
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
BLOCK DIAGRAM
V
V
CLKADC
DGND1
CCD1
STDBY
CCD2
47
DGND2
CLPADC
43
D10
37
D11
38
SHD
46
SHP
45
CLPOB
44
41
48
42
40
39
1
2
CLAMP
AGND4
IN
CLAMP
36
CLOCK
TRACK AND HOLD
D9
35
3
4
D8
AGND5
STGE
34
D7
5
6
10
AGND1
33
D6
4-BIT DAC
V
CCA1
32
V
TDA9965A
CCO2
7
8
12
OUTPUT
BUFFER
AGND2
12-BIT ADC
31
OGND2
V
CCA2
30
9
V
ref
V
CCO1
29
10
OGND1
PGA
PGAOUT
REF = 3.2 V
28
D5
10-BIT DAC
27
D4
11
12
ADCIN
n.c.
26
D3
25
INIT-ON-
POWER
SERIAL
INTERFACE
D2
REGULATOR
24
D1
23
D0
16
13
14 15
17
18
19
20
SEN
21
22
MGU713
V
V
DEC
SDATA
CCA3
RB
REGEN
V
SCLK
AGND3
REF32
RT
Fig.1 Block diagram.
2004 Jul 05
3
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
PINNING
SYMBOL
PIN
DESCRIPTION
AGND4
IN
1
2
analog ground 4
data input signal from CCD
analog ground 5
AGND5
STGE
AGND1
VCCA1
AGND2
VCCA2
Vref
3
4
clamp storage capacitor pin
analog ground 1
5
6
analog supply voltage 1
analog ground 2
7
8
analog supply voltage 2
9
ADC clamp reference voltage input; short-circuited to ground via a capacitor
PGA amplifier signal output
PGAOUT
ADCIN
n.c.
10
11
12
13
14
15
16
17
18
19
20
21
22
ADC analog signal input; externally connected to pin PGAOUT
not connected
REGEN
VRB
regulator enable input (active HIGH)
regulator reference voltage bottom
VRT
regulator reference voltage top
DEC
regulator decoupling; decoupled to ground via a capacitor
internal reference voltage; decoupled to ground via a capacitor
analog supply voltage 3
REF32
VCCA3
AGND3
SEN
analog ground 3
enable input for the serial interface shift register (active LOW)
serial clock input for the serial interface
SCLK
SDATA
serial data input: 10-bit PGA gain, 4-bit DAC for the frequency cut-off, 10 low significant bits for
the digital ADC clamp and edge pulse control
D0
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
ADC digital output 0 (LSB)
ADC digital output 1
D1
D2
ADC digital output 2
D3
ADC digital output 3
D4
ADC digital output 4
D5
ADC digital output 5
OGND1
VCCO1
OGND2
VCCO2
D6
digital output ground 1
digital output supply voltage 1
digital output ground 2
digital output supply voltage 2
ADC digital output 6
D7
ADC digital output 7
D8
ADC digital output 8
D9
ADC digital output 9
D10
D11
STDBY
ADC digital output 10
ADC digital output 11 (MSB)
standby control input (active HIGH); all output bits are logic 0 when standby is enabled
2004 Jul 05
4
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
SYMBOL
PIN
DESCRIPTION
VCCD1
40
41
42
43
44
45
46
47
48
digital supply voltage 1
digital ground 1
DGND1
CLKADC
CLPADC
CLPOB
SHP
ADC clock input
clamp control pulse input for ADC analog input signal
clamp control pulse input at optical black
preset sample and hold pulse input
data sample and hold pulse input
digital supply voltage 2
SHD
VCCD2
DGND2
digital ground 2
AGND4
1
2
3
4
5
6
7
8
9
36 D9
35 D8
34 D7
33 D6
IN
AGND5
STGE
AGND1
32
V
CCO2
V
31 OGND2
CCA1
TDA9965AHL
AGND2
30
V
CCO1
V
29 OGND1
28 D5
CCA2
V
ref
PGAOUT 10
ADCIN 11
27 D4
26 D3
12
25 D2
n.c.
MGU715
Fig.2 Pin configuration.
5
2004 Jul 05
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
note 1
MIN.
−0.3
MAX.
+7.0
UNIT
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
digital output supply voltage
supply voltage difference
between VCCA and VCCD
between VCCD and VCCO
input voltage
note 1
note 1
−0.3
−0.3
+7.0
+7.0
−1.0
−1.0
−0.3
−10
−55
−20
−
+1.0
+4.0
+7.0
+10
V
V
V
Vi
referenced to AGND
Io
output current
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
+150
+75
150
Note
1. All supplies are connected together.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
76
K/W
2004 Jul 05
6
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
CHARACTERISTICS
VCCA = VCCD = 5 V; VCCO = 3.0 V; fpix = 40 MHz; Tamb = −20 to +75 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
VCCD
VCCO
analog supply voltage
digital supply voltage
4.75
5.0
5.0
3.3
5.25
V
V
V
4.75
3.0
5.25
5.25
digital output supply
voltage
ICCA
ICCD
ICCO
analog supply current
digital supply current
with internal regulator
with internal regulator
−
−
−
65
19
1
−
−
−
mA
mA
mA
digital output supply
current
fpix = 40 MHz; CL = 10 pF
on all data outputs; ramp
input
Digital inputs
CLOCK INPUT: PIN CLKADC (REFERENCED TO DGND)
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input impedance
0
−
0.8
VCCD
+1
20
−
V
2.0
−1
−
−
V
VCLKADC = 0.8 V
VCLKADC = 2.0 V
−
µA
µA
kΩ
pF
IIH
Zi
−
−
63
1
Ci
input capacitance
−
−
CONTROL INPUTS: PINS SEN, SCLK, SDATA, STDBY, CLPOB, CLPADC AND REGEN
VIL
VIH
Ii
LOW-level input voltage
HIGH-level input voltage
input current
0
−
−
−
0.8
V
2.0
−2
VCCD
+2
V
µA
SAMPLE AND HOLD INPUTS: PINS SHP AND SHD
VIL
VIH
Ii
LOW-level input voltage
HIGH-level input voltage
input current
0
−
−
−
0.8
V
2.0
−10
VCCD
+10
V
µA
Clamp and Track/Hold (CTH) circuit: pins IN, SHD and SHP
Vi(IN)(p-p)
CTH input voltage
−
2
−
V
(peak-to-peak value)
Ii(IN)
input current
−3
−
−
+3
µA
tW(SHP)
SHP pulse width
Vi(IN) = 1000 mV;
transition (98.5%) in 1 pixel;
code fco(CTH) = 0000;
see Fig.5
8
−
ns
2004 Jul 05
7
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
SYMBOL
tW(SHD)
PARAMETER
SHD pulse width
CONDITIONS
Vi(IN) = 1000 mV;
MIN.
TYP.
MAX.
UNIT
8
−
−
ns
transition (98.5%) in 1 pixel;
code fco(CTH) = 0000;
see Fig.5
code fco(CTH)
0000
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
0001
12
16
22
32
49
3
0010
0100
1000
1111
th(IN-SHP)
CTH input hold time
compared to control pulse
SHP
see Fig.5
th(IN-SHD)
CTH input hold time
compared to control pulse
SHD
see Fig.5
−
−
3
−
−
ns
Programmable Gain Amplifier (PGA) output: pin PGAOUT
VPGAOUT(p-p) PGA output amplifier
dynamic voltage level
2000
mV
(peak-to-peak value)
VPGAOUT(b)
ZPGAOUT
PGA output amplifier black code C(CLP) = 0
level voltage
−
−
1.475
5
−
−
V
PGA output amplifier
output impedance
fpix at 10 kHz for minimum
and maximum values
Ω
IPGAOUT
PGA output current drive
static
−
−
−
1
mA
dB
GPGA(min)
minimum gain of PGA
circuit
code GPGA = 0
0
−
GPGA(max)
maximum gain of PGA
circuit
code GPGA ≥767
−
36
−
dB
Analog-to-Digital Converter (ADC)
fpix(max)
maximum pixel frequency
40
11
−
−
−
−
MHz
ns
tW(CLKADC)H
CLKADC pulse width
HIGH
Vi(IN) = 1000 mV;
transition (99.5%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128; see Fig.5
tW(CLKADC)L
CLKADC pulse width
LOW
Vi(IN) = 1000 mV;
11
−
−
ns
transition (99.5%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128
SRCLKADC
CLKADC input slew rate
rising and falling edges;
10% to 90%
0.5
−
−
−
V/ns
V
Vi(ADCIN)(p-p)
ADC input voltage
with internal regulator
−
2
(peak-to-peak value)
2004 Jul 05
8
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
SYMBOL
Ii(ADCIN)
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
+120
UNIT
ADC input current
−2
−
µA
VRB
ADC reference voltage
bottom
−
1.30
−
V
VRT
DNL
td(s)
ADC reference voltage top
differential non-linearity
sampling delay
−
−
−
3.65
±0.5
−
−
V
ramp input; fpix = 30 MHz
see Fig.5
±0.9
5
LSB
ns
Total chain characteristics (CTH + PGA + ADC)
td(SHD-CLKADC) delay between
SHD and CLKADC
Vi(IN) = 1000 mV;
transition (95%) in 1 pixel;
code fco(CTH) = 0000;
−
−
15
0
−
−
ns
ns
code GPGA = 128; see Fig.5
th(SHD-CLKADC) SHD hold time compared Vi(IN) = 32 mV;
to CLKADC transition (95%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128; see Fig.5
Ntot(rms)
total noise from CTH input GPGA = 0 dB;
−
−
0.85
6
−
LSB
LSB
mV
to ADC output
(RMS value)
code fco(CTH) = 0000
GPGA = 30 dB;
−
code fco(CTH) = 0000; note 1
OCCD(max)
maximum offset voltage
between CCD floating
level and CCD dark pixel
level
see Fig.11
−200
−
+200
Vn(i)(eq)(rms)
equivalent input noise
(RMS value)
GPGA = 30 dB;
code fco(CTH) = 0000; note 1
−
90
−
µV
Digital outputs (fpix = 40 MHz; CL = 10 pF)
VOH
VOL
th(o)
td(o)
HIGH-level output voltage IOH = −1 mA
LOW-level output voltage IOL = 1 mA
V
CCO − 0.5 −
VCCO
0.5
−
V
0
−
V
output hold time
output delay
see Fig.5
10
−
−
ns
ns
ns
VCCO = 5.25 V
VCCO = 3 V
20
26
25
−
31
Serial interface
fSCLK(max)
maximum clock frequency
of serial interface
5
−
−
MHz
Note
1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB.
2004 Jul 05
9
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
SDATA
SHIFT REGISTER
SD5 SD6 SD7 SD8
A0 A1
LATCH
SD0 SD1
LSB
SD3 SD4
SD9
SD2
SCLK
SEN
MSB
10
SELECTION
(SD0 to SD9)
(SD0 to SD3)
(SD0 to SD2)
(SD0 to SD9)
EDGE
CONTROL
LATCHES
CLAMP
ADC
LATCHES
FREQUENCY
LATCHES
PGA GAIN
LATCHES
edge control
clocks
PGA control
frequency
control CTH
10-bit LSB
ADC clamp
FCE709
Fig.3 Serial interface block diagram.
t
su2
t
h1
MSB
LSB
SDATA
A1
A0
SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
SCLK
SEN
t
t
su1
h2
t
su3
MGU158
tsu1 = tsu2 = tsu3 = 4 ns (minimum);
th1 = th2 = 4 ns (minimum).
Fig.4 Loading sequence of control DACs input data via the serial interface.
10
2004 Jul 05
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
Table 1 Serial interface programming
ADDRESS BITS
SDATA BITS SD0 to SD9
A1
A0
0
0
1
1
0
1
0
1
clamp reference of ADC (SD0 to SD9); note 1
cut-off frequency of CTH (SD0 to SD3)
PGA gain control (SD0 to SD9)
edge control for pulses SHP, SHD, CLPOB, CLPADC and CLKADC (note 2):
SD0 = 1, SHP and SHD sample on LOW level
SD1 = 1, CLPADC and CLPOB activated on HIGH level
SD2 = 1, CLKADC activated with rising edge
Notes
1. PGA gain register must always be refreshed after clamp code register content has been changed.
2. When pin CLPADC = HIGH (SD1 = 1; serial interface), the ADC input is clamped to the voltage level of Vref. Pin Vref
is connected to ground via a capacitor.
When the power supplies increase from zero to VCC, the init-on-power block initializes the circuit as follows:
• Cut-off frequency of the CTH circuit is set to: code fco(CTH) = 0
• PGA gain control is set to: code GPGA = 0
• Clamp code of the ADC is set to: code ADCCLP = 0
• SHP and SHD sample on HIGH level; CLKADC activated with rising edge
• CLPOB and CLPADC activated on HIGH level.
Table 2 Standby selection
PIN STDBY
DATA BITS SD9 to SD0
ICCA + ICCD
HIGH
LOW
logic 0
active
4 mA (typical); note 1
84 mA (typical)
Note
1. If an external regulator is used it has to be switched off in standby mode in order to avoid extra power consumption
by the TDA9965A.
2004 Jul 05
11
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
IN
from
CCD
N + 2
N + 3
N + 1
N
t
h(IN-SHP)
t
2.0 V
0.8 V
W(SHP)
SHP
SHD
t
h(IN-SHD)
t
2.0 V
W(SHD)
0.8 V
ADCIN
N − 1
N
N + 1
N + 2
t
t
h(SHD-CLKADC)
d(SHD-CLKADC)
t
W(CLKADC)H
t
2.0 V
0.8 V
CLKADC
DATA
t
50%
d(s)
h(o)
t
d(o)
90%
10%
N − 3
N − 2
N − 1
N
MGU389
The polarities used in this case are:
- SHP and SHD sample on HIGH level
- CLKADC activated with rising edge.
Fig.5 Pixel frequency timing diagram.
12
2004 Jul 05
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
1 pixel
1 pixel
PGAOUT
VIDEO
OPTICAL BLACK
HORIZONTAL FLYBLACK
DUMMY
VIDEO
CLPOB
WINDOW
CLPOB
(active HIGH)
CLPADC
CLPADC
WINDOW
WINDOW
CLPADC
(active HIGH)
MGU861
Fig.6 Line frequency timing diagram.
FCE775
FCE758
300
48
handbook, halfpage
handbook, halfpage
G
BW
(MHz)
PGA
(dB)
36
200
24
12
100
0
0
0
0000
256
512
768
1024
0010
0100
1000
1111
PGA control DAC input code
CTH control code
Fig.7 PGA gain as a function of PGA control DAC
input code.
Fig.8 CTH bandwidth as a function of CTH
control code.
2004 Jul 05
13
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
I
FCE689
handbo(oµk,Aha)lfpage
I
handbook, halfpage
400
(µA)
600
50
0
0
V (V)
2.4
V
V (V)
V
− 64 LSB
V
+ 64 LSB
O
O
O
(1)
−50
−
600
70 mV
MGU862
−400
(1) VO depends on the clamp code.
Fig.9 Typical clamp current as a function of
voltage on pin STGE.
Fig.10 Typical clamp current as a function of
voltage on pin Vref.
handbook, halfpage
+200 mV
−200 mV
FCE688
Fig.11 Maximum offset voltage between CCD
floating and dark pixel level.
2004 Jul 05
14
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
APPLICATION INFORMATION
from timing
generator
5.0 V
5.0 V
(2)
(2)
48 47 46 45 44 43 42 41 40 39 38 37
AGND4
IN
D9
D8
D7
1
2
36
CCD
35
34
33
32
33 pF
47 nF
AGND5
STGE
AGND1
3
4
5
D6
V
(3)
CCO2
(2)
(2)
(2)
(2)
V
OGND2
CCA1
31
30
29
28
27
26
25
6
7
5.0 V
5.0 V
TDA9965A
V
AGND2
CCO1
V
OGND1
D5
CCA2
8
9
(3)
V
ref
100 nF
D4
PGAOUT
(1)
ADCIN
10
11
12
D3
D2
n.c.
13 14 15 16 17 18 19 20 21 22 23 24
1
1
(2)
nF
µF
2.2
nF
1 nF
serial
interface
5.0 V
MGU714
(1) The clamp level of the signal input at pin ADCIN can be tuned from code 0 to code 1023 in one LSB step of the ADC via the serial interface (clamp
ADC activated).
(2) All supply pins must be decoupled with 100 nF capacitors mounted as closely as possible to the device.
(3) The capacitors on pins STGE and Vref have typical values, performing a typical device start-up time of 300 µs from standby to active (supplies on).
Fig.12 Application diagram.
2004 Jul 05
15
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
from timing
generator
5.0 V
5.0 V
(2)
(2)
48 47 46 45 44 43 42 41 40 39 38 37
AGND4
IN
D9
D8
D7
1
2
36
CCD1
35
34
33
32
33 pF
47 nF
AGND5
STGE
AGND1
3
4
5
D6
V
(3)
CCO2
(2)
(2)
(2)
(2)
V
OGND2
CCA1
31
30
29
28
27
26
25
6
7
5.0 V
5.0 V
TDA9965A
V
AGND2
CCO1
V
OGND1
D5
CCA2
8
9
(3)
V
ref
100 nF
D4
PGAOUT
(1)
ADCIN
10
11
12
D3
D2
n.c.
13 14 15 16 17 18 19 20 21 22 23 24
1
µF
1
nF
(2)
2.2
nF
1 nF
serial
5.0 V
interface
from timing
generator
5.0 V
5.0 V
(2)
(2)
48 47 46 45 44 43 42 41 40 39 38 37
AGND4
IN
D9
D8
D7
D6
1
2
36
CCD2
35
34
33
32
33 pF
47 nF
(3)
AGND5
STGE
AGND1
3
4
5
V
CCO2
(2)
(2)
(2)
V
OGND2
CCA1
31
30
29
28
27
26
25
6
7
5.0 V
5.0 V
TDA9965A
V
AGND2
CCO1
(2)
V
OGND1
D5
CCA2
8
9
(3)
V
ref
100 nF
D4
PGAOUT
(1)
ADCIN
10
11
12
D3
D2
n.c.
13 14 15 16 17 18 19 20 21 22 23 24
2.2
nF
For notes (1), (2) and (3) see Fig.12
(2)
serial
interface
5.0 V
MGU716
1
nF
1
nF
1
µF
Fig.13 Application diagram with two CCDs.
16
2004 Jul 05
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
Power and grounding recommendations
In a two-ground system, in order to minimize the noise
through the package and die parasitics, the following
recommendation must be implemented:
Care should be taken to minimize the noise when
designing a printed-circuit board for applications such as
PC cameras, surveillance cameras, camcorders, and
digital still cameras.
• The ground pin associated with the digital outputs must
be connected to the digital ground plane and special
care should be taken to avoid feedthrough in the analog
ground plane. The analog and digital ground planes
must be connected together with an inductor as closely
as possible to the IC in order for them to have the same
DC voltage.
For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of analog
components (such as classical operational amplifiers)
must be taken into account, particularly with respect to
power and ground connections.
• The digital output pins and their associated lines should
be shielded by the digital ground plane which can then
be used as a return path for the digital signals.
The connections between the CCD interface and the CTH
input should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analog and digital supplies provide the best
performance. If it is not possible to do this on the board
then the analog supply pins must be decoupled effectively
from the digital supply pins. The decoupling capacitors
must be placed as close as possible to the IC package.
2004 Jul 05
17
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w
p
M
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v
M
M
D
A
e
w
M
b
p
D
B
H
v
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT313-2
136E05
MS-026
2004 Jul 05
18
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
Introduction to soldering surface mount packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
– for all BGA, HTSSON-T and SSOP-T packages
Manual soldering
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
volume ≥ 350 mm3 so called thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 Jul 05
19
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
PLCC(5), SO, SOJ
not suitable(4)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
not recommended(7)
suitable
not suitable
not suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
2004 Jul 05
20
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Jul 05
21
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R78/03/pp22
Date of release: 2004 Jul 05
Document order number: 9397 750 13312
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