TDA9984AHW [NXP]
HDMI 1.3 transmitter with 1080p upscaler embedded; HDMI 1.3发射器,具有1080 upscaler嵌入式![TDA9984AHW](http://pdffile.icpdf.com/pdf1/p00140/img/icpdf/TDA99_777004_icpdf.jpg)
型号: | TDA9984AHW |
厂家: | ![]() |
描述: | HDMI 1.3 transmitter with 1080p upscaler embedded |
文件: | 总40页 (文件大小:194K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
Rev. 04 — 15 January 2009
Product data sheet
1. General description
The TDA9984A is a High-Definition Multimedia Interface (HDMI) v. 1.3 transmitter with
embedded 1080p upscaling functionality. It is backward compatible DVI 1.0 and can be
connected to any DVI 1.0 and HDMI sink. It allows mixing a 3 × 8-bit RGB or YCbCr video
stream with a pixel rate up to 150 MHz together with up to 4 × I2S-bus or one S/PDIF
audio streams with an audio sampling rate up to 192 kHz. It supports Gamut boundary
description (xvYCC), as well as HD audio, both HDMI 1.3 features.
A programmable upscaling block allows creating a 1080p output from a standard definition
input. An intrafield deinterlacer is included in the scaler.
In order to be compatible with most applications, and thanks to the integration of a fully
programmable input formatter and color space conversion block, the video input formats
accepted also include YCbCr 4 : 4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to
2 × 12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 × 12-bit). In case of
ITU656-like format, the input pixel clock can be made active on both edges.
The TDA9984A includes a HDCP 1.2 compliant cipher block. The HDCP key are stored
internally in a non-volatile OTP memory for maximum security.
The TDA9984A includes a true I2C-bus master interface for DDC-bus communication for
EDID purpose and HDCP purpose.
The TDA9984A can be controlled by an I2C-bus interface.
2. Features
I 3 × 8-bit video data input buses; CMOS and LV-TTL compatible
I Horizontal synchronization, vertical synchronization and data enable inputs or VREF,
HREF and FREF inputs which can be used for synchronization
I Pixel rate clock input can be made active on one or both edges; selectable via I2C-bus
I 4 × I2S-bus audio input channels, one S/PDIF channel; audio data rate up to 192 kHz
per input for both standards
I Dolby-True HD and DTS-HD High bit rate audio support through the use of the HBR
interface
I 250 MHz to 1.50 GHz TMDS transmitter operation
I Programmable input formatter and upsampler/interpolator allows input of any of the
4 : 4 : 4 or 4 : 2 : 2 semi-planar and 4 : 2 : 2 ITU656-like formats
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
I Programmable color space converter allows to input RGB video data and to output
RGB or YCbCr 4 : 2 : 2 HDMI video data, or to input YCbCr video data and to output
RGB or YCbCr 4 : 2 : 2 HDMI video data; converter can be passed
I Upscaler allows creating a 1080p output from a standard definition input by using
intelligent edge interpolation
I Repetition of video samples as required by the HDMI standard
I Insertion of HDMI additional information such as InfoFrames
I Color gamut metadata packet transmission (xvYCC)
I Downstream availability using hot plug detection (HPD input) and receiver detection
(RxSense circuit)
I Master DDC-bus interface
I Deals with multiple levels of HDCP receivers and repeaters
I Internal SHA-1 calculation
I Controllable via I2C-bus
I Low power dissipation
I 1.8 V and 3.3 V power supplies
I Power-down mode
I Hard reset
I Pin-to-pin compatible with TDA9983A/B and TDA9981A/B
I Software compatible with TDA9983A/B and TDA9981A/B
3. Applications
I Set-top box
I DVD player
I DVD recorder
I AV receiver
I Home theater
I Digital video camera
I Digital still camera
I Personal video recorder
I Media center PCs, graphic cards
I Switches
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
2 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
4. Quick reference data
Table 1.
Quick reference data
VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; unless otherwise specified.
Typical values are measured at Tamb = 25 °C and fclk = 150 MHz.
Symbol
Parameter
Conditions
Min Typ
Max Unit
VPP
programming voltage
5.0
3.0
5.25 5.5
V
VDDA(FRO)(3V3) free running oscillator analog supply
voltage (3.3 V)
3.3
3.6
V
VDDA(PLL)(3V3) PLL analog supply voltage (3.3 V)
3.0
3.0
3.0
3.3
3.3
3.3
3.6
V
VDDD(3V3)
VDDH(3V3)
VDDC(1V8)
digital supply voltage (3.3 V)
HDMI supply voltage (3.3 V)
core supply voltage (1.8 V)
3.6
V
3.6
V
1.65 1.8
1.65 1.8
1.95
1.95
630
940
400
V
VDDA(PLL)(1V8) PLL analog supply voltage (1.8 V)
V
[1][3]
[1][2]
[1][4]
Pcons
power consumption
input 480p, output 1080p
input 1080i, output 1080p
input 1080p, output 1080p
TMDS output current added
input 480p, output 1080p
input 1080i, output 1080p
input 1080p, output 1080p
-
-
-
500
742
320
mW
mW
mW
Ptot
total power dissipation
[1][3]
[1][2]
[1][4]
-
-
-
-
630
872
450
30
770
mW
1080 mW
540
40
mW
mW
Ppd
power dissipation in power-down mode
[1] The maximum current consumption is in this configuration for this group of pins.
[2] Video format:
a) Input 1080i, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels.
b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF.
[3] Video format:
a) Input 480p, ITU656 embedded sync, 48 kHz S/PDIF 2 channels.
b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF.
[4] Video format:
a) Input 1080p, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels.
b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF.
5. Ordering information
Table 2.
Ordering information
Type number Package[1]
Name
Description
Version
TDA9984AHW HTQFP80
plastic thermal enhanced thin quad flat package;
SOT841-4
80 leads; body 12 × 12 × 1 mm; exposed die pad
[1] A lead-free package is required to comply with the new legislation.
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
3 of 40
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V
DDA(PLL)(1V8)
V
V
V
V
V
V
DDA(PLL)(3V3) RST_N
A1 A0
40 41
DDD(3V3)
DDC(1V8)
DDA(FRO)(3V3)
I2C_SCL I2C_SDA DDC_SDA DDC_SCL
43 44 19 20
PP
DDH(3V3)
23
16, 45
38
13, 48, 71
42
59, 74
3
28, 34
21
4 to 11
TM
2
HARD
RESET
I C-BUS
SLAVE
DDC BUS
MASTER
INTERRUPT
GENERATION
17
18
AP0 to AP7
AUDIO CONTENT
AUDIO INFO-FRAME
ACR
AUDIO
FIFO
INT
AUDIO
PROCESSING
HPD
MANAGEMENT
DATA
ISLAND
PACKET
2
I C-BUS REGISTERS
HPD
12
CTS/N
ACLK
INSERTION
RxSENSE
VIDEO INFO-FRAME
OTHER INFO-FRAME
27
26
TXC+
OTP
MEMORY
KEYS
TXC−
66
CLOCK
MANAGMENT
30
29
VCLK
VHREF GENERATOR
TX0+
TX0−
HDCP
TMDS
PROCESSING
SERIALIZER
33
32
3 × 8-bit RGB or YCbCr 4 : 4 : 4
2 × 12-bit YCbCr 4 : 2 : 2 semi-planar
1 × 12-bit YCbCr 4 : 2 : 2 ITU656
TX1+
68 to 70
75 to 79
TX1−
DOWN-
SAMPLER
4 : 4 : 4
to
VPA[7:0]
57, 58
61 to 65,
67
36
35
2 × 12-bit YCbCr 4 : 2 : 2 semi-planar
1 × 12-bit YCbCr 4 : 2 : 2 ITU656
TX2+
COLOR
SPACE
CONVERTER
RGB to YCbCr
YCbCr to RGB
TX2−
4 : 2 : 2
VPB[7:0]
VPC[7:0]
VIDEO
INPUT
PROCESSOR
49 to 56
UPSAMPLER
4 : 2 : 2
to
2
24
VSYNC/VREF
HSYNC/HREF
DE/FREF
EXT_SWING
1
4 : 4 : 4
UPSCALER
4 : 2 : 2
TDA9984AHW
80
14, 47,
72
25, 31,
37
22
39
SSA(PLL)(3V3)
46, 15
60, 73
001aag595
V
V
V
V
V
V
SSA(PLL)(1V8)
SSD
SSC
SSH
SSA(FRO)(3V3)
The device can handle HDCP based on 1.2 features.
Fig 1. Block diagram
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
7. Pinning information
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
HSYNC/HREF
VSYNC/VREF
V
V
SSC
DDC(1V8)
3
V
VPB[6]
VPB[7]
VPC[0]
VPC[1]
VPC[2]
VPC[3]
VPC[4]
VPC[5]
VPC[6]
VPC[7]
PP
4
AP7
AP6
AP5
AP4
AP3
AP2
AP1
AP0
ACLK
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TDA9984AHW
V
V
V
V
V
DDD(3V3)
DDD(3V3)
V
SSD
SSD
V
SSA(PLL)(1V8)
SSA(PLL)(1V8)
DDA(PLL)(1V8)
V
DDA(PLL)(1V8)
INT
I2C_SDA
I2C_SCL
RST_N
A0
HPD
DDC_SDA
DDC_SCL
001aag597
Fig 2. Pin configuration
7.1 Pin description
Table 3.
Symbol
Pin description
Pin
Type[1]
Description
HSYNC/HREF
VSYNC/VREF
VPP
1
2
3
I
horizontal synchronization or reference input
vertical synchronization or reference input
I
P
programming voltage for OTP memory; connect to
ground for digital core in normal operation
AP7
AP6
AP5
AP4
AP3
4
5
6
7
8
I
I
I
I
I
audio port 7 input
audio port 6 input
audio port 5 input
audio port 4 input
audio port 3 input
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
5 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
Table 3.
Pin description …continued
Symbol
AP2
Pin
9
Type[1]
Description
I
audio port 2 input
AP1
10
11
12
13
14
15
16
17
I
audio port 1 input
AP0
I
audio port 0 input
ACLK
I
audio clock input
VDDD(3V3)
VSSD
P
G
G
P
O
digital supply voltage for I/O ports (3.3 V)
digital ground for I/O ports
analog ground for PLL
PLL analog supply voltage (1.8 V)
VSSA(PLL)(1V8)
VDDA(PLL)(1V8)
INT
interrupt output; warns the external microprocessor that
a special event has occurred
HPD
18
19
20
21
22
23
24
I
hot plug detect input; 5 V tolerant
DDC_SDA
DDC_SCL
TM
I/O
I
DDC-bus data input/output; 5 V tolerant
DDC-bus clock input; 5 V tolerant
I
internal test mode input; connect to ground
analog ground for free running oscillator
analog supply voltage for free running oscillator (3.3 V)
VSSA(FRO)(3V3)
VDDA(FRO)(3V3)
EXT_SWING
G
P
I
swing adjust input for TMDS output; a fixed resistor must
be connected to VDDH(3V3)
VSSH
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
G
O
O
P
O
O
G
O
O
P
O
O
G
P
G
I
ground for TMDS (HDMI) transmitter
negative clock channel for TMDS output
positive clock channel for TMDS output
supply voltage for TMDS (HDMI) transmitter (3.3 V)
negative data channel 0 for TMDS output
positive data channel 0 for TMDS output
ground for TMDS (HDMI) transmitter
negative data channel 1 for TMDS output
positive data channel 1 for TMDS output
supply voltage for TMDS (HDMI) transmitter (3.3 V)
negative data channel 2 for TMDS output
positive data channel 2 for TMDS output
ground for TMDS (HDMI) transmitter
analog supply voltage for PLL (3.3 V)
analog ground for PLL
TXC−
TXC+
VDDH(3V3)
TX0−
TX0+
VSSH
TX1−
TX1+
VDDH(3V3)
TX2−
TX2+
VSSH
VDDA(PLL)(3V3)
VSSA(PLL)(3V3)
A1
I2C-bus slave address bit 1 input
I2C-bus slave address bit 0 input
hard reset input; active LOW
I2C-bus clock input
I2C-bus data input/output
A0
I
RST_N
I2C_SCL
I2C_SDA
VDDA(PLL)(1V8)
VSSA(PLL)(1V8)
VSSD
I
I
I/O
P
G
G
PLL analog supply voltage (1.8 V)
analog ground for PLL
digital ground for I/O ports
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
6 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
Table 3.
Pin description …continued
Symbol
VDDD(3V3)
VPC[7]
VPC[6]
VPC[5]
VPC[4]
VPC[3]
VPC[2]
VPC[1]
VPC[0]
VPB[7]
VPB[6]
VDDC(1V8)
VSSC
Pin
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Type[1]
Description
P
I
digital supply voltage for I/O ports (3.3 V)
video port C input bit 7 (MSB)
video port C input bit 6
I
I
video port C input bit 5
I
video port C input bit 4
I
video port C input bit 3
I
video port C input bit 2
I
video port C input bit 1
I
video port C input bit 0 (LSB)
video port B input bit 7 (MSB)
video port B input bit 6
I
I
P
G
I
supply voltage for digital core (1.8 V)
ground for digital core
VPB[5]
VPB[4]
VPB[3]
VPB[2]
VPB[1]
VCLK
video port B input bit 5
I
video port B input bit 4
I
video port B input bit 3
I
video port B input bit 2
I
video port B input bit 1
I
video pixel clock input
VPB[0]
VPA[7]
VPA[6]
VPA[5]
VDDD(3V3)
VSSD
I
video port B input bit 0 (LSB)
video port A input bit 7 (MSB)
video port A input bit 6
I
I
I
video port A input bit 5
P
G
G
P
I
digital supply voltage for I/O ports (3.3 V)
digital ground for I/O ports
ground for digital core
VSSC
VDDC(1V8)
VPA[4]
VPA[3]
VPA[2]
VPA[1]
VPA[0]
DE/FREF
supply voltage for digital core (1.8 V)
video port A input bit 4
I
video port A input bit 3
I
video port A input bit 2
I
video port A input bit 1
I
video port A input bit 0
I
video data enable or field reference input
[1] P = Power supply; G = Ground; I = Input; O = Output.
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
7 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8. Functional description
The TDA9984A is designed to convert digital data (video and audio) provided by a
Set-Top Box or DVD into an HDMI output, which could be used in TV with HDMI or DVI
input.
The TDA9984A is able to output HDMI with the formats:
• RGB
• YCbCr 4 : 4 : 4
• YCbCr 4 : 2 : 2
The video data input formats are:
• RGB
• YCbCr 4 : 4 : 4
• YCbCr 4 : 2 : 2 semi-planar
• YCbCr 4 : 2 : 2 ITU656-like
It can also handle audio formats:
• 4 × I2S-bus channels
• One S/PDIF channel
• Dolby-True HD and DTS-HD through the use of HBR interface
8.1 Video processing
The TDA9984A has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0] and can
handle any of the following video input modes:
• RGB with 8-bit for each component
• YCbCr 4 : 4 : 4 with 8-bit for each component
• YCbCr 4 : 2 : 2 semi-planar with up to 12-bit for each component (Y, Cb and Cr)
• YCbCr 4 : 2 : 2 ITU656 with up to 12-bit data depth
The TDA9984A can be set to latch data at either the rising or the falling edge.
8.1.1 Internal assignment
The aim of the video input processor is to map internally the incoming data to the
corresponding mode, which can be handled by the video processing. The device expects
to have a big endian digital stream at its input. The internal signal name VP[23:0] is
assigned depending on the input mode as defined in Figure 3.
VPA[7:0]
VIDEO
VPB[7:0]
VP[23:0]
INPUT
PROCESSOR
VPC[7:0]
001aag599
Fig 3. Internal assignment of VP[23:0]
Rev. 04 — 15 January 2009
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
8 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
The device can swap and invert (in case of a little endian stream) the incoming video data
via the I2C-bus registers VIP_CNTRL_0, VIP_CNTRL_1 and VIP_CNTRL_2 (page 00h)
to match the expectation of the video processing block; see Table 4.
When input ports are not used, it is possible to map them to internal ground via the
I2C-bus registers ENA_VP_0, ENA_VP_1, ENA_VP_2, GND_VP_0, GND_VP_1 and
GND_VP_2 (page 00h).
Table 4.
Internal assignment
Internal port
RGB
YCbCr
4 : 4 : 4
Y[7]
4 : 2 : 2 semi-planar 4 : 2 : 2 ITU656-like
VP[23]
VP[22]
VP[21]
VP[20]
VP[19]
VP[18]
VP[17]
VP[16]
VP[15]
VP[14]
VP[13]
VP[12]
VP[11]
VP[10]
VP[9]
G[7]
G[6]
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]
Y[11]
YCbCr[11]
Y[6]
Y[10]
YCbCr[10]
Y[5]
Y[9]
YCbCr[9]
Y[4]
Y[8]
YCbCr[8]
Y[3]
Y[7]
YCbCr[7]
Y[2]
Y[6]
YCbCr[6]
Y[1]
Y[5]
YCbCr[5]
Y[0]
Y[4]
YCbCr[4]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[7]
Cr[0]
Y[3]
YCbCr[3]
Y[2]
YCbCr[2
Y[1]
YCbCr[1]
Y[0]
YCbCr[0]
CbCr[11]
CbCr[10]
CbCr[9]
CbCr[8]
CbCr[7]
CbCr[6]
CbCr[5]
CbCr[4]
CbCr[3]
CbCr[2]
CbCr[1]
CbCr[0]
-
-
-
-
-
-
-
-
-
-
-
-
VP[8]
VP[7]
VP[6]
VP[5]
VP[4]
VP[3]
VP[2]
VP[1]
VP[0]
8.1.2 Input format mappings
See Table 5 for more information concerning input format supported.
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
9 of 40
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Table 5.
Inputs of video input formatter
Space color Format
Channels
Sync
Rising
edge
Falling
edge
Double
edge[1]
Transmission Pixel clock
input format (MHz)
Maximum
input format
Reference
RGB
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2
3 × 8-bit
external
X
X
X
X
X
-
150 MHz
-
Section 8.1.2.1
X
X
X
X
X
-
150 MHz
-
embedded
external
-
150 MHz
-
-
150 MHz
-
YCbCr
YCbCr
3 × 8-bit
-
150 MHz
-
Section 8.1.2.2
Section 8.1.2.3
-
150 MHz
-
embedded
external
-
150 MHz
-
-
150 MHz
-
up to 1 × 12-bit
semi-planar
ITU656-like
ITU656-like
ITU656-like
ITU656-like
ITU656-like
ITU656-like
54.054 MHz
54.054 MHz
27.027 MHz
54.054 MHz
54.054 MHz
27.027 MHz
480p/576p
480p/576p
480p/576p
480p/576p
480p/576p
480p/576p
1080p
1080p
1080p
1080p
X
X
Section 8.1.2.4
Section 8.1.2.5
embedded
X
X
Section 8.1.2.6
Section 8.1.2.7
up to 2 × 12-bit
semi-planar
external
X
X
SMPTE293M 148.5 MHz
SMPTE293M 148.5 MHz
SMPTE293M 148.5 MHz
SMPTE293M 148.5 MHz
X
X
embedded
Section 8.1.2.8
[1] Double edge means both rising and falling edges.
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.1 RGB 4 : 4 : 4 external sync input (rising edge)
Table 6.
RGB 4 : 4 : 4 mapping
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.
Video port A
Pin
Video port B
RGB 4 : 4 : 4 Pin
Video port C
RGB 4 : 4 : 4 Pin
Control
RGB 4 : 4 : 4 Pin
RGB 4 : 4 : 4
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
VPB[6]
VPB[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
VPC[0]
VPC[1]
VPC[2]
VPC[3]
VPC[4]
VPC[5]
VPC[6]
VPC[7]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
HSYNC/HREF used
VSYNC/VREF used
DE/FREF
used
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPA[7:0]
VPB[7:0]
VPC[7:0]
B [7:0]
B [7:0]
B [7:0]
B [7:0]
...
...
...
B
[7:0]
[7:0]
[7:0]
B
[7:0]
xxx
0
1
2
3
xxx
G [7:0]
0
G [7:0]
1
G [7:0]
2
G [7:0]
3
G
R
G
R
[7:0]
[7:0]
xxx
xxx
R [7:0]
0
R [7:0]
1
R [7:0]
2
R [7:0]
3
xxx
xxx
001aag380
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 4. Pixel encoding RGB 4 : 4 : 4 external sync input (rising edge)
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
11 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.2 YCbCr 4 : 4 : 4 external sync input (rising edge)
Table 7.
YCbCr 4 : 4 : 4 mapping
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.
Video port A Video port B Video port C
YCbCr 4 : 4 : 4 Pin YCbCr 4 : 4 : 4 Pin
Control
Pin
YCbCr 4 : 4 : 4 Pin
YCbCr 4 : 4 : 4
used
VPA[0] Cb[0]
VPA[1] Cb[1]
VPA[2] Cb[2]
VPA[3] Cb[3]
VPA[4] Cb[4]
VPA[5] Cb[5]
VPA[6] Cb[6]
VPA[7] Cb[7]
VPB[0] Y[0]
VPB[1] Y[1]
VPB[2] Y[2]
VPB[3] Y[3]
VPB[4] Y[4]
VPB[5] Y[5]
VPB[6] Y[6]
VPB[7] Y[7]
VPC[0] Cr[0]
VPC[1] Cr[1]
VPC[2] Cr[2]
VPC[3] Cr[3]
VPC[4] Cr[4]
VPC[5] Cr[5]
VPC[6] Cr[6]
VPC[7] Cr[7]
HSYNC/HREF
VSYNC/VREF
DE/FREF
used
used
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPA[7:0]
VPB[7:0]
VPC[7:0]
Cb [7:0]
Cb [7:0]
Cb [7:0]
Cb [7:0]
...
...
...
Cb [7:0]
Cb [7:0]
xxx
0
1
2
3
xxx
Y [7:0]
0
Y [7:0]
1
Y [7:0]
2
Y [7:0]
3
Y
[7:0]
Y
[7:0]
xxx
xxx
Cr [7:0]
0
Cr [7:0]
1
Cr [7:0]
2
Cr [7:0]
3
Cr [7:0]
xxx
Cr [7:0]
xxx
001aag381
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 5. Pixel encoding YCbCr 4 : 4 : 4 external sync input (rising edge)
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
12 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.3 YCbCr 4 : 2 : 2 ITU656-like external sync input (rising edge)
Table 8.
YCbCr 4 : 2 : 2 ITU656-like rising edge mapping
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
Video port A Video port B
YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 (ITU656-like)
Control
Pin
Pin
YCbCr 4 : 2 : 2
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
Cb[0] Y0[0] Cr[0] Y1[0]
Cb[1] Y0[1] Cr[1] Y1[1]
Cb[2] Y0[2] Cr[2] Y1[2]
Cb[3] Y0[3] Cr[3] Y1[3]
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
VPB[6]
VPB[7]
Cb[4] Y0[4] Cr[4] Y1[4]
Cb[5] Y0[5] Cr[5] Y1[5]
Cb[6] Y0[6] Cr[6] Y1[6]
Cb[7] Y0[7] Cr[7] Y1[7]
Cb[8] Y0[8] Cr[8] Y1[8]
Cb[9] Y0[9] Cr[9] Y1[9]
Cb[10] Y0[10] Cr[10] Y1[10]
Cb[11] Y0[11] Cr[11] Y1[11]
HSYNC/HREF used
VSYNC/VREF used
DE/FREF
used
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPB[7:0]; VPA[3:0]
Cb [11:0]
0
Y [11:0]
0
Cr [11:0]
0
Y [11:0]
1
...
Cr [11:0]
xxx
Y [11:0]
xxx
001aag383
Fig 6. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external sync input (rising edge)
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
13 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.4 YCbCr 4 : 2 : 2 ITU656-like external sync input (rising and falling)
Table 9.
YCbCr 4 : 2 : 2 ITU656-like double edge mapping
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
Video port A Video port B
YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 (ITU656-like)
Control
Pin
Pin
YCbCr 4 : 2 : 2
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
Cb[0] Y0[0] Cr[0] Y1[0]
Cb[1] Y0[1] Cr[1] Y1[1]
Cb[2] Y0[2] Cr[2] Y1[2]
Cb[3] Y0[3] Cr[3] Y1[3]
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
VPB[6]
VPB[7]
Cb[4]
Cb[5]
Cb[6]
Cb[7]
Cb[8]
Cb[9]
Y0[4] Cr[4]
Y0[5] Cr[5]
Y0[6] Cr[6]
Y0[7] Cr[7]
Y0[8] Cr[8]
Y0[9] Cr[9]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
HSYNC/HREF used
VSYNC/VREF used
DE/FREF
used
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Cb[10] Y0[10] Cr[10] Y1[10]
Cb[11] Y0[11] Cr[11] Y1[11]
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPB[7:0]; VPA[3:0]
Cb [11:0]
0
Y [11:0]
0
Cr [11:0]
0
Y [11:0]
1
...
Cr [11:0]
xxx
Y
[11:0]
xxx
001aag382
Fig 7. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external sync input (rising and falling)
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
14 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.5 YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising edge)
Table 10. YCbCr 4 : 2 : 2 ITU656-like embedded rising edge mapping
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
Video port A
Video port B
Control
Pin
Pin
YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 (ITU656-like)
YCbCr 4 : 2 : 2
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
Cb[0] Y0[0] Cr[0] Y1[0]
Cb[1] Y0[1] Cr[1] Y1[1]
Cb[2] Y0[2] Cr[2] Y1[2]
Cb[3] Y0[3] Cr[3] Y1[3]
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
VPB[6]
VPB[7]
Cb[4] Y0[4]
Cb[5] Y0[5]
Cb[6] Y0[6]
Cb[7] Y0[7]
Cb[8] Y0[8]
Cb[9] Y0[9]
Cr[4]
Cr[5]
Cr[6]
Cr[7]
Cr[8]
Cr[9]
Y1[4] HSYNC/HREF not used
Y1[5] VSYNC/VREF not used
Y1[6] DE/FREF
not used
Y1[7]
Y1[8]
Y1[9]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Cb[10] Y0[10] Cr[10] Y1[10]
Cb[11] Y0[11] Cr[11] Y1[11]
VCLK
VPB[7:0]; VPA[3:0]
Cb [11:0]
0
Y [11:0]
0
Cr [11:0]
0
Y [11:0]
1
...
Cr [11:0]
xxx
Y
[11:0]
xxx
001aag385
Fig 8. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising edge)
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
15 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.6 YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising and falling)
Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded double edge mappings
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
Video port A
Video port B
Control
Pin
Pin
YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 (ITU656-like)
YCbCr 4 : 2 : 2
VPA[0] Cb[0] Y0[0] Cr[0] Y1[0]
VPA[1] Cb[1] Y0[1] Cr[1] Y1[1]
VPA[2] Cb[2] Y0[2] Cr[2] Y1[2]
VPA[3] Cb[3] Y0[3] Cr[3] Y1[3]
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
VPB[6]
VPB[7]
Cb[4] Y0[4]
Cb[5] Y0[5]
Cb[6] Y0[6]
Cb[7] Y0[7]
Cb[8] Y0[8]
Cb[9] Y0[9]
Cr[4]
Cr[5]
Cr[6]
Cr[7]
Cr[8]
Cr[9]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
HSYNC/HREF not used
VSYNC/VREF not used
DE/FREF
not used
VPA[4]
VPA[5]
VPA[6]
VPA[7]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Cb[10] Y0[10] Cr[10] Y1[10]
Cb[11] Y0[11] Cr[11] Y1[11]
VCLK
VPB[7:0]; VPA[3:0]
Cb [11:0]
0
Y [11:0]
0
Cr [11:0]
0
Y [11:0]
1
...
Cr [11:0]
xxx
Y
[11:0]
xxx
001aag384
Fig 9. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising and falling)
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
16 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.7 YCbCr 4 : 2 : 2 semi-planar external input (rising edge)
Table 12. YCbCr 4 : 2 : 2 semi-planar rising edge mapping
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.
Video port A Video port B Video port C
Pin YCbCr 4 : 2 : 2
semi-planar
Control
Pin
Pin
YCbCr 4 : 2 : 2
semi-planar
Pin
YCbCr 4 : 2 : 2
semi-planar
YCbCr
4 : 2 : 2
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
Y0[0]
Y0[1]
Y0[2]
Y0[3]
Cb[0]
Cb[1]
Cb[2]
Cb[3]
Y1[0]
VPB[0] Y0[4]
VPB[1] Y0[5]
VPB[2] Y0[6]
VPB[3] Y0[7]
VPB[4] Y0[8]
VPB[5] Y0[9]
VPB[6] Y0[10]
VPB[7] Y0[11]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
Y1[10]
Y1[11]
VPC[0]
VPC[1]
VPC[2]
VPC[3]
VPC[4]
VPC[5]
VPC[6]
VPC[7]
Cb[4]
Cb[5]
Cb[6]
Cb[7]
Cb[8]
Cb[9]
Cb[10]
Cb[11]
Cr[4]
HSYNC/HREF used
VSYNC/VREF used
Y1[1]
Y1[2]
Y1[3]
Cr[0]
Cr[1]
Cr[2]
Cr[3]
Cr[5]
Cr[6]
Cr[7]
Cr[8]
Cr[9]
Cr[10]
Cr[11]
DE/FREF
used
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
Y [11:0]
Y [11:0]
Y [11:0]
Y [11:0]
Y [11:0]
Y [11:0]
...
...
0
1
2
3
4
5
Cb [11:0]
0
Cr [11:0]
0
Cb [11:0]
2
Cr [11:0]
2
Cb [11:0]
4
Cr [11:0]
4
001aag386
Fig 10. Pixel encoding YCbCr 4 : 2 : 2 semi-planar external input (rising edge)
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
17 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.8 YCbCr 4 : 2 : 2 semi-planar embedded sync input (rising edge)
Table 13. YCbCr 4 : 2 : 2 semi-planar embedded rising edge mapping
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.
Video port A
Video port B
Pin YCbCr 4 : 2 : 2
semi-planar
Video port C
Control
Pin
Pin
YCbCr 4 : 2 : 2
semi-planar
Pin
YCbCr 4 : 2 : 2
semi-planar
YCbCr
4 : 2 : 2
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
Y0[0]
Y0[1]
Y0[2]
Y0[3]
Cb[0]
Cb[1]
Cb[2]
Cb[3]
Y1[0]
VPB[0] Y0[4]
VPB[1] Y0[5]
VPB[2] Y0[6]
VPB[3] Y0[7]
VPB[4] Y0[8]
VPB[5] Y0[9]
VPB[6] Y0[10]
VPB[7] Y0[11]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
Y1[10]
Y1[11]
VPC[0]
VPC[1]
VPC[2]
VPC[3]
VPC[4]
VPC[5]
VPC[6]
VPC[7]
Cb[4]
Cb[5]
Cb[6]
Cb[7]
Cb[8]
Cb[9]
Cb[10]
Cb[11]
Cr[4]
HSYNC/HREF not used
VSYNC/VREF not used
Y1[1]
Y1[2]
Y1[3]
Cr[0]
Cr[1]
Cr[2]
Cr[3]
Cr[5]
Cr[6]
Cr[7]
Cr[8]
Cr[9]
Cr[10]
Cr[11]
DE/FREF
not used
VCLK
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
Y [11:0]
Y [11:0]
Y [11:0]
Y [11:0]
Y [11:0]
Y [11:0]
...
...
0
1
2
3
4
5
Cb [11:0]
0
Cr [11:0]
0
Cb [11:0]
2
Cr [11:0]
2
Cb [11:0]
4
Cr [11:0]
4
001aag387
Fig 11. Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded sync input (rising edge)
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
18 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.3 Synchronization
The TDA9984A can be synchronized with external input signals HSYNC and VSYNC or
with extraction of the sync information from embedded sync codes (SAV/EAV) inside the
video.
8.1.3.1 Timing extraction generator
This block can extract the synchronization signals HREF, VREF and FREF from SAV and
EAV in case of embedded synchronization in the data stream.
Synchronization signals can be embedded in YCbCr 4 : 2 : 2 ITU656 (up to 1 × 12-bit)
and semi-planar (up to 2 × 12-bit).
8.1.3.2 Data enable generator
TDA9984A contains a Data Enable (DE) generator. This circuit generates an internal DE
signal for a system which does not provide one. The DE generator is controlled via the
I2C-bus register.
8.1.4 Input and output video format
Due to the flexible video input formatter, the TDA9984A can accept a large range of inputs
formats. This flexibility allows the TDA9984A to be compatible with the maximum number
of MPEG decoders. Moreover, these input formats may be changed in many ways (space
color converter, upsampler and scaler) to be transmitted across the HDMI link.
Table 14 gives the possible inputs and outputs.
Table 14. Inputs and outputs capability
Input
Scaler
Output
Space color Format
Channels
Space color Format
Channels
3 × 8-bit
3 × 8-bit
2 × 12-bit
3 × 8-bit
3 × 8-bit
2 × 12-bit
3 × 8-bit
3 × 8-bit
2 × 12-bit
3 × 8-bit
3 × 8-bit
2 × 12-bit
RGB
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2
3 × 8-bit
no scaling
RGB
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2
YCbCr
YCbCr
RGB
YCbCr
YCbCr
3 × 8-bit
no scaling
YCbCr
YCbCr
RGB
up to 1 × 12-bit scaling
semi-planar
YCbCr
YCbCr
RGB
up to 2 × 12-bit scaling
semi-planar
YCbCr
YCbCr
8.1.5 Scaler unit
8.1.5.1 Scaler features
The scaler unit has the following features:
• Up-scaling only: to expand input image horizontally and vertically
• Deinterlacer embedded (no need of output memory)
• Data processing: 12-bit data width
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
19 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
• Maximum output operating frequency is 148.5 MHz; HDTV supported 1080p both PAL
and NTSC
• Input video standards YCbCr 4 : 2 : 2 semi-planar and ITU656 (no RGB, nor
YCbCr 4 : 4 : 4)
8.1.5.2 Input and output video scaler
The scaler will convert the standard definition (high definition respectively) video signals
(480i/576i, 480p/576p and 720p, 1080i respectively) into 1080p as described in Figure 12.
Remark: All 4 : 2 : 2 input video formats can be bypassed, as well as all RGB and
YCbCr 4 : 4 : 4 input data, which will be directly fed to the color space converter.
VIDEO STANDARD OUTPUT
FORMAT
861B
FORMAT
861B
(1) (2) (3)
(2)
(2)
(4)
2, 3
720
1280
1920
720
×
×
×
×
480p
720p
1080i
480i
(1)
(1)
4
5
6, 7 (NTSC)
16
(4) (5) (6) (1) (5)
(1)
1920 × 1080p
(1) (2) (3)
(2)
(2)
17, 18
19
720
1280
1920
×
×
×
×
576p
720p
1080i
576i
(1)
(1)
(4)
20
(4) (5) (6) (1) (5)
(1)
21, 22 (PAL) 720
31
1920 × 1080p
001aag603
All upscaling modes are available only for YCbCr 4 : 2 : 2 input format.
(1) Pass-through
(2) Upscaling
(3) Upscaling and interlacing
(4) Deinterlacing
(5) Deinterlacing and upscaling
(6) Deinterlacing, upscaling and interlacing
Fig 12. Input and output video scaler
8.1.6 Upsampler
The incoming YCbCr 4 : 2 : 2 (2 × 12-bit) data stream format can be upsampled into an
8-bit YCbCr 4 : 4 : 4 (3 × 8-bit) data stream by repeating or linearly interpolating the
chrominance pixels.
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8.1.7 Color space converter
The color-space converter is used to convert input video data from one type to another
color space (e.g. RGB to YCbCr and YCbCr to RGB). This block can be bypassed and
each coefficient is programmable by the I2C-bus registers.
C11 C12 C13
C21 C22 C23
C31 C32 C33
OinGY
OinRCr
OinBCb
OoutYG
OoutCrR
OoutCbB
YG
CrR
CbB
GY
=
×
+
+
(1)
RCr
BCb
8.1.8 Downsampler
This block works only with YCbCr input format. These filters downsample the Cb and Cr
signals by a factor of two. A delay is added on the G/Y channel, which corresponds to the
pipeline delay of the filters, to put the Y channel in phase with the Cb and Cr channel.
8.2 Audio processing
The TDA9984A is compatible with audio features as per HDMI specification, Rev. 1.3:
• S/PDIF
• I2S-bus up to four channels
• Dolby-True HD and DTS-HD through the use of HBR interface
S/PDIF, I2S-bus or HBR can be selected via the I2C-bus. Only one audio format can be
used at a same time. Table 15 shows the audio port allocation.
Table 15. Audio port configuration
Audio port
Format
S/PDIF
I2S-bus
HBR
AP0
AP1
AP2
AP3
AP4
AP5
AP6
AP7
ACLK
-
WS (word select)
I2S-bus channel 0
I2S-bus channel 1
I2S-bus channel 2
I2S-bus channel 3
-
WS (word select)
HBR channel 0
HBR channel 1
HBR channel 2
HBR channel 3
-
-
-
-
-
MCLK
S/PDIF input
-
-
AUX (internal test)
-
AUX (internal test)
SCK
AUX (internal test)
SCK
All audio ports are LV-TTL compatible.
It is possible to map internally an unused port to internal ground via the I2C-bus registers
ENA_APx and GND_APx on page 00h (both audio inputs and clock input as well).
8.2.1 S/PDIF
The audio port AP6 is used for this feature. In this format, the TDA9984A supports
2-channel uncompressed PCM data (IEC 60958) layout 0, or compressed bit stream up to
8 multi-channels (Dolby Digital, DTS, AC3, etc.) layout 1.
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The TDA9984A is able to recover the original clock from the S/PDIF signal (no need of
external clock). In addition, it can also use an external clock to decode the S/PDIF signal.
8.2.2 I2S-bus
There are 4 × I2S-bus stereo inputs channels (AP1, AP2, AP3 and AP4) which allow
carrying eight uncompressed audio channels. The I2S-bus input interface receives an
I2S-bus signal including serial data in, word select and serial clock. Various I2S-bus
formats are supported and can be selected by setting the appropriate bits of the register.
Typical waveforms for the I2S-bus signals at 64fs are given in Figure 13.
LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL
DATA
(n−1)
(n−1)
(n)
(n)
(n+1)
(n+1)
WS
MSB
24-bit audio sample word
LSB
0
0
0
ACLK(64fs)
001aag607
a. Philips format
LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL
DATA
WS
(n−1)
(n−1)
(n)
(n)
(n+1)
(n+1)
MSB
24-bit audio sample word
LSB
0
0
0
ACLK(64fs)
001aag608
b. Left justified format
LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL
DATA
WS
(n−1)
(n−1)
(n)
(n)
(n+1)
(n+1)
0
0
0
MSB
24-bit audio sample word
LSB
ACLK(64fs)
001aag609
c. Right justified format
Fig 13. I2S-bus formats
The I2S-bus input interface can receive up to 24-bit wide audio samples via the serial data
input with a clock frequency of at least 32 times the input sample frequency fs. Audio
samples with a precision better than 24 bits are truncated to 24-bit format.
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If the input clock has a frequency of 32fs, only 16-bit audio samples can be received. If the
input clock has a frequency of 64fs and is left justified or Philips, the audio word is
truncated to 24-bit format and padded with zeros. If the input clock has a frequency of 64fs
and is right justified, audio sample must be strictly 24-bit length.
The word select signal WS indicates whether left or right channel information is
transferred over the serial data.
8.2.3 High bit rate audio
The High Bit Rate audio format is used to support both DTS-HD and Dolby-True HD audio
format provided for instance by Blu-Ray DVD. The transmitter is capable to receive a
single High Bit Rate IEC 61937 stream at a frame rate of 768 kHz. This is typically
stripped across 4 × I2S-bus interface to the HDMI transmitter with a corresponding I2S-bus
clock rate of 192 kHz.
As for I2S-bus, no additional information is required on the audio infoframe. All relevant
information are carried on the stream through the use of the channel status bit via the
I2C-bus table.
8.3 HDCP processing
8.3.1 High-bandwidth digital content protection
The HDMI transmitter contains an HDCP function, which encrypts the transmitted stream
content (both video and audio). This function can be enabled and disabled via the I2C-bus.
The keys can be stored internally in OTP non-volatile memory or can be loaded via the
I2C-bus. As the keys are stored internally, the security is maximized.
8.3.1.1 Repeater function
The TDA9984A can be used in a repeater device according to the HDCP specification,
Rev 1.2. The TDA9984A is able to store the KSV list of a maximum of 127 devices in a
register memory.
8.3.1.2 SHA-1
To deal with repeater, a SHA-1 calculation is performed by the transmitter and by the
downstream repeater. For security purposes and in order to relieve the microcontroller,
the SHA-1 has been implemented within the TDA9984A.
This calculation is worked out after the transmitter has loaded the KSV list (see HDCP
specification, Rev 1.2). If SHA-1 calculated by transmitter equals the SHA-1 calculated by
repeater, then an interrupt is sent.
8.4 TMDS serializer
8.4.1 RxSense detection
The TDA9984A has the capability to sense the receiver connectivity and working
behavior. This feature detects the presence of the 50 Ω pull-up resistor RT on the
downstream side onto the TMDS clock channel.
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V
DDA
R
T
R
T
TRANSMITTER
Z
0
D
D
RECEIVER
001aag601
Fig 14. Receiver sensitivity detection
As long as the receiver is connected to the transmitter and powered up, bit RXS_FIL is set
to logic 1 (see register INT_FLAGS_3, page 00h, address 12h).
As soon as the cable is unplugged or the receiver side is powered off (assuming in this
case that VDD is switched off), the RxSense generates an interrupt inside the TDA9984A,
changing the value of bit RXS_FIL to logic 0. This allows the application to stop sending
unnecessary video content.
This feature is very useful when the receiver has been recovered from an off-state and
does not generate a HPD transition HIGH-to-LOW-to-HIGH. In this particular case,
RxSense will generate an interrupt so that the TDA9984A restarts sending video.
Remark: According to the HDMI specification, only the HPD interrupt allows the
application to read the EDID. RxSense is not mandatory to initialize the EDID reading
procedure.
8.4.2 TMDS output buffers
The TMDS output amplitude can be adjusted via an external resistor connected between
pins EXT_SWING and VDDH(3V3); see Figure 15.
It is strongly recommended to use REXT_SWING = 610 Ω ± 1 % to get a nominal swing of
500 mV. By doing so, the TDA9984A shall meet the minimum low-level output voltage as
per HDMI specification, Rev 1.3a table 4-15.
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HDMI 1.3 transmitter with 1080p upscaler embedded
001aag602
650
(1)
(2)
V
(mV)
o(se)
550
450
(3)
350
500
600
700
800
R
(Ω)
EXT_SWING
(1) Swing character data
(2) Upper limit (600 mV)
(3) Lower limit (400 mV)
Fig 15. TMDS single-ended output swing as a function of external resistor REXT_SWING
8.4.3 Pixel repetition
To transmit video formats with pixel rates below 25 mega samples per second or to
increase the number of audio sample packets in each frame, the TDA9984A uses pixel
repetition to increase the number of pixels sent by the frame. The pixel clock is multiplied
by the same factor as given in Table 16.
Table 16. Pixel repetition
PR[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Others
Pixel repetition factor
no repetition: pixel sent once
2 times: pixel repeated once
3 times
4 times
5 times
6 times
7 times
8 times
9 times
10 times
reserved
8.5 Control blocks
8.5.1 Clock management
The system clock is composed of a series of three PLLs, which will generates different
clocks in the system taking into account the double edge, the scaling ratio and the
serialization.
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Here is described briefly the clock system architecture:
• PLL double edge: generates a clock at twice the VCLK input frequency to capture
correctly the data at the video formatter input
• PLL scaling: creates a new video processing scaled clock taking into account the
scaling ratio programmed in the scaler
• PLL serializer: a system clock generator, which enables the stream produced by the
encoder to be transmitted on the TMDS data channel at ten times or above the
sampling rate; see Section 8.4.3
Each PLL can be bypassed via the I2C-bus and then external clock VCLK can be provided
independently to each block.
8.5.2 Interrupt controller
Pin INT is used to alert the microcontroller that a critical event concerning the HDMI has
occurred. Some of theses interrupts are maskable. See Table 17 for the interrupt types
generated by the TDA9984A.
Table 17. Interrupts
Interrupt
Domain
HDCP
Definition
Maskable
feature
Interrupt name
r0
r0 = R’0 check done
pj = P’j check fails
V = V’ check success
bstatus available
maskable
pj
sha-1
bstatus
bcaps
t0
bcaps available
HDCP goes to initial state
security
HDCP encryption is off or blue
screen removed
not maskable
maskable
HPD
hpd
transition on HPD input
transition on RxSense
EDID block read finished
test purpose
RxSense
EDID
rx_sense
edid_block_rd
sw_intsoftware
Interrupt
8.5.3 Hot plug detection
Pin HPD is the hot plug detect pin; it is 5 V input tolerant. When asserted, the hot plug
detect signal tells the transmitter that the receiver is connected. When changing from
LOW to HIGH, the TDA9984A has to read EDID to match the video format to the format
the receiver can handle.
8.5.4 Initialization
After power-up, the TDA9984A is activated by a hard reset. Pin RST_N can be used to
activate the TDA9984A in a known state.
The device also offers the possibility to perform a soft reset that will affect a certain
number of I2C-bus registers, but not all of them. This soft reset is also mandatory for a
proper initialization of the device.
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8.5.5 Power management
The TDA9984A can be powered down via the I2C-bus register. In this mode, all PLLs are
switched off and the biasing structure of the output stage is disconnected (all activity is
reduced). Therefore, the TDA9984A has a very low power consumption which is suitable
for portable applications.
8.6 DDC-bus interface
8.6.1 DDC-bus channel
The DDC-bus pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at
Standard-mode (100 kHz) and Fast-mode (400 kHz). The DDC-bus is used as a master
interface in case of EDID reading, and while proceeding for HDCP. It is recommended not
going beyond 100 kHz for EDID as claimed by the HDMI specification. This frequency is
linked to the internal free running oscillator whose nominal frequency is 30 MHz as:
f FRO
f DDC = ---------------------------------
3 × 2Nclk – div
(2)
Where:
f
FRO = free running oscillator frequency
Nclk-div = value set by register
Then for convenience, it is recommended to keep the same frequency for HDCP purpose.
8.6.2 E-EDID
8.6.2.1 E-EDID reading
As a master interface for the EDID process, the DDC-bus is compliant to the I2C-bus
specification and has the possibility of the repeat and start condition to enable quick
access to the EDID content, as well as the large EDID reading possibility (with the use of
a segment pointer).
The TDA9984A has a full I2C-bus page (page 09h) dedicated to the EDID where one
block can be stored. The block can be read by the microprocessor to determine the
supported video and audio format of the downstream side.
Remark: When the block is read by the TDA9984A, it generates an interrupt to warn the
main processor that the TDA9984A is ready to transmit the content. Once the content is
read-out by the microprocessor, it can allow reading other blocks if required.
8.6.2.2 HDMI and DVI receiver discrimination
This information is located in the E-EDID receiver part, more exactly in the ‘Vendor
Specific Data block within the first CEA EDID timing extension.
If the 24-bit IEEE Registration Identifier contains the value 00 0C03h, then the receiver will
support HDMI; otherwise the device shall be treated as a DVI device.
However, even though the TDA9984A have directly access to that information, this is the
task of the microcontroller to ask to switch from DVI to HDMI mode.
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8.7 I2C-bus interface
The I2C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant. Pin I2C_SCL is only an input
pin. Both Fast-mode (400 kHz) and Standard-mode (100 kHz) are supported. The
registers of the TDA9984A can be accessed via the I2C-bus. All registers are R/W except
some, which cannot be read for confidentiality.
The TDA9984A is used as a slave I2C-bus device. Bits A0 and A1 of the I2C-bus device
address are externally selected by pins A0 and A1 (see Table 18).
Table 18. Device address
Device address
W/R
-
A6
A5
A4
A3
A2
A1
A0
1
1
1
0
0
pin A1
pin A0
0/1
The I2C-bus access format is shown in Figure 16.
Firstly, the master writes the TDA9984A address and the subaddress to access the
specific register, and then the data.
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
SDA
SLAVE ADDRESS
SUBADDRESS
DATA
STOP
001aaf292
Fig 16. I2C-bus access
9. I2C-bus registers definitions
9.1 Memory page management
The I2C-bus memory is split into several pages and the selection between pages is made
with common register CURPAGE_ADR. It is only necessary to write in this register once
to change the current page. So multiple read or write operations in the same page need a
write register CURPAGE_ADR once at the beginning.
Table 19. Memory pages
Page address
Memory page description
general control
00h
01h
02h
09h
10h
11h
12h
scaler and PLL scaling
PLL settings
EDID control page
InfoFrames and packets
audio settings and content info packets
HDCP and OTP
9.2 ID version
The ID-version readable via I2C-bus is defined as follows:
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• TDA9984AHW will have the value 1000 XXXX
The four LSBs are used for indicating the die version.
10. Limiting values
Table 20. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD(3V3)
VDD(1V8)
∆VDD
Tstg
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−55
−5
Max
+4.6
+2.5
+0.5
+150
+85
Unit
V
supply voltage (3.3 V)
supply voltage (1.8 V)
supply voltage difference
storage temperature
ambient temperature
junction temperature
V
V
°C
°C
°C
V
Tamb
Tj
-
+125
±2000
Vesd
electrostatic discharge voltage human body model
-
11. Thermal characteristics
Table 21. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from
junction to ambient
in free air
26.5
K/W
12. Static characteristics
Table 22. Supplies
VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; unless otherwise specified.
Typical values are measured at Tamb = 25 °C and fclk = 150 MHz.
Symbol
VPP
Parameter
Conditions
Min
5.0
3.0
Typ
5.25
3.3
Max
5.5
Unit
V
programming voltage
VDDA(FRO)(3V3)
free running oscillator analog
supply voltage (3.3 V)
3.6
V
VDDA(PLL)(3V3)
VDDD(3V3)
PLL analog supply voltage (3.3 V)
digital supply voltage (3.3 V)
HDMI supply voltage (3.3 V)
core supply voltage (1.8 V)
3.0
3.0
3.0
1.65
1.65
-
3.3
3.3
3.3
1.8
1.8
0.1
3.6
3.6
3.6
1.95
1.95
1
V
V
VDDH(3V3)
V
VDDC(1V8)
V
VDDA(PLL)(1V8)
IDDA(FRO)(3V3)
PLL analog supply voltage (1.8 V)
V
free running oscillator analog
supply current (3.3 V)
mA
[1][2]
[1][4]
IDDA(PLL)(3V3)
IDDD(3V3)
PLL analog supply current (3.3 V)
digital supply current (3.3 V)
HDMI supply current (3.3 V)
PLL analog supply current (1.8 V)
core supply current (1.8 V)
input 1080i, output 1080p
input 1080p, output 1080p
-
-
-
-
-
6
6.4
5
mA
mA
mA
mA
mA
-
IDDH(3V3)
14
75
283
15
92
345
[1][2]
[1][2]
IDDA(PLL)(1V8)
IDDC(1V8)
input 1080i, output 1080p
input 1080i, output 1080p
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Table 22. Supplies …continued
VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; unless otherwise specified.
Typical values are measured at Tamb = 25 °C and fclk = 150 MHz.
Symbol
Parameter
Conditions
Min
Typ
500
742
320
Max
630
940
400
Unit
mW
mW
mW
[1][3]
[1][2]
[1][4]
Pcons
power consumption
input 480p, output 1080p
input 1080i, output 1080p
input 1080p, output 1080p
TMDS output current added
input 480p, output 1080p
input 1080i, output 1080p
input 1080p, output 1080p
-
-
-
Ptot
total power dissipation
[1][3]
[1][2]
[1][4]
-
-
-
-
630
872
450
30
770
mW
1080 mW
540
40
mW
mW
Ppd
power dissipation in power-down
mode
[1] The maximum current consumption is in this configuration for this group of pins.
[2] Video format:
a) Input 1080i, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels.
b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF.
[3] Video format:
a) Input 480p, ITU656 embedded sync, 48 kHz S/PDIF 2 channels.
b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF.
[4] Video format:
a) Input 1080p, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels.
b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF.
Table 23. LV-TTL digital inputs
VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; typical values are measured at Tamb = 25 °C; unless
otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE
and RST_N
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.8
-
V
V
2.0
5 V tolerant input: pin HPD
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.8
-
V
V
2.0
Output: pin INT
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
CL = 10 pF; IOL = 2 mA
-
-
-
0.4
-
V
V
CL = 10 pF; IOH = −2 mA
2.4
Table 24. TMDS outputs
VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; typical values are measured at Tamb = 25 °C; unless
otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2−, TX2+, TXC− and TXC+
VO(dif)
differential output voltage
REXT_SWING = 610 Ω (1 % tolerance);
RL = 50 Ω
480
525
560
mV
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13. Dynamic characteristics
Table 25. Timing characteristics
VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; typical values are measured at Tamb = 25 °C; unless
otherwise specified.
Symbol
Video inputs; see Figure 17
fclk(max) maximum clock frequency
δclk
Parameter
Conditions
Min
Typ
Max
Unit
pin VCLK
pin VCLK
150
40
-
-
MHz
%
clock duty cycle
50
-
60
-
tsu(D)
data input set-up time
data input hold time
1.0
0.8
ns
th(D)
-
-
ns
Audio input
S/PDIF mode
fs
sampling frequency
2 channels
32
-
-
-
-
-
192
75
-
kHz
MHz
ns
[1]
[1]
fclk
clock frequency
clock period
pin AP5 (MCLK)
pin AP5 (MCLK)
Tclk
13.3
40
δclk
clock duty cycle
60
%
HBR mode
fs
sampling frequency
-
192
192
192
-
kHz
kHz
MHz
I2S-bus mode
fs sampling frequency
TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2−, TX2+, TXC− and TXC+
fclk(max) maximum clock frequency
DDC-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL
32
150
-
-
fSCL
SCL clock frequency
Standard-mode
-
-
-
-
100
400
kHz
kHz
Fast-mode
I2C-bus; 5 V tolerant; slave bus: pins I2C_SDA and I2C_SCL
fSCL
SCL clock frequency
Standard-mode
Fast-mode
-
-
-
-
100
400
kHz
kHz
[1] In case of MCLK is required, this frequency has to be coherent with S/PDIF input.
TDA9984A_4
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Product data sheet
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TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
VCLK
VPA[7:0]
VPB[7:0]
VPC[7:0]
DE, HSYNC, VSYNC
001aag604
t
t
h(D)
su(D)
a. Sync on rising edge
VCLK
VPA[7:0]
VPB[7:0]
VPC[7:0]
DE, HSYNC, VSYNC
001aag605
t
t
h(D)
su(D)
b. Sync on falling edge
VCLK
VPA[7:0]
VPB[7:0]
VPC[7:0]
DE, HSYNC, VSYNC
t
t
t
t
h(D)
su(D)
h(D)
su(D)
001aag606
c. Sync on rising and falling (double) edge
Data is not allowed to change in the shaded area.
Fig 17. Set-up and hold time for various clock modes
13.1 Input format
Mapping of the video ports:
• Port VPA has been mapped to Cb for YCbCr space and B for RGB color space
• Port VPB has been mapped to Y for YCbCr space and G for RGB color space
• Port VPC has been mapped to Cr for YCbCr space and R for RGB color space
Table 26. Input format
Input pins Signal
RGB
YCbCr
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2 (semi-planar)
4 : 2 : 2 (ITU656-like)[1]
Video port A
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
Cb[0]/B[0]
Cb[1]/B[1]
Cb[2]/B[2]
Cb[3]/B[3]
Cb[4]/B[4]
Cb[5]/B[5]
Cb[6]/B[6]
Cb[7]/B[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
Cb[0]
Cb[1]
Cb[2]
Cb[3]
Cb[4]
Cb[5]
Cb[6]
Cb[7]
Y0[0]
Y0[1]
Y0[2]
Y0[3]
Cb[0]
Cb[1]
Cb[2]
Cb[3]
Y1[0]
Y1[1]
Y1[2]
Y1[3]
Cr[0]
Cr[1]
Cr[2]
Cr[3]
Cb[0]
Cb[1]
Cb[2]
Cb[3]
L
Y0[0]
Y0[1]
Y0[2]
Y0[3]
L
Cr[0]
Cr[1]
Cr[2]
Cr[3]
L
Y1[0]
Y1[1]
Y1[2]
Y1[3]
L
L
L
L
L
L
L
L
L
L
L
L
L
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
32 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
Table 26. Input format …continued
Input pins Signal
RGB
YCbCr
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2 (semi-planar)
4 : 2 : 2 (ITU656-like)[1]
Video port B
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
VPB[6]
VPB[7]
Video port C
VPC[0]
VPC[1]
VPC[2]
VPC[3]
VPC[4]
VPC[5]
VPC[6]
VPC[7]
Y[0]/G[0]
Y[1]/G[1]
Y[2]/G[2]
Y[3]/G[3]
Y[4]/G[4]
Y[5]/G[5]
Y[6]/G[6]
Y[7]/G[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Y0[4]
Y0[5]
Y0[6]
Y0[7]
Y0[8]
Y0[9]
Y0[10]
Y0[11]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
Y1[10]
Y1[11]
Cb[4]
Cb[5]
Cb[6]
Cb[7]
Cb[8]
Cb[9]
Cb[10]
Cb[11]
Y0[4]
Y0[5]
Y0[6]
Y0[7]
Y0[8]
Y0[9]
Y0[10]
Y0[11]
Cr[4]
Cr[5]
Cr[6]
Cr[7]
Cr[8]
Cr[9]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
Cr[10] Y1[10]
Cr[11] Y1[11]
Cr[0]/R[0]
Cr[1]/R[1]
Cr[2]/R[2]
Cr[3]/R[3]
Cr[4]/R[4]
Cr[5]/R[5]
Cr[6]/R[6]
Cr[7]/R[7]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
Cr[0]
Cr[1]
Cr[2]
Cr[3]
Cr[4]
Cr[5]
Cr[6]
Cr[7]
Cb[4]
Cb[5]
Cb[6]
Cb[7]
Cb[8]
Cb[9]
Cr[4]
Cr[5]
Cr[6]
Cr[7]
Cr[8]
Cr[9]
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Cb[10] Cr[10]
Cb[11] Cr[11]
[1] L stands for tying to LOW voltage recommendation, e.g. ground.
TDA9984A_4
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Product data sheet
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33 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
13.2 Timing parameters for supported video
The TDA9984A supports all EIA/CEA-861B standards and ATSC video input formats.
Table 27. Timing parameters for EIA/CEA-861B
Format
Format
V frequency H total V total
(Hz)
H frequency Pixel frequency Pixel
Scaler
(kHz)
(MHz)
repetition
59.94 Hz systems
1 (VGA)
640 × 480p
59.9401
59.9401
59.9401
800
525
525
750
1125
525
262
263
525
262
263
525
1125
31.469
31.469
44.955
33.716
15.734
15.734
15.734
15.734
15.734
15.734
31.469
67.432
25.175
27.000
74.175
74.175
27.000
27.000
27.000
54.000
54.000
54.000
54.000
148.350
1
-
2, 3
4
720 × 480p
858
1
X
X
X
X
-
1280 × 720p
1650
2200
1716
1716
1716
3452
3452
3452
1716
2200
1
5
1920 × 1080i 59.9401
1
6, 7 (NTSC) 1440 × 480i
59.9401
59.9401
59.9401
59.9401
59.9401
59.9401
59.9401
2
8, 9
1440 × 240p
1440 × 240p
2880 × 480i
2880 × 240p
2880 × 240p
1440 × 480p
2
8, 9
2
-
10, 11
12, 13
12, 13
14, 15
16
4[1]
4[1]
4[1]
2
-
-
-
-
1920 × 1080p 59.9401
1
-
60 Hz systems
1 (VGA)
640 × 480p
60.000
60.000
60.000
800
525
525
750
1125
525
262
263
525
262
263
525
1125
31.500
31.500
45.000
33.750
15.750
15.750
15.750
15.750
15.750
15.750
31.500
67.500
25.200
27.027
74.250
74.250
27.027
27.027
27.027
54.054
54.054
54.054
54.054
148.50
1
-
2, 3
4
720 × 480p
858
1
X
X
X
X
-
1280 × 720p
1650
2200
1716
1716
1716
3452
3452
3452
1716
2200
1
5
1920 × 1080i 60.000
1
6, 7 (NTSC) 1440 × 480i
60.000
60.000
60.000
60.000
60.000
60.000
60.000
2
8, 9
1440 × 240p
1440 × 240p
2880 × 480i
2880 × 240p
2880 × 240p
1440 × 480p
2
8, 9
2
-
10, 11
12, 13
12, 13
14, 15
16
4[1]
4[1]
4[1]
2
-
-
-
-
1920 × 1080p 60.000
1
-
50 Hz systems
17, 18
19
720 × 576p
1280 × 720p
50.000
50.000
864
625
750
1125
625
312
313
314
625
312
313
31.250
37.500
28.125
15.625
15.625
15.625
15.625
15.625
15.625
15.625
27.000
74.250
74.250
27.000
27.000
27.000
27.000
54.000
54.000
54.000
1
X
X
X
X
-
1980
2640
1728
1728
1728
1728
3456
3456
3456
1
20
1920 × 1080i 50.000
1
21, 22 (PAL) 1440 × 576i
50.000
50.000
50.000
50.000
50.000
50.000
50.000
1
23, 24
23, 24
23, 24
25, 26
27, 28
27, 28
1440 × 288p
1440 × 288p
1440 × 288p
2880 × 576i
2880 × 288p
2880 × 288p
2
2
-
2
-
4[1]
4[1]
4[1]
-
-
-
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
34 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
Table 27. Timing parameters for EIA/CEA-861B …continued
Format
Format
V frequency H total V total
(Hz)
H frequency Pixel frequency Pixel
Scaler
(kHz)
(MHz)
54.000
54.000
148.50
repetition
27, 28
29, 30
31
720 × 288p
50.000
50.000
3456
1728
2640
314
15.625
31.250
56.250
4
2
1
-
-
-
1440 × 576p
625
1920 × 1080p 50.000
1125
[1] The format can also be defined with a repetition factor of up to 10.
Table 28. Timing parameters for ATSC DTV standards, which are not defined in EIA/CEA-861B
Standard
Format
V frequency H total V total
(Hz)
H frequency Pixel frequency Pixel
Scaler
(kHz)
(MHz)
74.250
74.175
74.250
74.175
repetition
SMPTE-296M 1280 × 720p 30.000
3300
3300
3960
4125
750
750
750
750
22.500
22.478
18.750
17.982
1
1
1
1
-
-
-
-
29.970
25.000
23.976
Table 29. Timing parameters for PC standards below 165 MHz
Standard
Format
V frequency H total V total
(Hz)
H frequency Pixel frequency Pixel
Scaler
(kHz)
(MHz)
repetition
640 × 350p
640 × 400p
720 × 400p
640 × 480p
85.080
85.080
85.039
59.9401
72.809
75.000
85.008
56.250
60.317
72.188
75.000
85.061
60.004
70.069
75.029
84.997
86.957
75.000
85.000
60.000
85.002
832
445
445
446
525
525
500
520
625
628
666
625
631
806
806
800
808
817
900
907
1000
1011
1066
1066
37.861
37.861
37.937
31.469
37.861
37.500
43.269
35.156
37.879
48.077
46.875
53.673
48.362
56.476
60.023
68.677
35.522
67.500
77.094
60.000
85.937
63.981
79.977
31.500
31.500
35.500
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
94.500
44.900
108.000
121.500
108.000
148.450
108.000
135.000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
832
936
VGA
800
832
840
832
SVGA
800 × 600p
1024
1056
1040
1056
1048
1344
1328
1312
1376
1264
1600
1576
1800
1728
1688
1688
XGA
1024 × 768p
1024 × 768i
1152 × 864p
1280 × 960p
SXGA
1280 × 1024p 60.002
75.025
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
35 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
14. Package outline
HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad
SOT841-4
c
y
exposed die pad
X
D
h
A
60
41
Z
61
40
E
e
(A )
3
A
A
2
E
E
H
E
h
M
w
θ
b
p
A
1
L
p
L
detail X
pin 1 index
80
21
1
20
M
v
v
A
M
w
Z
D
b
p
e
D
B
M
H
D
B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
1
A
2
A
3
b
c
D
D
E
E
e
H
D
H
E
L
L
v
w
y
Z
Z
θ
p
h
h
p
D
E
max
°
°
0.15 1.05
0.05 0.95
0.27 0.20 12.1 4.79 12.1 4.79
0.17 0.09 11.9 4.69 11.9 4.69
14.15 14.15
13.85 13.85
0.75
0.45
1.45 1.45
1.05 1.05
7
0
mm
1.2
0.25
0.5
1
0.2 0.08 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
06-04-25
06-06-20
SOT841-4
MS-026
Fig 18. Package outline SOT841-4 (HTQFP80)
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
36 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
15. Abbreviations
Table 30. Abbreviations
Acronym
ACR
Description
Audio Clock Recovery
AV
Audio Video
CMOS
CTS
Complementary Metal-Oxide Semiconductor
Clock Time Stamp
CTS/N
DDC
Clock Time Stamp integer divider
Display Data Channel
DE
Data Enable
DTS
Digital Transmission System
Desk Top Video
DTV
DVD
Digital Versatile Disc
DVI
Digital Visual Interface
EAV
End Active Video
EDID
E-EDID
FREF
HBR
Extended Display Identification Data
Enhanced Extended Display Identification Data
Field REFerence
High Bit Rate
HD
High Definition
HDCP
HDMI
HDTV
HREF
HSYNC
KSV
High-bandwidth Digital Content Protection
High-Definition Multimedia Interface
High-Definition Television
Horizontal REFerence
Horizontal SYNChronization
Key Selection Vector
LSB
Least Significant Bit
LV-TTL
MSB
Low Voltage Transistor-Transistor Logic
Most Significant Bit
NTSC
OTP
National Television System Committee
One Time Programming
PAL
Phase Alternated Line
PCM
Pulse Code Modulation
PLL
Phase-Locked Loop
SAV
Start Active Video
SHA-1
S/PDIF
TMDS
VHREF
VREF
VSYNC
YCbCr
Secure Hash Algorithm 1
Sony/Philips Digital Interface
Transition Minimized Differential Signalling
Vertical Horizontal REFerence
Vertical REFerence
Vertical SYNChronization
Y = luminance, Cb = Chroma component blue, Cr = Chroma component red
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
37 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
16. Revision history
Table 31. Revision history
Document ID
TDA9984A_4
Modifications:
Release date
20090115
Data sheet status
Change notice
Supersedes
Product data sheet
TDA9984A_3
• All document: changed Y-CB-CR in YCbCr, CB in Cb and CR in Cr for consistency
• Section 1: rewritten the first sentence
• Section 2: added "Dolby-True HD and DTS-HD"
• Figure 1, Figure 2 and Table 3: updated the pins 15, 16 and 45: name and description
• Table 1: added the row VDDA(PLL)(1V8)
• Section 8.2: changed the reference HDMI 1.2a in 1.3 and in the table 15, added the column
HBR
• Section 8.2.2: updated the input clock with a frequency at 64fs
• Section 8.2.3: added this paragraph High bit rate audio
• Table 22: updated
• Table 25: added the part HBR mode
• Table 1, Table 20, Table 22, Table 23, Table 24 and Table 25: changed the temperature min
0 °C to −5 °C and temperature max 70 °C to +85 °C
TDA9984A_3
TDA9984A_2
TDA9984_1
20080410
20080115
20070723
Product data sheet
Preliminary data sheet
Objective data sheet
-
-
-
TDA9984A_2
TDA9984_1
-
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
38 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Applications — Applications that are described herein for any of these
17.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.4 Licenses
Purchase of NXP ICs with HDMI technology
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
admin@hdmi.org.
17.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA9984A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 January 2009
39 of 40
TDA9984A
NXP Semiconductors
HDMI 1.3 transmitter with 1080p upscaler embedded
19. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
8.4.2
8.4.3
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.6
8.6.1
8.6.2
8.6.2.1
8.6.2.2
8.7
TMDS output buffers . . . . . . . . . . . . . . . . . . . 24
Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 25
Control blocks. . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock management . . . . . . . . . . . . . . . . . . . . 25
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 26
Hot plug detection . . . . . . . . . . . . . . . . . . . . . 26
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power management . . . . . . . . . . . . . . . . . . . . 27
DDC-bus interface . . . . . . . . . . . . . . . . . . . . . 27
DDC-bus channel. . . . . . . . . . . . . . . . . . . . . . 27
E-EDID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
E-EDID reading . . . . . . . . . . . . . . . . . . . . . . . 27
HDMI and DVI receiver discrimination . . . . . . 27
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 28
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
4
5
6
7
7.1
8
8.1
8.1.1
8.1.2
8.1.2.1
8.1.2.2
Functional description . . . . . . . . . . . . . . . . . . . 8
Video processing . . . . . . . . . . . . . . . . . . . . . . . 8
Internal assignment . . . . . . . . . . . . . . . . . . . . . 8
Input format mappings . . . . . . . . . . . . . . . . . . . 9
RGB 4 : 4 : 4 external sync input (rising edge) 11
YCbCr 4 : 4 : 4 external sync input
(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
YCbCr 4 : 2 : 2 ITU656-like external
sync input (rising edge) . . . . . . . . . . . . . . . . . 13
YCbCr 4 : 2 : 2 ITU656-like external
sync input (rising and falling) . . . . . . . . . . . . . 14
YCbCr 4 : 2 : 2 ITU656-like embedded
sync input (rising edge) . . . . . . . . . . . . . . . . . 15
YCbCr 4 : 2 : 2 ITU656-like embedded
sync input (rising and falling) . . . . . . . . . . . . . 16
YCbCr 4 : 2 : 2 semi-planar external input
(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
YCbCr 4 : 2 : 2 semi-planar embedded
9
9.1
9.2
I2C-bus registers definitions . . . . . . . . . . . . . 28
Memory page management . . . . . . . . . . . . . . 28
ID version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1.2.3
8.1.2.4
8.1.2.5
8.1.2.6
8.1.2.7
8.1.2.8
10
11
12
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29
Thermal characteristics . . . . . . . . . . . . . . . . . 29
Static characteristics . . . . . . . . . . . . . . . . . . . 29
13
13.1
13.2
Dynamic characteristics. . . . . . . . . . . . . . . . . 31
Input format . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Timing parameters for supported video . . . . . 34
14
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision history . . . . . . . . . . . . . . . . . . . . . . . 38
sync input (rising edge) . . . . . . . . . . . . . . . . . 18
Synchronization . . . . . . . . . . . . . . . . . . . . . . . 19
Timing extraction generator . . . . . . . . . . . . . . 19
Data enable generator . . . . . . . . . . . . . . . . . . 19
Input and output video format. . . . . . . . . . . . . 19
Scaler unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Scaler features . . . . . . . . . . . . . . . . . . . . . . . . 19
Input and output video scaler . . . . . . . . . . . . . 20
Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Color space converter. . . . . . . . . . . . . . . . . . . 21
Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 21
Audio processing . . . . . . . . . . . . . . . . . . . . . . 21
S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
High bit rate audio. . . . . . . . . . . . . . . . . . . . . . 23
HDCP processing . . . . . . . . . . . . . . . . . . . . . . 23
High-bandwidth digital content protection. . . . 23
Repeater function . . . . . . . . . . . . . . . . . . . . . . 23
SHA-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TMDS serializer . . . . . . . . . . . . . . . . . . . . . . . 23
RxSense detection . . . . . . . . . . . . . . . . . . . . . 23
17
Legal information . . . . . . . . . . . . . . . . . . . . . . 39
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1.3
8.1.3.1
8.1.3.2
8.1.4
8.1.5
8.1.5.1
8.1.5.2
8.1.6
8.1.7
8.1.8
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.1.1
8.3.1.2
8.4
17.1
17.2
17.3
17.4
17.5
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 39
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 January 2009
Document identifier: TDA9984A_4
相关型号:
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