TEA1755LT/1Y [NXP]
TEA1755LT - HV start-up DCM/QR flyback controller with integrated DCM/QR PFC controller SOP 16-Pin;
| 型号： | TEA1755LT/1Y |
| 厂家： | 
NXP |
| 描述： | TEA1755LT - HV start-up DCM/QR flyback controller with integrated DCM/QR PFC controller SOP 16-Pin 功率因数校正 光电二极管 |
| 文件： | 总35页 (文件大小：919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TEA1755LT
HV start-up DCM/QR flyback controller with integrated
DCM/QR PFC controller
Rev. 1 — 25 October 2012
Product data sheet
1. General description
The GreenChip is the latest generation of green Switched Mode Power Supply (SMPS)
controller ICs. The TEA1755LT combines a controller for Power Factor Correction (PFC)
and a flyback controller. Its high level of integration enables cost-effective power supply
design using a very low number of external components.
The PFC operates in Quasi-Resonant (QR) or Discontinuous Conduction Mode (DCM),
with valley switching.
The specially built-in green functions provide high efficiency at all power levels. At high
power levels the flyback operates in QR mode or DCM with valley detection. At medium
power levels, the flyback controller switches to Frequency Reduction (FR) mode and limits
the peak current to an adjustable minimum value. In low power mode, the PFC switches
off to maintain high efficiency. At very low power levels, when the flyback switching
frequency drops below 25 kHz, the flyback converter switches to burst mode. During the
non-switching phase of burst mode, the internal IC supply current is minimized to further
optimize efficiency. Valley switching is used in all operating modes.
The advanced burst mode ensures high efficiency at low power and good standby power
performance while minimizing audible transformer noise.
The TEA1755LT is a Multi-Chip Module, (MCM), containing two chips. The proprietary
high-voltage BCD800 process makes direct start-up possible from the rectified universal
mains voltage in an effective and green way. The second low voltage Silicon-On-Insulator
(SOI) is used for accurate, high-speed protection functions and control.
The TEA1755LT enables easy design of highly efficient and reliable supplies up to 250 W.
These power supply designs are cost-effective, requiring the minimum number of external
components.
Remark: All values in this document are typical values unless otherwise stated.
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
2. Features and benefits
2.1 Distinctive features
Integrated PFC and flyback controller
Universal mains supply operation between 70 V (AC) to 276 V (AC)
Dual-boost PFC with accurate maximum output voltage (NXP Semiconductors
patented)
High level of integration, results in cost-effective designs with very low external
component counts
Adjustable PFC switch off delay
External PFC switch on and switch off override
Accurate PFC switch on and switch off control (NXP Semiconductors patent pending)
2.2 Green features
On-chip start-up current source
Reduced IC supply current during burst mode enabling ErP lot 6
Power-down functionality for very low standby power
2.3 PFC green features
Valley/Zero-Voltage Switching (ZVS) for minimum switching losses
(NXP Semiconductors patented)
Frequency limitation reduces switching losses
PFC switched off when a low-load is detected at the flyback output
2.4 Flyback green features
Valley switching for minimum switching losses (NXP Semiconductors patented)
Frequency reduction with adjustable minimum peak current at low-power operation
maintains high-efficiency at low output power levels
Burst mode operation at very low-power levels for high-efficiency operation
2.5 Protection features
Safe restart mode for system fault conditions
Continuous mode protection using demagnetization detection for both converters
(NXP Semiconductors patented)
UnderVoltage Protection (UVP) (foldback during overload)
Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback
converter)
Mains voltage independent OverPower Protection (OPP)
Open control loop protection for both converters. The open-loop protection on the
flyback converter is latched
OverTemperature Protection (OTP)
Low and adjustable OverCurrent Protection (OCP) trip level for both converters
General-purpose input for latched protection, for use with system OverTemperature
Protection (OTP)
TEA1755LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
2 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
3. Applications
The device can be used in all applications requiring an efficient and cost-effective
power supply solution for up to 250 W. Notebook adapters in particular benefit from the
high level of integration
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
TEA1755LT/1
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
5. Block diagram
PFCDRIVER
12
FBDRIVER
13
V
en(PFC)FBCTRL
PFC driver
PFC gate
flyback driver
30.5 μA
3.5 V
PFC(swon)
PFC(swoff)
CONTROL
low power
driver
driver
5
LATCH
external
protection
power
down
low Vin
dual
boost
flyback gate
494 V
5.5 V
VINSENSE
PFCCOMP
7
6
protection
R
R
Q
S
PFC
protection
MAXIMUM
3.75 V
protection
enable PFC
Q
7.0 V
frequency
reduction
burst mode
latch
reset
S
enable flyback
29 μA
clamp
V
en(PFC)FBCTRL
PFC
FLYBACK
OSCILLATOR
OSCILLATOR
time-out
3
FBCTRL
t
on(max)
PFC clamp
2.5 V
dual
boost
frequency burst mode
reduction
V
good
CC
VOSENSE
9
t
on
low power delay
burst mode
8.1 μA
1.92 V
MINIMUM
REDUCTION
NEAR OVP
SMPS
CONTROL
3.32 V
OPP
V
th(burst)
start flyback
start stop PFC
dual boost
external protection
OCP
PFC clamp
low Vin
V
OVP
o
clamp
PFC
time-out
external protection
OTP
S
S
S
S
R
flyback driver
BLANK
protection
V
th(VOSENSE)
10
FBSENSE
LATCHED
low power
delay
PROTECTION
OVP flyback
latch reset
OCP
protection
ton max
S
R
S
SAFE
60 μA
2.1 μA
enable flyback
start flyback
PFC driver
BLANK
V
UVLO
RESTART
495 mV
60 μA
V
th(VOSENSE)
PFCSENSE 11
PROTECTION
START
power down
enable PFC
SOFT
power down
protection
V
good
SOFT START
SOFT STOP
CC
start stop PFC
CHARGE
CONTROL
external protection
charge
V
startup
OPP
OVP
OPP
V
th(UVLO)
TIMER 4.2 μs
VALLEY
DETECT
VALLEY
DETECT
OVP
flyback
COUNTER
OTP
internal supply
PFCAUX
8
4
FBAUX
flyback
gate
charge
ZERO
CURRENT
SIGNAL
V
V
V
startup
ZERO CURRENT
SIGNAL
PFC gate
th(burst)
th(UVLO)
TIMER 48 μs
90 mV
TEMPERATURE
OTP
-90 mV
low power
low power
delay
DELAY
14
2
16
HV
1
aaa-004601
PFCTIMER
V
GND
CC
Fig 1. TEA1755LT block diagram
TEA1755LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
3 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
6. Pinning information
6.1 Pinning
ꢔ
ꢕ
ꢖ
ꢗ
ꢘ
ꢙ
ꢚ
ꢛ
ꢔꢙ
ꢔꢘ
ꢔꢗ
ꢔꢖ
ꢔꢕ
ꢔꢔ
ꢔꢜ
ꢝ
ꢂ
ꢃꢂ
ꢁꢁ
ꢄꢅꢆ
ꢈꢉꢁꢊꢋꢌ
ꢈꢉꢐꢑꢒ
ꢃꢂꢇ
ꢍꢈꢁꢊꢀꢎꢏꢋ
ꢈꢉꢆꢋꢀꢂꢏꢋ
ꢍꢈꢁꢆꢋꢀꢂꢏꢋ
ꢍꢈꢁꢇꢏꢅꢇꢏ
ꢈꢉꢇꢏꢅꢇꢏ
ꢂꢓꢇꢏꢅꢇꢏ
ꢀꢁ
ꢌꢐꢊꢁꢃ
ꢍꢈꢁꢁꢓꢎꢍ
ꢂꢀꢅꢇꢏꢅꢇꢏ
ꢍꢈꢁꢐꢑꢒ
ꢀꢀꢀꢁꢂꢂꢃꢄꢃꢅ
Fig 2. TEA1755LT pin configuration (SOT109-1)
6.2 Pin description
Table 2.
Symbol
Pin description
Pin Description
VCC
1
2
supply voltage
ground
GND
FBCTRL
FBAUX
3
flyback control input
4
auxiliary winding input for demagnetization timing and flyback OVP
general-purpose protection input
LATCH
5
PFCCOMP
VINSENSE
PFCAUX
VOSENSE
FBSENSE
6
PFC frequency compensation
7
mains voltage sense input
8
auxiliary winding input for demagnetization timing of the PFC
sense input for PFC output voltage
flyback current sense input
9
10
PFCSENSE 11
PFCDRIVER 12
PFC current sense input
PFC gate-driver output
FBDRIVER
PFCTIMER
HVS
13
14
15
16
flyback gate-driver output
PFC override and switch off delay timer
high-voltage safety spacer; not connected
high-voltage start-up and flyback valley sensing
HV
TEA1755LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
4 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
7. Functional description
7.1 General control
The TEA1755LT contains a power factor correction circuit controller and a flyback circuit
controller. A typical configuration is shown in Figure 3.
D
2
Tr1
C
R
bulk
DRV1
R
R4
R5
S1
Tr2
R
D4
COMP
S2
V
OUT
C6
(1)
C
D1
R
SS1
SS1
SENSE1
C1
R
AUX1
R
DRV2
Z1
R
S1
OPTO-
FEEDBACK
V
mains
C
SS2
R
SS2
R
12 11
9
16 13
PFCAUX
R
R
S3
S2
FBSENSE
FBAUX
8
10
C3
C4
R3
PFCCOMP
6
R
SENSE2
FBAUX
D3
IC
R1
VINSENSE
FBCTRL
4
7
3
V
CC
1
5
LATCH
R2
C2
2
14
GND
PFCTIMER
R
C
VCC
NTC
C
C5
PFCTIMER
R
LOOP
C
TIMEOUT
OPTO-FEEDBACK
aaa-002624
(1) The HV pin can either be connected to the center tap of the flyback transformer or to the drain of MOSFET S2.
Fig 3. A typical TEA1755LT configuration
7.1.1 Start-up and UnderVoltage LockOut (UVLO)
Initially, the capacitor on the VCC pin is charged from the high-voltage mains using the HV
pin.
When VCC is less than Vtrip, the charge current is Ich(low). This low current protects the IC if
the VCC pin is shorted to ground. To ensure a short start-up time, the charge current above
the Vtrip level is increased to Ich(high), until VCC reaches Vth(UVLO). When VCC is between
V
th(UVLO) and Vstartup, the charge current goes low again to ensure a low safe restart duty
cycle during fault conditions.
The control logic activates the internal circuitry and switches off the HV charge current
when VCC passes the Vstartup level. First, the LATCH pin current source is activated and
the soft-start capacitors on the PFCSENSE and FBSENSE pins are charged. Also the
clamp circuit on the PFCCOMP pin is activated.
The PFC circuit is activated when the following conditions are met:
TEA1755LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
5 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
• the LATCH pin voltage exceeds the Ven(LATCH) voltage
• the PFCCOMP pin charging current drops below the absolute value of the
en(PFCCOMP) current
I
• the soft-start capacitor on the PFCSENSE pin is charged
The flyback converter is also activated if the soft-start capacitor on the FBSENSE pin is
charged. The flyback converter output voltage is then regulated to its nominal output
voltage. The auxiliary winding of the flyback converter takes over the IC supply. See
Figure 4.
If during start-up, the LATCH pin does not reach the Ven(LATCH) level before VCC reaches
V
th(UVLO), the LATCH pin output is deactivated. The charge current is switched on again.
When the flyback converter is started, VFBCTRL is monitored. If the output voltage does not
reach its intended regulation level within a specified time, VFBCTRL reaches the Vto(FBCTRL)
level. An error is then assumed and a latched protection is initiated.
When one of the safe restart or latched protection functions are triggered, both converters
stop switching and the VCC voltage drops to Vth(UVLO). A latched protection recharges
capacitor CVCC using the HV pin, but does not restart the converters. To provide safe
restart protection, the capacitor is recharged using the HV pin and the device restarts (see
block diagram, Figure 1).
If OVP is triggered on the PFC circuit (VVOSENSE > VOVP(VOSENSE)), the PFC controller
stops switching until the VVOSENSE < VOVP(VOSENSE). If a mains UVP is detected,
V
V
VINSENSE < Vstop(VINSENSE), the PFC controller stops switching until
VINSENSE > Vstart(VINSENSE) again.
When the VCC pin voltage drops under the UVLO level, both controllers stop switching and
enter safe restart mode. In the safe restart mode, the VCC pin capacitor is recharged using
the HV pin.
At very low burst mode repetition rates, VCC can drop under the UVLO level. The UVLO
protection feature Vprot(UVLO) prevents the decrease when the IC is in burst mode.
TEA1755LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
6 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
I
HV
V
startup
V
V
th(UVLO)
trip
V
CC
V
start(VINSENSE)
en(PFCCOMP)
VINSENSE
V
PFCCOMP
LATCH
V
en(LATCH)
PROTECTION
soft start
PFCSENSE
PFCDRIVER
soft start
FBSENSE
FBDRIVER
FBCTRL
V
to(FBCTRL)
start(fb)
V
VOSENSE
V
O
charging VCC
capacitor
starting
converters
normal
operation
protection
restart
014aaa744
Fig 4. Start-up sequence, normal operation and restart sequence
7.1.2 Power-down mode
The power-down mode can be activated for very low standby power applications by
pulling the VVINSENSE < Vth(pd) level. The TEA1755LT stops switching and safe restart
protection is activated. The high voltage start-up current source is also disabled during
power-down and the TEA1755LT does not restart until VVINSENSE is raised again.
During Power-down mode, all internal circuitry is disabled except for a voltage detection
circuit on the VINSENSE pin. This circuit is supplied by the HV pin and draws 12 A from
the HV pin for biasing.
TEA1755LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
7 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
7.1.3 Supply management
All internal reference voltages are derived from a temperature compensated and trimmed
on-chip band gap circuit. Internal reference currents are derived from a temperature
compensated and trimmed on-chip current reference circuit.
7.1.4 Latch input
The LATCH pin is a general-purpose input pin which is used to switch off both converters.
The pin sources a current IO(LATCH) of 30.5 A. Switching of both converters is stopped
when VLATCH is < 494 mV.
At initial start-up, switching is prevented until the capacitor on the LATCH pin is charged
above 582 mV. No internal filtering is performed on this pin. An internal 1.75 V clamp
protects the pin from excessive voltages.
7.1.5 Fast latch reset
In a typical application, the mains can be interrupted briefly to reset the latched protection.
The bulk capacitor Cbulk does not have to discharge for this latched protection to reset.
When the VINSENSE voltage drops below 750 mV and is then raised to 860 mV, the
latched protection is reset.
The latched protection is also reset by removing both the voltage on the VCC and HV pins.
7.1.6 Overtemperature protection
An accurate internal temperature protection is provided in the IC. When the junction
temperature exceeds the thermal shut-down temperature, the IC stops switching. While
OTP is active, the capacitor CVCC is not recharged from the HV mains. If the VCC supply
voltage is not sufficient, the OTP circuit is supplied from the HV pin.
OTP is a latched protection. It is reset by removing the voltage from both the VCC and HV
pins or by the fast latch reset function (see Section 7.1.5).
7.2 Power factor correction circuit
The Power Factor Correction (PFC) circuit operates in Quasi-Resonant (QR) or
Discontinuous Conduction Mode (DCM) with valley switching. The next primary stroke is
only started when the previous secondary stroke has ended and the voltage across the
PFC MOSFET has reached the minimum value.
VPFCAUX is used to detect transformer demagnetization and the minimum voltage across
the external PFC MOSFET switch.
7.2.1 ton control (PFCCOMP pin)
The power factor correction circuit is operated in ton control. The resulting mains harmonic
reduction is well within the class-D requirements.
VPFCCOMP determines the on-time of the PFC. The VVOSENSE is the transconductance
amplifier input which outputs current to the PFCCOMP pin. The regulation
V
VOSENSE = 2.5 V. The network connected to the PFCCOMP pin and the
transconductance amplifier determine the dynamic behavior of the PFC control.
TEA1755LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
8 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
Operating near the PFC OVP level causes the PFC stage on-time to decrease rapidly to
zero.
To reduce the response time, in case of load variation, the PFCCOMP pin is clamped to a
minimum level of 2 V during PFC operation. Clamping prevents the on-time increasing too
much and improves the PFC response time when the load decreases again.
7.2.2 Valley switching and demagnetization (PFCAUX pin)
The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry
connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the
voltage across the PFC MOSFET. To reduce switching losses and ElectroMagnetic
Interference (EMI), the next stroke is started when the voltage across the PFC MOSFET
is at its minimum (valley switching).
If a demagnetization signal is not detected on the PFCAUX pin, the controller generates a
Zero-Current Signal (ZCS) 48 s after the last PFC MOSFET gate signal.
If valley signal is not detected on the PFCAUX pin, the controller generates a valley signal
4.2 s after demagnetization is detected.
To protect the internal circuitry during, for example, lightning events, add a 5 k series
resistor to the PFCAUX pin. To prevent incorrect switching due to external interference,
place the resistor close to the IC on the PCB.
7.2.3 Frequency limitation
To optimize the transformer and minimize switching losses, the switching frequency is
limited to fsw(PFC)max. If the frequency for quasi-resonant operation is above the fsw(PFC)max
limit, the system switches to DCM. The PFC MOSFET is only switched on at a minimum
voltage across the switch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)
The equation for the transfer function of a power factor corrector contains the square of
the mains input voltage. In a typical application, this results in a low bandwidth for low
mains input voltages. At high mains input voltages, the Mains Harmonic Reduction (MHR)
requirements are hard to meet.
To compensate for the influence of the mains input voltage, the TEA1755LT contains a
correction circuit. The average input voltage is measured using the VINSENSE pin and
the information is fed to an internal compensation circuit. Using this compensation, it is
possible to keep the regulation loop bandwidth constant over the mains input range. This
feature gives a fast transient response on load steps while still complying with class-D
MHR requirements.
In a typical application, a resistor and two capacitors connected to the PFCCOMP pin set
the regulation loop bandwidth.
7.2.5 Soft-start (PFCSENSE pin)
To prevent audible transformer noise at start-up or during hiccup, the soft-start function
slowly increases the transformer peak current. Place a capacitor CSS1 in parallel with
resistor RSS1 (see Figure 5) to implement a soft-start function. An internal current source
charges the capacitor to:
TEA1755LT
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
9 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
VPFCSENSE = IstartsoftPFC RSS1
The voltage is limited to Vstart(soft)PFC
(1)
.
The start level and time constant of the increasing primary current level is externally
adjusted by changing the RSS1 and CSS1 values.
(2)
soft–start = 3 RSS1 CSS1
The charging current Istart(soft)PFC flows while the PFCSENSE pin voltage is < 0.5 V. If
V
PFCSENSE exceeds 0.5 V, the soft-start current source starts limiting current Istart(soft)PFC.
When the PFC starts switching, the Istart(soft)PFC current source is switched off; see
Figure 5.
S1
I
≤ 60 ꢞA
start(soft)PFC
SOFT-START
SOFT-STOP
CONTROL
R
C
SS1
SS1
11
OCP
PFCSENSE
495 mV
R
SENSE1
014aaa756
Fig 5. Soft-start of the PFC
7.2.6 PFC switch on/switch off control
When the flyback converter output power (see Section 7.3) is low, the flyback converter
switches to FR mode. When the switching frequency of the flyback in
FR mode < fsw(fb)swoff(PFC) (53 kHz), the PFC circuit is switched off to maintain high
efficiency. Connect a capacitor to the PFCTIMER pin (see Section 7.2.7) to delay the PFC
switching off.
During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of
3.32 V or 1.92 V and a maximum voltage of 3.75 V. The lower clamp voltage depends on
VVINSENSE. This voltage limits the maximum power that is delivered when the PFC is
switched on again. The upper clamp voltage ensures that the PFC returns from low-power
mode to its normal regulation point in a limited time.
In FR mode, when the flyback converter switching frequency exceeds
fsw(fb)swon(PFC) (73 kHz), the PFC circuit is switched on. If the flyback converter duty cycle
is > 50 % or VFBCTRL is > 3.75 V, the PFC circuit is also switched on.
7.2.7 PFC switch off delay (PFCTIMER pin)
When the flyback converter switching frequency in FR mode is < fsw(fb)swoff(PFC) (53 kHz),
the IC then outputs a 4.7 A current to the PFCTIMER pin. When VPFCTIMER reaches 3 V,
the PFC is switched off by performing a soft-stop.
TEA1755LT
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
10 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
A switch discharges the PFCTIMER pin capacitor when the flyback controller operating
frequency is > fsw(fb)swon(PFC) (73 kHz). At the same moment, the PFC stage is also
switched on.
Connect a capacitor to the PFCTIMER pin (see Section 7.2.7) to prevent the PFC from
switching off due to a dynamic load that leads to repetitive crossing of fsw(fb)swoff(PFC) and
fsw(fb)swon(PFC). A 1 nF minimum capacitor value is recommended to prevent noise
influencing the PFC switch on/ switch off behavior.
The PFCTIMER pin capacitor is also discharged when the flyback maximum switching
frequency is higher than 53 kHz. This feature prevents PFC on/off toggling during
dynamic loads causing the flyback to operate repetitively near fsw(fb)swoff(PFC) and
fsw(fb)swon(PFC)
.
It is also possible to control PFC switch-on and switch off externally. When VPFCTIMER is
driven below 1.03 V, the PFC stage is on. When the PFCTIMER pin voltage is driven
above 4.4 V, the PFC stage is switched off. The external control overrides the PFC stage
control by the flyback controller (see Figure 6).
The PFCTIMER pin has an internal clamp circuit starting around 10 V with a current
capability of 0.1 mA
low power
4.7 μA
4.4 V
5.5 kΩ
3 V
R
S
low power delay
(PFC on)
Q
1.03 V
R
S
Q
14
aaa-002670
PFCTIMER
Fig 6. PFC switch on and switch off using the PFCTIMER pin
7.2.8 Dual-boost PFC
The mains input voltage modulates the PFC output voltage. The mains input voltage is
measured using the VINSENSE pin. If VVINSENSE < 2.28 V, the current is sourced from the
VOSENSE pin. To ensure switch-over is stable, the current reaches its absolute maximum
value for VVINSENSE < 2.08 V, see Figure 7.
At low VINSENSE input voltages, the output current is 8.1 A. This output current, in
combination with the resistors on the VOSENSE pin, sets the lower PFC output voltage
level at low mains voltages. At high mains input voltages, the current is switched to zero.
The PFC output voltage is then at its maximum. As this current is zero in this situation, it
does not affect the accuracy of the PFC output voltage.
To ensure a correct switch-off of the application, the VOSENSE current switches to its
maximum value of 8.1 A when VVOSENSE drops below 2.1 V.
TEA1755LT
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
11 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
V
VINSENSE
2.08 V 2.28 V
-8.1 ꢞA
I
I(VOSENSE)
aaa-004486
Fig 7. Voltage to current transfer function for dual-boost PFC
7.2.9 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor, RSENSE1, on the source of the external MOSFET. The voltage is
measured using the PFCSENSE pin.
7.2.10 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, VVINSENSE is sensed
continuously. When VVINSENSE drops below the Vstop(VINSENSE) level, switching of the PFC
is stopped.
7.2.11 Overvoltage protection (VOSENSE pin)
To prevent output overvoltage during load steps and mains transients, an overvoltage
protection circuit is built in.
When VVOSENSE exceeds the VOVP(VOSENSE) level, switching of the PFC circuit is
prevented. Switching of the PFC restarts when the VOSENSE pin voltage drops below the
V
OVP(VOSENSE) level again.
OVP is also triggered when the resistor between the VOSENSE pin and ground is open.
7.2.12 PFC open-loop protection (VOSENSE pin)
The PFC circuit does not start switching until the VVOSENSE pin is greater than the
V
th(ol)(VOSENSE) level. This feature protects the application from open-loop and VOSENSE
short-circuit situations.
7.2.13 Driver (PFCDRIVER pin)
The driver circuit to the gate of the power MOSFET has a current sourcing capability of
500 mA at 2 V on the PFCDRIVER pin and a current sink capability of 1.2 A at 10 V on the
PFCDRIVER pin. These capabilities ensure fast switch-on and switch-off of the power
MOSFET for efficient operation.
7.3 Flyback controller
The TEA1755LT includes a controller for a flyback converter. The flyback converter
operates in quasi-resonant, discontinuous conduction mode or burst mode with valley
switching. The auxiliary winding of the flyback transformer provides demagnetization
detection and powers the IC after start-up.
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Product data sheet
Rev. 1 — 25 October 2012
12 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
7.3.1 Multimode operation
The TEA1755LT flyback controller can operate in several modes; see Figure 8.
flyback
switching
frequency
130 kHz
I
pmin
adjust
frequency
reduction
73 kHz
53 kHz
discontinuous
with valley
switching
PFC off
PFC on
quasi-resonant
36.5 kHz
25 kHz
burst mode
output power
aaa-002671
Fig 8. Multimode operation flyback
At high output power the converter switches to quasi-resonant mode. The next converter
stroke starts after demagnetization of the transformer and detection of the valley. In
quasi-resonant mode switching losses are minimized. This minimization is achieved by
the converter only switching on when the voltage across the external MOSFET is at its
minimum (see Section 7.3.2).
Valley switching is active in all operating modes.
To prevent high frequency operation at lower loads, the quasi-resonant operation switches
to discontinuous mode operation with valley skipping. When the frequency limit is
reached, the quasi-resonant operation changes to DCM with valley skipping. The
frequency limit reduces the MOSFET switch-on losses and conducted EMI.
At medium power levels, the controller enters Frequency Reduction (FR) mode. A Voltage
Controlled Oscillator (VCO) controls the frequency. The minimum frequency in this mode
is reduced to approximately 25 kHz. During frequency reduction mode, the primary peak
current is kept at an adjustable minimal level to maintain a high efficiency. Valley switching
is also active in this mode.
At very low power and standby levels, for which the switching frequency would drop below
25 kHz, the converter enters the burst mode. In burst mode, the switching frequency is
36.5 kHz. The primary peak current is fixed in burst mode.
In frequency reduction mode, the PFC controller switches off as soon as the flyback
switching frequency drops below 53 kHz. The flyback maximum frequency changes
linearly with the control VFBCTRL (see Figure 9). Hysteresis is added to ensure a stable
PFC switch-on and switch-off. In no-load operation, the switching frequency is reduced to
(almost) zero.
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
13 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
FR
DCM
QR
f
sw(fb)max
flyback
switching
frequency
PFC off
PFC on
QR: Quasi Resonant
DCM: Discontinuous Conduction Mode
FR: Frequency Reduction
BM: Burst Mode
burst mode
frequency
FR minimum
frequency
BM
0.77
2.4 2.8
4.0
4.9
V
(V)
FBCTRL
aaa-002672
Fig 9. Flyback frequency control
7.3.2 Valley switching (HV pin)
A new cycle starts when the external MOSFET is switched on. VFBSENSE and VFBCTRL
determine the on-time. The MOSFET is then switched off and the secondary stroke starts
(see Figure 10). After the secondary stroke, the drain voltage shows an oscillation with a
frequency of approximately:
1
f =
(3)
--------------------------------------------------
2 Lp Cd
where Lp is the primary self-inductance of the flyback transformer and Cd is the
capacitance on the drain node.
When the secondary stroke ends and the internal oscillator voltage is high again, the
circuit waits for the lowest drain voltage before starting a new primary stroke.
Figure 10 shows the drain voltage, valley signal, secondary stroke signal and the internal
oscillator signal.
Valley switching allows high frequency operation because capacitive switching losses are
reduced (see Equation 4). High frequency operation makes small and cost-effective
magnetic components possible.
1
2
2
--
P = C V f
(4)
d
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Product data sheet
Rev. 1 — 25 October 2012
14 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
primary
stroke
secondary
stroke
secondary
ringing
drain
valley
secondary
stroke
(2)
(1)
oscillator
014aaa027
(1) Start of a new cycle at lowest drain voltage.
(2) Start of a new cycle in a classical Pulse-Width Modulation (PWM) system without valley detection.
Fig 10. Signals for valley switching
7.3.3 Current mode control (FBSENSE pin)
Current mode control is used for the flyback converter because of its good line regulation.
The FBSENSE pin senses the primary current across an external resistor and compares it
to an internal control voltage. The internal control voltage is proportional to VFBCTRL (see
Figure 11).
The FBSENSE pin outputs a current of 2.1 A. This current runs through the resistors
from the FBSENSE pin to the sense resistor RSENSE and creates an offset voltage. The
minimum flyback peak current is adjusted using this offset voltage. Adjusting the minimum
peak current level, changes the frequency reduction slope (see Figure 8).
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
15 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
V
sense(fb)max
545 mV
FBSENSE
offset voltage
SENSE resistor
peak voltage
PFC off
PFC on
flyback
DCM or QR
flyback
FR mode
FBSENSE
peak voltage
232 mV
burst mode
0.77
2.8
4.0
4.9
V
(V)
FBCTRL
aaa-002673
Fig 11. Flyback part peak current control
7.3.4 Demagnetization (FBAUX pin)
The system is always in QR or DCM. The internal oscillator does not start a new primary
stroke until the previous secondary stroke has ended.
Demagnetization features a cycle-by-cycle output short-circuit protection by immediately
lowering the frequency (longer off-time) and reducing the power level.
Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time of 2.2 s.
This suppression can be necessary at low output voltages, during start-up and in
applications where the transformer has a large leakage inductance.
If the FBAUX pin is open-circuit or not connected, a fault condition is assumed and the
converter immediately stops. Operation restarts when the fault condition is removed.
7.3.5 Flyback control/time-out (FBCTRL pin)
The FBCTRL pin is connected to an internal voltage source of 7 V using an internal
13.2 k resistor. When VFBCTRL > 5.5 V, the resistor is disconnected. The pin is biased
with a 29 A current. When VFBCTRL > 7.75 V, a fault is assumed, switching is stopped and
a latched protection is activated.
If a capacitor and resistor are connected in series to the pin, a time-out function is created
which protects against open control loop situations. See Figure 12 and Figure 13. The
time-out function is disabled by connecting a resistor (200 k) to ground on the FBCTRL
pin.
If the pin is short-circuited to ground, switching of the flyback controller is stopped.
Under normal operating conditions, the converter regulates the output voltage. VFBCTRL
varies between 0.77 V at minimum output power and 4.9 V at maximum output power.
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Product data sheet
Rev. 1 — 25 October 2012
16 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
29 μA
5.5 V
7 V
7.75 V
13.2 kΩ
FBCTRL
time-out
aaa-002674
Fig 12. Time-out protection circuit
7.75 V
5.5 V
V
FBCTRL
output
voltage
intended output
latched
voltage not
reached within
time-out time.
aaa-004810
Fig 13. TEA1755LT latched time-out protection (signals)
7.3.6 Burst mode operation (FBCTRL pin)
The flyback controller enters the burst mode when the output power is very low and the
switching frequency is < 25 kHz. In burst mode, the flyback converter switching frequency
is 36.5 kHz. The minimum flyback sense voltage of 232 mV, in combination with an offset
voltage (see Section 7.3.3), determines the peak current.
A burst cycle starts when one of the following is made:
• VFBCTRL > 2.4 V
• VCC < Vprot(UVLO). This voltage level is typically 0.8 V > Vth(UVLO)
The burst cycle is stopped when VFBCTRL < 0.77 V.
In burst mode, the internal IC supply current is reduced to improve the no-load and
low-load input power.
The burst mode is exited and normal operation resumes when the VFBCTRL > 2.8 V (see
Figure 14).
TEA1755LT
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Product data sheet
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17 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
load
V
out
2.8 V
FBCTRL
2.4 V
25 kHz = flyback frequency
0.77 V
flyback active
burst mode
FBDRIVER
aaa-002676
Fig 14. Burst mode operation
7.3.7 Soft-start (FBSENSE pin)
To prevent audible transformer noise during start-up, the soft-start function slowly
increases the transformer peak current. Place a capacitor CSS2 in parallel with resistor
R
SS2 (see Figure 15) to implement the soft-start function.
An internal current source charges the capacitor to:
V = Istartsoftfb RSS2
(5)
(6)
with a maximum of 0.55 V.
The start level and the time constant of the increasing primary current level can be
adjusted externally by changing the values of RSS2 and CSS2
.
soft–start = 3 RSS2 CSS2
The soft-start current Istart(soft)fb switches on when VCC reaches Vstartup. When the
FBSENSE reaches 0.55 V, the flyback converter starts switching.
V
The charging current Istart(soft)fb flows when the VFBSENSE is < 0.55 V. If VFBSENSE exceeds
0.55 V, the soft-start current source starts limiting the current. After the flyback converter
has started, the soft-start current source is switched off.
When the IC is operating in the burst mode, the soft-start function is switched off.
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Product data sheet
Rev. 1 — 25 October 2012
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TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
S2
2.1 μA
I
ืꢀꢁꢂꢀμA
start(soft)fb
SOFT START
CONTROL
R
SS2
SS2
FBSENSE 10
OCP
ocp level
C
R
SENSE2
aaa-002677
Fig 15. Flyback soft-start
7.3.8 Maximum on-time
The flyback controller limits the on-time of the external MOSFET to 38.5 s. When the
on-time is longer than 38.5 s, the IC stops switching and enters the safe restart state.
7.3.9 Overvoltage protection (FBAUX pin)
An output OVP is implemented in the GreenChip series. In the TEA1755LT, the auxiliary
voltage is sensed using the current flowing into the FBAUX pin during the secondary
stroke. The auxiliary winding voltage is a well-defined replica of the output voltage. An
internal filter averages voltage spikes.
An internal up-down counter prevents false OVP detection which can occur during ESD or
lightning events. The internal counter counts up by one when the output voltage exceeds
the OVP trip level within one switching cycle. The internal counter counts down by two
when the output voltage has not exceeded the OVP trip level in one switching cycle.
When the counter has reached six, the IC assumes a true overvoltage, sets the latched
protection and switches off both converters.
The converter only restarts after the OVP latch is reset. In a typical application, the
internal latch is reset when the VINSENSE voltage drops below 750 mV and is then raised
to 860 mV. The latched protection is also reset by removing both the VCC and VHV
.
The demagnetization resistor, RFBAUX sets the output voltage Vo(OVP) at which the OVP
function trips:
Ns
----------
VoOVP
=
IovpFBAUX RFBAUX + VclampFBAUX
(7)
Naux
where Ns is the number of secondary winding and Naux is the number of auxiliary winding
of the transformer. Current Iovp(FBAUX) is internally trimmed.
Accurate OVP detection is made possible by adjusting the value of RFBAUX to the turns
ratio of the transformer.
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Product data sheet
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19 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
7.3.10 Overcurrent protection (FBSENSE pin)
The primary peak current in the transformer is measured accurately cycle-by-cycle using
the external sense resistor Rsense2. The OCP circuit limits VFBSENSE to a level set by
V
FBCTRL (see also Section 7.3.3). The OCP detection is suppressed during the
leading-edge blanking period, tleb (equals ton(fb)min td(FBDRIVER)), to prevent false
triggering due to switch-on spikes.
t
leb
OCP level
V
FBSENSE
t
014aaa022
Fig 16. OCP leading-edge blanking
7.3.11 Overpower protection
During the flyback converter primary stroke, the flyback converter input voltage is
measured by sensing the current that is drawn from the FBAUX pin.
The current information is used to limit the maximum flyback converter peak current and is
measured using the FBSENSE pin. The internal compensation is such, that a maximum
output power is obtained which is almost independent of the input voltage.
The OPP curve is given in Figure 17.
V
FBSENSE
(mV)
545
400
-360
-100
0
I
(μA)
FBAUX
aaa-002678
Fig 17. Overpower protection curve
7.3.12 Driver (FBDRIVER pin)
The driver circuit for the external power MOSFET gate has a current sourcing capability of
500 mA at 2 V on the FBDRIVER pin and a current sink capability of 1.2 A at 10 V on the
FBDRIVER pin. These capabilities ensure fast switch-on and switch-off of the power
MOSFET for efficient operation.
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Product data sheet
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NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Voltages
VCC
Parameter
Conditions
Min
Max
Unit
supply voltage
0.4
0.4
0.4
0.4
0.4
0.4
25
+38
+10
+9
V
V
V
V
V
V
V
V
V
V
V
VLATCH
VFBCTRL
voltage on pin LATCH
voltage on pin FBCTRL
current limited
VPFCCOMP voltage on pin PFCCOMP
VVINSENSE voltage on pin VINSENSE
VVOSENSE voltage on pin VOSENSE
+5
current limited
current limited
+10
+10
+25
+5
VPFCAUX
voltage on pin PFCAUX
VFBSENSE voltage on pin FBSENSE
VPFCSENSE voltage on pin PFCSENSE
VPFCTIMER voltage on pin PFCTIMER
current limited
current limited
current limited
0.4
0.4
0.4
0.4
+5
+10
+650
VHV
voltage on pin HV
Currents
IFBCTRL
IFBAUX
current on pin FBCTRL
current on pin FBAUX
3
0
mA
mA
mA
mA
A
1
+1
+10
+10
+2
+2
8
IPFCSENSE current on pin PFCSENSE
IFBSENSE current on pin FBSENSE
IFBDRIVER current on pin FBDRIVER
1
1
< 10 %
0.8
0.8
-
IPFCDRIVER current on pin PFCDRIVER < 10 %
A
IHV
current on pin HV
during start-up
and restart
mA
= 3 % due to
15
+30
mA
dV/dt on HV pin
General
Ptot
total power dissipation
storage temperature
junction temperature
Tamb < 75 C
-
0.6
W
Tstg
55
40
+150
+155
C
C
Tj
ESD
VESD
electrostatic discharge
voltage
human body
model
[1]
[1]
pins 1 to 14
pin 16 (HV)
2
2
kV
kV
V
1.5
500
1.5
500
charged device
model
[1] Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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Product data sheet
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HV start-up DCM/QR flyback and DCM/QR PFC controllers
9. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ Unit
thermal resistance from junction to ambient
thermal resistance from junction to case
in free air; JEDEC test board
in free air; JEDEC test board
127 K/W
Rth(j-c)
36
K/W
10. Characteristics
Table 5.
amb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Characteristics
T
Symbol Parameter
Start-up current source (HV pin)
Conditions
Min
Typ
Max Unit
IHV
current on pin HV
VHV > 75 V
VCC < Vtrip
0.9
0.8
4
1.1
1
1.3
1.2
6
mA
mA
mA
A
A
V
Vth(UVLO) < VCC < Vstartup
Vtrip < VCC < Vth(UVLO)
with auxiliary supply
in Power-down mode; VCC = 0 V
5
-
-
1.5
25
-
5
12
-
VBR
breakdown voltage
650
Supply voltage management (VCC pin)
Vtrip
trip voltage
0.5
0.6
0.7
V
V
V
Vstartup
Vth(UVLO)
start-up voltage
21.3 22.3
12.4 13.4
23.3
14.4
undervoltage lockout
threshold voltage
Vhys
hysteresis voltage
Vstartup Vth(UVLO)
8.3
-
8.9
9.5
-
V
V
Vprot(UVLO)
undervoltage lockout
protection voltage
Vth(UVLO)
+ 0.8
Ich(low)
low charging current
VHV > 75 V
VCC < Vtrip
1.15 1
0.85 mA
0.75 mA
Vth(UVLO) < VCC < Vstartup
1.05 0.9
5.8 4.9
2.45 2.7
Ich(high)
high charging current VHV > 75 V; Vtrip < VCC < Vth(UVLO)
4
mA
ICC(oper)
operating supply
current
no-load on pins FBDRIVER and
PFCDRIVER; VFBCTRL = 5 V;
2.95 mA
f
FB = fPFC = 100 kHz; = 30 %
IC in burst mode; no-load on pins
FBDRIVER and PFCDRIVER;
flyback switching; VFBCTRL = 1.6 V;
1.75 1.95
1.24 1.35
2.15 mA
V
PFCSENSE = 0 V
IC in burst mode; flyback not
switching; VFBCTRL = 0 V;
VPFCSENSE = 0 V
1.46 mA
ICC(prot)
protection supply
current
time-out protection triggered;
VHV = 0 V
0.3
0.45
0.6
mA
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Product data sheet
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NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
ICC(pd)
power-down mode
supply current
IC in power-down mode; VHV = 0 V
0.3
0.45
0.6
mA
Input voltage sensing PFC (VINSENSE pin)
Vstop(VINSENSE)
stop voltage on pin
VINSENSE
0.86 0.89
1.12 1.16
0.92
1.20
V
V
Vstart(VINSENSE)
start voltage on pin
VINSENSE
Vflr
fast latch reset voltage active after Vth(UVLO) is detected
0.6
60
0.75
110
0.9
V
Vflr(hys)
hysteresis of fast latch
reset voltage
160
mV
II(VINSENSE)
Vbst(dual)
input current on pin
VINSENSE
VVINSENSE > Vstop(VINSENSE) after
Vstart(VINSENSE) is detected
5
20
50
nA
dual boost voltage
high level
2.08 2.28
1.88 2.08
2.48
2.28
280
2.1
V
low level
V
switch-over region
120
1.9
200
2
mV
V
Vth(sel)clmp
Vth(sel)clmp(hys)
Vth(pd)
clamp select threshold on pin VINSENSE
voltage
clamp select threshold
voltage hysteresis
60
100
385
460
75
140
485
585
105
mV
mV
mV
mV
power-down threshold
voltage
285
335
45
Vth(pd)exit
Vhys(pd)
exit power-down
threshold voltage
VCC = 0 V
power-down
hysteresis voltage
Loop compensation PFC (PFCCOMP pin)
gm
transconductance
VVOSENSE to IO(PFCCOMP)
57
30
77
37
97
A/V
A
IO(PFCCOMP)
output current on pin VVOSENSE = 2 V; VPFCCOMP = 2.75 V
44
PFCCOMP
VVOSENSE = 3.3 V;
108 88
68
A
VPFCCOMP = 2.75 V
Ien(PFCCOMP)
enable current on pin
PFCCOMP
-
55
-
A
[1]
[2]
Vclamp(PFCCOMP)
clamp voltage on pin
PFCCOMP
low-power mode; PFC off; lower
clamp voltage.
VINSENSE Vth(sel)clmp
Vth(sel)clmp(hys) on pin VINSENSE;
VOSENSE = 2 V
+
3.2
1.8
3.32
1.92
3.44
2.04
V
V
V
[2]
VINSENSE < Vth(sel)clmp on pin
VINSENSE; VVOSENSE = 2 V
upper clamp voltage
3.6
1.9
3.75
2
3.9
2.1
V
V
high-power mode; PFC on;
uni-directional source clamp;
IPFCCOMP = 30 A;
VVOSENSE = 2.5 V
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Product data sheet
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TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Vton(PFCCOMP)zero
zero on-time voltage
on pin PFCCOMP
3.4
3.5
3.6
V
Pulse-width modulator PFC
ton(PFC)
PFC on-time
VVINSENSE = 3.3 V; VVOSENSE = 2 V;
VPFCCOMP = Vclamp(PFCCOMP)
1.8
17
2.8
27
3.8
37
s
s
V
VINSENSE = 1 V; VVOSENSE = 2 V;
VPFCCOMP = Vclamp(PFCCOMP)
Output voltage sensing PFC (VOSENSE pin)
Vth(start)VOSENSE
Vth(stop)VOSENSE
Vhys(VOSENSE)
Vreg(VOSENSE)
start threshold voltage open-loop
on pin VOSENSE
1.05 1.1
1.15
1.05
125
V
threshold stop voltage
on pin VOSENSE
0.95
75
1
V
hysteresis voltage on Vth(start)VOSENSE Vth(stop)VOSENSE
pin VOSENSE
100
mV
V
regulation voltage on for IO(PFCCOMP) = 0 A
pin VOSENSE
2.475 2.5
2.525
2.65
VOVP(VOSENSE)
Ibst(dual)
ton = 0 s
2.59 2.62
V
dual boost current
VVINSENSE < Vbst(dual) low-level or
VVOSENSE < 2.1 V; VFBCTRL = 5 V
9.1 8.1
7.1 A
V
VINSENSE = 4 V
50
25
5
nA
Overcurrent protection PFC (PFCSENSE pin)
Vsense(PFC)max
td(PFCDRIVER)
tleb(PFC)
maximum PFC sense V/t = 0 V/s
voltage
465
-
495
50
290
-
525
-
mV
ns
delay time on pin
PFCDRIVER
VPFCSENSE pulse-stepping 400 mV
around Vsense(PFC)max
PFC leading edge
blanking time
VPFCSENSE = 0.75 V
230
50
350
5
ns
Iprot(PFCSENSE)
protection current on
pin PFCSENSE
nA
Soft-start PFC (PFCSENSE pin)
Istart(soft)PFC
Vstart(soft)PFC
Vstop(soft)PFC
Oscillator PFC
fsw(PFC)max
PFC soft start current
73
60
47
0.55
0.5
A
V
PFC soft start voltage enabling voltage
PFC soft stop voltage disabling voltage
0.45 0.5
0.4
0.45
V
maximum PFC
119
139
159
kHz
switching frequency
toff(PFC)min
minimum PFC off-time secondary stroke
1.25 1.55
1.85 s
Valley switching PFC (PFCAUX pin)
(V/t)vrec(PFC)
PFC valley recognition
voltage change with
time
-
-
1.7
5.4
V/s
tto(vrec)PFC
PFC valley recognition
time-out time
3
4.2
s
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
24 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Demagnetization management PFC (PFCAUX pin)
Vth(comp)PFCAUX
comparator threshold
voltage on pin
PFCAUX
125 90
55
mV
tto(demag)PFC
Iprot(PFCAUX)
PFC demagnetization
time-out time
39
48
-
57
s
protection current on VPFCAUX = 50 mV
pin PFCAUX
75
5
nA
PFC off delay (PFCTIMER pin)
Isource(PFCTIMER)
Rsink(PFCTIMER)
Vstart(PFCTIMER)
Vstop(PFCTIMER)
Vth(off)PFCTIMER
source current on pin VPFCTIMER = 2.5 V
PFCTIMER
5.4 4.7
5.5
0.93 1.03
4
A
k
V
sink resistance on pin VPFCTIMER = 2.5 V
PFCTIMER
4
7
start voltage on pin
PFCTIMER
1.13
3.15
4.6
stop voltage on pin
PFCTIMER
2.85
4.2
3
V
switch-off threshold
voltage on pin
PFCTIMER
PFC override voltage
4.4
V
Driver (PFCDRIVER pin)
Isrc(PFCDRIVER)
Isink(PFCDRIVER)
VO(PFCDRIVER)max
source current on pin VPFCDRIVER = 2 V
PFCDRIVER
-
0.5
0.7
11
-
A
A
V
sink current on pin
PFCDRIVER
VPFCDRIVER = 2.5 V
-
-
maximum output
voltage on pin
PFCDRIVER
10
12
OverVoltage Protection flyback (FBAUX pin)
Iovp(FBAUX)
overvoltage protection
current on pin FBAUX
279
300
321
A
Demagnetization management flyback (FBAUX pin)
Vth(comp)FBAUX
comparator threshold
voltage on pin FBAUX
60
90
-
120
mV
nA
Iprot(FBAUX)
protection current on VFBAUX = 50 mV
pin FBAUX
65
5
Vclamp(FBAUX)
clamp voltage on pin
FBAUX
IFBAUX = 100 A
IFBAUX = 300 A
0.75 0.7
0.65
0.97
2.7
V
0.87 0.92
V
tsup(xfmr_ring)
transformer ringing
suppression time
1.7
2.2
s
Pulse width modulator flyback
ton(fb)max
maximum flyback
on-time
32.5 38.5
44.5 s
TEA1755LT
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Product data sheet
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NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Oscillator flyback
fsw(fb)max
maximum flyback
switching frequency
110
3.8
70
130
4
150
4.2
76
kHz
V
Vstart(red)f
frequency reduction
start voltage
transfer from DCM/QR to FR mode
fsw(fb)swon(PFC)
PFC switch-on flyback
switching frequency
73
kHz
fsw(fb)swoff(PFC)
PFC switch-off flyback
switching frequency
50
21
53
25
56
29
kHz
kHz
fsw(fb)burst(ent)
enter burst mode
flyback switching
frequency
enter burst mode
fsw(fb)burst
burst mode flyback
switching frequency
normal operation
override voltage
31
36.5
3.75
42
kHz
V
Ven(PFC)FBCTRL
PFC enable voltage
on pin FBCTRL
3.4
4.1
Peak current control flyback (FBCTRL pin)
VFBCTRL
voltage on pin
FBCTRL
for maximum flyback peak current
4.6
4.9
5.2
V
Vto(FBCTRL)
time-out voltage on
pin FBCTRL
enable voltage
trip voltage
5.3
7.3
5.5
5.7
V
V
V
7.75
8.2
Vth(burst)off
Vth(burst)on
Vth(burst)exit
Vburst(exit-on)
off-state burst mode
threshold voltage
on pin FBCTRL
0.62 0.77
0.92
on-state burst mode
threshold voltage
on pin FBCTRL
2.2
2.6
325
2.4
2.8
390
2.6
3
V
exit burst mode
threshold voltage
on pin FBCTRL
V
burst mode voltage
difference between
exit and on-state
pin FBCTRL = Vth(burst)exit Vth(burst)on
455
mV
Vburst(on-off)
burst mode voltage
difference between
on-state and off-state
pin FBCTRL = Vth(burst)on Vth(burst)off
1.5
9.8
1.63
13.2
1.76
V
Rint(FBCTRL)
IO(FBCTRL)
internal resistance on
pin FBCTRL
16.5 k
output current on pin VFBCTRL = 0 V
FBCTRL
0.75 0.6
0.45 mA
0.18 mA
VFBCTRL = 4.5 V
0.3 0.24
Ito(FBCTRL)
time-out current on pin VFBCTRL = 6 V
FBCTRL
35
29
23
A
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
26 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Valley switching flyback (HV pin)
[3]
[3]
(V/t)vrec(fb)
flyback valley
recognition voltage
change with time
75
-
+75
-
V/s
td(vrec-swon)
valley recognition to
switch-on delay time
-
75
ns
Soft-start flyback (FBSENSE pin)
Istart(soft)fb
flyback soft start
current
75
60
45
A
Vstart(soft)fb
flyback soft start
voltage
enable voltage
0.5
0.55
0.6
V
OverCurrent protection flyback (FBSENSE pin)
Vsense(fb)max
Vsense(fb)min
td(FBDRIVER)
ton(fb)min
maximum flyback
sense voltage
V/t = 0 V/s
525
221
-
545
232
80
565
243
-
mV
mV
ns
minimum flyback
sense voltage
V/t = 0 V/s
delay time on pin
FBDRIVER
VFBSENSE pulse-stepping 400 mV
around Vsense(fb)max
minimum flyback
on-time
VFBCRTL = 3 V; VFBSENSE = 0.75 V
280
340
400
ns
Iadj(FBSENSE)
adjust current on pin
FBSENSE
2.29 2.1
1.91 A
OverPower Protection flyback (FBSENSE pin)
Vsense(fb)max
maximum flyback
sense voltage
V/t = 0 V/s
IFBAUX = 80 A
IFBAUX = 120 A
IFBAUX = 240 A
IFBAUX = 360 A
525
495
400
345
545
540
445
400
565
565
490
455
mV
mV
mV
mV
Driver (FBDRIVER pin)
Isrc(FBDRIVER)
source current on pin VFBDRIVER = 2 V
FBDRIVER
-
0.5
0.7
11
-
A
A
V
Isink(FBDRIVER)
VO(FBDRIVER)(max)
sink current on pin
FBDRIVER
VFBDRIVER = 2.5 V
-
-
maximum output
voltage on pin
FBDRIVER
10
12
LATCH input (LATCH pin)
Vprot(LATCH) protection voltage on
pin LATCH
469
494
519
mV
IO(LATCH)
output current on pin Vprot(LATCH) < VLATCH < Voc(LATCH)
LATCH
32.5 30.5
552 582
28.5 A
612 mV
Ven(LATCH)
enable voltage on pin at start-up
LATCH
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
27 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Vhys(LATCH)
hysteresis voltage on Ven(LATCH) Vprot(LATCH)
68
88
108
mV
pin LATCH
Voc(LATCH)
open-circuit voltage on
pin LATCH
-
1.75
-
V
Temperature protection
Tpl(IC)
IC protection level
temperature
135
-
145
10
155
-
C
C
[3]
Tpl(IC)hys
hysteresis of IC
protection level
temperature
[1] A typical application with a compensation network on the PFCCOMP pin, such as the example in Figure 3.
[2] The clamp voltage on the PFCCOMP pin is dependent on the VINSENSE voltage. When the VVINSENSE rises above
Vth(sel)clmp + Vth(sel)clmp(hys), the high clamp level is active. When the voltage on the VINSENSE pin drops below the Vth(sel)clmp level
again, the low clamp level is active.
[3] Guaranteed by design.
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
28 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
11. Application information
A power supply with the TEA1755LT consists of a PFC circuit and a flyback converter (see
Figure 18).
Capacitor CVCC buffers the IC supply voltage. The IC supply voltage is powered using the
high voltage rectified mains during start-up and the auxiliary winding of the flyback
converter during operation. Sense resistors RSENSE1 and RSENSE2 convert the current
through the MOSFETs S1 and S2 into a voltage on the PFCSENSE and FBSENSE pins.
The RSENSE1 and RSENSE2 values define the maximum primary peak current in MOSFETs
S1 and S2.
In the example, the LATCH pin is connected to a Negative Temperature Coefficient (NTC)
resistor. The protection is activated when the resistance drops below a value as calculated
in Equation 8:
VprotLATCH
IOLATCH
= 16.2 k
(8)
-------------------------------
A capacitor CTIMEOUT is connected to the FBCTRL pin. RLOOP ensures that the time-out
capacitor does not interfere with the normal regulation loop.
R
S1 and RS2 are added to prevent the soft-start capacitors from being charged during
normal operation due to negative voltage spikes across the sense resistors.
Resistor RAUX1 is added to protect the IC from damage during lightning events.
RS3 and RCOMP are added to compensate for input voltage variations. The (stray)
capacitance on the drain of MOSFET S2 affects the frequency reduction slope and
therefore, the PFC switch-on and switch-off levels. Choosing the proper values for RS3
and RCOMP results in an input voltage independent PFC switch-on and switch-off power
level.
RDRV1 and RDRV2 prevent the output drivers from being damaged due to, for example,
power MOSFET avalanche.
In the application, the HV pin of the IC can either be connected to the center tap of the
flyback transformer or to the drain of MOSFET S2
Refer to application note AN11142 for more detailed information.
TEA1755LT
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 25 October 2012
29 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
D
2
Tr1
C
R
bulk
DRV1
R
R4
R5
S1
Tr2
R
D4
COMP
S2
V
OUT
C6
(1)
C
D1
C1
R
SS1
SS1
SENSE1
R
AUX1
R
DRV2
Z1
R
S1
OPTO-
FEEDBACK
V
mains
C
SS2
R
SS2
R
12 11
9
16 13
PFCAUX
R
R
S3
S2
FBSENSE
FBAUX
8
10
C3
C4
R3
PFCCOMP
6
R
SENSE2
FBAUX
D3
IC
R1
VINSENSE
FBCTRL
4
7
3
V
CC
1
5
LATCH
R2
C2
2
14
GND
PFCTIMER
R
C
VCC
NTC
C
C5
PFCTIMER
R
LOOP
C
TIMEOUT
OPTO-FEEDBACK
aaa-002624
(1) In the application, the HV pin of the IC can either be connected to the center tap of the flyback transformer or to the drain of
MOSFET S2.
Fig 18. TEA1755LT typical application diagram
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
30 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 19. Package outline SOT109-1 (SO16)
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
31 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
13. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TEA1755LT v.1
20121025
Product data sheet
-
-
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
32 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
14.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
33 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
GreenChip — is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TEA1755LT
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Product data sheet
Rev. 1 — 25 October 2012
34 of 35
TEA1755LT
NXP Semiconductors
HV start-up DCM/QR flyback and DCM/QR PFC controllers
16. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
7.3.10
7.3.11
7.3.12
Overcurrent protection (FBSENSE pin) . . . . . 20
Overpower protection. . . . . . . . . . . . . . . . . . . 20
Driver (FBDRIVER pin) . . . . . . . . . . . . . . . . . 20
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Distinctive features . . . . . . . . . . . . . . . . . . . . . . 2
Green features . . . . . . . . . . . . . . . . . . . . . . . . . 2
PFC green features . . . . . . . . . . . . . . . . . . . . . 2
Flyback green features. . . . . . . . . . . . . . . . . . . 2
Protection features . . . . . . . . . . . . . . . . . . . . . . 2
2.1
2.2
2.3
2.4
2.5
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal characteristics . . . . . . . . . . . . . . . . . 22
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
Application information . . . . . . . . . . . . . . . . . 29
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . 32
9
10
11
12
13
3
4
5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 33
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
14.1
14.2
14.3
14.4
7
7.1
Functional description . . . . . . . . . . . . . . . . . . . 5
General control. . . . . . . . . . . . . . . . . . . . . . . . . 5
Start-up and UnderVoltage LockOut (UVLO) . . 5
Power-down mode . . . . . . . . . . . . . . . . . . . . . . 7
Supply management. . . . . . . . . . . . . . . . . . . . . 8
Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Fast latch reset. . . . . . . . . . . . . . . . . . . . . . . . . 8
Overtemperature protection . . . . . . . . . . . . . . . 8
Power factor correction circuit . . . . . . . . . . . . . 8
ton control (PFCCOMP pin). . . . . . . . . . . . . . . . 8
Valley switching and demagnetization
15
16
Contact information . . . . . . . . . . . . . . . . . . . . 34
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.2
7.2.1
7.2.2
(PFCAUX pin). . . . . . . . . . . . . . . . . . . . . . . . . . 9
Frequency limitation . . . . . . . . . . . . . . . . . . . . . 9
Mains voltage compensation (VINSENSE pin). 9
Soft-start (PFCSENSE pin). . . . . . . . . . . . . . . . 9
PFC switch on/switch off control. . . . . . . . . . . 10
PFC switch off delay (PFCTIMER pin) . . . . . . 10
Dual-boost PFC . . . . . . . . . . . . . . . . . . . . . . . 11
Overcurrent protection (PFCSENSE pin) . . . . 12
Mains undervoltage lockout/brownout
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
protection (VINSENSE pin) . . . . . . . . . . . . . . 12
Overvoltage protection (VOSENSE pin). . . . . 12
PFC open-loop protection (VOSENSE pin) . . 12
Driver (PFCDRIVER pin) . . . . . . . . . . . . . . . . 12
Flyback controller . . . . . . . . . . . . . . . . . . . . . . 12
Multimode operation. . . . . . . . . . . . . . . . . . . . 13
Valley switching (HV pin) . . . . . . . . . . . . . . . . 14
Current mode control (FBSENSE pin) . . . . . . 15
Demagnetization (FBAUX pin) . . . . . . . . . . . . 16
Flyback control/time-out (FBCTRL pin) . . . . . 16
Burst mode operation (FBCTRL pin) . . . . . . . 17
Soft-start (FBSENSE pin) . . . . . . . . . . . . . . . . 18
Maximum on-time. . . . . . . . . . . . . . . . . . . . . . 19
Overvoltage protection (FBAUX pin) . . . . . . . 19
7.2.11
7.2.12
7.2.13
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 October 2012
Document identifier: TEA1755LT
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