TEA1771 [NXP]
GreenChip PC primary control IC; 绿色芯片PC初级控制IC
| 型号： | TEA1771 |
| 厂家： | 
NXP |
| 描述： | GreenChip PC primary control IC |
| 文件： | 总25页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TEA1771
GreenChip PC primary control IC
Rev. 01 — 6 February 2009
Product data sheet
1. General description
The TEA1771 is a primary control IC for an active clamp forward converter. This converter
enables higher duty cycles of up to 70 %. A higher maximum duty cycle lowers the
required breakdown voltage of both the primary and secondary switches, reducing the
total cost of the system.
The IC is optimized for (ATX) PC power supplies. Together with the TEA1781 and
TEA1782 a unique system can be made that reduces costs by integrating the standby
supply. It assures high output voltage accuracy and avoids cross regulation as the output
voltages are regulated separately. This system exceeds the current and proposed
efficiency standards such as 80 plus-gold, energy star and blue angel.
The TEA1771 is implemented in the high voltage EZ-HV SOI process. It enables direct
start-up from the rectified mains voltage, excluding the need for a start-up resistor. The
high voltage reset switch, required for the active clamp, is integrated in the IC. The IC has
a feed-forward control regulation, avoiding high resonant voltage peaks as a result of
output load or input voltage transients. This also assures proper regulation of the output
voltages at input voltage variations.
2. Features
I Designed for ATX PC power supplies
I Universal mains operation, 90 V (AC) to 265 V (AC)
I Integrated start-up current source
I Integrated high-voltage, high-side active clamp reset switch
I Feed-forward regulation
I Enhanced efficiency in Standby mode and Normal mode
I OverVoltage Protection (OVP)
I OverCurrent Protection (OCP)
I Short-Winding Protection (SWP)
I Low external component count
I Soft (re)start
I High voltage ramp-up detection assuring Zero Voltage Switching (ZVS) of the reset
switch
I Available in a 24-pin SO package
3. Applications
I PC desktop power supply
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
4. Quick reference data
Table 1.
Symbol
Voltages
VDM1
Quick reference data
Parameter
Conditions
Min
Typ
Max
Unit
voltage on pin DM1
continuous
−0.4
−0.4
-
-
+570
+650
V
V
peak; ∆t = 1 µs;
non-repetitive
VDM2
voltage on pin DM2
voltage on pin LVIN
continuous
−0.4
−0.4
-
-
+570
+650
V
V
peak; ∆t = 1 µs;
non-repetitive
[1]
VLVIN
continuous
VLVIN = 0 V
−0.4
-
+48
3.5
V
Currents
Ich(DM2)
charge current on pin
DM2
2.3
2.9
mA
Reset switch
RDSon drain-source on-state
resistance
running mode; VDD(float) = 12 V
IDM2 = 0.1 A
IDM2 = 0.3 A
20
11
25
15
30
22
Ω
Ω
Oscillator, opto control and secondary protection
fosc(max)
maximum oscillator
frequency
IOPTO(fmax) > IOPTO > Iprot(OPTO)
IIREF
−200 µA
IOPTO < IOPTO(δmax); IIREF = −100 mA;
VLVIN
12 V
;
=
80
100[2] 120
kHz
δmax
maximum duty cycle
=
54.0
59.0
-
64.0
+85
%
General
Tamb
ambient temperature
−20
°C
[1] Pin LVIN cannot be current driven.
[2] For the PSU, the recommended operating frequency is 75 kHz. The operating frequency can be raised to
100 kHz provided that the PSU input voltage, VI, is above a minimum level which is typically 200 V. An
application solution is available that automatically lowers the frequency when, during a mains dip, VI drops
below this minimum level. See the application note Guidelines for applying the GreenChip PC chipset.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TEA1771T
SO24
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
2 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
6. Block diagram
VRST
SUPPLY
I
ch(LVIN)
STATE DIAGRAM
VRESET
SUPPLY
V
< V
DECVCC
UVLO(DECVCC)
V
> V
> V
VRST
VRST(min)
charge
or
SWP OVP or
V
VRST
OK
I
> I
OPTO
prot(OPTO)
SYSTEM FAILURE
CHARGE
LVIN
DECPVCC
DECVCC
V
V
VRST
startup(LVIN)
VRST(max)
RUNNING
V
VRST
> V
ovp(VRST)
OVP
or
SWP OVP or
V
OK and
VRST
> V
V
UVLO(DECVCC)
I
> I
V
OPTO
prot(OPTO)
LVIN
startup(LVIN)
V
REF
SWP
DECPVCC
DRIVERS
SAWTOOTH
DIGITAL CONTROL
CB
M2
M1
I
I
IREF
Rsaw
I
R
Q
Q
CSS
DM2
∆t
S
2
M2
LS
CSS
sawcomp
DM1
R
S
DECPVCC
Rsaw
Csaw
∆t
1
DRIVER
I
I
OCP
IREF
Rsaw
OSCILLATOR
SWP
0.3 × I
STANDBY
CURPROT
osc
duty cycle δ
SENSE
+
+
+
−
t
, I
on Rsaw
V
swp1
I
IREF
I
OPTO
frequency, Iosc
−I
−
clock
OPTO
−V
swp2
blank
V
OPTO
V
IREF
OCP
−
I
osc
PGND
V
ocp
0.7 × I
osc
014aaa169
OPTO
IREF
Fig 1. Block diagram
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
3 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
7. Pinning information
7.1 Pinning
1
2
24
23
22
21
20
19
18
17
16
15
14
13
DM2
n.c.
DM1
CB
3
n.c.
n.c.
4
LVIN
n.c.
5
GND
HWGND
5VREF
PGND
SENSE
DRIVER
PGND
DECPVCC
n.c.
6
GND
TEA1771T
7
DECVCC
VRST
IREF
CSS
8
9
10
11
12
OPTO
n.c.
014aaa170
Fig 2. Pin configuration
7.2 Pin description
Table 3.
Symbol
DM2
Pin description
Pin
1
Description
drain reset switch
not connected
not connected
n.c.
2
n.c.
3
LVIN
4
low voltage input (rectified auxiliary input)
ground
GND
5
GND
6
ground
DECVCC
VRST
IREF
7
decoupling supply voltage
reset capacitor voltage
oscillator reference current
capacitor soft start
opto-coupler feedback input
not connected
8
9
CSS
10
11
12
13
14
15
16
17
18
19
20
21
OPTO
n.c.
n.c.
not connected
DECPVCC
PGND
DRIVER
SENSE
PGND
5VREF
HWGND
n.c
decoupling power supply
power ground
main switch gate driver
overcurrent sensing
power ground
5 V reference voltage
handler wafer ground
not connected
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
4 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
Table 3.
Pin description …continued
Symbol
n.c
Pin
22
23
24
Description
not connected
CB
boost capacitor
DM1
drain main switch (M1)
8. Functional description
8.1 Introduction
The TEA1771 is designed to cooperate with the TEA1781 and the TEA1782 secondary
side controllers in a forward converter topology, see Figure 11. A typical application area
of this converter is a power supply for a desktop PC.
The topology supported by the TEA1771 enables transformer resetting using an active
reset mechanism. For this purpose a reset switch in the form of a lateral IGBT has been
integrated into the IC. This reset switch can operate high-side using an external boost
capacitor.
Advantage of this active reset mechanism is, compared to a third winding solution, that a
higher maximum duty cycle (> 50%) can be achieved. Reducing dissipation by recovering
energy is another advantage of the reset mechanism when compared to the standard
R/C/D topology.
The TEA1771 has a feed-forward control regulation, avoiding high resonant voltage peaks
as a result of output load or input voltage transients.
8.2 Supply
At power-up, the primary and secondary ICs are not yet supplied via the auxiliary
windings as the main switch M1 is off, see Figure 11. Initially, before start-up, the primary
IC is in Charge mode and supplies itself with a current Ich(LVIN) from the high voltage pin
DM2, see the SUPPLY block in Figure 1. The voltage on pin DM2 is equal to the input
voltage in this static situation. It is connected to the input via the transformer and the
parallel diode of the reset switch, Drst, see Figure 11. In Charge mode LVIN is charged
from DM2 via an internal current source, Ich(LVIN). From LVIN the nodes DECVCC and
DECPVCC are supplied by internal regulators. As a result, when LVIN is charged, the
DECVCC and DECPVCC nodes, which are decoupled by external capacitors, are
charged simultaneously. This is illustrated in the left part of Figure 3.
When the voltage at LVIN reaches its start level Vstartup(LVIN) and the voltage on pin VRST
is in its start-up window, the IC enters Running mode and starts switching; see M1 signal
in Figure 3. The voltage on pin VRST is in the start-up window when the voltage on pin
VRST is between the minimum start voltage, Vstart(VRST)(min), and the maximum start
voltage, Vstart(VRST)(max). These start-up conditions are pointed out in the
STATE DIAGRAM block in Figure 1. If the logic signal VVRSTOK is high, the voltage VVRST
is in the start-up window.
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
5 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
charge mode
running mode
V
LVIN
V
startup(LVIN)
V
DECVCC)
V
UVLO(DECVCC)
open
M1
closed
014aaa171
Fig 3. Start-up sequence TEA1771
Figure 11 shows the primary windings on the transformer. The main switch M1 directly
powers up the primary winding. All remaining windings are also powered up via the
transformer. The primary auxiliary winding is used to supply LVIN. Thus, when in Running
mode, the primary IC is supplied externally by the primary auxiliary winding. The voltage
on this winding reflects the input voltage scaled by a turn ratio. The internal current source
between pin DM2 and pin LVIN is switched off in Running mode and System failure mode.
The secondary ICs are supplied via a rectified secondary winding. Because of this they
start up after the primary side has started switching.
The voltage on pin VRST has to be in the start-up window to enable the controller to enter
Running mode. Figure 11 shows that the pin VRST is connected to a resistive divider that
is connected to DM2 (R1 and R2 in Figure 11). In Charge mode the voltage on DM2 is
equal to the input voltage VI. This implies that VI must be in a specific window to start up
the PSU. The IC parameters Vstart(VRST)(min) and Vstart(VRST)(max) are scaled by the divider
ratio to a certain input voltage range. In a typical application setting the input voltage
range is from 90 V (AC) to 264 V (AC).
8.3 Modes of operation
The TEA1771 features three operation modes: Charge mode, Running mode and System
failure mode as shown in Figure 4.
When the DECVCC voltage is below the UVLO level the IC is in Charge mode. After
sufficient charging of the external capacitor on pin LVIN, the IC enters Running mode and
the system starts switching, see Figure 3.
When a system failure is detected, the IC enters System failure mode and the main switch
and reset switch are turned off.
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
6 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
The switch that is in series with the current source, charging LVIN via DM2, is opened
when the IC is in System failure mode (see the SUPPLY block in Figure 1). The IC
consumption slowly discharges the LVIN capacitor. When VLVIN has been discharged to
the level of VDECVCC and VDECPVCC, these nodes are also discharged. Eventually the
DECVCC voltage will drop below the UVLO level and the IC enters Charge mode. This is
called a safe restart cycle. The period of this cycle depends on the capacitors at pins
LVIN, DECVCC, and DECPVCC.
STATE DIAGRAM
V
< V
UVLO(DECVCC)
DECVCC
SWP or OVP or
> I
I
OPTO
prot(OPTO)
SYSTEM FAILURE
SWP or OVP or
CHARGE
RUNNING
V
OK and
VRST
I
> I
V
> V
OPTO
prot(OPTO)
LVIN startup(LVIN)
014aaa172
Fig 4. State diagram
8.4 Oscillator
In Figure 5 the OSCILLATOR block is shown together with the STANDBY block. The
OSCILLATOR block shows the internal capacitor that is subsequently charged and
discharged with the currents 0.3 × Iosc and 0.7 × Iosc. The lower part of Figure 5 shows the
oscillator signals. It points out that the Ich/Idch current ratio determines an internal clock
with a duty cycle of 0.7. In Section 8.5 will be made clear that the clock duty cycle
determines the max duty cycle that can be regulated.
Together with the capacitor value the Iosc current level determines the frequency. The Iosc
is not fixed and therefore the frequency varies also.
Figure 5 shows that Iosc is generated by the STANDBY block and fed to the
OSCILLATOR block. The curves in the STANDBY block show that Iosc is regulated by the
current on pin OPTO, IOPTO. For IOPTO > 2IIREF the Iosc current is set to the maximum level,
Iosc = IIREF. As a result the frequency is set to the maximum level by putting IOPTO > 2IIREF
.
IIREF
f osc(max)
=
(1)
------------
2
• fosc(max) (kHz)
• IIREF (µA)
IIREF is regulated by the external resistor to pin IREF. The voltage on this pin is set to
3.6 V. The current IIREF is set by choosing the resistor value.
VIREF
3.6
IIREF
=
=
(2)
--------------
--------------
RIREF
RIREF
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
7 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
Example:
A resistor of 36 kΩ sets IIREF to 100 µA. This results in a frequency of 50 kHz.
If the Power Supply Unit (PSU) is in Normal mode IOPTO is put at a high level,
IOPTO > 2IIREF. This sets the TEA1771 frequency to the maximum level. If the PSU is in
Standby mode, the frequency may be regulated to a lower level by lowering IOPTO. See
Section 8.8.
STANDBY
OSCILLATOR
0.3 × I
duty cycle δ
, I
osc
t
on Rsaw
I
IREF
I
OPTO
frequency, I
osc
clock
osc
−I
OPTO
V
OPTO
V
IREF
I
0.7 × I
osc
OPTO
IREF
T
t
0.3 × I
I
osc
cap
0
−0.7 × I
osc
V
osch
V
cap
V
oscl
clock
014aaa173
Fig 5. Oscillator
8.5 Feed-forward regulation
The output voltages of a GreenChip PC application are regulated at the secondary side by
the TEA1781 (3.3 V and 5 V) and the TEA1782 (12 V and 5 V standby). The duty cycle of
the secondary control switches (SB and SR, see Figure 11) are defined by Equation 3:
VO
δ_SB ⁄ R
=
(3)
--------------
VI ⁄ N
Where:
• VO is either 3.3 V, 5 V or 12 V
• VI is the PSU input voltage
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
8 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
• N is the transformer turn ratio: primary to secondary winding
The primary side has to ensure that a positive secondary voltage is available just before
the secondary side switches on the control switches SB and SR. To make sure there is a
positive secondary voltage, also during transients, the duty cycle of the primary control
switch, M1, has to be larger than the duty cycle of SB/SR.
VO
VO
δ_M1 >
≈ 1.2
(4)
--------------
--------------
VI ⁄ N
VI ⁄ N
As the transformer turn ratio and the output voltage of a PC power supply are constant
values, it implies that the primary duty cycle has to be inverse proportional to the input
voltage:
VI × δ = constant
(5)
This relation is implemented in the TEA1771. The primary duty cycle is only defined by
the input voltage, which is called feed-forward regulation. VI is hereby measured via LVIN,
which reflects the input voltage.
The sawtooth, the oscillator, and the digital control circuitry define the feed-forward
regulation. The frequency is defined in the oscillator and the on-time in the sawtooth
circuitry. The SAWTOOTH block, the DIGITAL CONTROL block, and their signals are
shown in Figure 6. The outputs of the DIGITAL CONTROL block define the states of the
output switches, the main switch (M1), and the reset switch (M2).
The oscillator generates a clock signal (see Section 8.4). When the clock becomes
positive, the reset switch is turned off. A short time (∆t1) after this the main switch M1 is
turned on. At the same time the charging of the capacitor Csaw is initiated.
As soon as the Csaw capacitor voltage exceeds an internal reference voltage, Vref(saw), the
sawcomp signal becomes a logic '1', turning off the main switch via digital control. After a
short delay (∆t2) the reset switch is turned on.
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
9 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
SAWTOOTH
DIGITAL CONTROL
M2
M1
I
I
/ 20
IREF
Rsaw
r
q
q
V
LVIN
∆t
s
2
sawcomp
V
Rsaw
r
sawrst
∆t
1
R
saw
C
saw
s
V
det
clock
clock
∆t = t
1
no(rstsw-mainsw)
sawrst
V = 400 V
I
V
Rsaw
V = 250 V
I
V
Csaw
sawcomp
M1
M2
∆t
∆t = t
2 no(bu)
2
014aaa174
Fig 6. Feed-forward regulation
The current that charges the Csaw capacitor is proportional to the LVIN voltage, which
reflects the input voltage. Figure 6 shows the signals for VI = 250 V and for VI = 400 V. A
higher input voltage results in a higher charge current, which consequently results in a
lower duty cycle. Thus, the duty cycle is made inverse proportional to the input voltage,
which is the feed-forward regulation of the GreenChip PC converter.
So far the assumption has been that VRsaw is fixed. This does hold when the PSU is in
Normal mode. In Standby mode this reference voltage may be lower causing a lower
on-time, ton. It is defined by IRsaw and the resistor Rsaw. Figure 1 shows that IRsaw is
generated by the STANDBY block. IRsaw, like Iosc, is regulated by IOPTO. This on-time
regulation is relevant when the PSU is in Standby mode. See Section 8.8. In Normal
mode IOPTO is set to a high level causing IRsaw to reach the maximum level, the assumed
fixed level.
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
10 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
When the PSU is in Normal mode the duty cycle is independent of the operating
frequency. The frequency is set to the maximum level and is proportional to IIREF. See
Section 8.4.
IIREF
f osc(max)
=
(6)
------------
2
• fosc(max) (kHz)
• IIREF (µA)
Figure 6 shows the sawtooth circuit. It also shows that the charge current of the Csaw
capacitor is proportional to IIREF. Thus both the oscillation period, tosc, and the on-time, ton,
are inverse proportional to IIREF. As a result the duty cycle, δ, is constant for varying
operating frequencies.
8.6 Non-overlap times
In the previous section the non overlap times ∆t1 and ∆t2 are introduced. In Figure 7 these
times are illustrated. The delays, ∆t1 and ∆t2 avoid overlap in the on-time of the main
switch and the reset switch. The delay ∆t1 is listed in the characteristics table:
∆t1 = tno(rstsw-mainsw). The value slightly differs for Standby mode and Normal mode. In the
characteristics table this is reflected by different delay values for a high and a low −IOPTO
value that hold in Normal mode and Standby mode, respectively.
The delay ∆t2 is less straightforward. It depends on the VDM1 signal. Figure 7 illustrates
the mechanism showing stylized signals. When M1 is turned off the DM1 node is charged
by the magnetizing current until it is clamped to the reset voltage. The primary controller
waits for DM1 to be charged to the reset voltage before M2 is turned on. In fact, when this
ramp has finished the controller waits an additional time, twait after which M2 is turned on.
The DM1 voltage signal varies strongly as the PSU load is varied. By sensing the VDM1
ramp-up, hard switching of the reset switch is avoided in all load conditions.
t
no(bu)
M1
V
rst
V
DM1
M2
t
t
wait
ramp
014aaa727
Fig 7. ∆t2 non-overlap time between the main switch (mainsw) being turned off and the
reset switch (rstw) being turned on.
If (dV/dt)r is below detection level the VDM1 ramp-up is not sensed at all. In that case a
delay is applied which, like ∆t1, is determined by the IC itself. This delay is called tno(bu)
,
the backup delay. In Figure 7 this delay is illustrated by the dashed variant of M2. Counting
time from the moment M1 is turned off M2 is turned after a delay of tno(bu) has passed.
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
11 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
8.7 Soft start
When entering Running mode, the IC starts switching at a minimum frequency set by an
external resistor on pin OPTO, typically about 20 kHz. To avoid overshoot on the reset
capacitor, Crst, when the system starts switching, the primary control IC has an integrated
soft start function. During this soft start period the on-time of the main switch slowly rises
from zero to the required value; see Figure 3.
SAWTOOTH
CONTROL
I
I
IREF
Rsaw
I
CSS
CSS
sawcomp
sawrst
∆t
1
Rsaw
Csaw
clock
clock
∆t
1
sawrst
V
Rsaw
V
Csaw
sawcomp
M1
014aaa175
Fig 8. Implementation of the soft start period
During the soft start period, the external capacitor connected to pin CSS is charged via
the current source ICSS. See Figure 8. This current slowly charges the capacitor from 0 V
to 4.1 V. The SAWTOOTH block in Figure 8 shows two multipliers. The left one points out
that VCSS modulates IRsaw. IRsaw in turn determines the reference voltage that is used to
make the on-time. The slow ramp from 0 V to 4.1 V causes the duty cycle to grow slowly in
time. This is called a soft start.
The duty cycle reaches the maximum level when the voltage on pin CSS pin is about
3.5 V. Eventually the voltage on pin CSS will be charged to the VCSS parameter that is
listed in Table 6, VCSS = 4.1 V.
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
12 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
The time constant for the soft start period equals, see Equation 7:
Css 3.5
τsoftstart
=
(7)
-------------------------------
ICSS(softstart)
Example:
With an external capacitor of 33 nF a time constant of about 2.8 ms is realized.
8.8 Standby regulation
In Section 8.4 and Section 8.5 it has already been explained that IOPTO regulates both the
oscillator frequency and the on-time. This section gives an overview of these regulations.
Figure 9 shows both regulations.
The whole PSU can be either in Standby mode or in Normal mode. In Normal mode all
outputs are active: 3.3 V, 5 V, 12 V, and 5 V standby. In Standby mode only the
5 V standby is active. In the PSU, IOPTO is determined by the controller ICs on the
secondary side of the transformer. Via an OPTO-coupler this current is transferred from
the secondary side to the primary side. The secondary control regulates the primary duty
cycle in Standby mode through IOPTO in such a way that the primary duty cycle follows the
duty cycle required on secondary side.
In Normal mode the IOPTO current is set to a high level where both the frequency and the
on-time are regulated to the maximum level.
When the PSU is in Normal mode IOPTO is in range (1) (Figure 9). This range is
characterized by the parameter IOPTO(δmax). The primary controller is in range (1)
(Figure 9) when −IOPTO > −IOPTO(δmax)
.
Remark: a current drawn from a pin is called a negative current by general convention.
In range (1) in Figure 9 the frequency is determined by the current IIREF (see Section 8.4).
The duty cycle, and therefore the on-time that goes with the duty cycle, is additionally
determined by VLVIN that reflects the input voltage (see Section 8.5).
TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
13 of 25
TEA1771
NXP Semiconductors
GreenChip PC primary control IC
Standby mode
Normal mode
(1)
(2)
(3)
duty cycle δ
t
on
t
on(min)
f
osc(max)
frequency
−I
−I
−I
OPTO
OPTO(fmax)
OPTO(δmax)
(1)
(2)
(3)
014aaa176
Fig 9. Duty cycle regulation via the IOPTO output current
To optimize the efficiency, the duty cycle of the primary controller is reduced when the
PSU enters Standby mode. In Standby mode the duty cycle is regulated via the current
IOPTO. The duty cycle can be reduced by lowering the current IOPTO. Starting from the high
duty cycle in Normal mode the on-time is reduced first. This is shown in range (2)
(Figure 9). In this range the on-time can be reduced to a minimum level, ton(min). When the
duty cycle is reduced further the frequency will be decreased, while the on-time stays at
its minimum level. The transition between ranges (2) and (3) (Figure 9) is 2IIREF. When
−IOPTO < −2IIREF the primary controller operates in range (3) (Figure 9). Here the on-time
is at the minimum level and the duty cycle is regulated via the frequency.
The duty cycle regulation has been made to obtain a good efficiency in Standby mode. By
reducing the duty cycle magnetizing losses are reduced in the transformer. The minimum
on-time is needed to obtain a minimum magnetizing current that makes sure the ZVS of
both the main switch and the reset switch.
TEA1771_1
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The opto coupler current is regulated by the secondary control. At start-up this current
may be zero. To arrange a minimum IOPTO level a resistor is placed at the OPTO pin, in
parallel to the opto coupler (see R3 in Figure 11). In this way a minimum operating
frequency is set. A 56 kΩ resistor on the OPTO pin sets the minimum frequency to
approximately 20 kHz.
8.9 Reset circuitry
The TEA1771 has an integrated reset switch (see M2 in the DRIVERS block in Figure 1).
The high side circuitry driving the high side reset switch is supplied from an external boost
capacitor at pin CB. This capacitor is charged via an internal diode from DECPVCC when
DM1 is low. This occurs when the primary main switch M1 is turned on.
8.10 Protections
To protect the controller ICs and the application against malfunction, the System failure
mode is entered at a fault condition. In this mode, the switching of the main switch and
reset switch is stopped.
The following protections are available in the TEA1771:
• Overcurrent protection
• Short-winding protection (swp1 and swp2)
• Overvoltage protection
• External protection via IOPTO
When the primary controller enters System failure mode the charge current from DM2 to
LVIN stays turned off. Because the switching is stopped, the auxiliary supply to LVIN is
stopped as well. The LVIN capacitor is slowly discharged by the IC. Eventually VDECVCC
drops below VUVLO(DECVCC). At this point the IC enters Charge mode and the current
source from DM2 to LVIN is turned on. This is called the system safe restart. The power
up sequence is explained in Section 8.2.
How long the IC is in System failure mode depends on the external capacitance at
DECVCC, DECPVCC and LVIN, and on the discharge current of the IC. As soon as
VUVLO(DECVCC) is reached, the IC enters Charge mode and restarts.
To avoid false triggering of overcurrent protection or short-winding protection, a blanking
period is activated when either M1 or M2 is turned on. During this blanking period the
overcurrent protection and short-winding protection detection are disabled. In the
characteristics table this period is called the leading edge blanking time tleb
.
8.10.1 Overcurrent protection
Figure 10 shows the current sense circuit that is involved with the OCP and SWP
protections.
When switch M1 is on, (and the reset switch M2 is off), the voltage at the SENSE pin
equals the voltage across Rsense1, This voltage is a used as a measure of the current
through M1. See Figure 10. When the voltage on pin SENSE exceeds the OCP voltage
level, VOCP (typically 250 mV), M1 is turned off and then turned on again at the next cycle.
The primary controller remains in Running mode. Here the overvoltage protection differs
from other protections where the IC enters System failure mode.
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V
I
V
prim
DM2
DM1
M2
primary control
V
rst
M1
SENSE
PGND
R
sense2
R
sense1
014aaa178
Fig 10. Current sense circuit
8.10.2 Short-winding protection
A shorted transformer winding can occur when either the primary main switch is on
(positive secondary winding voltage) or when the system is in the reset phase (negative
secondary winding voltage). In the first situation, a high positive current occurs through
Rsense1. In the latter situation, a high negative current occurs through Rsense2. Therefore,
the system has both a positive (Vswp1) and negative (Vswp2) SWP.
If the voltage on pin SENSE exceeds the voltage level Vswp1 (300 mV) or
Vswp2 (−255 mV), the system enters System failure mode, disabling both switches. A safe
restart will follow.
8.10.3 System failure mode externally activated
The primary side control IC can also be forced to enter System failure mode externally by
pulling a current of Iprot(OPTO) from the pin OPTO.
The secondary side activates this function if all secondary protections fail, e.g. when the
bidirectional switch is shorted. The secondary side then increases the current drawn from
the pin OPTO via the opto coupler.
Entering System failure mode is followed by a safe restart.
8.10.4 Reset capacitor voltage
The voltage across the reset capacitor (DM2) is sensed on pin VRST by using an external
high ohmic resistive divider. System failure mode is activated when the voltage on pin
VRST reaches the Vovp(VRST) level. A safe restart will follow.
As the voltage at DM2 equals the maximum drain voltage of the main switch M1 this
switch is protected from breaking down.
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8.11 Ground
The IC has a separate Power Ground (PGND) for sinking the driver currents. This
prevents signal noise on the signal, Ground (GND).
9. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Voltages
VLVIN
Parameter
Conditions
Min
Max
Unit
[1]
voltage on pin LVIN
voltage on pin DM1
continuous
continuous
−0.4
−0.4
−0.4
+48
V
V
V
VDM1
+570
+650
peak; ∆t = 1 µs;
non-repetitive
VDM2
voltage on pin DM2
continuous
−0.4
−0.4
+570
+650
V
V
peak; ∆t = 1 ms;
non-repetitive
Currents
IIREF
current on pin IREF
current on pin OPTO
−300
−13
-
µA
IOPTO
low power and
normal mode
0
mA
IDM1
IDM2
General
Ptot
current on pin DM1
current on pin DM2
−300
−300
+300
+300
mA
mA
total power dissipation
storage temperature
ambient temperature
junction temperature
Tamb < 45 °C
-
1.0
Ω
Tstg
−55
−20
−20
+150
+85
°C
°C
°C
Tamb
Tj
+145
Vesd
electrostatic discharge
voltage
human body model[2]
pins DM2, DM1,
and CB
−1500
−2000
+1500
+2000
V
V
all other pins
machine model[3]
all pins
−200
+200
500
V
V
charged device
model
-
[1] Pin LVIN cannot to be current driven.
[2] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
[3] Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω series
resistor.
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10. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
[1]
thermal resistance from junction in free air
to ambient
75
K/W
[1] Thermal resistance Rth(j-a) can be lower when pin GND is connected to sufficient copper area on the
printed-circuit board. See the TEA1771 application notes for details.
11. Characteristics
Table 6.
Characteristics
Tamb = 25 °C; no overtemperature; all voltages are measured with respect to ground; currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Start-up and supply management
Vstartup(LVIN)
VUVLO(DECVCC)
VDECVCC
start-up voltage on pin
LVIN
14.4
8.25
10.9
15.2
9.0
16.0
9.75
12.7
V
V
V
undervoltage lockout
voltage on pin DECVCC
voltage on pin DECVCC
running mode;
12.0
VLVIN = 25 V;
I
I
IREF = −200 µA;
OPTO = −2 mA
Vhys(DECVCC)
VDECPVCC
hysteresis voltage on pin
DECVCC
1.7
3.1
4.5
V
V
voltage on pin DECPVCC running mode;
LVIN = 25 V;
12.4
13.0
13.6
V
IIREF = −200 µA;
IOPTO = −2 mA;
C
DRIVER = 100 pF
charge mode; VDM2 = 100 V;
VLVIN
Ich(DM2)
Ich(LVIN)
ILVIN
charge current on pin
DM2
=
0.0 V
2.3
2.1
2.9
2.7
3.5
3.3
mA
mA
13.7 V
charge current on pin
LVIN
charge mode; VDM2 = 100 V; IOPTO = 0 mA; IIREF = 0 mA;
VLVIN
=
0.0 V
−3.2
−1.3
3.0
−2.6
−0.7
4.0
−2.0
−0.1
5.0
mA
mA
mA
13.7 V
current on pin LVIN
running mode;
I
I
OPTO = −2 mA;
IREF = −200 µA;
C
DRIVER = 100 pF
5 V reference
V5VREF
voltage on pin 5VREF
4.75
5.00
5.25
V
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Table 6.
Characteristics …continued
Tamb = 25 °C; no overtemperature; all voltages are measured with respect to ground; currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Soft start
VCSS
Parameter
Conditions
Min
Typ
Max
Unit
voltage on pin CSS
running mode;
after soft start has
completed
3.7
4.1
4.5
V
ICSS
current on pin CSS
running mode;
during soft start;
V
25
45
55
µA
kΩ
CSS = 0 V
internal resistance on pin charge mode or
CSS system failure mode;
CSS = 4 V
Oscillator, opto control and secondary protection
Rint(CSS)
4.5
5.5
7.0
V
VIREF
voltage on pin IREF
charge mode;
IREF = −1 mA
0.40
3.2
0.55
3.6
0.70
4.0
4.0
-
V
I
running mode;
IIREF = −1 mA
V
VOPTO
voltage on pin OPTO
running mode;
3.2
3.6
V
IOPTO = −1 mA
system failure mode;
-
0.0
V
IOPTO = −1 mA
IOPTO(fmax)
IOPTO(δmax)
Iprot(OPTO)
δmax
current on pin OPTO
(maximum frequency)
IIREF = −100 mA;
−250
−1.8
−11
−200
−1.4
−9
−170
−1.0
−7
µA
mA
mA
V
LVIN = 25 V
IIREF = −100 mA;
LVIN = 25 V
charge/running mode
current on pin OPTO
(maximum duty cycle)
V
protection current on pin
OPTO
maximum duty cycle
IOPTO < IOPTO(δmax); IIREF = −100 mA;
VLVIN
=
12 V
54.0
36.4
23.2
;
59.0
41.9
26.6
64.0
47.3
30.0
%
%
%
25 V
40 V
fosc(max)
maximum oscillator
frequency
IOPTO(fmax) > IOPTO > Iprot(OPTO)
IIREF
=
−100 µA
40
80
50
100[1]
60
kHz
kHz
−200 µA
120
ton(min)
minimum on-time
IOPTO > IOPTO(fmax);
VLVIN
=
12 V
25 V
40 V
0.7
0.5
0.3
1.1
0.7
0.5
1.5
0.9
0.7
µs
µs
µs
Non-overlap times of main switch and reset switch
tno(rstsw-mainsw)
non-overlap time from
reset switch to main
switch
IOPTO =
IOPTO = −0.5 mA
IOPTO = −1.5 mA
0.91
0.68
1.15
0.87
1.39
1.06
µs
µs
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Table 6.
Characteristics …continued
Tamb = 25 °C; no overtemperature; all voltages are measured with respect to ground; currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
3.14
1.51
Typ
4.16
1.85
Max
5.18
2.19
Unit
µs
tno(bu)
backup non-overlap time IOPTO = −0.5 mA
IOPTO = −1.5 mA
µs
Ramp detection
twait
wait time
after ramp-up
1.48
-
1.80
50
2.12
-
µs
(dV/dt)r
rise rate of change of
voltage
V/µs
Driver
RDSon
drain-source on-state
resistance
I = 50 mA
30
40
50
Ω
Ω
I = 150 mA
2.5
5.0
8.0
Reset capacitor measurement: pin VRST
Vstart(VRST)(min)
Vstart(VRST)(max)
Vovp(VRST)
minimum start voltage on charge mode
pin VRST
0.57
2.52
3.49
-
0.61
2.62
3.62
-
0.66
2.71
3.74
520
V
maximum start voltage on charge mode
pin VRST
V
overvoltage protection
voltage on pin VRST
running mode
V
Isink(VRST)
sink current on pin VRST voltage on pin > 0.5 V
nA
Overcurrent protection and short-winding protection: pin SENSE
Vocp
Vswp1
Vswp2
tleb
overcurrent protection
voltage
running mode
running mode
running mode
-
250
300
−250
400
-
mV
mV
mV
ns
short-winding protection
voltage 1
250
−290
-
350
−210
-
short-winding protection
voltage 2
leading edge blanking
time
Floating supply on pins CB and DM1 (VDD(float) = VCB − VDM1
)
VDD(float)
float supply voltage
-
8.0
-
V
V
VDD(float)UVLO
undervoltage lockout float
supply voltage
4.25
4.75
5
Reset switch
RDSon
drain-source on-state
resistance
running mode; VCB − VDM1 = 12 V
IDM2 = 0.1 A
IDM2 = 0.3 A
20
11
25
15
30
22
Ω
Ω
[1] For the PSU, the recommended operating frequency is 75 kHz. The operating frequency can be raised to 100 kHz provided that the
PSU input voltage, VI, is above a minimum level which is typically 200 V. An application solution is available that automatically lowers the
frequency when, during a mains dip, VI drops below this minimum level. See application note.
TEA1771_1
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Product data sheet
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12. Application information
Auxiliary
winding
C
LVIN
V (DC)
I
Main primary
winding
D
rst
1
2
24
DM2
DM1
23
22
n.c.
CB
n.c.
3
4
TEA1771
n.c.
R1
21
20
LVIN
GND
GND
DECVCC
n.c.
C
rst
5
6
GND
19
18
17
16
5VREF
PGND
7
8
V
SENSE
DRIVER
PGND
RST
M1
9
IREF
CSS
10
11
12
15
14
OPTO
n.c.
DECPVCC
n.c.
R2
13
R3
014aaa728
Fig 11. TEA1771 application diagram
TEA1771_1
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Product data sheet
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13. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 12. Package outline SOT137-1 (SO24)
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14. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TEA1771_1
20090206
Product data sheet
-
-
TEA1771_1
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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17. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Functional description . . . . . . . . . . . . . . . . . . . 5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Modes of operation. . . . . . . . . . . . . . . . . . . . . . 6
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Feed-forward regulation . . . . . . . . . . . . . . . . . . 8
Non-overlap times. . . . . . . . . . . . . . . . . . . . . . 11
Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Standby regulation . . . . . . . . . . . . . . . . . . . . . 13
Reset circuitry. . . . . . . . . . . . . . . . . . . . . . . . . 15
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overcurrent protection . . . . . . . . . . . . . . . . . . 15
Short-winding protection. . . . . . . . . . . . . . . . . 16
System failure mode externally activated . . . . 16
Reset capacitor voltage . . . . . . . . . . . . . . . . . 16
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.8
8.9
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.11
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal characteristics. . . . . . . . . . . . . . . . . . 18
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information. . . . . . . . . . . . . . . . . . 21
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 February 2009
Document identifier: TEA1771_1
相关型号：
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Synchronous rectification controller suitable for both high-side and low-side control SOIC 8-Pin
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