TJA1059TKJ [NXP]
TJA1059 - Dual high-speed CAN transceiver with Standby mode SON 14-Pin;
| 型号： | TJA1059TKJ |
| 厂家： | 
NXP |
| 描述： | TJA1059 - Dual high-speed CAN transceiver with Standby mode SON 14-Pin 电信 光电二极管 电信集成电路 |
| 文件： | 总21页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TJA1059
Dual high-speed CAN transceiver with Standby mode
Rev. 1 — 24 January 2014
Product data sheet
1. General description
The TJA1059 is a dual high-speed CAN transceiver that provides an interface between a
Controller Area Network (CAN) protocol controller and the physical two-wire CAN-bus.
The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in the
automotive and truck industries. It provides differential transmit and receive capabilities to
(a microcontroller with) a CAN protocol controller.
The TJA1059 belongs to the third generation of high-speed CAN transceivers from NXP
Semiconductors, offering significant improvements over first- and second-generation
devices such as the TJA1040. It offers improved Electro Magnetic Compatibility (EMC)
and ElectroStatic Discharge (ESD) performance, and also features:
• Ideal passive behavior to the CAN-bus when the supply voltage is off
• A very low-current Standby mode with bus wake-up capability on both channels
• Can be interfaced directly to microcontrollers with supply voltages from 3 V to 5 V
• Complies with global OEM requirements, allowing a one-fits-all approach
These features make the TJA1059 an excellent choice for all types of HS-CAN networks
containing more than one HS-CAN interface requiring a low-power mode with wake-up
capability via the CAN-bus, especially for Body Control and Gateway units.
2. Features and benefits
2.1 General
Two TJA1049 HS-CAN transceivers combined monolithically in a single package
Fully ISO 11898-2 and ISO 11898-5 compliant
Suitable for 12 V and 24 V systems
Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)
Excellent ElectroMagnetic Compatibility (EMC) performance, satisfying 'Hardware
Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications’,
Version 1.3, May 2012.
VIO input allows for direct interfacing with 3 V to 5 V microcontrollers
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.2 Predictable and fail-safe behavior
Functional behavior predictable under all supply conditions
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
Transceiver disengages from bus when not powered (zero load)
Transmit Data (TXD) and bus dominant time-out functions
Undervoltage detection on pins VCC and VIO
Internal biasing of TXD1/TXD2 and STB1/STB2 input pins
2.3 Low-power management
Very low-current Standby mode with host and bus wake-up capability
Wake-up receiver powered by VIO; allows shut down of VCC
2.4 Protection
High ESD handling capability on the bus pins
Bus pins protected against transients in automotive environments
Thermally protected
High-voltage robustness on the bus pins
3. Quick reference data
Table 1.
Symbol
VCC
Quick reference data
Parameter
Conditions
Min
4.75
-
Typ Max Unit
supply voltage
supply current
-
5.25
5
V
ICC
Standby mode
0.5
A
Normal mode
both channels recessive
one channel dominant
both channels dominant
-
-
20
mA
mA
mA
V
-
-
80
-
90
-
140
4.5
Vuvd(VCC)
undervoltage detection voltage on
pin VCC
3.5
VIO
IIO
supply voltage on pin VIO
supply current on pin VIO
2.85
-
-
5.25
V
Standby mode; VTXD = VIO
Normal mode
16.5 27
A
both channels recessive
one channel dominant
both channels dominant
-
-
-
-
55
A
A
A
V
-
400
600
-
Vuvd(VIO)
undervoltage detection voltage on
pin VIO
1.3
2.0 2.7
VESD
electrostatic discharge voltage
voltage on pin CANH
IEC 61000-4-2 at pins CANHx and CANLx 6
-
-
+6
kV
V
VCANH
pins CANH1 and CANH2; no time limit;
DC limiting value
58
+58
VCANL
Tvj
voltage on pin CANL
pins CANL1 and CANL2; no time limit; DC 58
limiting value
-
-
+58
V
virtual junction temperature
40
+150 C
TJA1059
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
2 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
4. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TJA1059TK
HVSON14
plastic, thermal enhanced very thin small outline package; no leads;
SOT1086-2
14 terminals; body 3 4.5 0.85 mm
TJA1059
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
3 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
5. Block diagram
V
V
3
IO
CC
11
V
/V
CC IO
TEMPERATURE
PROTECTION
UNDERVOLTAGE
DETECTION
13
12
CANH1
CANL1
SLOPE CONTROL
AND DRIVER
MODE
CONTROL
1
TIME-OUT
TXD1
STB1
V
V
CC
IO
V
IO
NORMAL
RECEIVER
14
WAKE-UP
FILTER
LOW-POWER
RECEIVER
V
CC
4
MUX and
DRIVER
RXD1
10
9
CANH2
CANL2
V
IO
SLOPE CONTROL
AND DRIVER
6
TXD2
STB2
TIME-OUT
V
IO
V
V
CC
8
NORMAL
RECEIVER
IO
WAKE-UP
FILTER
LOW-POWER
RECEIVER
7
2
MUX and
DRIVER
RXD2
GNDA
5
GNDB
015aaa425
Fig 1. Block diagram
TJA1059
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
4 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
6. Pinning information
6.1 Pinning
TJA1059TK
terminal 1
index area
TXD1
1
2
3
4
5
6
7
14 STB1
GNDA
13 CANH1
12 CANL1
V
CC
RXD1
GNDB
TXD2
RXD2
11
V
IO
10 CANH2
9
CANL2
STB2
8
015aaa424
Fig 2. Pin configuration diagram
6.2 Pin description
Table 3.
Pin description
Pin Description
Symbol
TXD1
GNDA
VCC
1
transmit data input 1
2[1] ground
3
transceiver supply voltage
RXD1
GNDB
TXD2
RXD2
STB2
CANL2
CANH2
VIO
4
receive data output 1; reads out data from bus line1
5[1] ground
6
7
8
9
transmit data input 2
receive data output 2; reads out data from bus line 2
standby control input 2 (HIGH = Standby mode, LOW = Normal mode)
LOW-level CAN-bus line 2
10 HIGH-level CAN-bus line 2
11 supply voltage for I/O level adapter
CANL1
CANH1
STB1
12 LOW-level CAN-bus line 1
13 HIGH-level CAN-bus line 1
14 standby control input 1 (HIGH = Standby mode, LOW = Normal mode)
[1] Pins 2 and 5 must be connected together externally in the application. The exposed die pad at the bottom
of the package allows for enhanced heat dissipation and grounding from the package to the printed circuit
board. Connect the exposed die pad to GND.
TJA1059
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
5 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
7. Functional description
The TJA1059 is a dual HS-CAN stand-alone transceiver with Standby mode and robust
ESD handling capability. It combines the functionality of two TJA1040/TJA1049
transceivers with improved EMC and quiescent current performance. Improved slope
control and high DC handling capability on the bus pins provide additional application
flexibility.
7.1 Operating modes
The TJA1059 supports two operating modes per transceiver, Normal and Standby. The
operating mode can be selected independently for each transceiver via pins STB1 and
STB2 (see Table 4).
Table 4.
Mode
Operating modes
Pin STB1/STB2
Pin RXD1/RXD2
LOW
HIGH
Normal
LOW
HIGH
bus dominant
bus recessive
Standby
wake-up request detected
no wake-up request detected
7.1.1 Normal mode
A LOW level on pin STB1/STB2 selects Normal mode. In this mode, the transceiver can
transmit and receive data via the bus lines CANH1/CANL1 and CANH2/CANL2 (see
Figure 1 for the block diagram). The differential receiver converts the analog data on the
bus lines into digital data which is output on pin RXD1/RXD2. The slope of the output
signals on the bus lines is controlled and optimized in a way that guarantees the lowest
possible EME.
7.1.2 Standby mode
A HIGH level on pin STB1/STB2 selects Standby mode. In Standby mode, the transceiver
is not able to transmit or correctly receive data via the bus lines. The transmitter and
Normal-mode receiver blocks are switched off to reduce supply current, and only a
low-power differential receiver monitors the bus lines for activity.
In Standby mode, the bus lines are biased to ground to minimize the system supply
current. The low-power receiver is supplied by VIO and can detect CAN-bus activity even if
V
IO is the only supply voltage available. When pin RXD1/RXD2 goes LOW to signal a
wake-up request, a transition to Normal mode is not triggered until STB1/STB2 is forced
LOW.
A dedicated wake-up sequence (specified in ISO11898-5) must be received before the
TJA1059 outputs the bus signals on RXD1/RXD2. This filtering is necessary to avoid
spurious wake-up events due to a dominant clamped CAN-bus or dominant phases
caused by noise or spikes on the bus.
A valid wake-up pattern consists of:
A dominant phase of at least twake(busdom) followed by
A recessive phase of at least twake(busrec) followed by
A dominant phase of at least twake(busdom)
TJA1059
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
6 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
The complete dominant-recessive-dominant pattern must be received within tto(wake)bus to
be recognized as a valid wake-up pattern (see Figure 3). Pin RXD1/RXD2 remains
recessive until the wake-up event has been triggered.
After a wake-up sequence has been detected, the TJA1059 remains in Standby mode
with the bus signals reflected on RXD1/RXD2. Note that dominant or recessive phases
lasting less than tfltr(wake)bus are not detected by the low-power differential receiver and will
not be reflected on RXD1/RXD2 in Standby mode.
A wake-up event is not registered if any of the following events occur while a wake-up
sequence is being transmitted:
• the TJA1059 switches to Normal mode
• the complete wake-up pattern was not received within tto(wake)bus
• a VIO undervoltage is detected (VIO < Vuvd(VIO); see Section 7.2.3)
If any of these events occur while a wake-up sequence is being received, the internal
wake-up logic is reset. The complete wake-up sequence will need to be retransmitted to
trigger a wake-up event.
t
wake(busrec)
CANHx
CANLx
V
O(diff)bus
t
t
wake(busdom)
wake(busdom)
RXDx
t
t
fltr(wake)bus
fltr(wake)bus
t
to(wake)bus
015aaa147
Fig 3. Wake-up timing
7.2 Fail-safe features
7.2.1 TXD dominant time-out function
A 'TXD dominant time-out' timer is started when pin TXD1/TXD2 is set LOW. If the LOW
state on this pin persists for longer than tto(dom)TXD, the transmitter is disabled, releasing
the bus lines to recessive state. This function prevents a hardware and/or software
application failure from driving the bus lines to a permanent dominant state (blocking all
network communications). The TXD dominant time-out timer is reset when pin
TXD1/TXD2 is set HIGH. The TXD dominant time-out time also defines the minimum
possible bit rate of 40 kbit/s. The TJA1059 has two TXD dominant time-out timers that
operate independently of each other.
TJA1059
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
7 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
7.2.2 Internal biasing of TXD1, TXD2, STB1 and STB2 input pins
Pins TXD1, TXD2, STB1 and STB2 have internal pull-ups to V . The pull-ups ensure a
IO
safe, defined state if any of these pins are left floating. Pins GNDA and GNDB must be
connected together in the application.
Pull-up currents flow in these pins in all states. Pins TXD1, TXD2, STB1 and STB2 should
be held HIGH in Standby mode to minimize standby currents.
7.2.3 Undervoltage detection on pins VCC and VIO
Should VCC drop below the VCC undervoltage detection level, Vuvd(VCC), both transceivers
will switch to Standby mode. The logic state of pins STB1 and STB2 is ignored until VCC
has recovered.
Should VIO drop below the VIO undervoltage detection level, Vuvd(VIO), the transceivers will
switch off and disengage from the bus (zero load) until VIO has recovered.
7.2.4 Overtemperature protection
The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, Tj(sd), both output drivers are
disabled. When the virtual junction temperature drops below Tj(sd) again, the output
drivers will recover independently once TXD1/TXD2 have been reset to HIGH. Including
the TXD1/TXD2 condition prevents output driver oscillation due to small variations in
temperature.
7.3 VIO supply pin
Pin VIO should be connected to the microcontroller supply voltage (see Figure 5). This
adjusts the signal levels of pins TXD1, TXD2, RXD1, RXD2, STB1 and STB2 to the I/O
levels of the microcontroller. Pin VIO also provides the internal supply voltage for the
low-power differential receiver of the transceiver. It allows applications running in
low-power mode to monitor the bus lines for activity, even if there is no supply voltage on
pin VCC
.
TJA1059
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
8 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter
Conditions
Min
Max
Unit
Vx
voltage on pin x
no time limit; DC value
on pins CANH1, CANL1, CANH2 and CANL2
58
+58
+7
V
V
V
on any other pin
0.3
[1]
[2]
[3]
[4]
Vtrt
transient voltage
on pins CANH1, CANL1, CANH2 and CANL2
150 +100
VESD
electrostatic discharge voltage
IEC 61000-4-2
on pins CANH1, CANL1, CANH2 and CANL2
6
+6
kV
HBM
on pins CANH1, CANL1, CANH2 and CANL2
6
4
+6
+4
kV
kV
at any other pin
MM
[5]
[6]
at any pin
CDM
300 +300
V
at corner pins
at any pin
750 +750
500 +500
V
V
[7]
Tvj
virtual junction temperature
storage temperature
40
55
+150
+150
C
C
Tstg
[1] Verified by an external test house to ensure pins CANH1, CANL1, CANH2 and CANL2 can withstand ISO7637 part 1 and 2 automotive
transient test pulses.
[2] IEC 61000-4-2 (150 pF, 330 ).
[3] ESD performance of pins CANH1, CANL1, CANH2 and CANL2 according to IEC 61000-4-2 (150 pF, 330 ) has been be verified by an
external test house.
[4] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k).
[5] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ).
[6] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF).
[7] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(vj-a), where Rth(vj-a) is a
fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
9. Thermal characteristics
Table 6.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
73
Unit
K/W
K/W
[1]
[2]
thermal resistance from junction to ambient
HVSON14; single-layer board
HVSON14; four-layer board
42
[1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board.
[2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers
(thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer.
TJA1059
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
9 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
10. Static characteristics
Table 7.
Static characteristics
Tvj = 40 C to +150 C, VCC = 4.75 V to 5.25 V, VIO = 2.85 V to 5.25 V and RL = 60 unless specified otherwise. All
voltages are defined with respect to ground. Positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pin VCC
VCC
supply voltage
4.75
3.5
-
-
5.25
4.5
V
V
Vuvd(VCC)
undervoltage detection
voltage on pin VCC
ICC
supply current
Standby mode; VTXD = VIO
Normal mode
-
0.5
5
A
both channels recessive
one channel dominant
both channels dominant
-
-
-
-
20
mA
mA
mA
-
80
90
140
I/O level adapter supply; pin VIO
VIO
supply voltage on pin VIO
2.85
1.3
-
5.25
2.7
V
V
Vuvd(VIO)
undervoltage detection
voltage on pin VIO
2.0
IIO
supply current on pin VIO Standby mode; VTXD = VIO
Normal mode
-
16.5
27
A
both channels recessive
-
-
-
-
-
-
55
A
A
A
one channel dominant
400
600
both channels dominant
Standby mode control input; pins STB1 and STB2
VIH
VIL
IIH
HIGH-level input voltage
0.7VIO
0.3
5
-
-
-
-
VIO + 0.3
0.3VIO
+5
V
LOW-level input voltage
HIGH-level input current VSTB[1] = VIO
V
A
A
IIL
LOW-level input current
VSTB = 0 V
15
1
CAN transmit data input; pins TXD1 and TXD2
VIH
VIL
IIH
IIL
HIGH-level input voltage
0.7VIO
0.3
5
-
VIO + 0.3
0.3VIO
+5
V
LOW-level input voltage
HIGH-level input current VTXD[2] = VIO
-
V
-
A
A
pF
LOW-level input current
input capacitance
VTXD = 0 V
260
-
150
30
[3]
Ci
5
10
CAN receive data output; pins RXD1 and RXD2
IOH
HIGH-level output current VRXD[4] = VIO 0.4 V; VIO = VCC
IOL LOW-level output current VRXD = 0.4 V; bus dominant
Bus lines; pins CANH1, CANL1, CANH2 and CANL2
8
3
1
mA
mA
1
-
12
VO(dom)
dominant output voltage VTXD = 0 V; t < tto(dom)TXD
pin CANH1/CANH2
2.75
0.5
3.5
1.5
4.5
V
V
pin CANL1/CANL2
2.25
TJA1059
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
10 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
Table 7.
Static characteristics …continued
Tvj = 40 C to +150 C, VCC = 4.75 V to 5.25 V, VIO = 2.85 V to 5.25 V and RL = 60 unless specified otherwise. All
voltages are defined with respect to ground. Positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[6]
Vdom(TX)sym transmitter dominant
voltage symmetry
Vdom(TX)sym = VCC VCANH[5] VCANL
400
-
+400
mV
VO(dif)bus
bus differential output
voltage
VTXD = 0 V; t < tto(dom)TXD
VCC = 4.75 V to 5.25 V; RL = 45 to 65
1.5
-
3
V
V
TXD = VIO; recessive; no load
50
2
-
+50
3
mV
V
VO(rec)
recessive output voltage Normal mode; VTXD = VIO; no load
Standby mode; no load
0.5VCC
-
0.1
0.5
0.4
+0.1
0.9
1.15
V
[7]
[7]
Vth(RX)dif
differential receiver
threshold voltage
Normal mode; Vcm(CAN) = 12 V to +12 V
0.7
V
Standby mode
0.7
V
Vcm(CAN) = 12 V to +12 V
[7]
Vhys(RX)dif
IO(dom)
differential receiver
hysteresis voltage
Normal mode; Vcm(CAN) = 12 V to +12 V
100
-
300
mV
dominant output current
VTXD = 0 V; t < tto(dom)TXD; VCC = 5 V
pin CANH1/CANH2; VCANH = 0 V
pin CANL1/CANL2; VCANL = 5 V/40 V
100
40
70
70
-
40
100
+5
mA
mA
mA
IO(rec)
IL
recessive output current Normal mode; VTXD = VIO
5
VCANH = VCANL = 40 V to +40 V
leakage current
input resistance
VCC = VIO = 0 V or VCC = VIO = shorted to
ground via 47 k; VCANH = VCANL = 5 V
5
-
+5
A
Ri
9
15
-
28
+3
k
Ri
input resistance deviation between pin CANH1/CANH2 and pin
CANL1/CANL2
3
%
Ri(dif)
Ci(cm)
Ci(dif)
differential input
resistance
19
-
30
-
52
20
10
k
pF
pF
[3]
[3]
common-mode input
capacitance
differential input
capacitance
-
-
Temperature detection
Tj(sd) shutdown junction
temperature
[3]
-
190
-
C
[1] STB refers to the input signal on pin STB1 or pin STB2.
[2] TXD refers to the input signal on pin TXD1 or pin TXD2.
[3] Not tested in production.
[4] RXD refers to the output signal on pin RXD1 or pin RXD2.
[5] CANH refers to the input/output signal on pin CANH1 or pin CANH2.
[6] CANL refers to the input/output signal on pin CANL1 or pin CANL2.
[7]
V
cm(CAN) is the common mode voltage of CANH1/CANL1 and CANH2/CANL2.
TJA1059
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 24 January 2014
11 of 21
TJA1059
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Tvj = 40 C to +150 C, VCC = 4.75 V to 5.25 V, VIO = 2.85 V to 5.25 V and RL = 60 unless specified otherwise. All
voltages are defined with respect to ground;. Positive currents flow into the IC.
Symbol
Parameter
Conditions
Min Typ
Max
Unit
Transceiver timing; pins CANH1, CANH2, CANL1, CANL2, TXD1, TXD2, RXD1 and RXD2; see Figure 4 and Figure 6
td(TXD-busdom) delay time from TXD to bus dominant
td(TXD-busrec) delay time from TXD to bus recessive
td(busdom-RXD) delay time from bus dominant to RXD
td(busrec-RXD) delay time from bus recessive to RXD
Normal mode
-
65
90
60
65
-
140
140
140
140
250
5
ns
ns
ns
ns
ns
ms
s
s
s
ms
s
Normal mode
-
Normal mode
-
Normal mode
-
tPD(TXD-RXD)
tto(dom)TXD
td(stb-norm)
propagation delay from TXD to RXD
TXD dominant time-out time
Normal mode
60
0.5
7
VTXD = 0 V; Normal mode
2
standby to normal mode delay time
25
-
47
5
twake(busdom) bus dominant wake-up time
Standby mode
Standby mode
0.5
0.5
0.5
0.5
twake(busrec)
tto(wake)bus
tfltr(wake)bus
bus recessive wake-up time
bus wake-up time-out time
bus wake-up filter time
-
5
2
5
Standby mode
1.5
5
HIGH
LOW
TXDx
CANHx
CANLx
dominant
0.9 V
0.5 V
V
O(dif)(bus)
recessive
HIGH
0.7V
IO
RXDx
0.3V
IO
LOW
t
t
d(TXD-busrec)
d(TXD-busdom)
t
t
d(busrec-RXD)
d(busdom-RXD)
t
t
PD(TXD-RXD)
PD(TXD-RXD)
015aaa211
Fig 4. CAN transceiver timing diagram
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12. Application information
ꢁꢃ9
%$7
ꢂꢃ9
ꢀꢁ
9
9
,2
&&
ꢁ
ꢀꢀ
&$1+ꢀ
ꢍꢀꢎ
67%ꢀ
67%ꢇ
9
''
ꢀꢅ
ꢆ
3[[
3\\
5
5
HꢌJꢌ
ꢅꢌꢊꢃQ)
7
7;'ꢀ
5;'ꢀ
ꢀ
ꢅ
7;ꢈ
5;ꢈ
0,&52ꢄ
ꢍꢀꢎ
&21752//(5
7
&$1/ꢀ
ꢀꢇ
ꢀꢈ
7-$ꢀꢁꢂꢃ
7;'ꢇ
5;'ꢇ
ꢉ
ꢊ
7;ꢀ
5;ꢀ
&$1+ꢇ
*1'
ꢍꢀꢎ
5
7
HꢌJꢌ
ꢅꢌꢊꢃQ)
*1'$
*1'%
ꢇ
ꢂ
ꢍꢀꢎ
5
7
&$1/ꢇ
ꢋ
ꢀꢁꢂDDDꢃꢄꢅ
(1) For bus line end nodes, RT = 60 in order to support the ‘split termination concept’. For
sub-nodes, an optional ‘weak’ termination of e.g. RT = 1.3 k can be used, if required by the OEM.
Fig 5. Typical application with 3 V microcontroller
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13. Test information
ꢏꢂꢃ9
ꢅꢊꢃ)
ꢀꢈꢈꢃQ)
9
9
67%ꢀ 67%ꢇ
,2
&&
&$1+ꢀ
5
5
ꢀꢈꢈꢃS)
ꢀꢈꢈꢃS)
/
7;'ꢀ
&$1/ꢀ
&$1+ꢇ
7;'ꢇ
7-$ꢀꢁꢂꢃ
5;'ꢀ
5;'ꢇ
/
ꢀꢂꢃS)
&$1/ꢇ
*1'%
ꢀꢂꢃS)
*1'$
ꢀꢁꢂDDDꢃꢄꢆ
Fig 6. Timing test circuit for CAN transceiver
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
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14. Package outline
HVSON14: plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 x 4.5 x 0.85 mm
SOT1086-2
X
D
B
A
E
A
A
1
c
terminal 1
index area
detail X
e
1
terminal 1
index area
C
v
C A
C
B
e
b
y
1
y
w
C
1
7
L
k
E
h
14
8
D
h
0
2.5
5 mm
w
scale
Dimensions
Unit
A
A
b
c
D
D
h
E
E
e
e
1
k
L
v
y
y
1
1
h
max 1.00 0.05 0.35
mm nom 0.85 0.03 0.32 0.2 4.5 4.20 3.0 1.60 0.65 3.9 0.30 0.40 0.1 0.05 0.05 0.1
min 0.80 0.00 0.29 4.4 4.15 2.9 1.55 0.25 0.35
4.6 4.25 3.1 1.65
0.35 0.45
sot1086-2
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
10-07-14
10-07-15
SOT1086-2
MO-229
Fig 7. Package outline SOT1086 (HVSON14)
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15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 8) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
350
220
< 2.5
235
220
2.5
220
Table 10. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 8.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 8. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of HVSON packages
Section 16 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
• AN10365 ‘Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
18. Revision history
Table 11. Revision history
Document ID
Release date
20140124
Data sheet status
Change notice
Supersedes
TJA1059 v.1
Product data sheet
-
-
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19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
19.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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21. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
20
21
Contact information . . . . . . . . . . . . . . . . . . . . 20
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Predictable and fail-safe behavior . . . . . . . . . . 1
Low-power management . . . . . . . . . . . . . . . . . 2
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
2.2
2.3
2.4
3
4
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
Functional description . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 6
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 7
TXD dominant time-out function. . . . . . . . . . . . 7
Internal biasing of TXD1, TXD2, STB1
and STB2 input pins . . . . . . . . . . . . . . . . . . . . . 8
Undervoltage detection on pins VCC and VIO . . 8
Overtemperature protection . . . . . . . . . . . . . . . 8
VIO supply pin . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.2.3
7.2.4
7.3
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal characteristics . . . . . . . . . . . . . . . . . . 9
Static characteristics. . . . . . . . . . . . . . . . . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 12
Application information. . . . . . . . . . . . . . . . . . 13
Test information. . . . . . . . . . . . . . . . . . . . . . . . 14
Quality information . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Handling information. . . . . . . . . . . . . . . . . . . . 16
9
10
11
12
13
13.1
14
15
16
Soldering of SMD packages . . . . . . . . . . . . . . 16
Introduction to soldering . . . . . . . . . . . . . . . . . 16
Wave and reflow soldering . . . . . . . . . . . . . . . 16
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 16
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 17
16.1
16.2
16.3
16.4
17
18
Soldering of HVSON packages. . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
19.1
19.2
19.3
19.4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 January 2014
Document identifier: TJA1059
相关型号：
TJA1080ATS/2/T
IC SPECIALTY INTERFACE CIRCUIT, PDSO20, 5.30 MM, PLASTIC, MO-150, SOT339-1, SSOP-20, Interface IC:Other
NXP
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