TJA1102A [NXP]
100BASE-T1 dual/single PHY for automotive Ethernet;
| 型号： | TJA1102A |
| 厂家： | 
NXP |
| 描述： | 100BASE-T1 dual/single PHY for automotive Ethernet |
| 文件： | 总67页 (文件大小：695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Rev. 1 — 7 June 2021
Product data sheet
1 General description
The TJA1102A is a 100BASE-T1-compliant dual-port Ethernet PHY optimized for
automotive use cases such as gateways, IP camera links, radar modules, driver
assistance systems and back-bone networks. The device provides 100 Mbit/s transmit
and receive capability over two unshielded twisted-pair cables, supporting a cable length
of up to at least 15 m. The TJA1102A has been designed for automotive robustness,
while minimizing power consumption and system costs. For added flexibility, a single
PHY version is available (TJA1102AS) in which one of the PHYs is disabled. Unless
otherwise specified, all references in this document to TJA1102A encompass both the
dual- and single-PHY variants.
The TJA1102A supports OPEN Alliance TC-10-compliant sleep and wake-up request
forwarding, with an always-on power domain connected directly to the battery supply
without the need for a dedicated voltage regulator.
2 Features and benefits
2.1 General
• Dual-port 100BASE-T1 PHY; single-port operation possible
• Single-port variant available
• MII- and RMII-compliant interfaces
• HVQFN 56-pin package (8 × 8 mm)
2.2 Optimized for automotive use cases
• Transmitter optimized for capacitive coupling to unshielded twisted-pair cable
• Adaptive receive equalizer optimized for automotive cable length of up to at least 15 m
• Enhanced integrated PAM-3 pulse shaping for low RF emissions
• EMC-optimized output driver strength for MII and RMII
• MDI pins meet class IV conducted emission limit as per OPEN Alliance EMC
Specification 2.0
• MDI pins protected against ESD to ±6 kV HBM and ±6 kV IEC61000-4-2
• MDI pins protected against transients in automotive environment
• MDI pins do not need external filtering or ESD protection
• Automotive-grade temperature range from -40 °C to +125 °C
• Automotive product qualification in accordance with AEC-Q100
• Host-configurable MDI polarity
• Automated polarity detection and correction
NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
2.3 Low-power mode
• OPEN Alliance TC-10-compliant sleep and wake-up forwarding
– Robust remote wake-up detection via bus lines
– Wake-up forwarding at PHY level (supporting global system wake-up)
• Inhibit output for voltage regulator control
• Dedicated PHY enable/disable input pin to minimize power consumption
• Local wake-up pin
• Wake-up via SMI-access
2.4 Diagnosis
• Signal Quality Indicator for real-time monitoring of link stability and transmitted data
quality
• Diagnosis of cable errors (shorts and opens)
• Gap-free supply undervoltage detection with fail-silent behavior
• Internal, external and remote loopback modes
2.5 Miscellaneous
• Internal reverse MII mode for repeater operation
• On-chip regulators to provide 3.3 V single-supply operation
• Supports optional 1.8 V external supply for digital core
• On-chip termination resistors for the differential cable pair
• Jumbo frame support up to 16 kB
3 Ordering information
Table 1.ꢀOrdering information
Type number
Package
Name
Description
Version
TJA1102AHN[1]
TJA1102AHN/S[2]
HVQFN56
plastic thermal enhanced very thin quad flat package; no leads; 56
terminals; body 8 × 8 × 0.85 mm
SOT684-13
[1] Dual PHY.
[2] Single PHY.
4 Block diagram
A block diagram of the TJA1102A is shown in Figure 1. The 100BASE-T1 sections
contain the functional blocks specified in the 100BASE-T1 standard that make up the
Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA) layer for
both the transmit and receive signal paths. The MII/RMII interface (including the Serial
Management Interface (SMI)) conforms to IEEE 802.3 clause 22.
Additional blocks are defined for mode control, register configuration, interrupt control,
system configuration, reset control, local wake-up, remote wake-up, undervoltage
detection and configuration control. A number of power-supply-related functional blocks
are defined: an internal 1.8 V regulator for the digital core, a Very Low Power (VLP)
supply for Sleep mode, the reset circuit, supply monitoring and inhibit control.
TJA1102A
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© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 1 — 7 June 2021
2 / 67
NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
The clock signals needed for the operation of the PHY are generated in the PLL block,
derived from an external crystal or an oscillator input signal.
Pin strapping allows a number of default PHY settings (e.g. Master or Slave
configuration) to be hardware-configured at power-up.
P0_V
P0_V
DDA(TX)
PMA
TRANSMITTER
P0_TXER
P0_TXEN
PCS-TX
DDA(TX)
100BASE-T1
P0_TXD[3:0]
P0_TXC
P0_TRX_P
P0_TRX_M
FRONT-END/
HYBRID
RMII/MII
LOGIC
PHY0
PHY CONTROL
P0_RXD[3:0]
P0_RXDV/P0_CRSDV
P0_RXER
PMA
RECEIVER
PCS-RX
PLL
P0_RXC/P0_REF_CLK
V
V
DDD(1V8)
DDD(3V3)
ACTIVITY
DETECT
LDO 1V8 DIG AND
1.8 V/3V3 UV DETECTION
PHY MODE
CONTROL
SEL_1V8
INT_N
1V8 SELECT
INT_N CONTROL
SMI
TOP MODE CONTROL
AND REGISTERS
V
V
V
V
DD(IO)
DD(IO)
DD(IO)
DD(IO)
UV 3V3
DETECTION
BASIC CONTROL
BASIC STATUS
MDC
MDIO
MODE CONTROL
CONFIGURATION
INTERRUPT SOURCE
INTERRUPT MASK
EXTENDED STATUS
UV 3V3
DETECTION
V
V
DDA(3V3)
BAT
CONFIG[7:0]
RST_N
CONFIG CONTROL
RESET CONTROL
1V2
VLP/RESET/
UV VBAT
reset
INH
EN
INH
CLK_IN_OUT
WAKE_IN_OUT
XI
XO-OSC/
CLOCK
ACTIVITY
DETECT
PHY MODE
CONTROL
XO
VDDD_1V8
P1_V
P1_V
DDA(TX)
P1_TXER
P1_TXEN
PMA
TRANSMITTER
PCS-TX
DDA(TX)
100BASE-T1
P1_TXD[3:0]
P1_TXC
P1_TRX_P
P1_TRX_M
FRONT-END/
HYBRID
RMII/MII
LOGIC
PHY1
PHY CONTROL
P1_RXD[3:0]
P1_RXDV/P1_CRSDV
P1_RXER
PMA
RECEIVER
PLL
P1_RXC/P1_REF_CLK
PCS-RX
GND
aaa-022037
Figure 1.ꢀBlock diagram (PHY1 is disabled in TJA1102AS)
TJA1102A
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© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 1 — 7 June 2021
3 / 67
NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
5 Pinning information
5.1 TJA1102A pinning
The pin configuration of the TJA1102A dual PHY is shown in Figure 2. Separate interface
and supply pins are provided for each PHY block. The SMI is shared between the
two PHYs. Since 100BASE-T1 allows for full-duplex bidirectional communication, the
standard MII signals COL and CRS are not needed.
terminal 1
index area
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P0_RXD3/CONFIG5
P0_RXD2/CONFIG6
P0_RXD1/CONFIG7
P0_RXD0
P1_TXD3
P1_TXEN
P1_TXC
3
4
V
DD(IO)
5
P0_RXC/P0_REF_CLK
P1_RXC/P1_REF_CLK
P1_RXD0/PHYAD3
6
V
DD(IO)
7
P0_TXC
P0_TXEN
P0_TXD3
P0_TXD2
P0_TXD1
P0_TXD0
P0_TXER
RST_N
P1_RXD1/PHYAD2
TJA1102A
8
P1_RXD2/PHYAD1
9
P1_RXD3/CONFIG3
10
11
12
13
14
P1_RXDV/P1_CRSDV/CONFIG2
P1_RXER/CONFIG1/P0_TXCLK
V
DD(IO)
MDC
MDIO
aaa-039085
Figure 2.ꢀPin configuration: TJA1102A
Table 2.ꢀTJA102A pin description
Symbol
Pin Type[1] Description
P0_RXD3
CONFIG5
P0_RXD2
CONFIG6
1
1
2
2
O
I
P0 MII mode: receive data output, bit 3 of RXD[3:0] nibble
pin strapping configuration input 5
O
I
P0 MII mode: receive data output, bit 2 of RXD[3:0] nibble
pin strapping configuration input 6
TJA1102A
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© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 1 — 7 June 2021
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 2.ꢀTJA102A pin description...continued
Symbol
Pin Type[1] Description
P0_RXD1
3
O
P0 MII mode: receive data output, bit 1 of RXD[3:0] nibble
P0 RMII mode: receive data output, bit 1 of RXD[1:0] nibble
CONFIG7
P0_RXD0
3
4
I
pin strapping configuration input 7
O
P0 MII mode: receive data output, bit 0 of RXD[3:0] nibble
P0 RMII mode: receive data output, bit 0 of RXD[1:0] nibble
P0_RXC
5
5
I
P0 MII reverse mode: external 25 MHz clock input
O
I
P0 MII mode: 25 MHz receive clock output
P0_REF_CLK
P0 RMII mode: interface reference clock input (50 MHz external oscillator)
O
P0 RMII mode: interface reference clock output (25 MHz crystal at PHY or 25 MHz clock
at input of pin CLK_IN_OUT)
[2]
VDD(IO)
6
7
P
I
3.3 V digital I/O supply voltage
P0_TXC
P0 MII reverse mode: external 25 MHz transmit clock input
P0 MII mode: 25 MHz transmit clock output
O
I
P0_TXEN
P0_TXD3
P0_TXD2
P0_TXD1
8
P0 MII/RMII mode: transmit enable input (active-HIGH, weak pull-down)
P0 MII mode: transmit data input, bit 3 of TXD[3:0] nibble (weak pull-down)
P0 MII mode: transmit data input, bit 2 of TXD[3:0] nibble (weak pull-down)
9
I
10
11
I
I
P0 MII mode: transmit data input, bit 1 of TXD[3:0] nibble (weak pull-down)
P0 RMII mode: transmit data input, bit 1 of TXD[1:0] nibble (weak pull-down)
P0_TXD0
12
I
P0 MII mode: transmit data input, bit 0 of TXD[3:0] nibble (weak pull-down)
P0 RMII mode: transmit data input, bit 0 of TXD[1:0] nibble (weak pull-down)
P0_TXER
RST_N
13
14
15
16
17
18
19
I
P0 MII/RMII: transmit error input (weak pull-down)
reset input (active-LOW; weak pull-up)
I
SEL_1V8
I
1.8 V LDO mode selection (external or internal; weak pull-down)
3.3 V analog supply voltage for the P0 transmitter
+ terminal for P0 transmit/receive signal
[3]
P0_VDDA(TX)
P
P0_TRX_P
P0_TRX_M
AIO
AIO
P
- terminal for P0 transmit/receive signal
[3]
P0_VDDA(TX)
3.3 V analog supply voltage for the P0 transmitter
local/forwarding wake-up input/output (configurable)
battery supply voltage
WAKE_IN_OUT 20
AIO
P
VBAT
21
22
23
24
25
26
27
28
29
30
INH
AO
P
inhibit output for voltage regulator control (VBAT-related, active-HIGH)
3.3 V analog supply voltage for the P1 transmitter
- terminal for P1 transmit/receive signal
[4]
P1_VDDA(TX)
P1_TRX_M
P1_TRX_P
P1_VDDA(TX)
EN
AIO
AIO
P
+ terminal for P1 transmit/receive signal
[4]
3.3 V analog supply voltage for the P1 transmitter
PHY enable input (active-HIGH, weak pull-down)
interrupt output (active-LOW, open-drain output, level-based)
SMI data I/O (weak pull-up)
I
INT_N
O
MDIO
IO
I
MDC
SMI clock input (weak pull-down)
TJA1102A
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© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 1 — 7 June 2021
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 2.ꢀTJA102A pin description...continued
Symbol
Pin Type[1] Description
[2]
VDD(IO)
31
32
32
32
33
33
33
34
34
35
35
P
O
I
3.3 V digital I/O supply voltage
P1_RXER
CONFIG1
P0_TXCLK
P1_RXDV
P1_CRSDV
CONFIG2
P1_RXD3
CONFIG3
P1_RXD2
PHYAD1
P1 MII/RMII receive error output
pin strapping configuration input 1
O
O
O
I
P0 transmit clock output in test mode and during slave jitter test
P1 MII receive data valid output
P1 RMII carrier sense/receive data valid output
pin strapping configuration input 2
O
I
P1 MII mode: receive data output, bit 3 of RXD[3:0] nibble
pin strapping configuration input 3
O
I
P1 MII mode: receive data output, bit 2 of RXD[3:0] nibble
pin strapping configuration input for bit 1 of the PHY address used for the SMI address/
Cipher scrambler
P1_RXD1
36
O
P1 MII mode: receive data output, bit 1 of RXD[3:0] nibble
P1 RMII mode: receive data output, bit 1 of RXD[1:0] nibble
PHYAD2
36
37
I
pin strapping configuration input for bit 2 of the PHY address used for the SMI address/
Cipher scrambler
P1_RXD0
O
P1 MII mode: receive data output, bit 0 of RXD[3:0] nibble
P1 RMII mode: receive data output, bit 0 of RXD[1:0] nibble
PHYAD3
P1_RXC
37
38
I
pin strapping configuration input for bit 3 of the PHY address used for the SMI address/
Cipher scrambler
I
P1 MII reverse mode: external 25 MHz clock input
O
I
P1 MII mode: 25 MHz receive clock output
P1_REF_CLK
38
P1 RMII mode: interface reference clock input (50 MHz external oscillator)
O
P1 RMII mode: interface reference clock output (25 MHz crystal at PHY or 25 MHz clock
at input of pin CLK_IN_OUT)
[2]
VDD(IO)
39
40
P
I
3.3 V digital I/O supply voltage
P1_TXC
P1 MII reverse mode: external 25 MHz transmit clock input
P1 MII mode: 25 MHz transmit clock output
O
I
P1_TXEN
P1_TXD3
P1_TXD2
P1_TXD1
41
42
43
44
P1 MII/RMII mode: transmit enable input (active-HIGH, weak pull-down)
P1 MII mode: transmit data input, bit 3 of TXD[3:0] nibble (weak pull-down)
P1 MII mode: transmit data input, bit 2 of TXD[3:0] nibble (weak pull-down)
I
I
I
P1 MII mode: transmit data input, bit 1 of TXD[3:0] nibble (weak pull-down)
P1 RMII mode: transmit data input, bit 1 of TXD[1:0] nibble (weak pull-down)
P1_TXD0
45
I
P1 MII mode: transmit data input, bit 0 of TXD[3:0] nibble (weak pull-down)
P1 RMII mode: transmit data input, bit 0 of TXD[1:0] nibble (weak pull-down)
P1_TXER
VDDD(1V8)
VDDD(3V3)
GND[5]
46
47
48
49
I
P1 MII/RMII: transmit error input (weak pull-down)
1.8 V digital supply voltage (configurable internal or external supply)
3.3 V digital supply voltage
P
P
G
ground reference
TJA1102A
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Product data sheet
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 2.ꢀTJA102A pin description...continued
Symbol
Pin Type[1] Description
XI
50
AI
crystal input - used in all MII/RMII and Reverse MII modes when a 25 MHz crystal is
used
XO
51
AO
crystal feedback - used in all MII/RMII and reverse MII modes when a 25 MHz crystal is
used
VDDA(3V3)
52
53
54
55
55
55
56
56
56
P
P
IO
O
I
3.3 V analog supply voltage
[2]
VDD(IO)
3.3 V digital I/O supply voltage
CLK_IN_OUT
P0_RXER
CONFIG0
25 MHz reference clock input/output (configurable)
P0 MII/RMII receive error output
pin strapping configuration input 0
P1_TXCLK
P0_RXDV
P0_CRSDV
CONFIG4
O
O
O
I
P1 transmit clock output in test mode and during slave jitter test
P0 MII receive data valid output
P0 RMII carrier sense/receive data valid output
pin strapping configuration input 4
[1] AIO: analog input/output; AO: analog output; AI: analog input; I: digital input (VDD(IO) related);
O: digital output (VDD(IO) related); IO: digital input/output (VDD(IO) related); P: power supply; G: ground.
[2] VDD(IO) pins are connected internally and should be connected together on the PCB (pins 6, 31, 39 and 53).
[3] P0_VDDA(TX) pins are connected internally and should be connected together on the PCB (pins 16 and 19).
[4] P1_VDDA(TX) pins are connected internally and should be connected together on the PCB (pins 23 and 26).
[5] HVQFN56 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground.
For enhanced thermal and electrical performance, it is also recommended to connect the exposed center pad to board ground.
TJA1102A
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Product data sheet
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
5.2 TJA1102AS pinning
The pin configuration of the TJA1102AS single PHY is shown in Figure 3.
terminal 1
index area
P0_RXD3/CONFIG5
P0_RXD2/CONFIG6
P0_RXD1/CONFIG7
P0_RXD0
n.c.
n.c.
n.c.
V
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3
4
DD(IO)
P0_RXC/P0_REF_CLK
n.c.
5
V
PHYAD3
6
DD(IO)
P0_TXC
P0_TXEN
P0_TXD3
P0_TXD2
P0_TXD1
P0_TXD0
P0_TXER
RST_N
PHYAD2
7
TJA1102AS
PHYAD1
8
CONFIG3
CONFIG2
CONFIG1/P0_TXCLK
9
10
11
12
13
14
V
DD(IO)
MDC
MDIO
aaa-039094
Figure 3.ꢀPin configuration: TJA1102AS
Table 3.ꢀTJA1102AS pin description
Symbol
Pin Type[1] Description
P0_RXD3
CONFIG5
P0_RXD2
CONFIG6
P0_RXD1
1
1
2
2
3
O
I
P0 MII mode: receive data output, bit 3 of RXD[3:0] nibble
pin strapping configuration input 5
O
I
P0 MII mode: receive data output, bit 2 of RXD[3:0] nibble
pin strapping configuration input 6
O
P0 MII mode: receive data output, bit 1 of RXD[3:0] nibble
P0 RMII mode: receive data output, bit 1 of RXD[1:0] nibble
CONFIG7
P0_RXD0
3
4
I
pin strapping configuration input 7
O
P0 MII mode: receive data output, bit 0 of RXD[3:0] nibble
P0 RMII mode: receive data output, bit 0 of RXD[1:0] nibble
TJA1102A
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© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 1 — 7 June 2021
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 3.ꢀTJA1102AS pin description...continued
Symbol
Pin Type[1] Description
P0_RXC
5
5
I
P0 MII reverse mode: external 25 MHz clock input
O
I
P0 MII mode: 25 MHz receive clock output
P0_REF_CLK
P0 RMII mode: interface reference clock input (50 MHz external oscillator)
O
P0 RMII mode: interface reference clock output (25 MHz crystal at PHY or 25 MHz clock
at input of pin CLK_IN_OUT)
[2]
VDD(IO)
6
7
P
I
3.3 V digital I/O supply voltage
P0_TXC
P0 MII reverse mode: external 25 MHz transmit clock input
P0 MII mode: 25 MHz transmit clock output
O
I
P0_TXEN
P0_TXD3
P0_TXD2
P0_TXD1
8
P0 MII/RMII mode: transmit enable input (active-HIGH, weak pull-down)
P0 MII mode: transmit data input, bit 3 of TXD[3:0] nibble (weak pull-down)
P0 MII mode: transmit data input, bit 2 of TXD[3:0] nibble (weak pull-down)
9
I
10
11
I
I
P0 MII mode: transmit data input, bit 1 of TXD[3:0] nibble (weak pull-down)
P0 RMII mode: transmit data input, bit 1 of TXD[1:0] nibble (weak pull-down)
P0_TXD0
12
I
P0 MII mode: transmit data input, bit 0 of TXD[3:0] nibble (weak pull-down)
P0 RMII mode: transmit data input, bit 0 of TXD[1:0] nibble (weak pull-down)
P0_TXER
RST_N
13
14
15
16
17
18
19
I
P0 MII/RMII: transmit error input (weak pull-down)
reset input (active-LOW; weak pull-up)
I
SEL_1V8
I
1.8 V LDO mode selection (external or internal; weak pull-down)
3.3 V analog supply voltage for the P0 transmitter
+ terminal for P0 transmit/receive signal
[3]
P0_VDDA(TX)
P
P0_TRX_P
P0_TRX_M
AIO
AIO
P
- terminal for P0 transmit/receive signal
[3]
P0_VDDA(TX)
3.3 V analog supply voltage for the P0 transmitter
local/forwarding wake-up input/output (configurable)
battery supply voltage
WAKE_IN_OUT 20
AIO
P
VBAT
21
22
23
24
25
26
27
28
29
30
31
32
32
33
INH
AO
P
inhibit output for voltage regulator control (VBAT-related, active-HIGH)
3.3 V analog supply voltage for the P0 transmitter
not connected; pin can be left open or shorted to GND
not connected; pin can be left open or shorted to GND
3.3 V analog supply voltage for the P0
[3]
P0_VDDA(TX)
n.c.
-
n.c.
-
[3]
P0_VDDA(TX)
EN
P
I
PHY enable input (active-HIGH, weak pull-down)
interrupt output (active-LOW, open-drain output, level-based)
SMI data I/O (weak pull-up)
INT_N
MDIO
MDC
O
IO
I
SMI clock input (weak pull-down)
[2]
VDD(IO)
P
3.3 V digital I/O supply voltage
CONFIG1
P0_TXCLK
CONFIG2
I
pin strapping configuration input 1
O
I
P0 transmit clock output in test mode and during slave jitter test
pin strapping configuration input 2
TJA1102A
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© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 1 — 7 June 2021
9 / 67
NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 3.ꢀTJA1102AS pin description...continued
Symbol
Pin Type[1] Description
CONFIG3
PHYAD1
34
35
I
I
pin strapping configuration input 3
pin strapping configuration input for bit 1 of the PHY address used for the SMI address/
Cipher scrambler
PHYAD2
PHYAD3
n.c.
36
37
I
I
pin strapping configuration input for bit 2 of the PHY address used for the SMI address/
Cipher scrambler
pin strapping configuration input for bit 3 of the PHY address used for the SMI address/
Cipher scrambler
38
39
40
41
42
43
44
45
46
47
48
49
50
-
not connected; pin can be left open or shorted to GND
3.3 V digital I/O supply voltage
[2]
VDD(IO)
P
-
n.c.
not connected; pin can be left open or shorted to GND
not connected; pin can be left open or shorted to GND
not connected; pin can be left open or shorted to GND
not connected; pin can be left open or shorted to GND
not connected; pin can be left open or shorted to GND
not connected; pin can be left open or shorted to GND
not connected; pin can be left open or shorted to GND
1.8 V digital supply voltage (configurable internal or external supply)
3.3 V digital supply voltage
n.c.
-
n.c.
-
n.c.
-
n.c.
-
n.c.
-
n.c.
-
VDDD(1V8)
VDDD(3V3)
GND[4]
XI
P
P
G
AI
ground reference
crystal input - used in all MII/RMII and Reverse MII modes when a 25 MHz crystal is
used
XO
51
AO
crystal feedback - used in all MII/RMII and reverse MII modes when a 25 MHz crystal is
used
VDDA(3V3)
52
53
54
55
55
56
56
56
P
P
IO
O
I
3.3 V analog supply voltage
[2]
VDD(IO)
3.3 V digital I/O supply voltage
CLK_IN_OUT
P0_RXER
CONFIG0
25 MHz reference clock input/output (configurable)
P0 MII/RMII receive error output
pin strapping configuration input 0
P0 MII receive data valid output
P0_RXDV
P0_CRSDV
CONFIG4
O
O
I
P0 RMII carrier sense/receive data valid output
pin strapping configuration input 4
[1] AIO: analog input/output; AO: analog output; AI: analog input; I: digital input (VDD(IO) related);
O: digital output (VDD(IO) related); IO: digital input/output (VDD(IO) related); P: power supply; G: ground.
[2] VDD(IO) pins are connected internally and should be connected together on the PCB (pins 6, 31, 39 and 53).
[3] P0_VDDA(TX) pins are connected internally and should be connected together on the PCB (pins 16, 19, 23 and 26).
[4] HVQFN56 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground.
For enhanced thermal and electrical performance, it is also recommended to connect the exposed center pad to board ground.
TJA1102A
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TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
6 Functional description
6.1 System configuration
The TJA1102A comprises two 100BASE-T1 compliant Ethernet PHYs, with 100 Mbit/s
transmit and receive capability over two unshielded twisted-pair cables. The TJA1102A
supports a cable length of up to at least 15 m, with a bit error rate of 1E-10 or less. It is
optimized for capacitive signal coupling to the twisted-pair lines. A common-mode choke
is typically inserted into the signal path to comply with automotive EMC requirements.
The TJA1102A is designed to provide a cost-optimized system solution for automotive
Ethernet links. It communicates with the Media Access Control (MAC) unit via the MII
or RMII interface. In combination with other devices (e.g. SJA1105 in Figure 4), it offers
a highly flexible 4-port switch solution, with two TJA1102A dual PHYs providing the
100BASE-T1 physical layer ports.
The TJA1102A can operate with a crystal or an external clock. The clock can be
forwarded to other PHYs (in the application diagram in Figure 4, the clock of one
TJA1102A is used as reference for a second TJA1102A). The clocking and power supply
schemes are independent of each other.
The TJA1102A can be powered via a single 3.3 V supply. An internal LDO generates the
required 1.8 V supply, requiring only the addition of a decoupling capacitor.
When the TJA1102A is used in a switch application with several PHY ports, it may be
more efficient to use an external SMPS to provide the 1.8 V supply. In this configuration,
the internal LDO is switched off to allow an external supply to be used.
The state of SEL_1V8 is captured and copied to bit LDO_MODE (see Table 12) when the
device is powered up. A bit value of 0 enables the internal 1.8 V LDO. If LDO_MODE =
1, the internal LDO is disabled and VDDD(1V8) must be supplied externally. The value of
LDO_MODE can be changed after power-up via register access.
Control and status information is exchanged with the host controller via the SMI interface.
The INH output can be used to switch off the external regulator when all ports are in
Sleep mode.
Note that the dual-port PHY can be configured to operate as a single PHY via pin
strapping or the SMI. Alternatively, a TJA1102AS could be used when only a single PHY
is needed.
A PCB layout based on the system diagrams shown in Section 6.1.1 and Section 6.1.2
would be able to accommodate any switch configuration comprising between one and
four ports.
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
6.1.1 Clocking scheme with MII and clock provided by the switch and one of the
TJA1102A devices
switch supply
V
BAT
VREG
25 MHz
±100 ppm
XO
XI
MII (2x)
CON
CON
P0
P1
EN
RST_N
INT_N
DUAL PHY
TJA1102A
0
MDC
MDIO
SJA1105
MII (2x)
CON
CON
P0
P1
EN
RST_N
INT_N
DUAL PHY
TJA1102A
1
MDC
MDIO
XI
XO
25 MHz
±100 ppm
HOST CONTROLLER
aaa-039095
One of the TJA1102A devices could be replaced by a TJA1102AS if only three PHYs are needed.
Figure 4.ꢀTypical TJA1102A MII switch application with SJA1105
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
6.1.2 Clocking scheme with RMII and clock provided by the switch
switch supply
V
BAT
VREG
25 MHz
±100 ppm
XO
XI
RMII (2x)
CON
CON
P0
P1
EN
RST_N
INT_N
DUAL PHY
TJA1102A
0
MDC
MDIO
REF_CLK (50 MHz)
REF_CLK (50 MHz)
SJA1105
RMII (2x)
CON
CON
P0
P1
EN
RST_N
INT_N
DUAL PHY
TJA1102A
1
MDC
MDIO
HOST CONTROLLER
aaa-039096
One of the TJA1102A devices could be replaced by a TJA1102AS if only three PHYs are needed.
Figure 5.ꢀTypical RMII switch application with SJA1105 (XTAL at SJA1105)
6.2 MII and RMII
The TJA1102A supports a number of MII modes that can be selected via pin strapping
or the SMI. The PHYs should be configured to operate in the same mode, with common
clocking. The following modes are supported:
• MII
• RMII (25 MHz XTAL or external 50 MHz via REF_CLK)
• Reverse MII (connected externally or internally to the second PHY)
Refer to the SMI register description (Section 6.11) for further configuration options.
The strength of the (R)MII output driver signals can be limited in all modes (via bit
MII_DRIVER; Table 22) to optimize EMC behavior.
TJA1102A
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NXP Semiconductors
6.2.1 MII
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
The connections between the PHY and the MAC are shown in more detail in Figure 6.
Data is exchanged via 4-bit wide data nibbles on TXD[3:0] and RXD[3:0]. Transmit and
receive data is synchronized with the transmit (TXC) and receive (RXC) clocks. Both
clock signals are provided by the PHY and are typically derived from an external clock or
crystal running at a nominal frequency of 25 MHz (±100 ppm). Normal data transmission
is initiated with a HIGH level on TXEN, while a HIGH level on RXDV indicates normal
data reception.
MII encoding is described in Table 4 and Table 5.
RXC
RXER
RXC
RXER
RXDV
RXD[3:0]
RXDV
RXD[3:0]
RXC
RXER
RXC
RXER
RXDV
RXD[3:0]
TXEN
TXD[3:0]
TXER
TXEN
TXD[3:0]
TXER
TXC
MAC/
SWITCH
PHY
XO
RXDV
RXD[3:0]
TXC
TXEN
TXD[3:0]
TXER
TXEN
TXD[3:0]
TXER
TXC
MAC/
SWITCH
PHY
XO
CLK_IN_OUT
XI
TXC
CLK_IN_OUT
XI
25 MHz clock to
other PHY or
25 MHz
switch (optional)
aaa-022105
25 MHz clock from
other PHY or switch
aaa-022106
a. Using external XTAL showing optional 25 MHz clock
output
b. Using external reference clock
Figure 6.ꢀMII signaling
Table 4.ꢀMII encoding of TXD[3:0], TXEN and TXER
TXEN
TXER
TXD[3:0]
Indication
0
0
1
1
0
1
0
1
0000 through 1111
0000 through 1111
0000 through 1111
0000 through 1111
normal interframe
reserved
normal data transmission
transmit error propagation
Table 5.ꢀMII encoding of RXD[3:0], RXDV and RXER
RXDV
RXER
RXD[3:0]
Indication
0
0
0
0
0
1
0
1
1
1
1
0
0000 through 1111
0000
normal interframe
normal interframe
reserved
0001 through 1101
1110
false carrier indication
reserved
1111
0000 through 1111
normal data transmission
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 5.ꢀMII encoding of RXD[3:0], RXDV and RXER...continued
RXDV
RXER
RXD[3:0]
Indication
1
1
0000 through 1111
data reception with errors
6.2.2 RMII
6.2.2.1 Signaling and encoding
RMII data is exchanged via 2-bit wide data nibbles on TXD[1:0] and RXD[1:0], as
illustrated in Figure 7. To achieve the same data rate as MII, the interface is clocked at
a nominal frequency of 50 MHz. A single clock signal, REF_CLK, is provided for both
transmitted and received data. This clock signal is provided by the PHY and is typically
derived from an external 25 MHz (±100 ppm) crystal (see Figure 7 (a)). Alternatively, a
50 MHz clock signal (±50 ppm) generated by an external oscillator can be connected to
pin REF_CLK (see Figure 7 (b)). A third option is to connect a 25 MHz (±100 ppm) clock
signal generated by another PHY or switch to pin CLK_IN_OUT (see Figure 7 (c)).
RMII encoding is described in Table 6 and Table 7.
Table 6.ꢀRMII encoding of TXD[1:0], TXEN
TXEN
TXD[1:0]
Indication
0
1
00 through 11
00 through 11
normal interframe
normal data transmission
Table 7.ꢀRMII encoding of RXD[1:0], CRSDV and RXER
CRSDV
RXER
RXD[1:0]
Indication
0
0
0
1
1
0
1
1
0
1
00 through 11
00
normal interframe
normal interframe
reserved
01 through 11
00 through 11
00 through 11
normal data transmission
data reception with errors
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
CRSDV
RXD[1:0]
RXER
CRSDV
RXD[1:0]
RXER
CRSDV
CRSDV
RXD[1:0]
RXER
RXD[1:0]
RXER
TXEN
PHY
TXEN
MAC/
SWITCH
TXD[1:0]
TXD[1:0]
TXEN
TXEN
MAC/
SWITCH
PHY
XO
REF_CLK
REF_CLK
TXD[1:0]
TXD[1:0]
CLK_IN_OUT
REF_CLK
XI
REF_CLK
XO
XI
25 MHz clock to
other PHYs or
25 MHz
switch (optional)
50 MHz
aaa-022189
oscillator
aaa-022190
a. Using external XTAL showing optional 25 MHz clock
output
b. Using external reference clock
CRSDV
RXD[1:0]
RXER
CRSDV
RXD[1:0]
RXER
TXEN
PHY
TXEN
MAC/
SWITCH
TXD[1:0]
TXD[1:0]
REF_CLK
REF_CLK
CLK_IN_OUT
XO
XI
25 MHz clock from
other PHY or switch
aaa-022191
c. Using externally generated 25 MHz reference clock
Figure 7.ꢀRMII signaling
6.2.3 Reverse MII
In Reverse MII mode, two PHYs are connected back-to-back via the MII interface to
realize a repeater function on the physical layer. The MII signals are cross-connected: RX
output signals from one PHY are connected to the TX inputs on the other PHY. The TXC
and RXC clock signals become inputs on the PHY connected in Reverse MII mode (P0 in
Figure 8 and Figure 9). Reverse MII mode is selected by setting bits MII_MODE = 11.
Two configuration options are available on the TJA1102A. The P0 and P1 MII pins can
be connected externally on the PCB (INT_REV_MII = 0). Alternatively, the MII ports
can communicate via existing internal connections (INT_REV_MII = 1), as illustrated in
Figure 8.
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
TJA1102A
PHY P1
IN MII
PHY P0
IN REVERSE MII
P1_TXC
P0_RXC
P1_TXER
P1_TXEN
P0_RXER
P0_RXDV
P0_RXD[3:0]
P0_TXEN
P0_TXD[3:0]
P0_TXER
P0_TXC
MDI 100BaseT1
MDI 100BaseT1
P1_TXD[3:0]
P1_RXDV
P1_RXD[3:0]
P1_RXER
P1_RXC
aaa-039097
Figure 8.ꢀ100BASE-T1 repeater with TJA1102A Reverse MII
The TJA1102AS can be configured in reverse MII mode by connecting the MII pins
externally to a fast Ethernet product, is illustrated in Figure 9.
TXC
TXER
TXEN
P0_RXC
P0_RXER
P0_RXDV
P0_RXD[3:0]
TXD[3:0]
MDI
Fast Ethernet
MDI
100Base-T1
TJA1102AS
PHY 100Base-TX
(Reverse MII)
RXDV
RXD[3:0]
RXER
P0_TXEN
P0_TXD[3:0]
P0_TXER
P0_TXC
RXC
XO
XI
XI
XO
25 MHz
XTAL
25 MHz
XTAL
aaa-039099
Figure 9.ꢀFast Ethernet to 100BASE-T1 media converter with TJA1102AS in Reverse MII
6.3 System controller
6.3.1 Operating modes
6.3.1.1 Power-off mode
Each PHY has its own dedicated power mode state machine. The TJA1102A remains
in Power-off mode as long as the voltage on pin VBAT is below the power-on reset
threshold. The analog blocks are disabled and the digital blocks are in a passive reset
state in this mode.
6.3.1.2 Standby mode
At power-on, when the voltage on pin VBAT rises above the under-voltage recovery
threshold (Vuvr(VBAT)), the TJA1102A enters Standby mode and switches on the INH
control output (pin INH HIGH). This control signal may be used to activate the supply to
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
the microcontroller in the ECU. Once the 3.3 V supply voltage is available, the internal
1.8 V regulator is activated (if selected) and the PHYs are configured according to the pin
strapping implemented on the CONFIGn and PHYADn pins. No SMI access takes place
during the power-on settling time (ts(pon)).
From an operating point of view, Standby mode corresponds to the IEEE 802.3 Power-
down mode, where the transmit and receive functions (in the PHY) are disabled. Standby
mode also acts as a fail-silent mode. The TJA1102A switches to Standby mode when an
undervoltage condition is detected on VDDA(3V3), VDDD(3V3), VDDD(1V8) or VDD(IO)
.
6.3.1.3 Normal mode
To establish a communication link, the TJA1102A must be switched to Normal mode,
either autonomously (AUTO_OP = 1; see Table 31) or via an SMI command from the
host (AUTO_OP = 0).
When the TJA1102A is configured for autonomous operation, the PHYs enter Normal
mode automatically and activate the link on power-on. When the TJA1102A is host-
controlled, the PHYs must be enabled via the SMI.
When a PHY is enabled and enters Normal mode, the internal PLL starts running and
the transmit and receive functions (both PCS and PMA) are enabled. After a period of
stabilization, tinit(PHY), the PHY is ready to set up a link.
If link control is enabled (LINK_CONTROL = 1; see Table 21), a PHY configured as
Master initiates the training sequence by transmitting an idle pattern. The receiver of
a PHY configured as Slave will attempt to synchronize with the idle pattern. Once the
descrambler is synchronized (SCR_LOCKED = 1), the slave PHY itself starts sending an
idle pattern using the recovered clock signal.
The link is established (LINK_STATUS = 1) when the TJA1102A PHY and the remote
PHY indicate that their local receiver status is OK.
6.3.1.4 Disable mode
When the Ethernet interface is not in use or must be disabled for fail-safe reasons, the
PHYs can be switched off by pulling pin EN LOW. The PHYs are switched off completely
in Disable mode, minimizing power consumption. The configuration register settings are
maintained. EN must be forced HIGH to exit Disable mode and activate the PHYs. The
PHYs can also be enabled/disabled via bit PHY_EN.
6.3.1.5 Sleep mode
If the network manager decides to withdraw a node from the network because it is no
longer needed, the PHYs can be switched to Sleep mode (powering down the entire
ECU).
In Sleep mode, the transmit and receive functions are switched off and no signal is driven
onto the twisted-pair lines. Transmit requests from the MII interface are ignored and the
MII output pins are in a high-ohmic state. The only valid SMI operations in Sleep mode
are reading the POWER_MODE status bits in the Extended control register and issuing a
Standby mode command (POWER_MODE = 1100; see Table 21).
Releasing the INH output (INH LOW) allows the ECU to switch off its main power supply
unit. Typically, the entire ECU is powered-down. The TJA1102A is kept partly alive by
the permanent battery supply and can still react to activity on the Ethernet lines. Once
valid Ethernet idle pulses longer than tdet(PHY) are detected on the lines of at least one
PHY (with REMWUPHY = 1), the TJA1102A wakes up in Standby mode and switches on
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
the main power unit via the INH control signal. The TJA1102A PHYs enter Normal mode
via autonomous operation once the supply voltages are stable within their operating
ranges, or can be switched to Normal mode via an SMI command if host-controlled. The
communication link to the partner can then be re-established. Only PHY0 switches to
Normal mode in the TJA1102AS.
Sleep mode can be entered from Normal mode via the intermediate Sleep Request
mode as well as from Standby mode, as shown in Figure 10. Note that the configuration
register settings are maintained in Sleep mode.
If CLK_IN_OUT is used to provide the clock for other devices (e.g. other PHYs), the clock
signal can be configured to remain active (CLK_HOLD = 1) along with INH even when
both PHYs are in Sleep mode or disabled. When CLK_HOLD = 1, the device enters
Sleep mode automatically but remains active until a FORCE_SLEEP SMI command is
received. Note that this command forces both PHYs to Sleep mode immediately (if they
are not already in Sleep mode or disabled).
6.3.1.6 Sleep Request mode
Sleep Request mode is an intermediate state used to initiate a transition to Sleep mode.
In Sleep Request mode, the PHY transmits scrambler code with an encoded LPS
command to inform the link partner about the request to enter Sleep mode.
The PHY sleep request timer (tto(req)sleep; see Table 38) starts when the TJA1102A
enters Sleep Request mode. This timer determines the maximum length of time the PHY
remains in Sleep Request mode. The PHY switches to Sleep mode (via an intermediate
step through Silent mode) on receiving LPS confirmation of the sleep request from the
Link partner. If the timer expires before confirmation is received from the link partner,
the PHY returns to Normal mode. This process is valid when LPS_ACTIVE = 1 and
SLEEP_CONFIRM = 1.
If bit SLEEP_ACK is not set when the PHY enters Sleep Request mode, it switches back
to Normal mode if data is detected on MII or MDI (see Table 22). The DATA_DET_WU
flag in the General status register is set and a WAKEUP interrupt is generated (if
REMWUPHY = 1).
If SLEEP_ACK is set when the PHY enters Sleep Request mode, the PHY sleep
acknowledge timer (tto(ack)sleep; see Table 38) is started. While the timer is running, the
PHY switches back to Normal mode in response to a host command or wake-up request.
When the timer expires, LPS transmission begins to initiate a transition to Sleep mode.
Data detected at MII or MDI is ignored.
INH is released when both PHYs are in Sleep mode or disabled.
6.3.1.7 Silent mode
Silent mode is an intermediate state between Sleep Request mode and Sleep mode.
It is provided to allow time to switch off the transmitter after a sleep request has been
accepted before entering Sleep mode. The TJA1102A switches to Sleep mode once the
channel goes silent.
If the channel remains active for longer than tto(req)sleep, the PHY returns to Normal mode
and a SLEEP_ABORT interrupt is generated.
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
6.3.1.8 Reset mode
The TJA1102A switches to Reset mode from any mode except Power-off or Sleep when
pin RST_N is held LOW for at least tdet(rst)(max), provided the voltage on VDD(IO) is above
the undervoltage threshold.
When RST_N goes HIGH again, or an undervoltage is detected on VDD(IO), the
TJA1102A switches to Standby mode. All register bits are reset to their default values in
Reset mode and the state of the pin strapping pins is captured.
6.3.2 Status of functional blocks in TJA1102A operating modes
Table 8 presents an overview of the status of TJA1102A functional blocks in each
operating mode.
Table 8.ꢀStatus of functional blocks in TJA1102A operating modes
Functional block
MII
Normal
on
Standby
high-ohmic[2] on
Sleep Request Sleep[1]
Disable
high-ohmic
high-ohmic
PMA/PCS-TX
PMA/PCS-RX
SMI
on
off
on
off
off
on
off
on
off
on[3]
off
on
on
on
off
Activity detection
Crystal oscillator
LDO_1V8
off
on
off
on
off[5]
off
on/off[4]
on/off[6]
on
off
on/off[6]
on/off[4]
on/off[6]
on
off
off
off
RST_N input
EN input
on
off
on
on
on
on
off
on
WAKE_IN_OUT
INT_N output
INH output
on/off[7]
on/off[7]
on/off[7]
on/off[7]
high-ohmic
off
off
on
on
on
high-ohmic
on/off[8]
off
on
on
on
Temp detection
on
on
on
off
[1] The TJA1102A only switches to Sleep mode if both PHYs are in Sleep mode or disabled via SMI-access (PHY_EN = 0).
The TJA1102AS will be in Sleep mode if PHY0 is in Sleep mode (since PHY1 is disabled).
[2] Outputs RXD[3:0], RXER and RXDV are LOW in Standby mode; the other MII pins are configured as inputs via internal
100 kΩ pull-down resistors.
[3] Limited access to SMI registers in Sleep mode to allow mode control/wake-up via SMI. VDD(IO) must be available.
[4] Configurable; depends on bits CLK_MODE in the Common configuration register.
[5] The crystal will be off in Sleep mode unless bit CLK_HOLD = 1 and bits CLK_MODE = 00 or 01.
[6] Configurable; VDDD(1V8) can be supplied internally (bit LDO_MODE in the Common configuration register LOW) or
externally (bit LDO_MODE HIGH).
[7] Configurable.
[8] The behavior of the INH output in Disable mode is configurable and depends on bit CONFIG_INH in the Common
configuration register.
TJA1102A
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TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
6.4 Mode transitions
A mode transition diagram for the TJA1102A is shown in Figure 10. Abbreviations used in
the mode transition diagram are defined in Table 9.
The following events, listed in order of priority, trigger mode transitions:
• Power on/off
• Undervoltage on VDD(IO)
• RST_N input
• EN input
• Overtemperature or Undervoltage on VDDA(3V3), VDDD(3V3), VDDD(1V8)
• SMI command and wake-up (local, remote or forwarding)
Table 9.ꢀState diagram legend
Transition
Abbreviation
Description
Silent to Normal
Normal to Sleep Request
sleep request timer expired
Sleep Request command
autonomous power-down
t > tto(req)sleep
POWER_MODE = 1011
no frame transmission or reception for longer than
tto(pd)autn AND AUTO_PWD = 1
LPS code group received
LPS_WUR_DIS = 0 (LPS/WUR enabled) AND
LPS_RECEIVED = 1 AND t > tto(req)sleep AND
LPS_ACTIVE = 1
no data detected on MDI or MII
sleep acknowledge timer enabled
Normal mode command
wake-up request
pcs_rx_dv = FALSE AND TXEN = LOW
SLEEP_ACK = 1
Sleep Request to Normal
POWER_MODE = 0011
(FWDPHYREM = 1 and WAKEUP = 1) OR WUR
symbols received at the bus pins
sleep acknowledge timer disabled
SLEEP_ACK = 0
sleep acknowledge time-out time not t < tto(ack)sleep
expired
data detected on MDI or MII
LPS enabled
pcs_rx_dv = TRUE OR TXEN = HIGH
LPS_WUR_DIS = 0
t > tto(req)sleep
sleep request timer expired
data detected on MDI or MII
sleep acknowledge timer disabled
LPS disabled
Normal to Normal
pcs_rx_dv = TRUE OR TXEN = HIGH
SLEEP_ACK = 0
Sleep Request to Sleep
LPS_WUR_DIS = 1
t > tto(req)sleep
sleep request timer expired
LPS enabled
Sleep Request to Silent
Standby to Normal
LPS_WUR_DIS = 0
see Section 6.6
autonomous operation
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100BASE-T1 dual/single PHY for automotive Ethernet
sleep request timer expired (t > t
)
to(req)sleep
[Sleep Request command OR
autonomous power-down OR
(LPS code group received AND
(no data detected on MDI or MII OR
sleep acknowledge timer enabled))]
AND
no WUR transmitted or received
Sleep Request command AND
data detected at MDI or MII AND
sleep acknowledge timer disabled
SLEEP
NORMAL
INH = on
REQUEST
INH = on
PHY enabled
PHY enabled
[(Normal mode command OR wake-up request)
AND (sleep acknowledge timer disabled OR
sleep acknowledge timer not expired)]
OR
(data detected at MDI or MII AND
sleep acknowledge timer disabled)
OR
LPS enabled AND
[LPS sent AND
(SLEEP_CONFIRM = 0 OR
(SLEEP_CONFIRM = 1
AND LPS received))
(LPS enabled AND sleep request timer expired)
OR LOC_RCVR_STATUS = 0]
Normal mode command OR
autonomous operation OR
(FWDPHYREM = 1 AND local wake-up)
SILENT
INH = on
PHY enabled
(SEND_Z)
Standby command
OR UV
OR Overtemperature
Standby command
OR UV
OR Overtemperature
(1)
(1)
LPS disabled AND
sleep request timer
(3)
expired
no bus activity
Sleep Request command OR
(4)
t > t
to(uvd)
EN pin HIGH OR
uv_VDD
DISABLE
STANDBY
INH = on
SLEEP
INH = off
(IO)
(2)
INH = on/off
)
PHY disabled
PHY disabled
PHY disabled
local wake-up OR
activity detected OR
Standby mode command
(PHY_EN = 0 OR
FORCE_SLEEP = 1)
AND no UV
Power-on
(no uv_VBAT)
RST_N HIGH OR uv_VDD
EN pin LOW AND
RST_N HIGH AND
(IO)
no uv_VDD
(Normal OR Standby OR Sleep_Request)
) AND
(IO)
Power-off
RST_N LOW AND (no uv_VDD
)
RESET
(INH =
no change)
(uv_VBAT)
(IO)
from any
POWER-OFF
(INH = off)
state
from any state other than
Power-off or Sleep
aaa-038965
1. UV means undervoltage on one of the power supply pins VDD(IO), VDDA(3V3), VDDD(1V8), VDDD(3V3)
.
2. INH can be configured to be on or off.
3. The PHY will not be in Sleep mode, and cannot be woken up, until the timeout associated with the transition has
expired (after tto(req)sleep).
4. At power-on, after a transition from Power-off to Standby mode, undervoltage detection timeout is enabled once all
supply voltages are available. When an undervoltage is detected, the TJA1102A switches to Sleep mode after tto(uvd)
.
Figure 10.ꢀMode transition diagram
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6.5 Sleep and wake-up forwarding concept
The sleep and wake-up forwarding concept of the TJA1102A is compliant with the
OPEN Alliance Sleep/Wake-up specification. The TJA1102A features a wake-up request
forwarding function that enables fast wake-up forwarding without the need for a switch,
MAC or μC action. The wake-up forwarding principle is illustrated in Figure 11. The wake-
up request can be forwarded via non-active (gray PHYs in the figure) or active links
(white PHY). In the case of a non-active link, a wake-up pulse (WUP; duration tw(wake)
)
is transmitted, to be detected as activity at the link partner. For an active link, wake up
request (WUR) scrambler code groups are sent.
The wake-up behavior of the PHYs can be configured individually. This arrangement
allows WAKE_IN_OUT to be used as a local wake-up or to have a mixed system with
only some ports forwarding wake-up requests. The following configuration options are
available and are selected via the SMI Configuration register 1 (Table 22):
REMWUPHY determines whether a PHY reacts to a remote wake-up request.
FWDPHYREM determines whether a PHY forwards a wake-up request (from another
port or via WAKE_IN_OUT) to its MDI. A WUP or WUR is sent, depending on the link
status.
LOCWUPHY determines whether a PHY should be woken up in response to a local
wake-up event (forwarded from another port or via WAKE_IN_OUT)
FWDPHYLOC determines whether wake-up event should be forwarded to other ports
(i.e. should the second PHY be informed and/or the WAKE_IN_OUT signal activated).
The WAKE_IN_OUT signal features a programmable timeout to enable it to support a
number of wake-up concepts (e.g. wake-up line). It reacts on a rising edge.
The wake-up detection time, tdet(wake) (see Table 38), on pin WAKE_IN_OUT is
determined by register bit settings LOC_WU_TIM (see Table 29). The wake-up pulse
duration (tp; see Table 38) is also determined by LOC_WU_TIM.
1.2 V
V
BAT
INH
3.3 V
WUP pulses
WUR codes
WUP pulses
PHY
PHY
PHY
aaa-022042
Figure 11.ꢀWake-up request forwarding
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6.6 Autonomous operation
When the TJA1102A is configured for autonomous operation (either via pin strapping,
see Section 6.10, or via bit AUTO_OP in the Common configuration register, Table 29),
it can operate and establish a link without further interaction with a host controller. On
power-on or wake-up from Sleep mode, the TJA1102A goes directly to Normal mode
once all supply voltages are available and the link-up process starts automatically.
Host configuration (e.g. for link or mode control) will not be possible until the device is
switched from autonomous to managed operation by resetting bit AUTO_OP.
6.7 Autonomous power-down
If autonomous power-down is enabled for a PHY (AUTO_PWD = 1), it goes to Sleep
Request mode automatically if no Ethernet frames have been received at the MDI and
(R)MII within the timeout time, tto(pd)autn
.
6.8 Test modes
Five test modes are supported. Only test modes 1, 2, 4 and 5 are included in the
100BASE-T1 specification [1]. The test modes can be selected individually via an SMI
command in Normal mode while link control is disabled. Pin P1_RXER is used as a
reference clock output for PHY0 test modes 1 to 4; pin P0_RXER is used as a reference
clock output for PHY1 test modes 1 to 4 (the nominal P1_RXER/P0_RXER function is
disabled when test modes are active). No load should be connected when the reference
clock is being measured.
6.8.1 Test mode 1
Test mode 1 is used to test transmitter droop. In Test mode 1, the PHY transmits ‘+1’
symbols for 600 ns followed by ‘-1’ symbols for a further 600 ns. This sequence is
repeated continuously.
6.8.2 Test mode 2
Test mode 2 is used to test transmitter timing jitter in Master mode. In Test mode 2, the
PHY transmits the data symbol sequence {+1, -1} repeatedly. The transmission of the
symbols is synchronized with the local external oscillator.
6.8.3 Test mode 3
Test mode 3 is used to test transmitter timing jitter in Slave mode. In Test mode 3, the
PHY transmits the data symbol sequence {+1, -1} repeatedly. The transmission of the
symbols is synchronized with the local external oscillator.
6.8.4 Test mode 4
Test mode 4 is used to test transmitter distortion. In Test mode 4, the PHY transmits the
sequence of symbols generated by the scrambler polynomial gs1 = 1 + x9 + x11.
The bit sequence x0n, x1n is derived from the scrambler according to the following
equations:
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This stream of 3-bit nibbles is mapped to a stream of ternary symbols according to
Table 10.
Table 10.ꢀSymbol mapping in test mode 4
x1n
0
x0n
0
PAM-3 transmit symbol
0
0
1
+1
0
1
0
1
1
-1
6.8.5 Test mode 5
Test mode 5 is used to test the transmit PSD mask. In Test mode 5, the PHY transmits a
random sequence of PAM-3 symbols.
6.8.6 Slave jitter test
To enable the Slave jitter test in Normal mode, bit SLAVE_JITTER_TEST must be set
to 1 before link control is enabled (LINK_CONTROL = 1; see Table 21). During this test,
the transmitter reference clock is fed to pin P1_TXCLK for PHY1 and/or P0_TXCLK for
PHY0 of the TJA1102A. For the TJA1102AS, the transmitter reference clock is fed to pin
P0_TXCLK.
6.9 Error diagnosis
The diagnostic features described in this section are available individually for each dual-
PHY port, except for undervoltage detection of common supply voltages.
6.9.1 Undervoltage detection
The TJA1102A continuously monitors the status of the supply voltages. Once a supply
voltage drops below the specified minimum operating threshold, the TJA1102A enters the
fail-silent Standby mode and communication is halted. If an undervoltage is detected on
VBAT, the TJA1102A switches to Power-off mode.
At power-on, after a transition from Power-off to Standby mode, undervoltage detection
timeout is enabled once all supply voltages are available. The timeout timer is started
when an undervoltage is detected. If the undervoltage is still active when the timer
expires (after tto(uvd)), the TJA1102A switches from Standby mode to Sleep mode.
The microcontroller can determine the source of the interruption by reading the contents
of the External status register (Table 29). The under-voltage detection/recovery range
is positioned immediately next to the operating range, without a gap. Since parameters
are specified down to the minimum value of the under-voltage detection threshold, it
is guaranteed that the behavior of the TJA1102A is fully specified and defined for all
possible voltage condition on the supply pins.
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6.9.2 Cabling errors
The TJA1102A can detect open and short circuits between the twisted-pair bus lines
when neither of the link partners is transmitting (link control disabled). It may make sense
to run the diagnostic before establishing the Ethernet link. When bit CABLE_TEST in
the Extended Control register (Table 21) is set to 1, test pulses are transmitted onto the
transmission medium with a repetition rate of 666.6 kHz. The TJA1102A evaluates the
reflected signals and uses impedance mismatch data along the channel to determine the
quality of the link. The results of the cable test are available in the External status register
(Table 29) within tto(cbl_tst). The tests performed and associated results are summarized in
Table 11.
Table 11.ꢀCable tests and results
The cable bus lines are designated BI_DA+ and BI_DA-, in alignment with 100BASE-T1 [1].
BI_DA+
BI_DA-
Result
open
open
open detected
short detected
open detected
open detected
short detected
open detected
open detected
short detected
+ shorted to -
shorted to VDD
open
- shorted to +
open
shorted to VDD
shorted to VDD
open
shorted to VDD
shorted to GND
open
shorted to GND
shorted to GND
shorted to GND
connected to active link partner connected to active link partner short and open detected
(master)
(master)
6.9.3 Link stability
The Signal Quality Indicator (SQI) is the parameter used to estimate link stability. The
PMA receive function monitors the SQI. Once the value falls below a configurable
threshold (SQI_FAILLIMIT), the link status is set to FAIL and communication is
interrupted. The TJA1102A allows for adjusting the sensitivity of the PMA receive function
by configuring this threshold. The microcontroller can always check the current value of
the SQI via the SMI, allowing it to track a possible degradation in link stability.
6.9.4 Link-fail counter
High losses and/or a noisy channel may cause the link to shut down when reception
is no longer reliable. In such cases, the PHY generates a LINK_STATUS_FAIL
interrupt. Retraining of the link begins automatically provided link control is enabled
(LINK_CONTROL = 1).
Bits LOC_RCVR_COUNTER and REM_RCVR_COUNTER in the Link-fail counter
register (Table 30) are incremented after every link fail event. Both counters are reset
when this register is read.
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6.9.5 Jabber detection
The Jabber detection function prevents the PHY being locked in the DATA state of the
PCS Receive state diagram when the End-of-Stream Delimiters, ESD1 and ESD2, are
not detected.
The maximum time the PHY can reside in the DATA state is limited to tto(PCS-RX)
(rcv_max_timer in the IEEE specification [1]). After this time, the PCS-RX state machine
is reset, triggering a transition to PHY Idle state.
6.9.6 Polarity detection
A polarity error occurs when the two signal wires in the twisted pair cable connected to a
port are swapped. According to the IEEE specification [1], the polarity is always observed
to be correct by the Master PHY; only the Slave is allowed to correct the polarity. When
the TJA1102A is in Slave configuration, it can detect if the ternary symbols sent from the
Master PHY are received with the wrong polarity and will correct this error internally and
set the POLARITY_DETECT bit in the External status register (Table 29). Irrespective of
the Master or Slave mode, the host can overwrite and swap the default MDI polarity by
setting MDI_POL in Configuration Register 3 (Table 32).
6.9.7 Interleave detection
A 100BASE-T1 PHY can send two different interleave sequences of ternary symbols
(TAn, TBn) or (TBn, TAn). The receivers in the TJA1102A are able to de-interleave both
sequences. The order of the ternary symbols detected by the receiver is indicated by the
INTERLEAVE_DETECT bit in the External status register (Table 29).
6.9.8 Loopback modes
The TJA1102A supports three loopback modes:
• Internal loopback (PCS loopback in accordance with IEEE 802.3bw)
• External loopback
• Remote loopback
To run a PHY in loopback mode, the LOOPBACK control bit in the Basic control register
should be set before enabling link control.
6.9.8.1 Internal loopback
In Internal loopback mode, the PCS receive function gets the ternary symbols An and
Bn directly from the PCS transmit function as shown in Figure 12. This action allows the
MAC to compare packets sent through the MII transmit function with packets received
from the MII receive function and, therefore, to validate the functionality of the 100BASE-
T1 PCS function.
PMA
PCS
RECEIVE
RECEIVE
MII Receive
MDI
HYBRID
A , B
n
n
PMA
TRANSMIT
PCS
TRANSMIT
MII Transmit
aaa-019866
Figure 12.ꢀInternal loopback
TJA1102A
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6.9.8.2 External loopback
In External loopback mode, the PMA receive function receives signals directly from the
PMA transmit function as shown in Figure 13. This external loopback test allows the MAC
to compare packets sent through the MII transmit function with packets received from the
MII receive function and, therefore, to validate the functionality of the 100BASE-T1 PCS
and PMA functions.
PMA
RECEIVE
PCS
RECEIVE
MII Receive
open
HYBRID
PMA
TRANSMIT
PCS
TRANSMIT
MII Transmit
aaa-019868
Figure 13.ꢀExternal loopback
6.9.8.3 Remote loopback
In Remote loopback mode, the packet received by the link partner at the MDI is passed
through the PMA receive and PCS receive functions and forwarded to the PCS transmit
function, which in turn sends it back to the link partner from where it came. The PCS
receive data is made available at the MII. Remote loopback allows the MAC to compare
the packets sent to the MDI with the packets received back from the MDI and, therefore,
to validate the functionality of the physical channel, including both 100BASE-T1 PHYs.
PMA
RECEIVE
PCS
RECEIVE
MII Receive
MII
MAC
PHY
HYBRID
PMA
TRANSMIT
PCS
TRANSMIT
MII Transmit
PHY in Remote loopback mode
aaa-019869
Figure 14.ꢀRemote loopback
6.10 Hardware configuration
A number of pins are provided to allow default values for a number of features to be
hardware-configured, without microcontroller interaction. The pull-up/down behavior
of these pins is sensed at power-up and after a reset. A pull-up behavior is coded
as logic 1, while a pull-down behavior is coded as logic 0. The results are stored in
the corresponding SMI registers. All pre-configuration settings (except for the PHY
addresses) can be overwritten via SMI commands.
Pin strapping at pins 37 (PHYAD3), 36 (PHYAD2) and 35 (PHYAD1) determines bits
3, 2 and 1, respectively, of the PHY address used for the SMI address/Cipher scrambler.
The PHY address cannot be changed once the PHY has been configured. Besides
the address configured via pin strapping, the TJA1102A can always be accessed via
address 0.
Table 12 gives an overview of the functions to be configured via hardware pins.
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Table 12.ꢀPin strapping configuration[1]
Symbol
Pin
Value
000[2]
001
010
011
100
101
110
111
0
Description
MASTER_SLAVE/
PHY_EN
34 (CONFIG3)
33 (CONFIG2)
32 (CONFIG1)
P0 disabled, P1 Master
P0 disabled, P1 Slave
P0 Master, P1 disabled
P0 Master, P1 Master
P0 Master, P1 Slave
P0 Slave, P1 disabled
P0 Slave, P1 Master
P0 Slave, P1 Slave
AUTO_OP
55 (CONFIG0)
managed operation
1
autonomous operation
bit 3 of PHY address used for the SMI
bit 2 of PHY address used for the SMI
bit 1 of PHY address used for the SMI
PHYAD[3:1]
37 (PHYAD3)
36 (PHYAD2)
35 (PHYAD1)
-
-
-
MII_CONFIG
1 (CONFIG5)
56 (CONFIG4)
00[3]
MII mode enabled for both PHYs (bits
MII_MODE in Table 22 set to 00)
01[4]
10[3]
RMII mode enabled for both PHYs (bits
MII_MODE in Table 22 set to 01 or 10,
depending on CLK_MODE)
Reverse MII mode P0;
MII mode P1, internal MII
(bits MII_MODE in Table 22 set to 11 for P0
and 00 for P1; bit INT_REV_MII in Table 29
set to 1)
11[3]
Reverse MII mode P0;
MII mode P1; external MII;
(bits MII_MODE in Table 22 set to 11 for P0
and 00 for P1; bit INT_REV_MII in Table 29
set to 0)
CLK_MODE
LDO_MODE
3 (CONFIG7)
2 (CONFIG6)
00
01
10
11
25 MHz XTAL; no clock at CLK_IN_OUT
25 MHz XTAL; 25 MHz at CLK_IN_OUT
25 MHz external clock at CLK_IN_OUT
50 MHz input at REF_CLK; RMII mode only;
no XTAL; no clock at CLK_IN_OUT
15 (SEL_1V8)
0
1
internal 1.8 V LDO enabled
external 1.8 V supply
[1] Pin strapping functionality relating to PHY1 is not relevant to the TJA1102AS, since P1 is permanently disabled.
[2] Ordered from MSB to LSB; for value 011 for example, pin 34 = 0, pin 33 = 1 and pin 32 = 1. Note that PHY1 is always
disabled in the TJA1102AS, regardless of the value level of on these pins during pin strapping.
[3] CLK_MODE = 00, 01 or 10.
[4] All clock modes (CLK_MODE = xx).
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6.11 SMI registers
A dedicated register set is provided for each PHY. Some register bits are only valid for
block P0 and always return 0 when read from block P1. These bits are indicated in the
appropriate tables. Two shared configuration registers are provided to configure common
parameters.
Access to the register sets for both PHY blocks on the TJA1102A is provided via the
SMI. Which PHY block is selected by an SMI read/write access depends on the PHY
address in the SMI frame (read/write access to disabled block P1 is not supported on the
TJA1102AS).
6.11.1 Register mapping overview
Copies of the registers listed in Table 13 are provided for each PHY (except for the
Common configuration registers which are shared) and are accessible via SMI with the
appropriate PHY address.
Table 13.ꢀSMI register mapping
Register index (dec)
Register name
Group
0
Basic control register
Basic
1
Basic status register
Basic
2
PHY identification register 1
PHY identification register 2
Extended status register
PHY identification register 3
Extended control register
Configuration register 1
Configuration register 2
Symbol error counter register
Interrupt source register
Interrupt enable register
Communication status register
General status register
External status register
Link-fail counter register
Common configuration register
Configuration register 3
Extended (P0 only)
Extended (P0 only)
Extended
3
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NXP specific (P0 only)
NXP specific
NXP specific
NXP specific
NXP specific
NXP specific
NXP specific
NXP specific
NXP specific
NXP specific
NXP specific
NXP specific (P0 only)
NXP specific
Table 14.ꢀRegister notation
Notation
Description
Read/write
Read only
R/W
R
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Table 14.ꢀRegister notation...continued
Notation
Description
LH
LL
Latched HIGH; must be read out to reset
Latched LOW; must be read out to reset
Self-clearing
SC
PS
Pin strapping
6.11.2 TJA1102A registers
Table 15.ꢀBasic control register (register 0)
Bit
Symbol
Access
Value
Description
15
RESET
R/W
SC
software reset control:
normal operation
PHY reset
0[1]
1
14
13
LOOPBACK[2]
R/W
R/W
loopback control:
normal operation
loopback mode
0[1]
1
[3]
SPEED_SELECT (LSB)
speed select (LSB):
0
10 Mbit/s if SPEED_SELECT (MSB) = 0
1000 Mbit/s if SPEED_SELECT (MSB) = 1
1[1]
0[1]
100 Mbit/s if SPEED_SELECT (MSB) = 0
reserved if SPEED_SELECT (MSB) = 1
12
11
AUTONEG_EN
POWER_DOWN
R/W
SC
Auto negotiation not supported; always 0; a write access is
ignored.
R/W
Standby power down enable:
0[1]
normal operation (clearing this bit automatically triggers
a transition to Normal mode, provided control bits
POWER_MODE are set to 0011 Normal mode, see
Table 21)
1
power down and switch to Standby mode (provided
ISOLATE = 0; ignored if ISOLATE = 1 and
CONTROL_ERR interrupt generated)
10
ISOLATE
R/W
PHY isolation:
0[1]
1
normal operation
isolate PHY from MII/RMII (provided POWER_DOWN =
0; ignored if POWER_DOWN = 1 and CONTROL_ERR
interrupt generated)
9
RE_AUTONEG
R/W
SC
0[1]
1[1]
Auto negotiation not supported; always 0; a write access is
ignored.
8
7
DUPLEX_MODE
R/W
R/W
R/W
only full duplex supported; always 1; a write access is
ignored.
COLLISION_TEST
SPEED_SELECT (MSB)
0[1]
COL signal test not supported; always 0; a write access is
ignored.
[3]
6
speed select (MSB):
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Table 15.ꢀBasic control register (register 0)...continued
Bit
Symbol
Access
Value
Description
0[1]
10 Mbit/s if SPEED_SELECT (LSB) = 0
100 Mbit/s if SPEED_SELECT (LSB) = 1
1
1000 Mbit/s if SPEED_SELECT (LSB) = 0
reserved if SPEED_SELECT (LSB) = 1
5
UNIDIRECT_EN
R/W
unidirectional enable when bit 12 (AUTONEG_EN) = 0 and bit
8 (DUPLEX_MODE) = 1:
0[1]
enable transmit from MII only when the PHY has
determined that a valid link has been established
1
enable transmit from MII regardless of whether the PHY
has determined that a valid link has been established
4:0
reserved
R/W
00000[1]
always write 00000; ignore on read
[1] Default value.
[2] The loopback mode is selected via bits LOOPBACK_MODE in the Extended control register (Table 21).
[3] Speed Select: 00: 10 Mbit/s; 01: 100 Mbit/s; 10: 1000 Mbit/s; 11: reserved; a write access value other than 01 is ignored.
Table 16.ꢀBasic status register (register 1)
Bit
Symbol
Access Value Description
15
100BASE-T4
R
R
R
R
R
R
R
R
R
0[1]
PHY not able to perform 100BASE-T4
1
PHY able to perform 100BASE-T4
14
13
12
11
10
9
100BASE-X_FD
100BASE-X_HD
10Mbps_FD
0[1]
1
0[1]
PHY not able to perform 100BASE-X full-duplex
PHY able to perform 100BASE-X full-duplex
PHY not able to perform 100BASE-X half-duplex
PHY able to perform 100BASE-X half-duplex
PHY not able to perform 10 Mbit/s full-duplex
PHY able to perform 10 Mbit/s full-duplex
PHY not able to perform 10 Mbit/s half-duplex
PHY able to perform 10 Mbit/s half-duplex
PHY not able to perform 100BASE-T2 full-duplex
PHY able to perform 100BASE-T2 full-duplex
PHY not able to perform 100BASE-T2 half-duplex
PHY able to perform 100BASE-T2 half-duplex
no extended status information in register 15h
extended status information in register 15h
1
0[1]
1
0[1]
10Mbps_HD
1
100BASE-T2_FD
100BASE-T2_HD
EXTENDED_STATUS
UNIDIRECT_ ABILITY
0[1]
1
0[1]
1
8
0
1[1]
7
0
PHY able to transmit from MII only when the PHY has
determined that a valid link has been established
1[1]
0
PHY able to transmit from MII regardless of whether the
PHY has determined that a valid link has been established
6
MF_PREAMBLE_SUPPRESSION
R
PHY will not accept management frames with preamble
suppressed
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Table 16.ꢀBasic status register (register 1)...continued
Bit
Symbol
Access Value Description
1[1]
PHY will accept management frames with preamble
suppressed
5
4
3
2
1
0
AUTONEG_COMPLETE
REMOTE_FAULT
R
0
Autonegotiation process not completed
Autonegotiation process completed
no remote fault condition detected
remote fault condition detected
1[1]
0[1][2]
1
R
LH
AUTONEG_ABILITY
LINK_STATUS
R
0[1]
PHY not able to perform Autonegotiation
1
PHY able to perform Autonegotiation
R
0[1][2][3] link is down
LL
1
0[1][2]
link is up
JABBER_DETECT
EXTENDED_CAPABILITY
R
no jabber condition detected
jabber condition detected
basic register set capabilities only
extended register capabilities
LH
1
R
0
1[1]
[1] Default value.
[2] Reset to default value when link control is disabled (LINK_CONTROL = 0).
[3] According to IEEE 802.3; LINK_STATUS = 1 when LOC_RCVR_STATUS = 1.
Table 17.ꢀPHY identification register 1 (register 2)
Bit
Symbol
Access
Value
0180h[1]
Description
bits 3 to 18 of the Organizationally Unique Identifier (OUI)[2]
15:0
PHY_ID
R
[1] Default value (PHY0 only in dual PHY variant; returns all 0s for PHY1).
[2] OUI = 00.60.37h (PHY0 only in dual PHY variant; returns all 0s for PHY1).
Table 18.ꢀPHY identification register 2 (register 3)
Bit
Symbol
PHY_ID
TYPE_NO
Access
Value
Description
bits 19 to 24 of the OUI[2]
15:10
9:4
R
R
110111[1]
001000[3]
001001[4]
0010[1]
six-bit manufacturer’s type number
3:0
REVISION_NO
R
four-bit manufacturer’s revision number
[1] Default value (PHY0 only in dual-PHY variant; returns all 0s for PHY1).
[2] OUI = 00.60.37h (PHY0 only in dual-PHY variant; returns all 0s for PHY1).
[3] Default value for TJA1102A dual-PHY variant (PHY0 only; returns all 0s for PHY1).
[4] Default value for TJA1102AS.
Table 19.ꢀPHY identification register 3 (Register 16)
Bit
Symbol
Access
Value
Description
15:8
reserved
R
-
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Table 19.ꢀPHY identification register 3 (Register 16)...continued
Bit
Symbol
Access
Value
Description
7:0
VERSION_NO
R
xxh[1]
8-bit manufacturer's firmware revision number
[1] Default value (PHY0 only in dual-PHY variant; returns all 0s for PHY1).
Table 20.ꢀExtended status register (register 15)
Bit Symbol
Access Value
Description
15
14
13
12
1000BASE-X_FD
R
R
R
R
0[1]
PHY not able to perform 1000BASE-X full-duplex
PHY able to perform 1000BASE-X full-duplex
PHY not able to perform 1000BASE-X half-duplex
PHY able to perform 1000BASE-X half-duplex
PHY not able to perform 1000BASE-T full-duplex
PHY able to perform 1000BASE-T full-duplex
PHY not able to perform 1000BASE-T half-duplex
PHY able to perform 1000BASE-T half-duplex
always 0000; ignore on read
1
1000BASE-X_HD
1000BASE-T_FD
1000BASE-T_HD
0[1]
1
0[1]
1
0[1]
1
0000[1]
11:8 reserved
R
R
7
100BASE-T1
0
PHY not able to 1-pair 100BASE-T1 100 Mbit/s
PHY able to 1-pair 100BASE-T1 100 Mbit/s
PHY not able to support RTPGE
1[1]
0[1]
1
6
1000BASE-RTPGE
R
R
PHY supports RTPGE
5:0 reserved
-
ignore on read
[1] Default value.
Table 21.ꢀExtended control register (register 17)
Bit
Symbol
Access
Value
Description
[1]
15
LINK_CONTROL
R/W
link control enable:
0
link control disabled
1
link control enabled
[2]
14:11
POWER_MODE
R/W
operating mode select:
no change
0000[3]
0011
1001
1010
1011
1100
Normal mode (command)
Silent mode (read only)
Sleep mode (read only)
Sleep Request mode (command)
Standby mode (command)
enable/disable Slave jitter test
disable Slave jitter test
10
SLAVE_JITTER_TEST[4] R/W
0[3]
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Table 21.ꢀExtended control register (register 17)...continued
Bit
Symbol
Access
Value
Description
1
enable Slave jitter test
9
TRAINING_RESTART
R/W
SC
Autonegotiation process restart:
halts the training phase
forces a restart of the training phase
test mode selection:
0[3]
1
8:6
TEST_MODE[4]
R/W
000[3]
001
010
011
100
101
110
111
no test mode
100BASE-T1 test mode 1
100BASE-T1 test mode 2
test mode 3
100BASE-T1 test mode 4
100BASE-T1 test mode 5
scrambler and descrambler bypassed
reserved; ignore on read
TDR-based cable test:
stops TDR-based cable test
forces TDR-based cable test
loopback mode select:
internal loopback
5
CABLE_TEST
R/W
SC
0[3]
1
4:3
LOOPBACK_MODE[4][5] R/W
00[3]
01
external loopback
10
external loopback
11
remote loopback
[3]
2
CONFIG_EN
R/W
configuration register access:
configuration register access disabled
configuration register access enabled
ignore on read
0[3]
1
1
0
reserved
R/W
SC
-
WAKE_REQUEST
wake-up request configuration:
no wake-up signal to be transmitted
0[3]
1
LINK_CONTROL = 0: transmit idle symbols as bus wake-up
request
LINK_CONTROL = 1: transmit WUR symbols
[1] Default value is 0 when AUTO_OP = 0; default value is 1 when AUTO_OP = 1.
[2] Any other value generates a CONTROL_ERR interrupt.
[3] Default value.
[4] Link control must be disabled (LINK_CONTROL = 0) before entering this mode.
[5] The selected loopback mode is enabled when bit LOOPBACK in the Basic control register (Table 15) is set to 1.
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Table 22.ꢀConfiguration register 1 (register 18)
Bit
Symbol
Access
Value
Description
[1]
15
MASTER_SLAVE
R/W
PHY Master/Slave configuration:
PHY configured as Slave
PHY configured as Master
local wake-up forwarding:
wake-up event not forwarded locally
wake-up event forwarded locally
ignore on read
0
1
[2]
14
FWDPHYLOC
R/W
0
1[3]
13:12
11
reserved
R/W
R/W
-
[2]
REMWUPHY
remote wake-up:
0
1[3]
PHY does not react to a remote wake-up
PHY reacts to a remote wake-up
local wake-up:
[2] [4]
10
LOCWUPHY
MII_MODE
R/W
R/W
0
1[3]
PHY does not react to a local wake-up
PHY reacts to a local wake-up
MII mode:
[1]
9:8
00
01
10
11
MII mode enabled
RMII mode enabled (50 MHz input on Px_REF_CLK)
RMII mode enabled (25 MHz XTAL output on Px_REF_CLK)
Reverse MII mode
7
6
MII_DRIVER
R/W
MII output driver strength:
standard
0[3]
1
reduced
SLEEP_CONFIRM R/W
sleep confirmation setting:
0[3]
1
no confirmation needed from another PHY before going to
sleep
confirmation needed from another PHY before going to sleep
LPS/WUR setting:
5
4
LPS_WUR_DIS
SLEEP_ACK
R/W
R/W
0[3]
1
LPS/WUR enabled
LPS/WUR disabled
sleep acknowledge:
0[3]
sleep acknowledge timer disabled; auto-transition back from
Sleep Request mode to Normal mode enabled during data
transmission on MII or MDI
1
sleep acknowledge timer enabled; auto-transition back from
Sleep Request mode to Normal mode disabled during data
transmission on MII or MDI
3
2
reserved
R/W
R/W
-
ignore on read
[2]
FWDPHYREM
remote wake-up forwarding:
remote wake-up event not forwarded
0[3]
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Table 22.ꢀConfiguration register 1 (register 18)...continued
Bit
Symbol
Access
Value
Description
1
remote wake-up event forwarded
autonomous power down:
1
AUTO_PWD
R/W
0[3]
1
autonomous power-down disabled
autonomous power-down enabled
LPS code group reception:
0
LPS_ACTIVE
R/W
0
automatic transition from Normal to Sleep Request when LPS
code group received disabled
1[3]
automatic transition from Normal to Sleep Request when LPS
code group received enabled
[1] Default value determined by pin strapping (see Section 6.10).
[2] Clear bits FWDPHYLOC, REMWUPHY, LOCWUPHY and FWDPHYREM if the corresponding wake-up/forwarding feature is not being used.
[3] Default value.
[4] Setting LOCWUPHY has an activation time of tdet(wake). If a wake-up occurs within the activation time, it may not be detected.
Table 23.ꢀConfiguration register 2 (register 19)
Bit
Symbol
Access Value
Description
[1]
15:11
PHYAD[4:0]
R
PHY address used for the SMI address and for initializing the
Cipher scrambler key:
PHYAD[4] is set to 0
PHYAD[3:1] is predetermined by the hardware configuration
straps on pins 37, 36 and 35 respectively
PHYAD[0] set to 0 for P0 and 1 for P1
Signal Quality Indicator (SQI) averaging:
SQI averaged 32 symbols
SQI averaged 64 symbols
SQI averaged 128 symbols
SQI averaged 256 symbols
SQI warning limit:
[2]
10:9
SQI_AVERAGING
R/W
00
01[3]
10
11
8:6
SQI_WLIMIT
R/W
000
no warning limit
001[3]
class A SQI warning limit
class B SQI warning limit
class C SQI warning limit
class D SQI warning limit
class E SQI warning limit
class F SQI warning limit
class G SQI warning limit
SQI fail limit:
010
011
100
101
110
111
5:3
SQI_FAILLIMIT
R/W
000[3]
001
no fail limit
class A SQI fail limit
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Table 23.ꢀConfiguration register 2 (register 19)...continued
Bit
Symbol
Access Value
Description
010
class B SQI fail limit
class C SQI fail limit
class D SQI fail limit
class E SQI fail limit
class F SQI fail limit
class G SQI fail limit
Jumbo packet support:
packets up to 4 kB supported
packets up to 16 kB supported
sleep request/acknowledge timeout:
0.4 ms/0.2 ms
011
100
101
110
111
2
JUMBO_ENABLE
R/W
0
1[3]
[4]
1:0
SLEEP_REQUEST_TO R/W
00
01[3]
1 ms/0.5 ms
10
4 ms/2 ms
11
16 ms/8 ms
[1] Default value determined by pin strapping (see Section 6.10).
[2] The SQI is derived from the actual internal slicer margin and includes filtering. Averaging the SQI value itself does not, therefore, have any added value.
[3] Default value.
[4] The specified values are nominal settings; see parameters tto(req)sleep and tto(ack)sleep, respectively, for the limits.
Table 24.ꢀSymbol error counter register (register 20)
Bit
Symbol
Access
Value
Description
15:0
SYM_ERR_CNT
R
0000h[1]
The symbol error counter is incremented when an invalid code
symbol is received (including idle symbols). The counter is
incremented only once per packet, even when the received packet
contains more than one symbol error. This counter increments up to
216. When the counter overflows, the value FFFFh is retained. The
counter is reset when the register is read.
[1] Default value. Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 25.ꢀInterrupt source register (register 21)
Bit
Symbol
Access
Value
0[1]
1
Description
15
PWON
R
power-on not detected
LH
power-on detected
14
13
WAKEUP
R
0[2][3]
no local or remote wake-up detected
local or remote wake-up detected
no dedicated wake-up request detected
dedicated wake-up request detected
LH
1
WUR_RECEIVED
R
0[2]
1
LH
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 25.ꢀInterrupt source register (register 21)...continued
Bit
Symbol
Access
Value
0[2]
1
Description
12
LPS_RECEIVED
R
no LPS code groups received
LPS code groups received
LH
11
10
9
PHY_INIT_FAIL
LINK_STATUS_FAIL
LINK_STATUS_UP
SYM_ERR
R
0[2]
no PHY initialization error detected
PHY initialization error detected
link status not changed
LH
1
R
0[2][4]
1
0[2][4]
1
0[2][4]
1
LH
link status bit LINK_UP changed from ‘link OK’ to ‘link fail’
link status not changed
R
LH
link status bit LINK_UP changed from ‘link fail’ to ‘link OK’
no symbol error detected
8
R
LH
symbol error detected
7
TRAINING_FAILED
SQI_WARNING
CONTROL_ERR
R
0[2]
no training phase failure detected
training phase failure detected
SQI value above warning limit
SQI value below warning limit and bit LINK_UP set
no SMI control error detected
SMI control error detected
LH
1
6
R
0[2][4]
1
0[2]
LH
5
R
LH
1
4
3
reserved
UV_ERR
R
-
ignore on read
R
0[1]
no undervoltage detected
LH
1
undervoltage detected on VDD(IO), VDDD(3V3), VDDD(1V8) or
VDDA(3V3)
2
1
0
UV_RECOVERY
TEMP_ERR
R
0[1]
1
0[1]
no undervoltage recovery detected
undervoltage recovery detected
no overtemperature error detected
overtemperature error detected
LH
R
LH
1
0[2]
SLEEP_ABORT
R
no transition from Sleep Request back to Normal as a result of
the Sleep Request timer expiring
LH
1
transition from Sleep Request back to Normal as a result of the
Sleep Request timer expiring
[1] Default value (P0 only; always returns 0 for P1 block).
[2] Default value.
[3] Bit WAKEUP may be set when an undervoltage is detected on VDD(IO) in Sleep_Request mode. Ignore this bit when bit UV_VDDIO is set.
Bit WAKEUP is reset by a read operation; however wake-up detection will not be enabled again until a state transition has been completed.
[4] Interrupts LINK_STATUS_FAIL, LINK_STATUS_UP, SYM_ERR and SQI_WARNING are cleared on entering Sleep Request mode, on entering Standby
mode due to an undervoltage and when an undervoltage is detected in Standby mode.
Table 26.ꢀInterrupt enable register (register 22)
Disabling an interrupt source disables signaling at pin INT_N for that interrupt. However, the corresponding bit in the
Interrupt source register (Table 25) remains active.
Bit
Symbol
Access
Value
Description
15
PWON_EN
R/W
0[1]
PWON interrupt disabled
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Table 26.ꢀInterrupt enable register (register 22)...continued
Disabling an interrupt source disables signaling at pin INT_N for that interrupt. However, the corresponding bit in the
Interrupt source register (Table 25) remains active.
Bit
14
13
12
11
10
9
Symbol
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
1[1]
0[2]
1
Description
PWON interrupt enabled
WAKEUP_EN
WAKEUP interrupt disabled
WAKEUP interrupt enabled
WUR_RECEIVED_EN
LPS_RECEIVED_EN
PHY_INIT_FAIL_EN
LINK_STATUS_FAIL_EN
LINK_STATUS_UP_EN
SYM_ERR_EN
0[2]
WUR_RECEIVED interrupt disabled
WUR_RECEIVED interrupt enabled
LPS_RECEIVED interrupt disabled
LPS_RECEIVED interrupt enabled
PHY_INIT_FAIL interrupt disabled
PHY_INIT_FAIL interrupt enabled
LINK_STATUS_FAIL interrupt disabled
LINK_STATUS_FAIL interrupt enabled
LINK_STATUS_UP interrupt disabled
LINK_STATUS_UP interrupt enabled
SYM_ERR interrupt disabled
1
0[2]
1
0[2]
1
0[2]
1
0[2]
1
8
0[2]
1
0[2]
SYM_ERR interrupt enabled
7
TRAINING_FAILED_EN
SQI_WARNING_EN
CONTROL_ERR_EN
TRAINING_FAILED interrupt disabled
TRAINING_FAILED interrupt enabled
SQI_WARNING interrupt disabled
SQI_WARNING interrupt enabled
CONTROL_ERR interrupt disabled
CONTROL_ERR interrupt enabled
always write 0; ignore on read
UV_ERR interrupt disabled
1
6
0[2]
1
0[2]
5
1
4
3
reserved
R/W
R/W
0[2]
0[2]
1
UV_ERR_EN
UV_ERR interrupt enabled
2
1
0
UV_RECOVERY_EN
TEMP_ERR_EN
R/W
R/W
R/W
0[2]
UV_RECOVERY interrupt disabled
UV_RECOVERY interrupt enabled
TEMP_ERR interrupt disabled
TEMP_ERR interrupt enabled
SLEEP_ABORT interrupt disabled
SLEEP_ABORT interrupt enabled
1
0[2]
1
0[2]
SLEEP_ABORT_EN
1
[1] Default value is 1 for block P0 and 0 for block P1 (TJA1102A).
[2] Default value.
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Table 27.ꢀCommunication status register (register 23)
Bit
Symbol
Access Value
Description
15
LINK_UP
R
R
0[1][2]
link failure
1
link OK
14:13 TX_MODE
00[1][2]
01
transmitter disabled
transmitter in SEND_N mode
transmitter in SEND_I mode
transmitter in SEND_Z mode
local receiver not OK
local receiver OK
10
11
12
11
10
9
LOC_RCVR_STATUS
R
0[1][2]
1
0[1][2]
1
0[1][2]
1
0[1][2]
1
0[1][2]
1
LL
REM_RCVR_STATUS
SCR_LOCKED
SSD_ERR
R
remote receiver not OK
remote receiver OK
LL
R
descrambler unlocked
descrambler locked
R
no SSD error detected
SSD error detected
LH
8
ESD_ERR
R
no ESD error detected
ESD error detected
LH
7:5
SQI
R
000[1][2]
001
010
011
100
101
110
111
0[1][2]
0
worse than class A SQI (unstable link)
class A SQI (unstable link)
class B SQI (unstable link)
class C SQI (good link)
class D SQI (good link; bit error rate < 1e-10)
class E SQI (good link)
class F SQI (very good link)
class G SQI (very good link)
no receive error detected
receive error detected since register last read
no transmit error detected
transmit error detected since register last read
PHY Idle
4
RECEIVE_ERR
TRANSMIT_ERR
PHY_STATE
R
LH
3
R
0[1][2]
LH
1
2:0
R
000[1]
001
010
011
100
101
110
111
PHY Initializing
PHY Configured
PHY Offline
PHY Active
PHY Isolate
PHY Cable test
PHY Test mode
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[1] Default value.
[2] Reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 28.ꢀGeneral status register (register 24)
Bit
Symbol
Access
Value
0[1]
1
Description
15
INT_STATUS
R
all interrupts cleared
unmasked interrupt pending
PLL unstable and not locked
PLL stable and locked
no local wake-up detected
local wake-up detected
no remote wake-up detected
remote wake-up detected
14
13
12
11
PLL_LOCKED
LOCAL_WU
R
0[1]
LL
1
R
0[1][2]
1
0[1][2]
1
LH
REMOTE_WU
DATA_DET_WU
R
LH
R
0[1][3]
no 100BASE-T1 data detected at MDI or MII in Sleep
Request mode
LH
1
100BASE-T1 data detected at MDI (pcs_rx_dv = TRUE; see
[1]) or MII (TXEN = 1) in Sleep Request mode
10
9
EN_STATUS
R
0[4]
1
0[4]
EN HIGH
LH
EN switched LOW since register last read
no hardware reset detected
hardware reset detected since register last read
ignore on read
RESET_STATUS
R
LH
1
8
reserved
R
R
R
-
7:3
2:0
LINKFAIL_CNT
reserved
00000[1][5] number of link fails since register last read
-
ignore on read
[1] Default value.
[2] Status bit is cleared by a read operation; however wake-up detection will not be enabled again until a state transition has been completed.
[3] Bit DATA_DET_WU may be set when an undervoltage is detected on VDD(IO) in Sleep_Request mode. Ignore this bit when bit UV_VDDIO is set.
[4] Default value (P0 only; always returns 0 for P1 block).
[5] Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 29.ꢀExternal status register (register 25)
Bit
Symbol
Access
Value
0[1]
1
Description
15
UV_VDDD_3V3
R
no undervoltage detected on pin VDDD(3V3)
undervoltage detected on pin VDDD(3V3)
no undervoltage detected on pin VDDA(3V3)
undervoltage detected on pin VDDA(3V3)
no undervoltage detected on pin VDDD(1V8)
undervoltage detected on pin VDDD(1V8)
ignore on read
LH
14
13
UV_VDDA_3V3
UV_VDDD_1V8
R
0[1]
LH
1
R
0[1]
1
LH
12
11
reserved
R
-
UV_VDDIO
R
0[1]
no undervoltage detected on pin VDD(IO)
undervoltage detected on pin VDD(IO)
LH
1
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Table 29.ꢀExternal status register (register 25)...continued
Bit
Symbol
Access
Value
0[1]
1
Description
10
TEMP_HIGH
R
temperature below high level
LH
temperature above high level
9
TEMP_WARN
R
0[1]
temperature below warning level
temperature above warning level
no short circuit detected
LH
1
8
SHORT_DETECT
OPEN_DETECT
POLARITY_DETECT
INTERLEAVE_DETECT
reserved
R
0[2]
1
0[2]
LH
short circuit detected since register last read
no open circuit detected
7
R
LH
1
open circuit detected since register last read
no polarity inversion detected at MDI
polarity inversion detected at MDI
interleave order of detected ternary symbols: TAn, TBn
interleave order of detected ternary symbols: TBn, TAn
ignore on read
6
R
R
R
0[2]
1
0[2]
5
1
4:0
-
[1] Default value (P0 only; always returns 0 for P1 block).
[2] Default value; bit NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 30.ꢀLink fail counter register (register 26)
Bit
Symbol
Access
Value
Description
15:8
LOC_RCVR_CNT
R
00h[1][2]
The counter is incremented when local receiver is NOT_OK;
when the counter overflows, the value FFh is retained. The
counter is reset when the register is read.
7:0
REM_RCVR_CNT
R
00h[1][2]
The counter is incremented when remote receiver is NOT_OK;
when the counter overflows, the value FFh is retained. The
counter is reset when the register is read.
[1] Default value.
[2] Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 31.ꢀCommon configuration register (register 27)[1]
Bit
Symbol
Access
Value
Description
[2]
15
AUTO_OP
R/W
managed/autonomous operation:
managed operation
0
1
autonomous operation
[2]
14
INT_REV_MII
CLK_MODE
R/W
R/W
PHY Master/Slave configuration (P0 in Reverse MII mode; P1 in
MII mode)
0
P1 must be connected externally to P0 (external PHY must be
connected to P0 in the TJA1102AS)
1
P1 connected internally to P0 (TJA1102A)
clock mode:
[2]
13:12
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Table 31.ꢀCommon configuration register (register 27)[1]...continued
Bit
Symbol
Access
Value
00
Description
25 MHz XTAL; no clock at CLK_IN_OUT
01
25 MHz XTAL; 25 MHz output at CLK_IN_OUT
25 MHz external clock at CLK_IN_OUT
10
11
50 MHz input at REF_CLK; RMII mode only; no XTAL; no
clock at CLK_IN_OUT
[2]
11
10
9
LDO_MODE
CLK_DRIVER
CLK_HOLD
R/W
R/W
R/W
LDO mode:
0
1
internal 1.8 V LDO enabled
external 1.8 V supply
output driver strength on CLK_IN_OUT:
standard output driver strength at output of CLK_IN_OUT
reduced output driver strength at output of CLK_IN_OUT
local wake-up:
0[3]
1
0[3]
1
XTAL and CLK_IN_OUT output switched off when not needed
by P0 and P1
XTAL and CLK_IN_OUT output remain active until device
switched to Sleep mode via SMI
8:7
LOC_WU_TIM
R/W
local wake-up timer:
00[3]
01
longest (10 ms to 20 ms)
long (250 μs to 500 μs)
short (100 μs to 200 μs)
shortest (10 μs to 40 μs)
local wake configuration:
absolute input threshold
10
11
6
CONFIG_WAKE
CONFIG_INH
reserved
R/W
R/W
R/W
0
1[3]
ratiometric input threshold (VDD(IO)
)
5
INH configuration:
0[3]
1
INH switched off in Disable mode
INH switched on in Disable mode
ignore on read
4:0
-
[1] Read/write operations valid for P0 only (read operation always returns 0 for P1 block).
[2] Default value determined by pin strapping (see Section 6.10).
[3] Default value.
Table 32.ꢀConfiguration register 3 (register 28)
Bit
Symbol
Access
Value
Description
15:3
reserved
R/W
-
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 32.ꢀConfiguration register 3 (register 28)...continued
Bit
Symbol
Access
Value
Description
MDI polarity:
regular polarity:
2
MDI_POL
R/W
0[1]
pin 17 = P0_TRX_P; pin 18 = P0_TRX_M
pin 25 = P1_TRX_P; pin 24 = P1_TRX_M
1
swapped polarity:
pin 17 = P0_TRX_M; pin 18 = P0_TRX_P
pin 25 = P1_TRX_M; pin 24 = P1_TRX_P
1
0
FORCE_SLEEP
PHY_EN
R/W
SC
forced sleep operation:
0[2]
forced sleep inactive
1
force both PHYs to Sleep mode and device to system sleep
[3]
R/W
PHY enable:
PHY disabled
PHY enabled
0
1
[1] Default value.
[2] Default value (P0 only; always returns 0 for P1 block).
[3] Default value determined by pin strapping (see Section 6.10).
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7 Limiting values
Table 33.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter
Conditions
Min Max
Unit
V
Vx
voltage on pin x[1]
on pin VBAT
-0.3 +40
on pin INH
-0.3 VBAT + 0.3
V
on pin WAKE_IN_OUT
-36
+42
V
on pins VDDA(3V3), P0_VDDA(TX), P1_VDDA(TX)
VDDD(3V3), VDD(IO), P0_TRX_P, P0_TRX_M,
P1_TRX_P, P1_TRX_M
,
-0.3 +4.6
V
on pins VDDD(1V8), XI, XO
-0.3 +2.5
V
V
on input pins MDC, MDIO, RST_N, INT_N, EN,
CLK_IN_OUT, SEL_1V8 and MII digital input
pins
-0.3 min(VDD(IO)
0.3, +4.6)
+
on digital output pins
-0.3 VDD(IO) + 0.3
V
IO(INH)
Vtrt
output current on pin INH
transient voltage
-2
-
mA
[2]
on pins WAKE_IN_OUT, VBAT, P0_TRX_P,
P0_TRX_M, P1_TRX_P, P1_TRX_M
pulse 1
-100
-
V
V
V
V
pulse 2a
-
75
-
pulse 3a
-150
-
pulse 3b
100
[3]
[4]
VESD
electrostatic discharge
voltage
IEC 61000-4-2; 150 pF, 330 Ω
on pins P0_TRX_P, P0_TRX_M, P1_TRX_P,
P1_TRX_M
-8.0 +8.0
kV
[5]
[6]
on pin WAKE_IN_OUT
on pin VBAT to GND
Human Body Model (HBM)
on any pin
-8.0 +8.0
-8.0 +8.0
kV
kV
[7]
-2.0 +2.0
-6.0 +6.0
kV
kV
on pins P0_TRX_P, P0_TRX_M, P1_TRX_P,
P1_TRX_M
[8]
[9]
on pin WAKE_IN_OUT
on pin VBAT
-6.0 +6.0
-6.0 +6.0
kV
kV
Charged Device Model (CDM)
on any pin
[10]
-500 +500
V
Tamb
Tstg
ambient temperature
storage temperature
-40
-55
+125
+150
°C
°C
[1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these
values.
[2] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637.
[3] Verified by an external test house according to IEC TS 62228, Section 4.3.
[4] Tested with a common mode choke and 100 nF coupling capacitors.
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[5] Tested with 10 nF capacitor to GND and 10 kΩ in series between the capacitor and the WAKE_IN_OUT pin.
[6] Tested with 100 nF capacitor from VBAT to GND.
[7] According to AEC-Q100-002.
[8] With 10 nF capacitor to GND and 10 kΩ in series between the capacitor and the WAKE_IN_OUT pin.
[9] With 100 nF from VBAT to GND.
[10] According to AEC-Q100-011.
8 Thermal characteristics
Table 34.ꢀThermal characteristics
Symbol Parameter
Conditions
Typ
Unit
[1]
Rth(j-a)
Rth(j-c)
Ψj-top
thermal resistance from junction to ambient
HVQFN56 package; in free air
LDO disabled (LDO_MODE = 1)
LDO enabled (LDO_MODE = 0)
HVQFN56 package; in free air
LDO disabled (LDO_MODE = 1)
LDO enabled (LDO_MODE = 0)
HVQFN36 package; in free air
LDO disabled (LDO_MODE = 1)
LDO enabled (LDO_MODE = 0)
26
31
K/W
K/W
[2]
[1]
thermal resistance from junction to case
3
8
K/W
K/W
thermal characterization parameter from
junction to top of package
1
6
K/W
K/W
[1] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers( thickness: 35 μm)
and thermal via array under the exposed pad connected to the first inner copper layer.
[2] Determined using an isothermal cold plate.
9 Static characteristics
Table 35.ꢀSupply characteristics
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Battery supply: pin VBAT
VBAT
Vuvd
Vuvr
battery supply voltage
operating range
3.1
2.8
-
-
36
-
V
undervoltage detection voltage
undervoltage recovery voltage
undervoltage hysteresis voltage
battery supply current
-
V
-
3.1
-
V
Vuvhys
IBAT
15
-
100
-
mV
mA
TJA1102A; all modes except
Sleep; VBAT < 36 V; IINH = 0 μA
2.7
TJA1102AS; all modes except
Sleep; VBAT < 36 V; IINH = 0 μA
-
-
-
1.7
mA
μA
Sleep mode; Tvj ≤ 85 °C;
VBAT < 7.4 V
150
300
Sleep mode; Tvj ≤ 85 °C;
7.4 V < VBAT < 30 V
-
-
45
-
100
6.5
μA
VBAT < 40 V; IINH = 0 μA
mA
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 35.ꢀSupply characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
3.3 V analog supply: pin VDDA(3V3)
VDDA(3V3) analog supply voltage (3.3 V)
Vuvd
Parameter
Conditions
Min
Typ
Max
Unit
operating range
3.1
2.9
-
3.3
-
3.5
-
V
undervoltage detection voltage
undervoltage recovery voltage
undervoltage hysteresis voltage
analog supply current (3.3 V)
V
Vuvr
-
3.1
-
V
Vuvhys
IDDA(3V3)
50
-
80
43
mV
mA
TJA1102A; Normal/Sleep
Request modes
55
TJA1102AS; Normal/Sleep
Request modes
-
22
27
mA
Standby mode
-
-
130
4
250
50
μA
μA
Disable/Reset modes
3.3 V digital supply: pin VDDD(3V3)
VDDD(3V3) digital supply voltage (3.3 V)
Vuvd
operating range
3.1
2.9
-
3.3
-
3.5
-
V
undervoltage detection voltage
undervoltage recovery voltage
undervoltage hysteresis voltage
digital supply current (3.3 V)
V
Vuvr
-
3.1
-
V
Vuvhys
IDDD(3V3)
50
-
80
100
mV
mA
TJA1102A: Normal/Sleep
120
Request modes; LDO_MODE = 0
TJA1102AS: Normal/Sleep
Request modes; LDO_MODE = 0
-
-
-
51
5
61
8
mA
mA
mA
TJA1102A; Normal/Sleep
Request modes; LDO_MODE = 1
TJA1102AS; Normal/Sleep
2.5
4
Request modes; LDO_MODE = 1
Standby mode; LDO_MODE = 0
Disable/Reset modes
-
-
0.2
1
10
50
mA
μA
1.8 V digital supply: pin VDDD(1V8)
VDDD(1V8) digital supply voltage (1.8 V)
Vuvd
operating range; LDO_MODE = 1
LDO_MODE = 1
1.745
1.84 1.95
V
undervoltage detection voltage
undervoltage recovery voltage
undervoltage hysteresis voltage
digital supply current (1.8 V)
1.65
-
-
V
Vuvr
LDO_MODE = 1
-
-
1.745
-
V
Vuvhys
IDDD(1V8)
LDO_MODE = 1
20
-
35
95
mV
mA
[1]
[1]
TJA1102A; Normal/Sleep
Request modes; LDO_MODE = 1
115
TJA1102AS; Normal/Sleep
Request modes; LDO_MODE = 1
-
48
57
mA
V
Transmitter analog supply: pins P0_VDDA(TX) and P1_VDDA(TX)
VDDA(TX)
transmitter analog supply voltage operating range
3.1
3.3
3.5
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 35.ꢀSupply characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
27
0
Max
33
Unit
mA
μA
IDDA(TX)
transmitter analog supply current Normal/Sleep Request modes
Standby/Disable/Reset modes
-
-
50
Input/output supply: pin VDD(IO)
VDD(IO) input/output supply voltage
Vuvd
operating range
3.1
2.9
-
3.3
-
3.5
-
V
undervoltage detection voltage
undervoltage recovery voltage
undervoltage hysteresis voltage
input/output supply current
V
Vuvr
-
3.1
-
V
Vuvhys
IDD(IO)
50
-
80
10
mV
mA
[1]
TJA1102A; Normal/Sleep
Request modes; Cload on MII pins
= 15 pF
15
TJA1102AS; Normal/Sleep
Request modes; Cload on MII pins
= 15 pF
-
-
5
3
7.5
40
mA
μA
Standby/Disable modes;
no currents in pull-up resistors on
digital inputs
[1]
Reset mode; no currents in pull-
up resistors on digital inputs
-
35
80
μA
Power consumption
P
power dissipation
TJA1102A; Normal/Sleep
Request modes; LDO_MODE = 0
-
-
-
-
700
360
560
290
900
480
760
400
mW
mW
mW
mW
TJA1102AS; Normal/Sleep
Request modes; LDO_MODE = 0
TJA1102A; Normal/Sleep
Request modes; LDO_MODE = 1
TJA1102AS; Normal/Sleep
Request modes; LDO_MODE = 1
[1] Not measured in production; guaranteed by design.
Table 36.ꢀxMI interfaces characteristics
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SMI interface: pins MDC and MDIO
VIH
VIL
Ci
HIGH-level input voltage
LOW-level input voltage
input capacitance
2
-
-
-
-
-
-
V
0.8
8
V
[1]
[1]
pin MDC
pin MDIO
-
pF
pF
-
10
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 36.ꢀxMI interfaces characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
pin MDIO; IOH = -4 mA
VDD(IO)
- 0.4
-
-
V
VOL
IIH
LOW-level output voltage
HIGH-level input current
LOW-level input current
pin MDIO; IOL = 4 mA
VIH = VDD(IO)
-
-
0.4
20
-
V
-
-
μA
μA
μA
kΩ
kΩ
IIL
pin MDC; VIL = 0 V
pin MDIO; Vi = 0 V
on pin MDC
-20
-100
262.5
70
-
-
-20
-
Rpd
Rpu
pull-down resistance
pull-up resistance
500
100
on pin MDIO
130
(R)MII interface: pins P0_TXER, P0_TXEN, P0_TXDx, P0_TXC, P0_RXDx, P0_RXDV, P0_RXER, P0_RXC, P1_TXER,
P1_TXEN, P1_TXDx, P1_TXC, P1_RXDx, P1_RXDV, P1_RXER, P1_RXC[2]
VIH
VIL
Ci
HIGH-level input voltage
LOW-level input voltage
input capacitance
2
-
-
-
-
-
-
V
0.8
8
V
[1]
-
pF
V
VOH
HIGH-level output voltage
IOH = -4 mA
VDD(IO)
- 0.4
-
VOL
IIH
LOW-level output voltage
HIGH-level input current
LOW-level input current
pull-down resistance
IOL = 4 mA
VIH = VDD(IO)
VIL = 0 V
-
-
0.4
200
-
V
-
-
μA
μA
kΩ
IIL
-20
70
-
Rpd
on pins P0_TXER, P0_TXEN,
P0_TXDx, P1_TXER, P1_TXEN,
P1_TXDx
100
130
on pins P0_TXC and P1_TXC;
Reverse MII mode
70
100
130
kΩ
[1] Not measured in production; guaranteed by design.
[2] Pins P1_xxx only valid for TJA1102A.
Table 37.ꢀGeneral electrical characteristics
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
pins RST_N, EN
VIH
VIL
Vhys(i)
Ci
HIGH-level input voltage
LOW-level input voltage
input hysteresis voltage
input capacitance
2
-
-
V
-
-
0.8
-
V
0.36
0.5
V
[1]
-
-
-
-
8
pF
μA
μA
IIH
HIGH-level input current
LOW-level input current
at pin RST_N; VIH = VDD(IO)
at pin EN; VIL = 0 V
-
20
-
IIL
-20
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 37.ꢀGeneral electrical characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Rpd
Parameter
Conditions
on pin EN
Min
70
Typ
100
100
Max
130
130
Unit
kΩ
pull-down resistance
pull-up resistance
Rpu
on pin RST_N
70
kΩ
pin INT_N
VOL
LOW-level output voltage
IOL = 2 mA
-
-
0.4
-
V
pin SEL_1V8
VIH
HIGH-level input voltage
LOW-level input voltage
input hysteresis voltage
0.7 ×
-
-
-
V
V
V
VDD(IO)
VIL
-
0.3 ×
VDD(IO)
Vhys(i)
0.1 ×
-
VDD(IO)
IIL
LOW-level input current
pull-down resistance
VIL = 0 V
-5
-
+5
μA
kΩ
Rpd
on pin SEL_1V8
70
100
130
pin CLK_IN_OUT
VIH
HIGH-level input voltage
0.7 ×
-
-
-
-
-
V
V
V
V
VDD(IO)
VIL
LOW-level input voltage
input hysteresis voltage
HIGH-level output voltage
-
0.3 ×
VDD(IO)
Vhys(i)
0.1 ×
-
VDD(IO)
VOH
CLK_MODE = 01; IOH = -4 mA
VDD(IO)
- 0.4
-
VOL
IIL
LOW-level output voltage
LOW-level input current
pull-down resistance
CLK_MODE = 01; IOL = 4 mA
CLK_MODE = 00 or 11; VIL = 0 V
CLK_MODE = 00 or 11
-
-
0.4
+5
V
-5
-
μA
kΩ
Rpd
70
100
130
pins P0_RXD[3:0], P0_RXER, P0_RXDV, P1_RXD[3:0], P1_RXER, P1_RXDV during pin strapping[2]
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
2
-
-
-
-
V
V
0.8
pin WAKE_IN_OUT
VIH HIGH-level input voltage
CONFIG_WAKE = 0 (see Table
29)
2.8
-
-
4.1
V
V
CONFIG_WAKE = 1
0.44 ×
VDD(IO)
0.64 ×
VDD(IO)
VIL
LOW-level input voltage
input hysteresis voltage
CONFIG_WAKE = 0
CONFIG_WAKE = 1
2.4
-
-
3.75
V
V
0.38 ×
VDD(IO)
0.55 ×
VDD(IO)
Vhys(i)
CONFIG_WAKE = 0
0.25
-
0.8
V
TJA1102A
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Product data sheet
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 37.ꢀGeneral electrical characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CONFIG_WAKE = 1
0.025 × -
VDD(IO)
0.2 ×
V
VDD(IO)
Ii
input current
-5
-
-
+5
μA
V
VOH
HIGH-level output voltage
all modes except Sleep and
Power-off; IWAKE_IN_OUT = 0 mA
VBAT
0.8
-
VBAT
IOL
LOW-level output current
all modes except Sleep, Power-
off; VWAKE_IN_OUT = 0 V
-30
-
-
mA
pin INH
VOH
HIGH-level output voltage
LOW-level output current
leakage current
all modes except Sleep, Power-
off; IINH = -1 mA
VBAT - 1 -
VBAT
-2
V
IOL
all modes except Sleep, Power-
off; VINH = 0 V
-15
-5
-7
mA
μA
IL
Sleep, Power-off modes
-
+5
pins XI, XO
Ci
[1]
[1]
input capacitance
pin XI
-
3.5
2
-
pF
pin XO
-
-
pF
gm(DC)
DC transconductance
Normal, Sleep Request modes;
MII_MODE = 00, 01 or 11
13.3
25
47
mA/V
Transmitter test results: pins P0_TRX_M, P0_TRX_P, P1_TRX_M, P1_TRX_P[3]
[1]
Vdroop/VM
droop voltage to peak voltage
ratio
100BASE-T1 test mode 1; with
respect to initial peak value
-45
-
-
-
+45
15
%
[1]
[1]
Vdist(M)
PSDM
peak distortion voltage
100BASE-T1 test mode 4
100BASE-T1 test mode 5
f = 1 MHz
mV
power spectral density mask
-70.9
-75.8
-89.2
-
-
-
-
-
-63.3
-64.8
-68.5
-76.5
dBm/
Hz
f = 20 MHz
dBm/
Hz
f = 40 MHz
dBm/
Hz
f = 57 MHz to 200 MHz
dBm/
Hz
Transmitter output amplitude: pins P0_TRX_M, P0_TRX_P, P1_TRX_M, P1_TRX_P[2][3]
VoM(TX)
Rterm
transmitter peak output voltage
termination resistance
-
1
-
V
[4]
on each pin; Normal, Sleep
Request modes; LINK_
CONTROL = 1
47.5
50
52.5
Ω
Temperature protection
Tj(sd)
shutdown junction temperature
180
-
200
°C
TJA1102A
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Product data sheet
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 37.ꢀGeneral electrical characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tj(sd)rel
release shutdown junction
temperature
147
-
167
°C
Tj(warn)
warning junction temperature
155
147
-
-
175
167
°C
°C
Tj(warn)rel
release warning junction
temperature
Tj(warn)hys
warning junction temperature
hysteresis
2
8
-
°C
[1] Not measured in production; guaranteed by design.
[2] Pins P1_xxx only valid for TJA1102A.
[3] Test carried out with external common mode choke and coupling capacitors connected.
[4] Includes the influence of the nominal series resistance of an external common mode choke and 1 kΩ parallel resistors of the common-mode termination
circuit.
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
10 Dynamic characteristics
Table 38.ꢀDynamic characteristics
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
MII transmit timing (see Figure 15); MII_DRIVER = 0 (standard output driver strength)[1]
Tclk
δ
clock period
pin TXC
-
40
-
-
ns
%
duty cycle
pin TXC
35
14
14
65
-
tWH
tWL
tsu
pulse width HIGH
pulse width LOW
set-up time
pin TXC
20
20
ns
ns
pin TXC
-
TXC to TXD[3:0], TXER, TXEN
MII
10
10
-
-
-
-
ns
ns
Reverse MII
TXC to TXD[3:0], TXEN, TXER
MII
th
hold time
0
-
-
-
-
ns
ns
Reverse MII
10
MII receive timing (see Figure 16); MII_DRIVER = 0 (standard output driver strength)[1]
Tclk
δ
clock period
pin RXC
-
40
-
-
ns
%
duty cycle
pin RXC
35
14
14
65
-
tWH
tWL
td
pulse width HIGH
pulse width LOW
delay time
pin RXC
20
20
ns
ns
pin RXC
-
RXC to RXD[3:0], RXDV, RXER
MII
15
0
-
-
25
25
ns
ns
Reverse MII
RMII transmit and receive timing (see Figure 17 and Figure 18); MII_DRIVER = 0 (standard output driver strength)[1]
Tclk
δ
clock period
duty cycle
pin REF_CLK
-
20
-
-
ns
%
pin REF_CLK
35
7
7
4
2
4
65
-
tWH
tWL
tsu
th
pulse width HIGH
pulse width LOW
set-up time
pin REF_CLK
10
10
-
ns
ns
ns
ns
ns
pin REF_CLK
-
REF_CLK to TXD[1:0], TXEN, TXER
REF_CLK to TXD[1:0], TXEN, TXER
REF_CLK to RXD[1:0], RXER, CRSDV
-
hold time
-
-
td
delay time
-
13
(R)MII interface timing[1]
tf
fall time[2]
MII: RXD[3:0], RXDV, RXER
MII_DRIVER = 0; CL = 15 pF
MII_DRIVER = 1; CL = 7.5 pF
MII: TXC, RXC; CL = 15 pF
RMII: RXD[1:0], CRSDV, RXER
1.3
2
-
-
-
5
ns
ns
ns
7.7
5
1.3
TJA1102A
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 38.ꢀDynamic characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
MII_DRIVER = 0; CL = 15 pF
Min
0.7
0.9
0.7
Typ
Max Unit
-
-
-
2.5
3.4
2.5
ns
ns
ns
MII_DRIVER = 1; CL = 7.5 pF
RMII: REF_CLK; CL = 15 pF
MII: RXD[3:0], RXDV, RXER
MII_DRIVER = 0; CL = 15 pF
MII_DRIVER = 1; CL = 7.5 pF
MII: TXC, RXC; CL = 15 pF
RMII: RXD[1:0], CRSDV, RXER
MII_DRIVER = 0; CL = 15 pF
MII_DRIVER = 1; CL = 7.5 pF
RMII: REF_CLK; CL = 15 pF
tr
rise time[3]
1.3
2
-
-
-
5
ns
ns
ns
7.7
5
1.3
0.7
0.9
0.7
-
-
-
2.5
3.4
2.5
ns
ns
ns
SMI timing (see Figure 19)[1]
Tclk(MDC)
tWH(MDC)
tWL(MDC)
tsu(MDIO)
th(MDIO)
MDC clock period
MDC pulse width HIGH
MDC pulse width LOW
MDIO set-up time
400
160
160
10
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
-
to rising edge on MDC
-
MDIO hold time
from rising edge on MDC
10
-
td(MDC-MDIO) delay time from MDC to MDIO
WAKE timing; pin WAKE_IN_OUT[1]
from rising edge on MDC; read from
PHY
0
300
tdet(wake)
wake-up detection time
LOC_WU_TIM = 00
LOC_WU_TIM = 01
LOC_WU_TIM = 10
LOC_WU_TIM = 11
LOC_WU_TIM = 00
LOC_WU_TIM = 01
LOC_WU_TIM = 10
LOC_WU_TIM = 11
10
-
-
-
-
-
-
-
-
2
20
ms
μs
μs
μs
ms
250
100
20
500
200
40
tp
pulse duration
20
40
500
200
40
1000 μs
400
80
μs
μs
μs
ton
toff
turn-on time
turn-off time
RL = 100 kΩ; CL = 50 pF; VWAKE_IN_OUT
= 2 V
0
50
RL = 100 kΩ; CL = 50 pF; VWAKE_IN_OUT
= 2 V
5
50
65
μs
INH timing[1]; pin INH
ton turn-on time
toff turn-off time
RL = 100 kΩ; CL = 50 pF; Vth(INH) = 2 V
RL = 100 kΩ; CL = 50 pF; Vth(INH) = 2 V
0
5
2
50
65
μs
μs
50
TJA1102A
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Product data sheet
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 38.ꢀDynamic characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
interrupt timing[1]; pin INT_N
ton
toff
turn-on time
turn-off time
Rpu = 10 kΩ; CL = 15 pF
Rpu = 10 kΩ; CL = 15 pF
8
8
-
-
20
20
μs
μs
PCS-RX timeout timing
[4]
tto(PCS-RX)
PCS-RX time-out time
Normal and Sleep Request modes
JUMBO_ENABLE = 0
-
-
1.1
2.2
-
-
ms
ms
JUMBO_ENABLE = 1
Cable test timing
tto(cbl_tst)
cable test time-out time
Normal mode; CABLE_TEST = 1
-
100
-
μs
pins RST_N, EN[1]
tdet(rst)
reset detection time
on pin RSTN;
5
5
-
-
20
20
μs
μs
Vuvd(VDDIO) < VDD(IO) ≤ 3.5 V
tdet(EN)
detection time on pin EN
Vuvd(VDDIO) < VDD(IO) ≤ 3.5 V
Transmitter test results
tjit(RMS)
RMS jitter time
Master mode
-
-
-
-
50
ps
ps
[1]
[5]
Slave mode (with link); SLAVE_
JITTER_TEST = 1
150
Undervoltage detection[1]
tdet(uv)
undervoltage detection time
on pin VBAT; VBAT = 2.7 V
on pin VDDA(3V3); VDDA(3V3) = 2.8 V
on pin VDDD(3V3); VDDD(3V3) = 2.8 V
on pin VDDD(1V8)
0
-
-
-
-
-
-
-
-
-
-
30
30
30
30
30
30
30
30
30
670
μs
μs
μs
μs
μs
μs
μs
μs
μs
ms
2
2
2
VDD(IO) = 2.8 V
2
trec(uv)
undervoltage recovery time
on pin VDDA(3V3); VDDA(3V3) = 3.2 V
on pin VDDD(3V3); VDDD(3V3) = 3.2 V
on pin VDDD(1V8)
2
2
2
on pin VDD(IO); VDD(IO) = 3.2 V
2
tto(uvd)
undervoltage detection time-out
time
for transition from Standby to Sleep
mode (see Section 6.9.1)
300
General timing parameters[1]
ts(pon)
power-on settling time
from power-on to Standby mode
from Standby mode to Normal mode
SLEEP_REQUEST_TO = 00
SLEEP_REQUEST_TO = 01
SLEEP_REQUEST_TO = 10
-
-
-
-
-
-
2
ms
ms
μs
tinit(PHY)
tto(req)sleep
PHY initialization time
-
2
sleep request time-out time
360
900
3.6
500
1150 μs
4.4 ms
TJA1102A
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Product data sheet
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Table 38.ꢀDynamic characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
14.4
180
450
1.8
7.2
-
Typ
Max Unit
SLEEP_REQUEST_TO = 11
SLEEP_REQUEST_TO = 00
SLEEP_REQUEST_TO = 01
SLEEP_REQUEST_TO = 10
SLEEP_REQUEST_TO = 11
-
-
-
-
-
-
17.6 ms
tto(ack)sleep
sleep acknowledge time-out time
250
575
2.2
8.8
0.7
μs
μs
ms
ms
ms
[6]
tdet(PHY)
tto(pd)autn
tPD
PHY detection time
on bus pins P0_TRX_P, P0_TRX_M,
P1_TRX_P and P1_TRX_M
autonomous power-down time-out Normal mode; AUTO_PWD = 1
time
1
-
2
s
propagation delay
from MII to MDI; Normal mode
from MDI to MII; Normal mode
from RMII to MDI; Normal mode
from MDI to RMII; Normal mode
140
760
190
700
0.7
-
300
920
540
ns
ns
ns
-
-
-
1070 ns
1.3 ms
tw(wake)
wake-up pulse width
Normal mode; no active link; wake-up
forwarding
1.0
[1] Not measured in production; guaranteed by design.
[2] From 2 V to 0.8 V.
[3] From 0.8 V to 2 V.
[4] rcv_max_timer in the IEEE specificatio [1].
[5] Measured at the P0_RXER pin, representing the transmit clock (TX_CLK) of P1, or measured at the P1_RXER pin, representing the transmit clock of P0.
[6] Pins P1_xxx only valid for TJA1102A.
T
t
t
WL(TXC)
clk(TXC)
WH(TXC)
TXC
t
t
t
t
h(MII)
su(MII)
su(MII)
h(MII)
TXEN
TXD[3:0]
TXER
aaa-038936
Figure 15.ꢀMII transmit timing diagram
TJA1102A
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Product data sheet
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
T
t
t
WL(RXC)
clk(RXC)
WH(RXC)
RXC
t
t
d(MIIrx)
d(MIIrx)
RXDV
t
t
d(MIIrx)
d(MIIrx)
RXD[3:0]
RXER
aaa-038937
Figure 16.ꢀMII receive timing diagram
t
t
T
WH(REF_CLK) WL(REF_CLK)
clk(REF_CLK)
REF_CLK
t
t
t
t
h(RMII)
su(RMII)
h(RMII)
su(RMII)
TXEN
TXD[1:0]
aaa-038938
Figure 17.ꢀRMII transmit timing diagram
TJA1102A
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Product data sheet
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
T
clk(REF_CLK)
REF_CLK
t
t
d(RMIIrx)
d(RMIIrx)
CRSDV
RXER
RXD[1:0]
aaa-038939
Figure 18.ꢀRMII receive timing diagram
t
t
WL(MDC)
T
WH(MDC)
clk(MDC)
MDC
t
t
d(MDC-MDIO)
d(MDC-MDIO)
MDIO
(Data-out)
t
t
h(MDIO)
su(MDIO)
MDIO
(Data-in)
aaa-038940
Figure 19.ꢀSMI timing diagram
11 Application information
The MDI circuit used for each PHY port is shown in Figure 20. The common mode
termination depends on OEM requirements and might vary, depending on the application.
The common mode choke is expected to be compliant with the OPEN Alliance CMC
specification. The 100 nF coupling capacitors should have a voltage range ≥ 50 V with
10 % (max) tolerance.
The TJA1102A provides an ESD robustness of ±6 kV according to IEC61000-4-2 and
HBM at the IC pins. With CMC and coupling capacitors, it is able to withstand ≥ ±8 kV for
IEC 61000-4-2 on the connector pins.
TJA1102A
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Product data sheet
Rev. 1 — 7 June 2021
59 / 67
NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
common
mode choke
100 nF
TRX_P
TRX_M
BI_DA+
PHY
BI_DA-
200 µH
according to
OPEN Alliance CMC Spec
100 nF
1 kΩ
1 kΩ
100 kΩ
4.7 nF
optional
according to OPEN Alliance
System Implementation Spec
aaa-022043
Figure 20.ꢀMDI circuit diagram
Further information can be found in the TJA1102A application hints [2].
12 Package information
The TJA1102A comes in the HVQFN-56 package as shown in Figure 21. Measuring
just 64 mm2 with a pitch of 0.5 mm, it is particularly suited to PCB space-constrained
applications, such as an integrated IP camera module. The package features wettable
sides/flanks to allow for optical inspection of the soldering process. The exposed die pad
shown in the package diagram must be connected to ground.
TJA1102A
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Product data sheet
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NXP Semiconductors
TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
13 Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
SOT684-13
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
v
w
C
C
A B
C
b
e
1/2 e
y
1
y
C
b
1
L
15
28
29
14
K
e
E
e
2
h
1/2 e
1
42
terminal 1
index area
56
43
X
K
D
h
0
5
10 mm
scale
Dimensions (mm are the original dimensions)
(1)
(1)
(1)
Unit
A
A
b
b
c
D
D
h
E
E
e
e
1
e
2
L
K
v
w
y
y
1
1
1
h
max 1.00 0.05 0.30 0.32
nom 0.85 0.02 0.25 0.27
min 0.80 0.00 0.20 0.22
8.1 5.15 8.1 5.15
8.0 5.00 8.0 5.00
7.9 4.85 7.9 4.85
0.6
0.5
0.4 0.8
mm
0.2
0.5 6.5 6.5
0.1 0.05 0.05 0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot684-13_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
- - -
JEITA
15-05-29
15-07-13
SOT684-13
Figure 21.ꢀPackage outline SOT684-13 (HVQFN56)
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14 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
14.4 Reflow soldering
Key characteristics in reflow soldering are:
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• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 22) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 39 and Table 40
Table 39.ꢀSnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
235
≥ 350
< 2.5
≥ 2.5
220
220
220
Table 40.ꢀLead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 22.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 22.ꢀTemperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15 References
[1] IEEE 802.3bw-2015 — IEEE Standard for Ethernet Amendment 1: Physical Layer Specifications and Management
Parameters for 100 Mb/s Operation over a Single Balanced Twisted Pair Cable (100BASE-
T1)
[2] AN13171
— Application note for TJA1102A 100BASE-T1 dual/single PHY for automotive Ethernet, NXP
Semiconductors
16 Revision history
Table 41.ꢀRevision history
Document ID
Release date
20210607
Data sheet status
Change notice
Supersedes
TJA1102A v.1
Product data sheet
-
-
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17 Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.2 Definitions
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP product has
been qualified for use in automotive applications. If this product is used
by customer in the development of, or for incorporation into, products or
services (a) used in safety critical applications or (b) in which failure could
lead to death, personal injury, or severe physical or environmental damage
(such products and services hereinafter referred to as “Critical Applications”),
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
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then customer makes the ultimate design decisions regarding its products
and is solely responsible for compliance with all legal, regulatory, safety,
and security related requirements concerning its products, regardless of
any information or support that may be provided by NXP. As such, customer
assumes all risk related to use of any products in Critical Applications and
NXP and its suppliers shall not be liable for any such use by customer.
Accordingly, customer will indemnify and hold NXP harmless from any
claims, liabilities, damages and associated costs and expenses (including
attorneys’ fees) that NXP may incur related to customer’s incorporation of
any product in a Critical Application.
their lifecycles to reduce the effect of these vulnerabilities on customer’s
applications and products. Customer’s responsibility also extends to other
open and/or proprietary technologies supported by NXP products for use
in customer’s applications. NXP accepts no liability for any vulnerability.
Customer should regularly check security updates from NXP and follow up
appropriately. Customer shall select products with security features that best
meet rules, regulations, and standards of the intended application and make
the ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may
be provided by NXP. NXP has a Product Security Incident Response Team
(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,
reporting, and solution release to security vulnerabilities of NXP products.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Security — Customer understands that all NXP products may be subject
to unidentified or documented vulnerabilities. Customer is responsible
for the design and operation of its applications and products throughout
NXP — wordmark and logo are trademarks of NXP B.V.
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Contents
1
2
General description ............................................ 1
6.9.6
6.9.7
6.9.8
6.9.8.1
6.9.8.2
6.9.8.3
6.10
6.11
6.11.1
6.11.2
7
8
9
10
11
12
13
14
Polarity detection ............................................. 27
Interleave detection ......................................... 27
Loopback modes ............................................. 27
Internal loopback ............................................. 27
External loopback ............................................ 28
Remote loopback .............................................28
Hardware configuration ....................................28
SMI registers ................................................... 30
Register mapping overview ............................. 30
TJA1102A registers ......................................... 31
Limiting values ..................................................46
Thermal characteristics ....................................47
Static characteristics ........................................47
Dynamic characteristics ...................................54
Application information ....................................59
Package information .........................................60
Package outline .................................................61
Soldering of SMD packages .............................62
Introduction to soldering .............................
Features and benefits .........................................1
General .............................................................. 1
Optimized for automotive use cases ..................1
Low-power mode ............................................... 2
Diagnosis ........................................................... 2
Miscellaneous .................................................... 2
Ordering information .......................................... 2
Block diagram ..................................................... 2
Pinning information ............................................ 4
TJA1102A pinning ..............................................4
TJA1102AS pinning ........................................... 8
Functional description ......................................11
System configuration ....................................... 11
Clocking scheme with MII and clock
2.1
2.2
2.3
2.4
2.5
3
4
5
5.1
5.2
6
6.1
6.1.1
provided by the switch and one of the
TJA1102A devices ...........................................12
Clocking scheme with RMII and clock
6.1.2
provided by the switch .....................................13
MII and RMII ....................................................13
MII ....................................................................14
RMII ................................................................. 15
Signaling and encoding ................................... 15
Reverse MII ..................................................... 16
System controller .............................................17
Operating modes ............................................. 17
Power-off mode ............................................... 17
Standby mode ................................................. 17
Normal mode ...................................................18
Disable mode ...................................................18
Sleep mode ..................................................... 18
Sleep Request mode .......................................19
Silent mode ......................................................19
Reset mode ..................................................... 20
Status of functional blocks in TJA1102A
14.1
14.2
14.3
14.4
15
6.2
6.2.1
6.2.2
6.2.2.1
6.2.3
Wave and reflow soldering .........................
Wave soldering ...........................................
Reflow soldering .........................................
References .........................................................64
Revision history ................................................ 64
Legal information ..............................................65
16
17
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.6
6.3.1.7
6.3.1.8
6.3.2
operating modes ..............................................20
Mode transitions .............................................. 21
Sleep and wake-up forwarding concept ...........23
Autonomous operation .....................................24
Autonomous power-down ................................24
Test modes ...................................................... 24
Test mode 1 .....................................................24
Test mode 2 .....................................................24
Test mode 3 .....................................................24
Test mode 4 .....................................................24
Test mode 5 .....................................................25
Slave jitter test .................................................25
Error diagnosis ................................................ 25
Undervoltage detection ....................................25
Cabling errors ..................................................26
Link stability .....................................................26
Link-fail counter ............................................... 26
Jabber detection .............................................. 27
6.4
6.5
6.6
6.7
6.8
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 June 2021
Document identifier: TJA1102A
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