TJA1441DT_技术文档

TJA1441

High-speed CAN transceiver

Rev. 1 — 12 August 2020

Product data sheet

1 General description

The TJA1441 is a member of the TJA144x family of transceivers that provide an interface

between a Controller Area Network (CAN) or CAN FD (Flexible Data rate) protocol

controller and the physical two-wire CAN bus. TJA144x transceivers implement the CAN

physical layer as defined in ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5, and

are fully interoperable with high-speed Classical CAN and CAN FD transceivers. All

TJA144x variants enable reliable communication in the CAN FD fast phase at data rates

up to 5 Mbit/s.

The TJA1441 is intended as a simple replacement for high-speed Classical CAN

and CAN FD transceivers, such as the TJA1051 or TJA1057 from NXP. It offers pin

compatibility and is designed to avoid changes to hardware and software design,

allowing the TJA1441 to be easily retrofitted to existing applications.

An AEC-Q100 Grade 0 variant, the TJR1441, is available for high temperature

applications, supporting operation at 150 °C ambient temperature. A variant intended for

industrial applications, the TJF1441, is also available.

1.1 TJA1441 variants

The TJA1441 comes in three variants, each available in an SO8 or HVSON8 package:

• The TJA1441A is a high-speed CAN transceiver with Normal and Silent modes and a

VIO supply pin. The VIO pin allows for direct interfacing with 3.3 V and 5 V-supplied

microcontrollers.

• The TJA1441B is a high-speed CAN transceiver with Normal and Silent modes.

• The TJA1441D is a high-speed CAN transceiver with Normal and Silent modes with a

transmitter/receiver On/Off input.

2 Features and benefits

2.1 General

• ISO 11898-2:2016, SAE J2284-1 to SAE J2284-5 and SAE J1939-14 compliant

• Standard CAN and CAN FD data bit rates up to 5 Mbit/s

• Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI)

• Qualified according to AEC-Q100 Grade 1

• Silent mode for node diagnosis and failure containment

• TJA1441A only: VIO input for interfacing with 3.3 V to 5 V microcontrollers

• TJA1441D only: dedicated input for switching to very low-current Off mode and

disengaging from the bus

• All variants are available in SO8 and leadless HVSON8 (3.0 mm x 3.0 mm) packages;

HVSON8 with improved Automated Optical Inspection (AOI) capability.

NXP Semiconductors

TJA1441

High-speed CAN transceiver

• Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)

compliant)

2.2 Predictable and fail-safe behavior

• Undervoltage detection with defined handling on all supply pins

• Full functionality guaranteed from the undervoltage detection thresholds up to the

maximum limiting voltage values

• Defined behavior below the undervoltage detection thresholds

• Transceiver disengages from the bus (high-ohmic) when the supply voltage drops

below the Off mode threshold

• Internal biasing of TXD and mode selection input pins, to enable defined fail-safe

behavior

2.3 Protection

• High ESD handling capability on the bus pins (8 kV IEC and HBM)

• Bus pins protected against transients in automotive environments

• Transmit Data (TXD) dominant time-out function

• Thermally protected

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Product data sheet

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TJA1441

High-speed CAN transceiver

3 Quick reference data

Table 1.ꢀQuick reference data

Symbol

V_CC

Parameter

Conditions

Min

Typ

-

Max Unit

supply voltage

supply current

4.5

5.5

60

7

V

I_CC

Normal mode, dominant

Normal mode, recessive

Silent mode

-

38

4

mA

μA

V

-

3

6

Off mode (TJA1441D only)

-

90

-

250

4.5

V_uvd(VCC)

undervoltage detection voltage

on pin VCC

4

V_uvhys(VCC)

undervoltage hysteresis voltage

on pin VCC

50

-

mV

V

V_{uvd(swoff)(VCC)}switch-off undervoltage detection TJA1441B/D

voltage on pin VCC

2.65

2.95

V_IO

I_IO

supply voltage on pin VIO

supply current on pin VIO

2.95

-

5.5

V

Normal mode, dominant; V_TXD= 0 V

Normal mode, recessive; V_TXD= V_IO

Silent mode; V_TXD= V_IO

-

250

150

70

-

760

460

200

2.95

µA

V

-

V_{uvd(swoff)(VIO)}switch-off undervoltage detection TJA1441A

voltage on pin VIO

2.65

V_ESD

V_CANH

V_CANL

T_vj

electrostatic discharge voltage

voltage on pin CANH

IEC 61000-4-2 on pins CANH and CANL -8

-

+8

kV

V

limiting value according to IEC 60134

-36

-40

+40

voltage on pin CANL

V

virtual junction temperature

+150 °C

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TJA1441

High-speed CAN transceiver

4 Ordering information

Table 2.ꢀOrdering information

Type number

Package

Name

SO8

Description

Version

TJA1441AT

TJA1441BT

TJA1441DT

TJA1441ATK

TJA1441BTK

TJA1441DTK

plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

HVSON8

plastic thermal enhanced very thin small outline package; no

leads; 8 terminals; body 3 × 3 × 0.85 mm

SOT782-1

5 Block diagrams

(1)

VIO

VCC

3

5

TJA1441A/B

TEMPERATURE

PROTECTION

(2)

IO CC

V

/V

7

CANH

TRANSMITTER

1

6

TIME-OUT

TXD

CANL

(2)

IO CC

V

/V

MODE

CONTROL

8

S

(2)

IO CC

V

/V

differential

receiver

MUX

AND

4

RXD

DRIVER

2

aaa-030972

GND

(1) V_IOis only available in the TJA1441A (pin 5 is not connected in the TJA1441B).

(2) V_IOin TJA1441A; V_CCin TJA1441B.

Figure 1.ꢀBlock diagram: TJA1441A/B

TJA1441

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TJA1441

High-speed CAN transceiver

VCC

3

TJA1441D

TEMPERATURE

PROTECTION

V

CC

7

CANH

TRANSMITTER

1

8

TXD

6

TIME-OUT

CANL

OFF

S_N

RXD

MODE

CONTROL

5

4

V

CC

differential

receiver

MUX

AND

DRIVER

2

aaa-030973

GND

Figure 2.ꢀBlock diagram: TJA1441D

TJA1441

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TJA1441

High-speed CAN transceiver

6 Pinning information

6.1 Pinning

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

TXD

GND

VCC

RXD

S

TXD

GND

VCC

RXD

S

TXD

GND

VCC

RXD

OFF

CANH

CANL

VIO

CANH

CANL

n.c.

CANH

CANL

S_N

aaa-030469

aaa-030470

aaa-030471

TJA1441AT: SO8

TJA1441BT: SO8

TJA1441DT: SO8

terminal 1

index area

terminal 1

index area

terminal 1

index area

TXD

GND

VCC

RXD

1

2

3

4

8

S

TXD

GND

VCC

RXD

1

2

3

4

8

S

TXD

GND

VCC

RXD

1

2

3

4

8

OFF

7

6

5

CANH

CANL

VIO

7

6

5

CANH

CANL

n.c.

7

6

5

CANH

CANL

S_N

aaa-030472

aaa-030473

aaa-030474

Transparent top view

TJA1441ATK: HVSON8

TJA1441BTK: HVSON8

TJA1441DTK: HVSON8

Figure 3.ꢀPin configuration diagrams

6.2 Pin description

Table 3.ꢀPin description

Symbol

TXD

GND^[2]

VCC

RXD

VIO

1

Type^[1]Description

I

transmit data input; inputs data (from the CAN controller) to be written to the bus lines

ground

2

G

3

P

5 V supply voltage input

4

O

receive data output; outputs data read from the bus lines (to the CAN controller).

supply voltage input for I/O level adapter in TJA1441A

not connected in TJA1441B

5

P

n.c.

-

S_N

I

Silent mode control input in TJA1441D; active-LOW

LOW-level CAN bus line

CANL

CANH

S

6

7

8

AIO

HIGH-level CAN bus line

I

Silent mode control input in TJA1441A and TJA1441B; active-HIGH

Off mode control input in TJA1441D; active-HIGH

OFF

[1] I: digital input; O: digital output; AIO: analog input/output; P: power supply; G: ground.

[2] HVSON package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground. For

enhanced thermal and electrical performance, it is also recommended to solder the exposed center pad to board ground.

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TJA1441

High-speed CAN transceiver

7 Functional description

7.1 Operating modes

The TJA1441 supports three operating modes, Normal, Silent and Off. The operating

mode is selected via pin S in the TJA1441A/B and via pins S_N and OFF in the

TJA1441D. See Table 4 and Table 5 for a description of the operating modes under

normal supply conditions. Mode changes are completed after transition time t_t(moch)

.

Table 4.ꢀOperating modes: TJA1441A/B

Mode

Inputs

Pin S

LOW

Outputs

Pin TXD

LOW

CAN driver

dominant

recessive

Pin RXD

Normal

LOW

HIGH

LOW when bus dominant

HIGH when bus recessive

LOW when bus dominant

HIGH when bus recessive

high-ohmic state

Silent

Off^[1]

HIGH

X

biased to V_CC/2

high-ohmic state

[1] Off mode is only entered when the voltage on supply pin VCC or VIO (TJA1441A) is below any undervoltage detection

threshold (see Figure 4 and Figure 5).

Table 5.ꢀOperating modes: TJA1441D

Mode

Inputs

Outputs

Pin S_N Pin OFF Pin TXD

CAN driver

dominant

recessive

Pin RXD

Normal

HIGH

LOW

HIGH

LOW

LOW when bus dominant

HIGH when bus recessive

LOW when bus dominant

HIGH when bus recessive

high-ohmic state

Silent

Off^[1]

LOW

X

LOW

HIGH

X

biased to V_CC/2

high-ohmic state

[1] Off mode is also entered when the voltage on supply pin VCC is below the undervoltage detection threshold (see

Figure 6).

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TJA1441

High-speed CAN transceiver

from any mode when

V

< V for t > t

IO

uvd(swoff)(VIO) uvd(swoff)

OFF

(CAN BIAS

= high-

ohmic)

S = LOW

AND V

> V

for t > t

CC

uvd(VCC)

uvd(swoff)(VIO)

rec(uv)

for t > t

V

CC

< V for t > t

uvd(VCC) det(uv)

AND V > V

IO

startup

V

CC

< V for t > t

uvd(VCC) det(uv)

S = HIGH

> V for t > t

AND V > V

AND V

CC

uvd(VCC)

uvd(swoff)(VIO)

rec(uv)

for t > t

IO

startup

S = LOW AND

< V for t > t )

det(uv)

SILENT

(CAN BIAS

= VCC/2)

NORMAL

(CAN BIAS

= VCC/2)

NOT(V

CC

uvd(VCC)

S = HIGH AND

NOT(V

< V

for t > t

)

det(uv)

CC

uvd(VCC)

aaa-031270

Figure 4.ꢀ TJA1441A state diagram

from any mode when

for t > t

V

CC

< V

uvd(swoff)(VCC)

uvd(swoff)

OFF

(CAN BIAS

= high-

ohmic)

S = LOW

AND V

> V

for t > t

CC

uvd(VCC)

rec(uv)

for t > t

V

CC

< V for t > t

uvd(VCC) det(uv)

AND V

> V

CC

uvd(swoff)(VCC)

startup

V

CC

< V for t > t

uvd(VCC) det(uv)

S = HIGH

> V for t > t

> V

AND V

CC

uvd(VCC)

uvd(swoff)(VCC)

rec(uv)

for t > t

AND V

CC

startup

S = LOW AND

< V for t > t )

det(uv)

SILENT

(CAN BIAS

= VCC/2)

NORMAL

(CAN BIAS

= VCC/2)

NOT(V

CC

uvd(VCC)

S = HIGH AND

< V for t > t

)

det(uv)

CC

uvd(VCC)

aaa-036910

Figure 5.ꢀ TJA1441B state diagram

TJA1441

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TJA1441

High-speed CAN transceiver

from any mode when

for t > t

V

CC

< V

uvd(swoff)(VCC)

uvd(swoff)

OFF

(CAN BIAS

= high-

ohmic)

S_N = HIGH AND OFF = LOW

AND V > V for t > t

V

CC

< V

for t > t

det(uv)

CC

uvd(VCC)

uvd(swoff)(VCC)

rec(uv)

for t > t

uvd(VCC)

AND V

> V

CC

startup

OR OFF = HIGH

V

CC

< V for t > t

uvd(VCC) det(uv)

OR OFF = HIGH

S_N = LOW AND OFF = LOW

AND V > V for t > t

CC

> V

uvd(VCC)

uvd(swoff)(VCC)

rec(uv)

for t > t

AND V

CC

startup

S_N = HIGH AND OFF = LOW AND

NOT(V < V for t > t

SILENT

(CAN BIAS

= VCC/2)

NORMAL

(CAN BIAS

= VCC/2)

)

det(uv)

CC uvd(VCC)

S_N = LOW AND OFF = LOW AND

NOT(V < V for t > t

)

det(uv)

CC uvd(VCC)

aaa-036911

Figure 6.ꢀ TJA1441D state diagram

7.1.1 Off mode

The TJA1441 switches to Off mode from any mode when the supply voltage on pin

VIO/VCC falls below the switch-off undervoltage detection threshold (V_{uvd(swoff)(VIO)}in

TJA1441A; V_{uvd(swoff)(VCC)}in TJA1441B/D) or when V_CCdrops below V_uvd(VCC). This is

the default mode when the supply is first connected.

The CAN pins and pin RXD are in a high-ohmic state in Off mode.

When the supply voltage rises above the switch-off undervoltage detection threshold,

the TJA1441 starts to boot up, triggering an initialization procedure. It switches to the

selected mode after t_startup, provided V_CC> V_uvd(VCC)

.

7.1.2 Silent mode

A HIGH level on pin S selects Silent mode in the TJA1441A and TJA1441B.

A LOW level on pins S_N and OFF selects Silent mode in the TJA1441D.

The transmitter is disabled in Silent mode, releasing the bus pins to V_CC/2. All other IC

functions, including the receiver, continue to operate as in Normal mode. Silent mode can

be used to prevent a faulty CAN controller disrupting network communications.

7.1.3 Normal mode

A LOW level on pin S selects Normal mode in the TJA1441A and TJA1441B.

A HIGH level on pin S_N and a LOW level on pin OFF selects Normal mode in the

TJA1441D.

In Normal mode, the transceiver can transmit and receive data via bus lines CANH and

CANL. Pin TXD must be HIGH at least once in Normal mode before transmission can

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TJA1441

High-speed CAN transceiver

begin. The differential receiver converts the analog data on the bus lines into digital data

on pin RXD. The slopes of the output signals on the bus lines are controlled internally

and are optimized in a way that guarantees the lowest possible EME. In recessive state,

the output voltage on the bus pins is V_CC/2.

7.1.4 Controlled Off mode (TJA1441D)

A HIGH level on pin OFF selects Off mode. In Off mode the entire transceiver is disabled,

allowing the microcontroller to save power when CAN communication is not required.

The bus pins are high-ohmic in Off mode, making the transceiver invisible to the rest of

the network.

7.1.5 Operating modes and gap-free operation

Gap-free operation guarantees defined behavior at all voltage levels. Supply voltage-

to-operating mode mapping is detailed in Figure 7 and in the state diagrams (Figure 4,

Figure 5 and Figure 6).

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TJA1441

High-speed CAN transceiver

TJA1441A

TJA1441B/D

[1]

[2][3]

[1]

[2][3]

5.5 V - 6 V

Fully functional

5.5 V - 6 V

Fully functional

[2][3]

Fully functional

OR

[2]

Fully functional and

Fully functional AND

characteristics

[4]

Off

V

operating range

CC

(4.5 V - 5.5 V)

V operating range

CC

(4.5 V - 5.5 V)

characteristics

[5]

guaranteed

Off

[2]

Fully functional OR

[6]

V

range

V

range

uvd(VCC)

[4]

Off

2.95 V - 4 V

range

Off

[4]

-0.3 V - 4 V

Off

V

Off

uvd(swoff)(VCC)

-0.3 V - 2.65 V

Off

Voltage range on VIO

[1] 6 V is the IEC 60134 Absolute Maximum Rating (AMR) for VCC and VIO (see Limiting values table). Above the AMR, irreversible changes in

characteristics, functionality or performance may occur. Returning from above AMR to the operating range, datasheet characteristics and

functionality cannot be guaranteed.

[2] Target transceiver functionality as described in this datasheet is applicable.

[3] Prolonged operation of the device outside the operating range may impact reliability over lifetime. Returning to the operating range, datasheet

characteristics are guaranteed provided the AMR has not been exceeded.

For a given value of V

(and V in TJA1441A), a specific device will be in a single defined state determined by its undervoltage detection

[4]

CC

, V

IO

thresholds (V

and V

). The actual thresholds can vary between devices (within the ranges specified

uvd(swoff)(VCC)

uvd(VCC) uvd(swoff)(VIO)

in this data sheet). To guarantee the device will be in a specific state, V and V

must be either above the maximum or below the

IO

CC

minimum thresholds specified for these undervoltage detection ranges.

Datasheet characteristics are guaranteed within the V

characteristics tables.

and V operating ranges. Exceptions are described in the Static and Dynamic

[5]

CC

IO

[6] The following applies to TJA1441A:

- The device is fully functional when both V and V are above the undervoltage threshold.

CC IO

- If V

or V falls below any undervoltage threshold, the device switches to Off mode.

CC

IO

aaa-038561

Figure 7.ꢀSupply voltage ranges and gap-free operation

7.2 Fail-safe features

7.2.1 TXD dominant time-out function

A 'TXD dominant time-out' timer is started when pin TXD is set LOW. If the LOW state on

this pin persists for longer than t_to(dom)TXD, the transmitter is disabled, releasing the bus

lines to recessive state. This function prevents a hardware and/or software application

failure from driving the bus lines to a permanent dominant state (blocking all network

communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.

7.2.2 Internal biasing of TXD and mode input pins

Pins TXD, S, S_N and OFF have internal pull-ups to V_CC/V_IOto ensure a safe, defined

state in case one or more of these pins is left open or become floating. Pull-up resistors

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TJA1441

High-speed CAN transceiver

are active on these pins in all states; they should be held at the V_CC/V_IOlevel in Silent (or

Off in TJA1441D) mode to minimize supply current.

7.2.3 Undervoltage detection on pins VCC and VIO

If V_CCor V_IOdrops below the undervoltage detection threshold (V_uvd(VCC)or V_{uvd(swoff)VCC}

for V_CC; V_{uvd(swoff)VIO}for V_IO) the transceiver switches to Off mode and disengages from

the bus (zero load; bus pins high-ohmic) until the supply voltage has recovered. If Normal

mode is selected, the output drivers are enabled once both V_CCand V_IOare again within

their operating ranges and TXD has been reset to HIGH.

7.2.4 Overtemperature protection

The device is protected against overtemperature conditions. If the junction temperature

exceeds the shutdown junction temperature, T_j(sd), the CAN bus drivers are disabled.

When the junction temperature drops below T_j(sd)rel, the CAN bus drivers recover once

TXD has been reset to HIGH and Normal mode is selected (waiting for TXD to go HIGH

prevents output driver oscillation due to small variations in temperature).

7.2.5 I/O levels

Pin VIO of the TJA1441A should be connected to the microcontroller supply voltage (see

Figure 11). This adjusts the signal levels on pins TXD, RXD and S to the I/O levels of the

microcontroller, allowing for direct interfacing without additional glue logic.

All I/O levels are related to V_CCin the TJA1441B/D and are, therefore, compatible with

5 V microcontrollers. Spurious signals from the microcontroller on pins S, S_N and OFF

are filtered out with a filter time of t_fltr(IO)

.

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TJA1441

High-speed CAN transceiver

8 Limiting values

Table 6.ꢀLimiting values

In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are referenced to pin GND, unless

otherwise specified.

Symbol

Parameter

Conditions

Min Max

Unit

V_x

voltage on pin x^[1]

on pins VCC, VIO (TJA1441A), TXD, S

(TJA1441A/B), OFF (TJA1441D), S_N

(TJA1441D)

-0.3 +6

V

-

+7^[2]

on pins CANH, CANL

on pins RXD

-36

+40

V

TJA1441A

-0.3 V_IO+0.3^[3]

-0.3 V_CC+0.3^[3]

V

TJA1441B, TJA1441D

V_(CANH-CANL)voltage between pin CANH

and pin CANL

-40

+40

[4]

V_trt

transient voltage

on pins CANH, CANL

pulse 1

-100

-

V

pulse 2a

-

+75

-

pulse 3a

-150

-

pulse 3b

+100

[5]

V_ESD

electrostatic discharge

voltage

IEC 61000-4-2 (150 pF, 330 Ω discharge circuit)

on pins CANH, CANL

Human Body Model (HBM)

on any pin

-8

+8

kV

[6]

[7]

[8]

-4

-8

+4

+8

kV

on pins CANH, CANL

Charged Device Model (CDM)

on corner pins

-750 +750

-500 +500

V

on any other pin

V

[9]

T_vj

virtual junction temperature

storage temperature

-40

-55

+150

°C

T_stg

[1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these

values.

[2] The device can withstand voltages between 6 V and 7 V for a total of 20 s over the product lifetime.

[3] Subject to the qualifications detailed in Table notes 1 and 2 above for pins VCC, VIO, TXD, S, OFF, and S_N.

[4] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637.

[5] Verified by an external test house according to IEC TS 62228, Section 4.3.

[6] According to AEC-Q100-002.

[7] Pins stressed to reference group containing all ground and supply pins, emulating the application circuits (Figure 11, Figure 12 and Figure 13). HBM pulse

as specified in AEC-Q100-002 used.

[8] According to AEC-Q100-011.

[9] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T_vj= T_amb+ P # R_th(j-a), where R_th(j-a)is a fixed value used in

the calculation of T_vj. The rating for T_vjlimits the allowable combinations of power dissipation (P) and ambient temperature (T_amb).

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NXP Semiconductors

TJA1441

High-speed CAN transceiver

9 Thermal characteristics

Table 7.ꢀThermal characteristics

Value determined for free convection conditions on a JEDEC 2S2P board.

Symbol

Parameter

Conditions^[1]

SO8

Typ

96

57

19

9

Unit

K/W

R_th(j-a)

thermal resistance from junction to ambient

HVSON8

SO8

R_th(j-c)

Ѱ_j-top

thermal resistance from junction to case^[2]

thermal characterization parameter from junction to top of package

HVSON8

9

[1] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm)

and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 μm).

[2] Case temperature refers to the center of the heatsink at the bottom of the package.

10 Static characteristics

Table 8.ꢀStatic characteristics

T_vj= -40 °C to +150 °C; V_CC= 4.5 V to 5.5 V; V_IO= 2.95 V to 5.5 V (TJA1441A); R_L= 60 Ω; unless specified otherwise; all

voltages are defined with respect to ground; positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply; pin VCC

V_CC

V_uvd

supply voltage

4.5

4

-

5.5

4.5

V

[2]

undervoltage detection

voltage

V_uvhys

V_uvd(swoff)

I_CC

undervoltage hysteresis

voltage

50

-

mV

V

switch-off undervoltage

detection voltage

TJA1441B/D

Normal mode

2.65

2.95

supply current

dominant; V_TXD= 0 V; t < t_to(dom)TXD

-

38

-

60

mA

dominant; V_TXD= 0 V;

125

short circuit on bus lines;

-3 V < (V_CANH= V_CANL) < +40 V

[3]

recessive; V_TXD= V_IO

-

4

7

mA

μA

[3]

Silent mode; V_TXD= V_IO

3

6

Off mode; (TJA1441D only)

90

250

I/O level adapter supply; pin VIO (TJA1441A)

V_IO

supply voltage

2.95

2.65

-

5.5

V

V_uvd(swoff)

switch-off undervoltage

detection voltage

2.95

I_IO

supply current

Normal mode; dominant; V_TXD= 0 V

Normal mode; recessive; V_TXD= V_IO

Silent mode; V_TXD= V_IO

-

250

150

70

760

460

200

µA

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TJA1441

High-speed CAN transceiver

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CAN transmit data input; pin TXD

[3]

V_IH

HIGH-level input voltage

LOW-level input voltage

0.7V_IO

-

V

[3]

V_IL

-

0.3V_IO

V

V_hys(TXD)

hysteresis voltage on pin

TXD

50

-

mV

R_pu

C_i

pull-up resistance

input capacitance

20

-

80

10

kΩ

pF

[4]

CAN receive data output; pin RXD

I_OH

I_OL

HIGH-level output current

LOW-level output current

V_RXD= V_IO^[3]- 0.4 V

V_RXD= 0.4 V

-10

+1

-

-1

mA

+10

Silent control inputs; pins S (TJA1441A/B), S_N (TJA1441D) and OFF (TJA1441D)

[3]

V_IH

V_IL

V_hys

R_pu

C_i

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

0.7V_IO

-

V

[3]

-

0.3V_IO

V

50

20

-

mV

kΩ

pF

pull-up resistance

80

10

[4]

input capacitance

Bus lines; pins CANH and CANL

V_O(dom)

dominant output voltage

V_TXD= 0 V; t < t_to(dom)TXD; V_CC≥ 4.75 V

pin CANH; R_L= 50 Ω to 65 Ω

2.75

0.5

3.5

1.5

-

4.5

V

pin CANL; R_L= 50 Ω to 65 Ω

2.25

[4]

[5]

V_TXsym

V_cm(step)

V_cm(p-p)

V_O(dif)

transmitter voltage

symmetry

V_TXsym= V_CANH+ V_CANL

;

0.9V_CC

1.1V_CC

+150

C_SPLIT= 4.7 nF;

f_TXD= 250 kHz, 1 MHz or 2.5 MHz

[4]

[5]

[6]

common mode voltage step

-150

-

mV

[4]

[5]

[6]

peak-to-peak common mode

voltage

-300

+300

differential output voltage

dominant; Normal mode; V_TXD= 0 V;

t < t_to(dom)TXD; V_CC≥ 4.75 V

R_L= 50 Ω to 65 Ω

R_L= 45 Ω to 70 Ω

1.5

1.4

1.5

-

3

V

3.3

5

[4]

R_L= 2240 Ω

recessive; no load

[3]

Normal or Silent mode; V_TXD= V_IO

-50

2

-

+50

3

mV

V

V_O(rec)

recessive output voltage

Normal or Silent mode; V_TXD= V_IO^[3]; no

load

2.5

V_th(RX)dif

differential receiver

threshold voltage

Normal or Silent mode;

-12 V ≤ V_CANH≤ +12 V;

-12 V ≤ V_CANL≤ +12 V

0.5

-

0.9

V

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Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_rec(RX)

receiver recessive voltage

Normal or Silent mode;

-12 V ≤ V_CANH≤ +12 V;

-12 V ≤ V_CANL≤ +12 V

-4

-

0.5

V

V_dom(RX)

receiver dominant voltage

Normal or Silent mode;

-12 V ≤ V_CANH≤ +12 V;

-12 V ≤ V_CANL≤ +12 V

0.9

50

-

9

-

V

V_hys(RX)dif

differential receiver

hysteresis voltage

Normal or Silent mode;

-12 V ≤ V_CANH≤ +12 V;

-12 V ≤ V_CANL≤ +12 V

mV

I_O(sc)

short-circuit output current

-15 V ≤ V_CANH≤ +40 V;

-15 V ≤ V_CANL≤ +40 V

-

115

+3

mA

[3]

I_O(sc)rec

recessive short-circuit output Normal mode; V_TXD= V_IO

;

-3

current

-27 V ≤ V_CANH≤ +32 V;

-27 V ≤ V_CANL≤ +32 V

I_L

leakage current

input resistance

input resistance deviation

V_CC= V_IO= 0 V or pins shorted to GND

via 47 KΩ; V_CANH= V_CANL= 5 V;

-10

25

-

+10

50

µA

kΩ

R_i

-2 V ≤ V_CANL≤ +7 V;

-2 V ≤ V_CANH≤ +7 V

40

ΔR_i

0 V ≤ V_CANL≤ +5 V; 0 V ≤ V_CANH≤ +5 V

-3

-

+3

%

R_i(dif)

differential input resistance -2 V ≤ V_CANL≤ +7 V;

-2 V ≤ V_CANH≤ +7 V

50

80

100

kΩ

[4]

C_i(cm)

C_i(dif)

common-mode input

capacitance

-

20

10

pF

differential input capacitance

Temperature detection

T_j(sd)

shutdown junction

temperature

180

175

-

200

195

°C

T_j(sd)rel

release shutdown junction

temperature

[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified

temperature and power supply voltage range.

[2] Undervoltage is detected between min and max values. Undervoltage is guaranteed to be detected below min value and guaranteed not to be detected

above max value.

[3] V_CCin TJA1441B/D

[4] Not tested in production; guaranteed by design.

[5] The test circuit used to measure the bus output voltage symmetry (which includes C_SPLIT) is shown in Figure 15

[6] See Figure 10

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11 Dynamic characteristics

Table 9.ꢀDynamic characteristics

T_vj= −40 °C to +150 °C; V_CC= 4.5 V to 5.5 V; V_IO= 2.95 V to 5.5 V (TJA1441A); R_L= 60 Ω; unless specified otherwise. All

voltages are defined with respect to ground.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max Unit

CAN timing characteristics; t_bit(TXD)≥ 200 ns; see Figure 8, Figure 9 and Figure 14

t_{d(TXD-busdom)}delay time from TXD to bus dominant

t_{d(TXD-busrec)}delay time from TXD to bus recessive

t_{d(busdom-RXD)}delay time from bus dominant to RXD

t_{d(busrec-RXD)}delay time from bus recessive to RXD

Normal mode

-

102.5 ns

127.5 ns

Normal mode

Normal or Silent mode

t_d(TXDL-RXDL)delay time from TXD LOW to RXD LOW Normal mode

t_d(TXDH-RXDH)delay time from TXD HIGH to RXD HIGH Normal mode

CAN FD timing characteristics; see Figure 9 and Figure 14

230

ns

t_bit(bus)

t_bit(RXD)

Δt_rec

transmitted recessive bit width

t_bit(TXD)= 500 ns

t_bit(TXD)= 200 ns

t_bit(TXD)= 500 ns

t_bit(TXD)= 200 ns

t_bit(TXD)= 500 ns

t_bit(TXD)= 200 ns

435

155

400

120

-65

-

530

210

550

220

40

ns

bit time on pin RXD

receiver timing symmetry

-45

15

Dominant time-out time; pin TXD

[2]

[3]

t_to(dom)TXD

TXD dominant time-out time

V_TXD= 0 V; Normal mode

0.8

-

9

ms

Mode transitions

[2]

t_t(moch)

t_startup

IO filter; pins S (TJA1441A/B), S_N (TJA1441D) and OFF (TJA1441D)

t_fltr(IO)I/O filter time

Undervoltage detection; see Figure 4, Figure 5 and Figure 6

mode change transition time

-

50

1

µs

start-up time

ms

[4]

1

-

5

µs

[2]

t_det(uv)

undervoltage detection time

on pin VCC

-

30

50

µs

t_uvd(swoff)

switch-off undervoltage detection time

on pin VCC; TJA1441B/D

on pin VIO; TJA1441A

on pin VCC

t_rec(uv)

undervoltage recovery time

[1] All parameters are guaranteed over the junction temperature range by design. Factory testing uses correlated test conditions to cover the specified

temperature and power supply voltage ranges.

[2] Not tested in production; guaranteed by design.

[3] Time-out occurs between the min and max values. Time-out is guaranteed not to occur below the min value; time-out is guaranteed to occur above the

max value.

[4] Pulses shorter than the min value are guaranteed to be filtered out; pulses longer than the max value are guaranteed to be processed.

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High-speed CAN transceiver

HIGH

LOW

70 %

TXD

30 %

CANH

CANL

dominant

0.9 V

0.5 V

V

O(dif)

recessive

HIGH

70 %

RXD

30 %

LOW

t

d(TXD-busrec)

d(TXD-busdom)

t

d(busdom-RXD)

d(busrec-RXD)

aaa-029311

Figure 8.ꢀCAN transceiver timing diagram

70 %

TXD

30 %

t

5 x t

d(TXDL-RXDL)

bit(TXD)

t

bit(TXD)

0.9 V

V

O(dif)

0.5 V

t

bit(bus)

70 %

RXD

30 %

t

d(TXDH-RXDH)

t

bit(RXD)

aaa-029312

Figure 9.ꢀCAN FD timing definitions according to ISO 11898-2:2016

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CANH

CANL

V

cm(step)

V

CANH

+ V

CANL

V

cm(p-p)

aaa-037830

Figure 10.ꢀCAN bus common-mode voltage

12 Application information

12.1 Application diagrams

BAT

3.3 V

(1)

on/off control

(1)

5 V

VCC

VIO

CANH

CANL

VDD

Pxx

Pyy

TX0

RX0

S

µC + CAN

CONTROLLER

TJA1441A

TXD

RXD

GND

aaa-030773

(1) Optional, depends on regulator.

Figure 11.ꢀTypical TJA1441A application with a 3.3 V microcontroller

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TJA1441

High-speed CAN transceiver

BAT

5 V

(1)

VCC

VDD

CANH

CANL

S

Pxx

TJA1441B

CONTROLLER

GND

TXD

RXD

TX0

RX0

GND

aaa-030772

(1) Optional, depends on regulator.

Figure 12.ꢀTypical TJA1441B application with a 5 V microcontroller

BAT

5 V

(1)

VCC

VDD

CANH

CANL

S_N

Pxx

OFF

TXD

RXD

Pyy

TX0

RX0

TJA1441D

CONTROLLER

GND

aaa-030847

(1) Optional, depends on regulator.

Figure 13.ꢀTypical TJA1441D application with a 5 V microcontroller

12.2 Application hints

Further information on the application of the TJA1441 can be found in NXP application

hints AH2002 'TJx144x/TJx146x Application Hints', available on request from NXP

Semiconductors.

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13 Test information

TXD

RXD

CANH

CANL

R

60 Ω

C

L

100 pF

L

15 pF

aaa-030850

Figure 14.ꢀCAN transceiver timing test circuit

TXD

RXD

CANH

CANL

30 Ω

f

TXD

C

4.7 nF

SPLIT

aaa-030851

Figure 15.ꢀTest circuit for measuring transceiver driver symmetry

13.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 Rev-H - Failure mechanism based stress test qualification for

integrated circuits, and is suitable for use in automotive applications.

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14 Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

4

e

detail X

w

M

b

p

0

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

0.25

0.01

0.25

0.1

1.75

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT96-1

076E03

MS-012

Figure 16.ꢀPackage outline SOT96-1 (SO8)

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HVSON8: plastic thermal enhanced very thin small outline package; no leads;

8 terminals; body 3 x 3 x 0.85 mm

SOT782-1

X

B

A

D

E

A

1

c

detail X

terminal 1

index area

e

1

C

terminal 1

index area

B

A

v

w

C

e

b

y

C

1

4

L

K

E

h

8

5

D

h

0

1

2 mm

L

scale

Dimensions

(1)

Unit

A

b

c

D

h

E

e

1

K

v

w

y

1

h

max 1.00 0.05 0.35

mm nom 0.85 0.03 0.30 0.2 3.00 2.40 3.00 1.60 0.65 1.95 0.30 0.40 0.1 0.05 0.05 0.1

min 0.80 0.00 0.25 2.90 2.35 2.90 1.55 0.25 0.35

3.10 2.45 3.10 1.65

0.35 0.45

Note

1. Plastic or metal protrusions of 0.075 maximum per side are not included.

sot782-1_po

Issue date

References

Outline

version

European

projection

IEC

- - -

JEDEC

JEITA

- - -

09-08-25

09-08-28

SOT782-1

MO-229

Figure 17.ꢀPackage outline SOT782-1 (HVSON8)

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15 Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

16 Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached

to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides

both the mechanical and the electrical connection. There is no single soldering method

that is ideal for all IC packages. Wave soldering is often preferred when through-hole

and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is

not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming

from a standing wave of liquid solder. The wave soldering process is suitable for the

following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

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• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads

to higher minimum peak temperatures (see Figure 18) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board

is heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder

paste characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 10 and Table 11

Table 10.ꢀSnPb eutectic process (from J-STD-020D)

Package thickness (mm)

Package reflow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

< 2.5

≥ 2.5

220

Table 11.ꢀLead-free process (from J-STD-020D)

Package thickness (mm)

Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 18.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Figure 18.ꢀTemperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17 Soldering of HVSON packages

Section 16 contains a brief introduction to the techniques most commonly used to solder

Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON

leadless package ICs can be found in the following application note:

• AN10365 “Surface mount reflow soldering description”

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18 Appendix: ISO 11898-2:2016 parameter cross-reference list

Table 12.ꢀISO 11898-2:2016 to NXP data sheet parameter conversion

ISO 11898-2:2016

NXP data sheet

Notation Symbol Parameter

Parameter

HS-PMA dominant output characteristics

Single ended voltage on CAN_H

Single ended voltage on CAN_L

Differential voltage on normal bus load

Differential voltage on effective resistance during arbitration

Optional: Differential voltage on extended bus load range

HS-PMA driver symmetry

V_{CAN_H}

V_{CAN_L}

V_Diff

V_O(dom)

dominant output voltage

differential output voltage

V_O(dif)

Driver symmetry

V_SYM

V_TXsym

transmitter voltage symmetry

Maximum HS-PMA driver output current

Absolute current on CAN_H

I_{CAN_H}

I_{CAN_L}

I_O(sc)dom

dominant short-circuit output

current

Absolute current on CAN_L

HS-PMA recessive output characteristics, bus biasing active/inactive

Single ended output voltage on CAN_H

Single ended output voltage on CAN_L

Differential output voltage

V_{CAN_H}

V_{CAN_L}

V_Diff

V_O(rec)

recessive output voltage

differential output voltage

TXD dominant time-out time

V_O(dif)

Optional HS-PMA transmit dominant time-out

Transmit dominant time-out, long

t_dom

t_to(dom)TXD

Transmit dominant time-out, short

HS-PMA static receiver input characteristics, bus biasing active/inactive

Recessive state differential input voltage range

Dominant state differential input voltage range

V_Diff

V_th(RX)dif

differential receiver threshold

voltage

V_rec(RX)

receiver recessive voltage

receiver dominant voltage

V_dom(RX)

HS-PMA receiver input resistance (matching)

Differential internal resistance

R_Diff

R_{CAN_H}

R_{CAN_L}

R_i(dif)

R_i

differential input resistance

input resistance

Single ended internal resistance

Matching of internal resistance

HS-PMA implementation loop delay requirement

Loop delay

MR

ΔR_i

input resistance deviation

t_Loop

t_d(TXDH-RXDH)delay time from TXD HIGH to

RXD HIGH

t_d(TXDL-RXDL)

delay time from TXD LOW to

RXD LOW

TJA1441

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 12 August 2020

27 / 31

NXP Semiconductors

TJA1441

High-speed CAN transceiver

ISO 11898-2:2016

Parameter

NXP data sheet

Notation Symbol Parameter

Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to 2

Mbit/s and above 2 Mbit/s up to 5 Mbit/s

Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,

intended

t_Bit(Bus)

t_bit(bus)

transmitted recessive bit width

Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s

Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s

HS-PMA maximum ratings of V_{CAN_H}, V_{CAN_L}and V_Diff

Maximum rating V_Diff

t_Bit(RXD)

Δt_Rec

t_bit(RXD)

Δt_rec

bit time on pin RXD

receiver timing symmetry

V_Diff

V_(CANH-CANL)voltage between pin CANH and

pin CANL

General maximum rating V_{CAN_H}and V_{CAN_L}

V_{CAN_H}

V_{CAN_L}

V_x

voltage on pin x

Optional: Extended maximum rating VCAN_H and VCAN_L

HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered

Leakage current on CAN_H, CAN_L

I_{CAN_H}

I_{CAN_L}

I_L

leakage current

TJA1441

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Product data sheet

Rev. 1 — 12 August 2020

28 / 31

NXP Semiconductors

TJA1441

High-speed CAN transceiver

19 Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

19.2 Definitions

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

TJA1441

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 12 August 2020

29 / 31

NXP Semiconductors

TJA1441

High-speed CAN transceiver

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Security — While NXP Semiconductors has implemented advanced

security features, all products may be subject to unidentified vulnerabilities.

Customers are responsible for the design and operation of their applications

and products to reduce the effect of these vulnerabilities on customer’s

applications and products, and NXP Semiconductors accepts no liability for

any vulnerability that is discovered. Customers should implement appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

19.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

NXP — wordmark and logo are trademarks of NXP B.V.

TJA1441

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Product data sheet

Rev. 1 — 12 August 2020

30 / 31

NXP Semiconductors

TJA1441

High-speed CAN transceiver

Contents

1

General description ............................................ 1

1.1

2

2.1

2.2

2.3

3

4

5

6

TJA1441 variants ...............................................1

Features and benefits .........................................1

General .............................................................. 1

Predictable and fail-safe behavior ..................... 2

Protection ...........................................................2

Quick reference data .......................................... 3

Ordering information .......................................... 4

Block diagrams ................................................... 4

Pinning information ............................................ 6

Pinning ...............................................................6

Pin description ...................................................6

Functional description ........................................7

Operating modes ............................................... 7

Off mode ............................................................9

Silent mode ........................................................9

Normal mode .....................................................9

Controlled Off mode (TJA1441D) .................... 10

Operating modes and gap-free operation ........ 10

Fail-safe features .............................................11

TXD dominant time-out function ...................... 11

Internal biasing of TXD and mode input pins ....11

Undervoltage detection on pins VCC and

6.1

6.2

7

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.2

7.2.1

7.2.2

7.2.3

VIO ...................................................................12

Overtemperature protection .............................12

I/O levels ..........................................................12

Limiting values ..................................................13

Thermal characteristics ....................................14

Static characteristics ........................................14

Dynamic characteristics ...................................17

Application information ....................................19

Application diagrams ....................................... 19

Application hints .............................................. 20

Test information ................................................21

Quality information ...........................................21

Package outline .................................................22

Handling information ........................................24

Soldering of SMD packages .............................24

Introduction to soldering .............................

Wave and reflow soldering .........................

Wave soldering ...........................................

Reflow soldering .........................................

Soldering of HVSON packages ........................26

Appendix: ISO 11898-2:2016 parameter

cross-reference list ...........................................27

Legal information ..............................................29

7.2.4

7.2.5

8

9

10

11

12

12.1

12.2

13

13.1

14

15

16

16.1

16.2

16.3

16.4

17

18

19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 August 2020

Document identifier: TJA1441


型号：	TJA1441DT
厂家：	NXP
描述：	High-speed CAN transceiver
文件：	总31页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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