TZA1047HL/M2_技术文档

TZA1047

Preprocessor IC for CD and DVD rewritable

Rev. 02 — 1 June 2005

Product data sheet

1. General description

The TZA1047 is a multipurpose analog preprocessor IC for use in an optical bit engine.

Typical applications are DVDRW (a compound name that stands for a multitude of writable

and re-writable DVD standards), high-speed DVD-ROM, the COMBI drive

(CDR/RW-writer with DVD read-out) and the Double Writer (writes both CDR/RW and

DVDRW).

At the input, TZA1047 will interface with many standard OPUs having either voltage or

current outputs. At the output, TZA1047 will interface with Philips decoder/encoder ICs

such as the SAA7810, SAA7811, SAA7846, SAA7849 and PNX7850.

The TZA1047 has four versions:

• TZA1047/M1A: standard functionality

• TZA1047/M1B: Fast Track Count (FTC) circuit with improved signal range

• TZA1047/M2: FTC circuit with improved signal range; Distributor circuit with common

offset added to Left (L) and Right (R) signals to improve normalized push-pull signal

(wobble) CNR

• TZA1047/M3: negative segment input offset range and offset compensation is

possible; increased BWPP bandwidth.

2. Features

■ Operates with DVD-ROM, DVD+RW, DVD+R, DVD-RW, CD-ROM, CD-RW and CD-R

media

■ Speciﬁcally suited for double-writer and combination applications

■ Operates up to 64× CD-ROM read, 20× DVD-ROM read, 48× CDR/RW write,

12× DVDR/RW write to 16× DVDR/RW write

■ Optimized input interface to operate with Philips optical pick-up IC TZA1045

■ Selectable input termination resistors; allows characteristic termination of the ﬂex

connection to the Optical Pick-Up (OPU) head for high speed performance; no

external components required

■ Programmable RF equalizer function with bandwidth equivalents of 64× CD or

20× DVD

■ Programmable noise ﬁlter in RF ampliﬁer for improved signal quality

■ Programmable RF gain for DVD-ROM / DVDRW / CD-RW / CDROM applications; AGC

possible with Philips decoder ICs (SAA7810, SAA7811, SAA7846, SAA7849 or

PNX7850)

■ Differential RF signal input and output for high-speed operation with minimum

interference

TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

■ Programmable DC offset cancellation in RF path to allow DC-coupling to Philips

decoder ICs (SAA7810, SAA7811, SAA7846, SAA7849 or PNX7850)

■ Programmable Differential Phase Detection (DPD) circuit for DVD radial tracking

■ Push-Pull (P-P) signal channel for reading Address In Pre-groove (ADIP) information

on recordable and re-writable media

■ Versatile FTC function with programmable ﬁltering

■ I²C-bus interface allows the device to be programmed by a decoder IC or

microcontroller

■ Works with externally supplied sample timing signals or on-board Eight-to-Fourteen

(EFM) signal decoder for write synchronization

■ Programmable normalization for servo signals

■ Servo outputs programmable as direct unprocessed currents or as error signals

■ Fast running Optimum Power Control (OPC) processing for phase change media

(ALFA loop)

■ On-board processing circuit for write power calibration and OPC (BETA loop).

3. Quick reference data

Table 1:

Symbol

Supply

V_DD

Quick reference data

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

4.5

-

5

-

5.5

V

[1]

I_DD(tot)

total positive supply current

circuit active; highest

dissipation mode

175

mA

I_stby

supply current in Standby

mode

STBY = 1

-

5

mA

I_q

quiescent supply current

IDDQTST = 1

-

100

-

µA

V_ref(int)

reference voltage for internal

current settings

external R_REF= 47 kΩ

2.3

V

T_amb

ambient temperature

operating

0

-

70

°C

Input circuit

Z_i(seg)

segment signal input

impedance (pins VIA to VIH

with respect to pin VREF)

LDSEG[1:0] = 00

LDSEG[1:0] = 01

LDSEG[1:0] = 10

LDSEG[1:0] = 11

-

150

300

600

> 10

-

Ω

-

Ω

-

Ω

-

kΩ

V

V_ref

V_i

reference voltage for segment programmable by

and RF inputs

1.3

2.8

parameter VSEG

input voltage

pins VIA to VIH

V

_ref− 0.05

-

V_ref+ 1

V

RF ampliﬁer (RF AMP)

Z_i(RF)

RF input impedance (RFPIN

and RFNIN with respect to

VREF)

LDRF[1:0] = 00

-

75

150

300

> 5

-

Ω

kΩ

V

LDRF[1:0] = 01

-

LDRF[1:0] = 10

-

LDRF[1:0] = 11

-

V_i(dif)

V_i(se)

differential input voltage

pins RFPIN and RFNIN

pins WRF and RRF

1.0

V

_DD− 1

single-ended input voltage

-

V

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 1:

Symbol

G_RF

Quick reference data …continued

Parameter

Conditions

Min

Typ

Max

Unit

gain range RF path

programmable by

parameters

−14

-

+40

dB

GRFW/GRFR, GRF

and HA

B_RF

−3 dB bandwidth of RF path

ENEQ = 0; ENNF = 0

180

16

-

MHz

f_0(RF)

noise ﬁlter and equalizer

corner frequency

programmable by

parameter BWRF

180

V_i(ref)

RF voltage reference input

pin RFREF

1.0

−1

−2

-

2.5

+1

+2

70

V

Ω

V_o(dif)(RF)RF differential output voltage

(RFP to RFN)

V_RFREF< 2 V

V_RFREF> 2 V

pins RFP and RFN

Z_o(RF)

RF output impedance

FTC output circuit

V_o(FTC)

FTC output voltage

FTCSL[0] = 1 (digital

3.3 V output)

0

2

-

3.3

3

V

FTCSL[0] = 0 (analog

output)

V_CFTC

CFTC pin voltage

-

2.5

-

V

Z_o(FTC)

FTC output impedance

300

Ω

Push-pull processor circuit

V_O

Z_o

V_o

DC output voltage at pin

PPNO

I_i(PPN)= 0 A; no input

signal

-

0.5V_DD

-

V

Ω

V

output impedance at pin

PPNO

-

130

AC output voltage at pin

PPNO

0.6

V

_DD− 0.6

Write synchronization circuit (EFMTIM)

I_i(EFM)

input current on pins

REF/ECN, RS/ECP, TH1/EDN

and TH2/EDP

0

-

5000

µA

I_i(dif)H

differential input current for

HIGH level

I_P− I_Nor I_sig− I_REF

330

1800

5000

µA

ns

Ω

I_i(dif)L

differential input current for

LOW level

−330

−1800

−5000

I_i(dif)(th)

t_r(in)(se)

t_r(in)(dif)

R_i(EFM)

differential input current

threshold level

-

0

-

rise time of single-ended input EFMINT = 0; 12× DVD

signals

1

2

-

rise time of differential input

signals

EFMINT = 1; 4× DVD

-

input resistance to GND on

pins REF/ECN, RS/ECP,

TH1/EDN, TH2/EDP

70

Normalizer circuit and servo outputs

V_o(S),V_o(D)servo output voltage

S1 and S2, D1 to D4;

operating

1.2

-

0.5V_DD

V

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 1:

Symbol

Quick reference data …continued

Parameter

Conditions

Min

Typ

Max

Unit

Fast running OPC (ALFA) circuit

I_o(ALFA)

V_o(ALFA)

I_i(LASP)

ALFA output current

V_o(ALFA)= 0 V

operating

0

5

0

-

100

µA

V

ALFA output voltage

LASP control current input

-

V_DD− 1.5

r/w = 0

-

100

15

-

µA

V

r/w = 1

-

V_i(LASP)

Z_i(LASP)

LASP input voltage

I_i(LASP)= 100 µA

1.7

-

LASP input impedance

-

2

kΩ

Write power calibration (BETA) circuit

V_o(BETA)

A1, A2 and CALF output

voltage

V_DD= 5 V

0

-

3.3

V

Z_o(BETA)

A1, A2 and CALF output

impedance

300

Ω

Monitor outputs (MON)

V_o(MON)monitor output voltage

R_L= 10 kΩ; C_L= 10 pF

0.7

-

V_DD− 0.7

V

V_ref(MON)monitor voltage reference level I_i= 0 A

0.5V_DD− 0.1 0.5V_DD

0.5V_DD+ 0.1 V

R_O(MON)

output resistance on pins

MON1 and MON2

-

120

-

Ω

I²C-bus interface

V_IL

V_IH

LOW-level input voltage

HIGH-level input voltage

pins SCL and SDA

−0.5

-

1.0

V

2.2

V_DD+ 0.5

Digital inputs

V_IL

LOW-level input voltage

pins R/W, SILD, SIDA,

SICL and IDDQTST

−0.5

-

+1.1

V

V_IH

HIGH-level input voltage

pins R/W, SILD, SIDA,

SICL and IDDQTST

2.1

V_DD+ 0.5

[1] Dependent on the actual register settings; most unused circuits are powered down.

4. Ordering information

Table 2:

Ordering information

Type number

Package

Name

Description

Version

TZA1047HL/M1A LQFP64

TZA1047HL/M1B

plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2

TZA1047HL/M2

TZA1047HL/M3

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

5. Block diagram

V

DD2

V

GND1

2, 5, 37, 42

GND2 GNDD

30, 32 23

DD1

DDD

8, 11, 44

29

22

31

RFP

62

32

s/d

WRF

RF AMPLIFIER

RFN

33

RFREF

7

6

40,

39, 38

RFPIN

RFNIN

MUX

CCALF,

CA1, CA2

54,

BETA

ALFA

61

56, 55

CALF,

A1, A2

RRF

s/d = single-ended to

differential converter

58

ALFA

59

LASP

10,

4,

3,

VIA,

VIB,

VIC,

VID,

VIE,

VIF,

VIG,

VIH

TZA1047

9,

D1,

12,

64,

13,

1

52, 51, 50,

49, 48, 47,

OFFSET

CONTROL

D2/TLN,

D3/REN,

D4/FEN,

S1/MIRN,

S2/XDN

NORM

SAMPLE-

AND-HOLD

INPUT

V/I

LPF

MUX

CIRCUIT

63

43

VREF

CMPP

45

46

MON1

MON2

MON

GAIN

DPD

24

25

26

27

21

L, R

34

REF/ECN

RS/ECP

TH1/EDN

TH2/EDP

R/W

P-P PROCESSOR

PPNO

36

35

FTC

to ALFA and NORM

r/w

FTC

EFMTIM

CFTC

control

switches

18

19

17

28

57

SIDA

20

14

SICL

control

currents

TIMOUT

RWOUT

SERIAL BUS

INTERFACE

SILD

SERTST

SROUT

REGISTERS

AND

DACs

LOGIC

15

16

SDA

SCL

2

I C-BUS

INTERFACE

BAND GAP

REFERENCE

60

53

TEST

41

POR

RREF

IDDQTST

001aab187

Fig 1. TZA1047 block diagram.

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

6. Pinning information

6.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VIH

S1/MIRN

S2/XDN

MON2

GND1

VIC

3

4

VIB

MON1

5

GND1

RFNIN

RFPIN

V

DD1

6

CMPP

GND1

RREF

CCALF

CA2

7

8

V

DD1

VID

TZA1047

9

10

11

12

13

14

15

16

VIA

V

CA1

DD1

VIE

GND1

FTC

VIG

RWOUT

SDA

CFTC

PPNO

RFREF

SCL

001aab182

Fig 2. TZA1047 pin conﬁguration.

6.2 Pin description

Table 3:

Pin description

Symbol

VIH

1

Description

satellite segment H input

analog supply 1 ground

central segment C input

central segment B input

analog supply 1 ground

GND1

VIC

2

3

VIB

4

GND1

RFNIN

RFPIN

V_DD1

VID

5

6

inverse differential RF input or single-ended RF read input

differential RF input or single-ended RF write input

positive analog supply 1 voltage

7

8

9

central segment D input

VIA

10

11

central segment A input

V_DD1

positive analog supply 1 voltage

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 3:

Symbol

VIE

Pin description …continued

Description

satellite segment E input

12

13

14

15

16

17

18

19

20

21

22

23

24

VIG

satellite segment G input

R/W signal output

I²C-bus data input/output

I²C-bus clock input

RWOUT

SDA

SCL

SILD

strobe line input of serial bus interface

data line of serial bus interface

clock line input of serial bus interface

EFMTIM test output

SIDA

SICL

TIMOUT

R/W

external Read/Write signal input

positive digital supply voltage

digital supply ground

reference input for timing signals in EFMTIM bypass mode^[1]or

inverse EFM clock input^[2]

V_DDD

GNDD

REF/ECN

RS/ECP

TH1/EDN

TH2/EDP

SERTST

25

26

27

28

RF sampling signal^[1]or EFM clock input^[2]

segment sampling timing signal^[1]or inverse EFM data input ^[2]

segment sampling timing signal^[1]or EFM data input^[2]

enable test mode input (tie to GND or leave unconnected for

normal operation)

V_DD2

29

30

31

32

33

positive analog supply 2 voltage

analog supply 2 ground

GND2

RFP

RF output voltage; positive

RF output voltage; negative

RFN

RFREF

reference voltage input for differential RF output common mode

level

PPNO

CFTC

FTC

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

push-pull voltage output

FTC high-pass ﬁlter capacitor

FTC output

GND1

CA1

analog supply 1 ground

BETA circuit external capacitor

reference resistor to ground

CA2

CCALF

RREF

GND1

CMPP

V_DD1

analog supply 1 ground

MPP external capacitor

positive analog supply 1 voltage

monitor output 1 voltage

MON1

MON2

S2/XDN

S1/MIRN

D4/FEN

D3/REN

monitor output 2 voltage

servo output current or x position voltage output

servo output current or MIRN error signal output

servo output current or FEN error signal output

servo output current or REN error signal output

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 3:

Symbol

D2/TLN

D1

Pin description …continued

51

52

53

Description

servo output current or TLN error signal output

servo output current

IDDQTST

zero dissipation mode selection input (tie to GND for normal

operation)

CALF

A2

54

55

56

57

58

59

60

61

62

63

64

RF average level signal input

RF bottom level signal output

RF top level signal output

A1

SROUT

ALFA

LASP

TEST

RRF

WRF

VREF

VIF

shift register output for register test mode

ALFA current output

laser power setpoint signal input

test output; leave unconnected

single-ended RF read input

single-ended RF write input

photodiode IC (PDIC) reference voltage output

satellite segment F input

[1] Only in EFM bypass mode.

[2] EFM clock and data when not in EFM bypass mode.

7. Functional description

7.1 Detector layout

The TZA1047 supports OPUs having the detector layout shown in Figure 3. The detector

segments are denoted A to H which conforms to the generally accepted standard for

8 segment PDICs.

CENTRAL SEGMENTS

(HIGH BANDWIDTH)

A

D

B

C

E

F

G

H

SATELLITE SEGMENTS

mce511

Fig 3. Detector layout supported.

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

7.2 Supported servo modes

The TZA1047 supports several servo modes. The deﬁnitions of output signals FTC and

Q1 to Q6 depend on the servo mode that is selected via the I²C-bus. The bits that deﬁne

the servo mode and their meaning are summarized in Table 4.

The various servo signals are generated in the Normalizer (Norm), DPD and FTC blocks.

For details, refer to the appropriate sections in this Chapter.

Table 4:

Name

Servo modes

Value

Conditions

Meaning

CA/PP

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DPD = 0

push-pull signal processing

3-spot Central Aperture signal processing

non-DPD based radial error signal

DPD-based radial error signal

DTD based on individual segments

DTD based on combined segments

DTD4 or DTD4a detection method

DTD2a method

DPD

DTDC/I

PD1

DPD = 1

SP3/1

FSEL

D/F

D/F = 0; FSEL = 1

FTC based on 1-spot push-pull

FTC based on 3-spot push-pull

FTC based on 1-spot Central Aperture

other FTC method

FSEL = 1

non-DPD based FTC

DPD based FTC

7.3 Diagram conventions

Single-bit control names have the format X/Y. When:

X/Y = 0: port Y is selected, or Y is TRUE

X/Y = 1: port X is selected, or X is TRUE.

Some internal signals control sampling switches. The switch is on when the signal is

1 (HIGH).

Many signals to and from the TZA1047 are currents. External currents which sink via the

TZA1047 are positive and currents sourced by the TZA1047 are negative.

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

7.4 Input circuit

Refer to Figure 4.

GSEG

VUA to VUD

DPD

TH1

TH2

VRA to VRD

VRA to VRH

VSA to VSH

+

VIA to VIH

LDSEG

−

SAMPLE-AND-HOLD (8×)

VSEG

R

0

R

1

R

2

R

3

(8×) (8×) (8×) (8×)

REFERENCE

CIRCUIT

V

REF

001aab193

V

REF

Fig 4. Input circuit.

The Input circuit comprises a voltage reference circuit, sample-and-hold circuit, and a

programmable gain ampliﬁer. The input signals to the Input circuit are VIA to VIH, and can

be either currents or voltages. The signal names correspond to the PDIC segments shown

in the detector layout Figure 3. Each signal is connected to reference voltage V_REFby a

termination resistor that is selectable by the control word LDSEG[1:0]. The currents of

input signals, for example from the TZA1045, are converted to voltages across the input

termination resistors.

The voltage reference circuit is a DAC which is programmable by control word VSEG[3:0]

to allow different PDICs to be supported. The voltage reference circuit has a sufﬁciently

large sink capability for the 150 Ω termination resistors, allowing the TZA1047 to work

with a characteristically terminated ﬂex connection to the OPU.

Note that when the TZA1047 is in Standby mode (STBY = 1), V_REFand the input resistors

remain active to allow the TZA1045 to deliver current to the TZA1047 without the risk of

‘latch-up’.

The reference voltage is subtracted from the input signals and the resulting signals VRA

to VRH are optionally sampled by a sample-and-hold circuit. The sampling signals TH1

and TH2 originate either directly from the codec IC or from the EFMTIM circuit. The

resultant signals VSA to VSH are sent to the Distributor for further processing. If sampling

is disabled (bit SMPLON = 0), both switches remain closed and the sample-and-hold

circuit is transparent.

The central signals VRA to VRD are ampliﬁed for DPD use at a gain programmable by

control word GSEG[1:0]. The resultant four signals VUA to VUD go to the DPD circuit. The

GSEG gain is enabled when bit DPD = 1 and is disabled, to save power, when bit

DPD = 0.

The input signal range for VIA to VIH − V_refis 1 V maximum.

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Preprocessor IC for CD and DVD rewritable

The Distributor combines and processes the (optionally sampled) signals VSA to VSH

coming from the Input circuit to produce the servo signals Q1 to Q6 and the input signals

for the FTC and for the push-pull processor. Sections Section 7.5.1 to Section 7.5.4

describe how the Distributor output signals are derived.

7.5.1 Signals Q1 to Q6

Refer to Figure 5.

The servo currents Q1 to Q4 are offset-free and ﬁltered current versions of the segment

voltages VSA to VSD. They are converted from voltage to current by the resistance R_Q.

The signals Q5 and Q6 depend on the servo mode (3-spot CA, 3-spot PP or DPD).

Segment signals VSA to VSH are converted from voltages to currents. The currents are

low-pass ﬁltered to remove the EFM noise from the signals if no sampling is applied

during read and write.

Offset compensation can be applied by adding an offset current to each of the 8 segment

signals to cancel the offset in the segment signal from the PDIC. Separate offsets can be

speciﬁed to cancel the different offsets for read and write. For read, the offsets are set by

5-bit registers ORA to ORH, for write, by registers OWA to OWH. In order to specify the

correct value for a speciﬁc offset register, the offset for the corresponding segment is

measured externally via signals Q1 to Q4. The gain control bits GCAL[1:0] set the

measured offset current to within the range of the measuring device; a range of 0 µA

to 10 µA is suitable for most Philips decoders. The gain adjusted central segment signals

QA to QD and satellite segment signals QE to QH can be swapped by setting bit

CALSAT to logic 1 to allow all QA to QH signals to be measured externally via Q1 to Q4.

After offset cancelling, the central segment signals Q1 to Q4 are routed to the Distributor

output as offset-free and ﬁltered current signal versions of the segment voltage signals

VSA to VSD.

Note that Q3 corresponds to QD and that Q4 corresponds to QC. These signal

associations were swapped over in earlier Philips preprocessor devices.

The characteristics of signals Q5 and Q6 depend on the status of bit CA/PP and bit DPD;

see Table 5.

Table 5:

Q5/Q6 modes

Servo Mode

3-spot PP

3-spot CA

CA/PP

Q5

Q6

0

1

γ × (QE + QG)

γ × (QE + QF)

γ × (QF + QH)

γ × (QG + QH)

Symbol γ is the gain factor which compensates for the power difference between the

central spot and the satellite spot. This is determined by the grating ratio of the OPU and

possibly gain differences between the central and satellite segments in the PDIC. The

value of γ is controlled by bit GRAT and control word AT[7:0].

7.5.2 Signal Q_s

Q_sis the sum of the central segment signals and is used in the DPD circuit for drop-out

concealment detection. It is deﬁned by: Q_S= 0.2 × (Q_A+ Q_B+ Q_C+ Q_D)

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

7.5.3 FTC circuit signals

The signals to the FTC circuit comprise the following:

FA = VSA/R_FTCto FH = VSH/R_FTC

FAD = FA + FD

FBC = FB + FC

Where R_FTCis the conversion resistance.

These signals are combined in the FTC block to provide various Fast Track Count

methods.

7.5.4 Signals L and R

The output currents L and R represent the signals from the left and right halves,

respectively, of the PDIC pupil. They are processed by the P-P Normalizer/Balancer to

obtain a P-P signal suitable for wobble detection. Signals L and R are deﬁned by:

PA = VSA/R_PPto PD = VSD/R_PP

L = 2(PA + PD + I_RLOFF) + I_PPOFFfor bit R/L = 0; L = 2(PA + PD) + I_PPOFFfor bit R/L = 1

R = 2(PB + PC + I_PPOFF) for bit R/L = 0; R = 2(PB + PC + I_RLOFF) for bit R/L = 1

Where R_PPis the conversion resistance; I_RLOFFis the offset current between signals

L and R.

The bandwidth of signals L and R is determined by low-pass ﬁlter LPF2 and can be

selected using the control bits BWPP1[2:0].

In order to set I_RLOFF, the offset of signals L and R must be measured separately by

setting bit CALRL to logic 1. In this mode, R is sent to Q1 and L is sent to Q2 and are NOT

available to the push-pull circuit.

When the P-P Normalizer/Balancer circuit is not used (bit PPBAL = 0), the related circuit

in the Distributor is switched off to save power.

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7.6 RF ampliﬁer

A detailed block diagram of the RF ampliﬁer is shown in Figure 6.

TSTVRF

(open)

r/w

V

WRF

DIFFW

−

G

RFW

+

s/d

WRF

G

RFR

RFPIN

RFNIN

r/w

TSTDPD1

LDRF

REFON

rfp

rfn

R0

R1

R2

R3

(2×) (2×) (2×) (2×)

(open)

dtdtst

V

REF

+

VWRF

VRRF

s/d

RRF

−

DIFFR

V

WRF

RRF

REF

CIRCUIT

(open)

V

RRF

TSTVRF

PDCRF

RDCRF

ENEQ

KEQ

DC

RF

HA GRF

VGA

BWRF ENNF BWRF

DRVON

5X

rfp

RFP

RFN

+

−

+

−

rf

DC CONTROL

a

EQ

NF

b

rfn

RFREF

1/2

RFItest

rf-beta1

rf-beta2

R

rf

OFFSET

CONTROL

V/I

rf-norm

rftst

1/3

OFF

rf-cal

RFW

OFF

RFCAL

001aab183

RFR

r/w

Fig 6. RF ampliﬁer.

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The RF ampliﬁer input supports many of the different signal conﬁgurations that are

produced by the various types of PDIC available. The possible input signals are either a

differential pair RFPIN and RFNIN which can be either currents or voltages, or two

single-ended voltages WRF and RRF.

7.6.1 Input section

The differential inputs RFPIN and RFNIN are connected to each other by programmable

termination resistors. These resistors provide a characteristic termination of the

connection to the OPU and convert current to voltage in the case of a current output PDIC

such as the TZA1045. The midpoint of these resistors is either connected to V_REF

(bit REFON = 1) or is left ﬂoating (bit REFON = 0). The resistor values are 75 Ω, 150 Ω,

300 Ω or high-ohmic (> 5 kΩ) and are selectable by word LDRF[1:0].

Both differential inputs can be used for read or write (bit DIFFR = 1, bit DIFFW = 1). Of the

single-ended inputs, RRF can be used for read (bit DIFFR = 0, signal r/w = 1) and WRF

for write (bit DIFFW = 0, signal r/w = 0). Depending on the setting of bit DIFFR and bit

DIFFW, the non-active inputs are disabled to save power. The single-ended input signals

are made differential by subtracting programmable reference voltages V_WRFfrom WRF

and V_RRFfrom RRF. Reference voltages V_WRFand V_RRFare programmable by word

VWRF[3:0] and word VRRF[3:0] respectively.

The control bit TSTVRF is intended for test purposes only and should be set to logic 0 for

normal operation.

7.6.2 Differential data path

The r/w multiplexer outputs one common differential RF signal for all possible modes,

which is ampliﬁed at a gain set by word GRFW[3:0] during write and a gain set by word

GRFR[3:0] during read.

A DC-control block allows the output signal to be DC-coupled to a channel decoder. The

relationship between input and output of the DC-control block is given by rf_b= rf_a− DC_RF

Where DC_RFis the RF DC control voltage controlled by word DCRF[5:0] set via the Fast

Serial Bus (FSB).

.

The DC control block has two functions: the ﬁrst function allows the output signal to be

DC-coupled to a channel decoder in which the DC control is adjusted in a closed-loop by

the decoder IC. This function requires both PDCRF and RDCRF bits to be set to logic 0.

The second function allows a DC offset calibration to be performed which is required if a

DC measurement for OPC is performed via the differential data path (BETA measurement

in PNX7850). For this purpose, the DC control polarity can be set by bit PDCRF and the

DAC accuracy can be increased (at the cost of decreasing the range) by setting bit

RDCRF. The relationship between input and output of the DC-control block is given by:

0.01

1 + RDCRF

rf_b= rf_a− DC_RF, where DC

=

1 – (2 × PDCRF) ×

× DCRF

-----------------------------

RF

If bit PDCRF is logic 0, DC_RFis subtracted from rf_a; if bit PDCRF is logic 1, DC_RFis added

to rf_a. The step size is 10 mV when bit RDCRF = 0 and 5 mV when RDCRF = 1. The

control word DCRF[5:0] and bits PDCRF and RDCRF are set via the FSB.

A Variable Gain Ampliﬁer (VGA), also controlled via the FSB (word GRF[3:0]), is used to

create an AGC loop in conjunction with the decoder IC.

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If the DC-control loop is used, it provides sufﬁcient headroom to select an additional gain

of 12 dB in the VGA (bit HA = 1). This allows the amplitude of the signal into the ﬁlters to

be scaled and optimized, which improves SNR.

The output of the VGA is connected to a ﬁlter section that comprises an Equalizer (EQ)

and a Noise Filter (NF), which are controlled by bits KEQ, ENEQ, ENNF and word

BWRF[6:0]. The equalizer has a transfer function H_e(s) shown by Equation 1.

s²

1 – k ×

--------------

ω

2

1

0RF

H_e(s) =

×

(1)

------------------------------------------------------ -------------------------------

s²

s

1 + τ ×

------------

1 +

+ α ×

------------

---------------

2

ω_0RF

This represents a 3rd degree equi-ripple phase ﬁlter with a good delay response. The

boost factor k is programmable by control bit KEQ via the I²C-bus. The corner frequency

ω_0RF= 2 π f_0RFis programmable by control word BWRF[6:0]. The equalizer is activated by

control bit ENEQ.

The noise ﬁlter is a 3rd-order Butterworth low-pass ﬁlter which has a transfer function

H_n(s) shown by equation Equation 2.

1

H_n(s) =

×

(2)

-------------------------------------------- ----------------------

s²

s

1 +

------------

1 +

+

--------------- ------------

ω_0RF

2

ω_0RF

The corner frequency ω_0RFin this ﬁlter is equal to the corner frequency of the equalizer

ﬁlter. The noise ﬁlter is activated by bit ENNF. To reduce power dissipation, the ﬁlters

auxiliary circuits, such as the DACs, are switched off when bit ENNF and bit ENEQ are

both logic 0.

The low-ohmic differential output voltage is produced by a driver stage, where the

externally sourced reference voltage at pin RFREF deﬁnes the common mode voltage of

output signals RFP and RFN. The driver stage can be disabled to save power by setting

bit DRVON to logic 0.

A low-power, low-speed mode is anticipated for applications such as slim line notebooks,

where maximum speed is less important than power dissipation. By setting bit 5X, the

output bandwidth is limited to approximately 5× DVD. Note that the maximum speed of the

output is inﬂuenced by the output load. Therefore it may be possible to use the ‘low

dissipation’ mode up to higher speeds in applications having lower output loads, such as

Magnetic Core Memory (MCM).

To enable testing of the DPD ﬁlters, signal dtdtst from the input ﬁlter of the DPD circuit can

be routed to the output by setting bit TSTDPD1 to logic 1. Due to the implementation, not

all settings of word GRFR[3:0] or GRFW[3:0] are possible in this mode.

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7.6.3 Single-ended current path

Apart from the RF output signal, the RF ampliﬁer also produces four identical derivative rf

signals in the current domain for use in other circuits. They are called rf-beta1, rf-beta2,

rf-norm and rf-cal, and are routed to blocks BETA and Normalizer and to the XDN output.

V_RFa+ V_OO(RF)

The outgoing signals are offset-compensated rf-currents: rf =

----------------------------------------

R_rf

The offset voltage V_OO(RF)is set via the I²C-bus interface. In read mode (r/w = 1), V_OO(RF)

is controlled by OFFRF[5:0]. In write mode (r/w = 0), V_OO(RF)is controlled by

OFFRFW[5:0]. Voltage V_RFais the output voltage of the ﬁrst output stage across rfp and

rfn; R_rfis the RF V-to-I conversion resistance. Separate offset settings for read and write

are necessary because the combined offset of PDIC and the TZA1047 RF path will be

different in read and write modes. Read and write modes use different gain settings set by

GRFR[3:0] and GRFW[3:0], so an offset at the input to the DC-control block will have a

different effect on V_RFain read and write mode.

The offset is calibrated by measuring the voltage of the calibration signal rf-cal via the

output at pin XDN with the laser off. Avoid adding other rf currents as they may

signiﬁcantly increase the offset since it is assumed that all rf currents are offset-free after

calibration of rf-cal.

The control signal RFItest is intended only for test and evaluation purposes. It is set by

I²C-bus control bits TST[2:0]. For normal operation these bits should all be set to logic 0.

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The DPD circuit is enabled by control bit DPD. If DPD = 0 the entire circuit is switched off

to reduce power dissipation in applications where DPD is not used.

The four input signals VUA to VUD, generated in the Input circuit, correspond to the

signals from the four central segments of the PDIC. There are four possible DPD methods

available DTD4, DTD4a, DTD2a or DTD2 which are speciﬁed by bits PD1, PD2 and

DTDC/I. The relationship between signals VUA to VUD and signals s1 to s4 for each DPD

method is shown in Table 6.

Table 6:

DPD selection method

PD1

0

PD2

0

DTDC/I

S1

S2

S3

S4

0

1

VUA

VUB

VUD

VUB

VUD

VUC

VUA

VUD

VUB

VUD

0

1

0

1

X

VUA + VUC VUB + VUD VUA + VUC VUB + VUD

The signals VUA to VUD are fed through a low-pass ﬁlter LPF1 to ﬁlter out noise, then

through a high-pass ﬁlter (HPF) to remove the DC content and ﬁnally through a lead

network (equalizer) to boost the I3 amplitude. The cut-off frequency of LPF1 is controlled

via I²C-bus word FDPD[1:0] while the lead ﬁlter is controlled by word FLL[1:0]. The

selected signals s1 to s4 are then sliced to produce two pairs of binary value signals (Φ1)

and (Φ2). Each signal pair is fed to the input of a phase detector. The outputs of both

phase detectors are combined and low-pass ﬁltered by LPF2 to produce signals dtd1 and

dtd2 as shown by equations Equation 3 and Equation 4.

1

T _p

dtd1 = D₀+ k_DTD

dtd2 = D₀+ k_DTD

×

× avg(D(s1, s2) + D(s3, s4))

× avg(D(s2, s1) + D(s4, s3))

(3)

(4)

------

1

------

T _p

Where T_pis the average period of s1 to s4, and D₀is an offset depending on the delay

parameter set by word DL[2:0] (D₀= DL/T_P), via the I²C-bus, which is introduced to reduce

the sensitivity to noise. k_DTDis the sensitivity of the phase detector (typically equal to 1)

and D(sx, sy) represents the delay time between signal sx and signal sy, given by:

D(sx, sy) = del(sx, sy) if del(sx, sy) ≥ 0

D(sx, sy) = 0 if del(sx, sy) < 0

where del(sx, sy) is the time delay between signal sx and signal sy; if signal sx leads

signal sy then del(sx, sy) > 0.

The difference between dtd1 and dtd2 (dtd1 − dtd2) is multiplied with a drop-out

concealed normalization current I_Nand added to a ﬁxed offset current I_D0. Two outputs are

produced which have an opposite sign in the modulation term, the polarity is speciﬁed by

bit DPOL. The possible values for the output signals are shown in Table 7.

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Table 7:

DTD_Pand DTD_noutput values

DPOL

Q_S

DTD_P

DTD_n

0

1

Q_S> I_T

Q_S< I_T

Q_S> I_T

Q_S< I_T

I_Do+ (dtd1 − dtd2)I_N

I

_Do− (dtd1 − dtd2)I_N

I_Do+ (dtd1 − dtd2)I_NQ_S/I_T

I_Do− (dtd1 − dtd2)I_NQ_S/I_T

I_Do− (dtd1 − dtd2)I_N

I_Do+ (dtd1 − dtd2)I_N

I_Do− (dtd1 − dtd2)I_NQ_S/I_T

I_Do+ (dtd1 − dtd2)I_NQ_S/I_T

Q_Sis the central-spot sum signal generated by the Distributor. I_Tis the level of threshold

current for dropout concealment with which it is compared. I_Nis an output-scaling current.

I_Tand I_Nare programmable via the I²C-bus by IN[3:0] and IT[3:0].

7.7.1 Test mode

The control bits TSTDPD1 and TSTDPD2 are intended for test and evaluation purposes

only and should be set to logic 0 for normal operation.

7.8 FTC circuit

A detailed block diagram of the FTC subcircuit is shown in Figure 8. The entire FTC block

can be powered down by setting bit FTCON to logic 0.

FTCON

FAD + FBC

3.0

SP3/1

FE to FH

FTC CIRCUIT

FAD, FBC

from

γ

Distributor

FF + FH

FE + FG

FAD, FBC

X

CA/PP2

FSEL

FTCSL

[FAD + γ × (FF + FH)]

[FBC + γ × (FE + FG)]

D/F

GFTC

I/V

FTCF

LPF

γ

HPF

R

FTCOUT

FTC

FE + FF

FG + FH

X

CFTC

γ

D

AT, GRAT

V

FTC(DC)

DTDp, DTDn

001aab188

from DPD

3.0

Fig 8. FTC circuit.

The FTC circuit supports detection modes: CA, PP, DPD with either 1 or 3-spot tracking.

The FTC mode is controlled by bits FSEL, CA/PP2, SP3/1 and D/F. The different modes of

signal ftc (output FTC before ﬁltering and slicing) that are possible are given in Table 8.

Note that bit CA/PP2 is not the same as bit CA/PP which is used to control the operation

of the Distributor. Having two CA/PP bits allows different settings for FTC and servo

signals in the application.

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Table 8:

FTC Modes

FSEL

CA/PP2 SP3/1 D/F

FTC

3 × R_FTCOUT× (FAD + FBC)

0

1

X

0

1

X

0

X

0

1

R

_FTCOUT× (FAD − FBC)

1

_FTCOUT× {[FAD + γ × (FF + FH)] − [FBC + γ × (FE + FG)]}

_FTCOUT× γ × (FE + FF − FG − FH)

X

3 × R_FTCOUT× (DTD_p− DTD_n)

R_FTCOUTis a programmable I to V conversion resistance, set by control word GFTC[1:0].

The parameter γ is a programmable gain representing the ratio between the satellite and

central segment signals. It is equal to the γ used in the Distributor and is controlled by

GRAT and word AT[7:0].

The FTC signal is high-pass ﬁltered in order to limit the offset and then low-pass ﬁltered to

suppress noise. The low-pass ﬁlter LPF is a second order ﬁlter with a target transfer

function H_t(s):

1

H_t(s) =

; where Q_FTCis a ﬁlter quality factor.

-----------------------------------------------------------------------

s²

------------------ ------------------------------------

s

1 +

+

2

Q

_FTC× ω_0FTC

ω_0FTC

The ﬁlter corner frequency is selectable by FTCF[1:0]. The ﬁlter can be bypassed by

setting FTCF to logic 11.

The FTC output can be either an analog AC voltage superimposed on a DC bias level

(FTCSL = 0) or it can be sliced (FTCSL = 1), producing a digital output signal at 3.3 V

CMOS levels. The bias level V_FTC(DC)is generated inside TZA1047.

7.9 Push-pull processor

The detailed block diagram of the P-P processor is shown in Figure 9.

PPTST1

PPBAL

IPPN

D/A

BAL

TBAL

P-P PROCESSOR

DACdump

I

PPN

V

c

GPP

BWPP PPTST1

LPF

R

L

PPOUT

L

B

ppn

I/V

from

Distributor

GAIN

BALANCER

NORMALIZER

PPN

R

B

I/V

0.5 × (L + R )

B

001aab185

R

PPTST

Fig 9. P-P processor.

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The left-hand side of this diagram shows the Balancer and Normalizer sections. The input

signals L and R are low-pass ﬁltered before processing. When balancing is switched on

(bit BAL = 1), it outputs a normalized, current mode, push-pull signal that can be used for

wobble read-out of a pre-groove. The gain balancer is used to balance the low-pass

ﬁltered left and right central spot signals in such a way that the resultant normalized output

signal (ppn) is free of DC. The integrator time constant of the Balancer, τ_PP, is controlled

by parameter TBAL[1:0].

The relationship between the Gain Balancer and Normalizer is given in the following

equations:

L_B= (1 – V_c)L

R_B= (1 + V_c)R

(R_B– L_B)

ppn =

------------------------

(L_B+ R_B)

1

τ_PP

V_c

=

(ppn)dt if BAL = 1

--------

∫

V_c= 0 if BAL = 0

On the right-hand side of the diagram, the balanced and normalized signal ppn is scaled

by current I_PPN, converted to a voltage by R_PPOUTand ﬁnally ampliﬁed at a gain selected

by GPP[3:0]. The output signal is low-pass ﬁltered at an adjustable bandwidth of between

2 MHz and 20 MHz to improve signal-to-noise ratio. The various ampliﬁers and ﬁlters are

controlled by IPPN[3:0], GPP[3:0] and BWPP[2:0]. The components of the output signal

PPN are:

PPN = ppn × I_PPN× R_PPOUT× G_PP

0.05 × k_PPN× IPPN

I

= I

× 10

0, PPN

PPN

where IPPN is the decimal value of control word IPPN[3:0], and k_PPNis the scaling current

factor.

If not used, the P-P Normalizer/Balancer can be switched off to save power by setting bit

PPBAL to logic 0.

The output signal at pin PPN is a bipolar voltage around 0.5V_DD

.

7.9.1 Test mode

The control bit PPTST1 is intended for test and evaluation use only and should be set to

logic 0 for normal operation.

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7.10 EFMTIM Timing

The EFMTIM circuit supplies the various timing signals that are required for the writing

functions. The input and output signals of this circuit are shown in Figure 10.

EFMINT

TH1

TH2

RS

EFMINT

REF/ECN

RS/ECP

INPUT

CIRCUIT

TH1,

TH2,

RS,

r/w

TH1/EDN

TH2/EDP

efmcp

efmcn

efmdp

RWOUT

r/w

EFMTIM

CORE

R/W

SELECT

TIM8

TIMOUT

SMPLON, P/L, L/T, FR, FW, RST,

EFMON, ENRW, ENRS, EFMTST

001aab195

Fig 10. EFMTIM.

The EFMTIM can operate in internal mode (bit EFMINT = 1) or external mode (bit

EFMINT = 0). In internal mode, the various write sampling signals are generated inside

the TZA1047. In external mode, the internal EFMTIM block is disabled and the separate

signals: r/w, RS TH1 and TH2 can be controlled externally via the appropriate pins. In

internal mode, the EFMTIM block can be switched off by setting bit EFMON to logic 0.

This mode can be used to conserve current in sample-less systems. An overview of

EFMTIM modes is given in Table 9.

Table 9:

EFMTIM modes

EFMINT EFMON

Mode

Expected input signals

EFM clock and data

N/A

1

0

1

0

1

0

internal; active

internal; inactive (power save)

do not use^[1]

external

sample signals: RS, TH1 and TH2

[1] This mode is not harmful to the device but does not produce useful results.

7.10.1 Input signals

As the inputs of EFMTIM, in both internal and external modes, are high frequency digital

signals, a special interface is provided to enable the transfer of these signals from the

decoder IC to TZA1047. The exception to this is the signal R/W, which has less stringent

timing requirements and is a normal 3.3 V CMOS level signal. The general principle of the

input circuit is shown in Figure 11.

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PCB or

driver IC

driver IC TZA1047

driver IC

1

driver IC

TZA1047

1

RS,

TH1,

TH2

R

70

Ω

RS,

TH1,

TH2,

Ω

efmdp, efmcp,

efmdn, efmcn

N.C.

−1

EFMD,

EFMC

R

2 × R

70

Ω

REF/ECN

EFMINT = 1

EFMINT = 0

001aab197

Fig 11. EFMTIM input signal connections.

The input circuit is designed to present a low-ohmic, appropriate characteristic termination

to the PCB tracks. To limit EMI, the voltage swing on the PCB track can be kept small by

series resistors placed close to, or inside, the driver IC.

In internal mode, the driving EFMclock and EFMdata signals are supplied as

complementary signals. The inputs of EFMTIM on the TZA1047 act as current

comparators:

efmdp = 1 if I_TH2/EDP> I_TH1/EDN; efmcp = 1 if I_RS/ECP> I_REF/ECN

In external mode, the input signals are single-ended. The input circuit operates in the

same manner as in internal mode, as a current comparator. A reference current equal to

half the maximum input current is supplied to pin EFMREF to provide a threshold value:

RS = 1 if I_RS/ECP> I_REF/ECN; TH1 = 1 if I_TH1/EDN> I_REF/ECNetc.

Note that for the same input slew rate, the resistor values in external mode should be half

the value in internal mode.

To ensure good signal integrity, the currents through the series resistors must not be too

low. The maximum allowable input current for TZA1047 is larger than 5 mA. Using higher

value resistors will reduce power dissipation and will also reduce speed.

7.10.2 Signal generation in internal mode

In the following, the EFM clock and data signals that are routed to the input circuit in

current mode, are represented by the symbols efmc and efmd.

7.10.2.1 r/w signal

The r/w signal selects the read or write mode and can be produced either automatically or

it can be forced externally. In internal mode (bit EFMON = 1, bit FR = 0 and bit FW = 0)

signal r/w is derived from the EFM input signals as shown in Figure 12.

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READ

WRITE

T

EFMc

EFMd

≤ 15 × T

r/w

(18 + D ) × T

1

WRITE

READ

EFMc

EFMd

(18 + D ) × T

1

r/w

mce520

Fig 12. Generation of r/w in internal mode.

When bit FR = bit FW = 0, a transition from read to write is indicated by the occurrence of

two edges in signal efmd within an interval of 15T or less, where T is the period of efmc.

Then r/w goes LOW after (18 + D₁) × T after the ﬁrst edge in efmd, where D₁is a

programmable parameter. A transition from write to read occurs when during an interval of

15T no edges are detected in efmd. Then r/w becomes HIGH after (18 + D₁) × T after the

ﬁnal edge in efmd. Note that the HIGH or LOW state of efmd is irrelevant for read/write

detection, only the occurrence of transitions matter. In general, both efmc and efmd will

become stationary in either LOW or HIGH states during read, although this is not

required.

The status of bits FR and FW control the mode of the r/w signal as shown in Table 10.

Table 10: R/W modes

FW

FR

Mode

r/w

EFMINT = 1

EFMINT = 0

0

internal

determined by

EFM clock and

data

undeﬁned

0

1

0

1

forced read

forced write

external

1

0

1

0

determined by

external R/W

determined by

external R/W

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7.10.2.2 TH1 and TH2

TH1 and TH2 are the sampling signals used in the Input circuit. When bit EFMON equals

bit SMPLON = 1 they are generated according to the timing diagram in Figure 13.

T

T/2

EFMc

EFMd

pit

land

pit

land

pit

(17 + D ) × T

2

pit

land

pit

land

LIGHT

N × T

m × T/2

(L/T = 0)

n × T/2

m × T/2

(L/T = 1)

TH1

(P/L = 1)

2T

TH2

(P/L = 1)

m × T/2

(L/T = 1)

m × T/2

(L/T = 0)

n × T/2

TH1

(P/L = 0)

2T

TH2

(P/L = 0)

mce521

Fig 13. Sampling signals TH1 and TH2.

The auxiliary signal LIGHT represents the laser light. It has a delay (17 + D₂) × T with

respect to signal efmd, where D₂is a programmable parameter that is used to

synchronize signals within TZA1047 with the actual laser light pulse. If bit P/L = 1, TH1

starts in a pit region, if bit P/L = 0, TH1 starts in a land region. The leading edge of TH1

occurs ‘m’ periods of T/2 either after the start (bit L/T = 1) or before the end (bit L/T = 0) of

a pit (bit P/L = 1) or a land (bit P/L = 0). The width of TH1 equals ‘n’ periods of T/2. The

signal TH2 has its rising edge at the falling edge of TH1, and its falling edge 2T later, for all

EFM run lengths.

In the timing diagram, two versions of TH1 and TH2 are shown, for the ﬁrst version,

bit P/L = 1, bit L/T = 1, m = 1, n = 3; for the second version, bit P/L = 0, L/T = 0, m = 3,

n = 2. If bit SMPLON = 0, EFMON = 0 or r/w = 1, signals TH1 and TH2 are always HIGH.

It is possible to disable sampling for a speciﬁc run length of N < N_DIS1, where N is the run

length and N_DIS1is the run length discrimination parameter. TH1 and TH2 will remain

LOW when N < N_DIS1, bit EFMON = bit SMPLON = 1, r/w = 0, and the sample-and-hold

remains in hold. This feature is called run length discrimination and is added, if needed,

to avoid critical timing at very high speeds.

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Sampling on the current run length with length N is disabled if N < N_DIS1. The value of

N_DIS1can be in the range 3 to 6 selected by TIM9[1:0]. If N_DIS1= 3, all run lengths in a

regular EFM-sequence are sampled (no discrimination), if N_DIS1= 4, all run lengths >3T

are sampled, and so on.

7.10.2.3 Signal RS

The signal RS is used in the Normalizer for sampling the RF signal to obtain the reﬂection

from the disc. It is deﬁned in the timing diagram shown in Figure 14.

T

T/2

EFMc

EFMd

pit

land

pit

land

pit

(17 + D ) × T

2

pit

land

pit

land

LIGHT

RS

001aab196

m

× T/2

(n − 2) × T/2

1

Fig 14. Signal RS.

The signal LIGHT is the same signal shown in the timing diagram for TH1 and TH2,

Figure 13. Signal RS is synchronously derived from LIGHT. It is either active or inactive,

deﬁned by bit ENRS and the state of signal r/w. Signal RS is inactive when bit ENRS = 0

or signal r/w = 1; when inactive, signal RS is always HIGH. Signal RS is active when bit

ENRS = 1 and signal r/w = 0; when active, RS goes HIGH m₁× T/2 periods after the

trailing edge of LIGHT (i.e. in the land region), and LOW (n₁− 2) × T/2 periods after the

rising edge of LIGHT, where m₁= 0 to 15 and n₁= 0 to 7. For run lengths of length N × T,

RS remains LOW if m₁/2 ≥ N (run length discrimination). Also, if for a given land region

the rising and falling edges of RS coincide or even reverse in places due to the choice of

values for m₁and n₁, RS remains LOW.

7.10.3 Enabling bits

In internal mode with EFMTIM active or inactive (EFMINT = 1, EFMON = 0 or 1), the state

of the various EFMTIM output signals can be overruled by the enabling bits ENRS, ENRW

and SMPLON according to Table 11. The signals should comply with this table even if

the EFMTIM block has not been reset.

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Table 11: EFMTIM enabling bits

Signal

r/w

Enabling bit

ENRW

Value when enabling bit = 0

1

RS

ENRS . (r/w)

TH1

TH2

SMPLON . (r/w)

1

7.10.4 Signal generation in external mode

In external mode, the EFM timing signals r/w, TH1, TH2, and RS are simply copies of the

signals supplied to the appropriate pins.

7.10.5 Timing parameters

The timing parameters shown in Figure 12, Figure 13 and Figure 14 are controlled by

I²C-bus registers TIM0 to TIM5 as shown in Table 12.

Table 12: Selection of timing parameters

Timing parameter

Register

TIM0[4:0]

TIM1[5:0]

TIM2[2:0]

TIM3[2:0]

TIM4[3:0]

TIM5[2:0]

Range

0 to 31

0 to 49^[1]

0 to 7

D₁

D₂

m

n

0 to 7

m₁

n₁

0 to 15^[2]

0 to 7^[2]

[1] If the value of register TIM1 > 49, D₂will remain at 49T.

[2] Certain values of m₁may cause the rising and falling edges of RS to coincide or to reverse position. In

these cases RS will remain LOW.

The values of run length discrimination parameter N_DIS1are speciﬁed by register TIM9

and are given in Table 13.

Table 13: Selection of run length discrimination

TIM9[1:0]

N_DIS1value

00

01

10

11

3

4

5

6

7.10.6 Miscellaneous

7.10.6.1 RWOUT

The r/w signal is available at pin RWOUT and can be used to drive other circuits such as

the OPU.

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7.10.6.2 TIMOUT

For test purposes, any one of the output signals from the EFMTIM block can be routed to

pin TIMOUT. Signals will be output from pin TIMOUT when bit EFMINT = 1 or 0. The value

of register TIM8[2:0] selects which signal is sent to pin TIMOUT as shown in Table 14.

Note, to allow compatibility with the TZA1039, settings 001 and 010 are not used.

Table 14: TIMOUT signal selection

TIM8[2:0]

000

Signal at pin TIMOUT

LOW (0 V)

LIGHT

RS

001

010

011

100

r/w

101

TH1

110

TH2

111

HIGH (V_DD)

7.10.6.3 Bit RST

The EFMTIM block has a local reset input which is software-controlled by bit RST. The

EFMTIM asynchronous reset circuit has to be loaded serially by setting bit RST with the

sequence 0, 1, 0. The reset is actually established after less than 16 edges in signal

EFMc.

After reset, the output signals are left in read state (r/w = RS = TH1 = TH2 = HIGH).

7.10.6.4 Bit EFMTST

Bit EFMTST is used for test purposes only and should be set to logic 0 for normal

operation.

7.11 Normalizer

The Normalizer block produces the servo error signals from the current mode signals Q1

to Q6. It consists of various sub-blocks shown in Figure 15.

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Q/NE, ALF1/2, S4/8, CA/PP

mir

satsum

Q

Q1 to Q6

AUX

SNORM

QM1 to QM6

QT1 to QT6

FEN4/2

PFEN

I

OF , OF

R W

DOC1

r/w

Q1 to Q4

FEN

FOC

MON

(1) n.c.

(2) TLN

(3) REN

(4) FEN

(5) MIRN

(6) XDN

I

DOC2

DOC3

REN4/2, PREN, DPD, PXDN,

RFCAL, S4/8, CA/PP

rfcal

Q/NE

MON

XDN

REN

MON

Q1 to Q6

RAD

DTDp, DTDn

(1) D1

(2) D2/TLN

(3) D3/REN

(4) D4/FEN

(5) S1/MIRN

(6) S2/XDN

(1) QT1

(2) QT2

(3) QT3

(4) QT4

RTLN, PTLN,

CLMP, CA/PP

I

DOC4

DPD

(5) QT5

(6) QT6

Q

SNORM

Q1 to Q6

satsum

TL

TLN

MON

(5) DTDp

(6) DTDn

VARP, ALF1/2

MIR1/2,

BWRS

I

MIR

I

, I

,

TW

, I , I

r/w

RS

TR

N1 N2 N3

r/w

I

rf-norm

DOC1

CAN

DOC

to

LASP

mir

I

DOC4

MIRN

CANORM

MIRNMON

SLASP

srf

CANMON

CANALF

satsum

001aab194

Fig 15. Normalizer sub-blocks.

The normalized error signals FEN, REN, TLN, MIRN and XDN from the Normalizer

sub-blocks are multiplexed with signals Q1 to Q6, controlled by bit Q/NE. If Q/NE = 1

(direct mode) the Normalizer circuits and associated DACs are switched off to save power.

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7.11.1 Auxiliary block

Q/NE, ALF1/2,

S4/8, CA/PP

mir

satsum

AUX

Q1 to Q6

Q

SNORM

QM1 to QM6

QT1 to QT6

001aab192

Fig 16. AUX block.

The AUX block produces the auxiliary signals QM1 to QM6, QT1 to QT6, Q_SNORM, satsum

and mir which are deﬁned as:

QM1 to QM6 = Q1 to Q6 (routed to MON block).

QT1 to QT6 = Q1 to Q6 (routed to output).

Q

_SNORM= Q₁+ Q₂+ Q₃+ Q₄.

satsum = Q₅+ Q₆(switched off when ALF1/2 = 0).

The mirror signal mir components are deﬁned in Table 15.

Table 15: Signal mir components

Bit S4/8

Bit CA/PP

Signal mir

Q_SNORM

0

1

0

1

0

1

Q_SNORM

Q₅+ Q₆+ Q_SNORM

Q₅+ Q₆

7.11.2 Dropout concealment block (normalizer sub-block)

The DOC block produces currents I_DOC1to I_DOC4(I_DOCi) for the Normalizer circuits within

sub-blocks FOC, RAD and TL.

A Normalizer circuit N with input currents I₁and I₂produces the following

dropout-concealed output current I_O:

I₁– I₂

I_O

=

× I

---------------

DOC

I₁+ I₂

where I_DOCis a dropout-concealed scaling current, produced by the DOC block, that is

chosen according to the modulation depth of the signal to be normalized.

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The dropout-concealed scale currents I_DOCiare deﬁned as I_DOCi= G_DOC× I_Ni, where I_Ni

are programmable reference currents (I_N1to I_N4) and scale factor G_DOCis deﬁned by:

G_DOC= 1 if CAN > I_T

G_DOC= CAN/I_Tif CAN ≤ I_T

where I_Tis the threshold level for dropout-concealment with which the normalized sum

current CAN is compared. If CAN drops below I_T, the scale factor G_DOCwill decrease

linearly with CAN in order to prevent ‘dividing by zero’. There is a threshold I_TWfor write

and a threshold I_TRfor read: I_T= I_TWif r/w = 0, I_T= I_TRif r/w = 1. The currents I_Ni, I_TWand

I_TRare programmable via the I²C-bus.

7.11.3 Focus servo signal block (normalizer sub-block)

The FOC block produces a normalized focus error signal FEN. A detailed block diagram of

the FOC block is shown in Figure 17.

I

DOC1

N

FEN4/2

PFEN

Q1

Q3

FEN

+/−

0.5

r/w

I

DOC1

N

OF

W

Q4

Q2

OF

R

mce526

Fig 17. FOC block.

Signal FEN is based on either 2 or 4 input currents selected by bit FEN4/2. Setting

bit FEN4/2 to logic 1 selects all four input currents. The normalizer blocks (N) perform the

same function in the DOC block described in Section 7.11.3. An offset can be applied to

compensate for chromatic aberration in the optics. The offset signal (either OF_Wor OF_R)

is selected by the state of signal r/w; if r/w = 1 (read mode) OF_Ris used. The polarity of

signal FEN is reversed by setting bit PFEN to logic 1. Signal FEN is available at output D4

by setting bit Q/NE to logic 0, and is also routed to the MON block for test purposes. The

relationship between the FEN signal components is shown in Table 16.

Table 16: FEN signal (bit PFEN = 0)

Bit FEN4/2

Signal FEN^[1]

0

1

N[Q1, Q3] × G_DOC× I_N1+ OF

{N[Q1, Q3] × G_DOC× I_N1+ N[Q4, Q2] × G_DOC× I_N1} × 0.5 + OF

[1] OF = OF_wif r/w = 0, OF = OF_Rif r/w = 1.

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7.11.4 Radial servo signal block (normalizer sub-block)

The RAD block produces a normalized radial error signal REN. A detailed block diagram

of the RAD block is shown in Figure 18.

S4/8, CA/PP

I

REN4/2, CA/PP

S4/8

DOC2

N

DPD

PREN

Q1 to Q6

LPF1

+/−

REN

REN to MON

DTDp

DTDn

CMPP

+

−

S4/8, CA/PP

I

DOC3

N

PXDN

XDN to MON

RFCAL

Q1 to Q6

+/−

XDN

001aab190

rfcal

Fig 18. RAD block.

Signal REN is based on either 2 or 4 input currents selected by bit REN4/2 and bit DPD.

Setting bit DPD and bit REN4/2 both to logic 0 selects the associated tracking methods:

1-spot PP (4 segments), 3-spot CA or 3-spot PP. Setting bit DPD to logic 0 and REN4/2 to

logic 1 selects associated tracking method 1-spot PP (8 segments). For this method the

offset correction signal obtained from the lower branch is low-pass ﬁltered before it is

added to the main normalized PP signal. An external capacitor named CCMPP,

connected to pin CMPP, deﬁnes the −3 dB frequency of the ﬁlter. If bit DPD = 1 the

tracking method is DPD, and REN is obtained from the difference between Q5 and Q6.

The polarity of signal REN is reversed if bit PREN is set to logic 1. If bit Q/NE = 0, signal

REN is available at servo output pin D3 and is also routed to the MON block for test

purposes. The relationship between the REN signal components is shown in Table 17.

Table 17: REN signal (bit PREN = 0)

Bit S4/8

Bit CA/PP Bit

REN4/2

Bit DPD

Signal REN

0

1

0

1

X

1

0

X

0

1

N[(Q1 + Q3), (Q2 + Q4)] × G_DOC× I_N2

N[Q5, Q6] × G_DOC× I_N2

1

X

1

N[(Q1 + Q3), (Q2 + Q4)] × G_DOC× I_N2+ LPF1[N(Q5, Q6) × G_DOC× I_N3

N[(Q1 + Q3 + Q6), (Q2 + Q4 + Q5)] × G_DOC× I_N2

DTD_p− DTD_n

]

X

An additional signal XDN (normalized spot position) is generated based on 3-spot PP,

1-spot PP (4 segments) or 1-spot PP (8 segments). The XDN signal can be inverted by

setting bit PXDN to logic 1. The XDN signal is also routed to the MON block for test

purposes.

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If bit RFCAL = 1, output XDN provides an ampliﬁed, low-pass ﬁltered version of signal

rf-cal (see Section 7.6). This can be used to eliminate the offset in the RF path.

Note that the rf-cal output is unipolar, so only positive outputs are possible. If bit

Q/NE = 0, signal XDN (or rf-cal) is output at pin S2.

The relationship between the XDN signal components is shown in Table 18.

Table 18: XDN signal (bit PXDN = 0)

Bit S4/8

Bit CA/PP

Bit RFCAL

Signal XDN

0

X

1

X

0

1

0

X

0

1

N[Q5, Q6] × G_DOC× I_N3

N[(Q1 + Q3), (Q2 + Q4)] × G_DOC× I_N3

N[(Q1 + Q3 + Q5), (Q2 + Q4 + Q6)] × G_DOC× I_N3

rfcal

Calculation of XDN gain: In TZA1047/M1 XDN was a voltage output on a 1.3 V bias level,

made with a conversion resistance of 80 kΩ. This was connected to S2 on centaurus1

with a 100 series resistor. The reference voltage on S2 was set to 1.2 V. With a second

resistor, a bias current was added to have a 6 µA bias level. (S2 is a 12 µA range unipolar

input).

This situation resulted in a full range (6 µA) swing with IN3 = 0h so Idoc3 = 16 µA.

Calculating back, the modulation on XDN is (6 µA × 80/100)/16 µA = 30 %. This is more

than expected but will be accepted as a fact of life.

Intermezzo: XDN is used to measure lens position. The beam is 3.5 mm diameter through

the lens, the position shift range required is 0.4mm. This is 11.5 %, but XDN will not be

linear with position because the beam intensity in the middle is higher than at the edges.

Calculation for TZA1047/M2: Assume 30 % modulation. XDN will be connected to D2, a

bipolar input with ±12 µA range. The nominal reference current should be

12 × (1/0.3) = 40 µA. By using I_N3= 4 + 4 × IN3, this is achieved at IN3 = 9h which is nicely

in the middle of the range.

7.11.5 Track loss servo signal block (normalizer sub-block)

The TL block produces a normalized track loss error signal TLN. A detailed block diagram

of the TL block is shown in Figure 19.

RTLN

I

PTLN

CLMP

I

CL

DOC4

N

CA/PP

Q

1/3

SNORM

+/−

CLAMP

TLN

Q5, Q6,

Q

snorm

TLN to MON

001aab191

Fig 19. TL block.

If bit RTLN = 1, signal TLN is only valid for the tracking methods 3-spot CA and 3-spot PP.

If bit RTLN = 0, signal TLN is the low-pass ﬁltered central sum signal Q_S, scaled with a

factor of ¹⁄₃.

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Signal TLN (both positive and negative components) can be clamped to a maximum value

I_CLin order to deal with media that have a high and low modulation depth of TLN on one

disc (e.g. written and blank regions). The clamp can be enabled or disabled by bit CLMP.

The signal should recover from the clamped state within 2 µs. The polarity of TLN is

reversed by setting bit PTLN to logic 1. Signal TLN is sent as signal D2 to the output if

bit Q/NE is logic 0. The TLN signal is also routed to the MON block for test purposes. Note

that this version of the TLN signal routed to the MON block is not clamped. The

relationship between the TLN signal components is shown in Table 19, (note that

Q5 + Q6 = satsum):

Table 19: TLN signal (bit PTLN = 0)

CA/PP

RTLN

TLN

0

1

X

1

0

N[Q_SNORM, (Q5 + Q6)] × G_DOC× I_N4

N[Q_SNORM, (Q5 + Q6)] × 2 − Q_S] × G_DOC× I_N4

Q_SNORM/3

When not used, the TLN circuit can be switched off by setting the DOC current to zero,

IN4[3:0] = 0000.

7.11.6 CA signal block (normalizer sub-block)

The CANORM block produces normalized error signal MIRN.

RS

BWRS

LPF2

MIR1/2

srf

rf-norm

ALF1/2

mir

r/w

I

0

IMIR

CANtest

satsum

INA

r/w

0

MIRN

CAN

CANT

MIR1/2

4.0

VARP

RS

I

01

I

PR

18.0

LPF2

ALF1/2

r/w

LASP

4.0

8.0

BWRS

SLASP

001aab186

0

Fig 20. CANORM block.

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When signal RS is active, signal rf-norm is sampled and ﬁltered and then normalized to

the laser power. When rf-norm is sampled and ﬁltered, externally sourced signal LASP

must also be sampled and ﬁltered in order to obtain a quotient which is a normalized

reﬂection signal free of EFM. Signals srf and SLASP are the sampled and ﬁltered versions

of rf-norm and LASP, respectively, which are used in the ALFA block. The ﬁlter corner

frequency is selectable by bit BWRS. For high speeds, the ﬁngerprint correction loop has

to be faster than at low write speeds. For dye media, the laser power does not vary during

sampling, however, the LASP signal does vary during sampling. In these situations, a

reference current I_PRis used as a read power reference. Signal srf is also used to produce

the disc reﬂection signal CAN via a divider circuit which is routed to the DOC and MON

blocks.

A test mode is entered by setting bit CANtest to logic 1. CANtest is controlled from the

TEST block via register TST[2:0], bit CANtest is logic 1 if TST[2:0] = 001. In this mode,

signal CAN can be forced externally via pin TEST (signal CANT). This mode can be used

to facilitate debugging and testing of the DOC and ALFA blocks without having to set-up

an RF signal input.

Mirror signal mir must be normalized to the laser power. Signal mir is derived from signals

Q1 to Q6 which have been sampled and ﬁltered in the Input circuit. Because signal mir is

already sampled and ﬁltered, signal LASP must also be sampled and ﬁltered in order to

produce a quotient signal MIRN which is a normalized reﬂection signal free of EFM. In

some situations the laser power does not vary during sampling, while LASP does. In those

situations, a reference current I_PRis used as a read power reference. Signal I_PRshould be

used in writing modes for which the LASP input signal is carrying ALFA information (e.g.

reﬂection control for phase change media writing). This is because if ALFA information is

used in the calculation instead of a ﬁxed reference power, it would render the result of the

block invalid. If signals Q1 to Q6 are not sampled during write, the mirror signal MIRN

must be based on rf-norm, which is selected by setting bit MIR1/2 to logic 0. If bit

Q/NE = 0, signal MIRN is routed as signal S1 to the output, and is also routed to the MON

block for test purposes.

7.11.7 Output current polarities

The currents TLN, REN, FEN and XDN are bipolar currents, and if bit Q/NE = 0, are

routed to servo current outputs D2, D3, D4 and S2 respectively. The current MIRN is

unipolar, and if bit Q/NE = 0, is routed to servo current output S1. It is negative according

to the deﬁnition used in this document, i.e. sourced by TZA1047. The internal servo

currents Q1 to Q6 are unipolar currents, and if bit Q/NE = 1, are routed directly to D1 to

D4, S1 and S2, and are sourced by the TZA1047.

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7.11.8 Normalizer block I²C-bus control signal overview

Table 20: Normalizer single bit I²C-bus controls

Signal name

S4/8

1

0

central 4-segment detector mode

central aperture mode

central 8-segment detector mode

push-pull mode

CA/PP

FEN4/2

PFEN

normalized focus error signal from 4 inputs

inverted focus error polarity

normalized focus error signal from 2 inputs

normal focus error polarity

REN4/2

PREN

normalized radial error signal from 4 inputs normalized radial error signal from 2 inputs

inverted radial error polarity

normal radial error polarity

normal spot position polarity

PXDN

inverted spot position polarity

connect rf-cal signal to XDN output

RFCAL

normal XDN output (x-position output

voltage)

DPD

DPD tracking method ON

DPD tracking method OFF

PTLN

RTLN

CLMP

Q/NE

VARP

inverted track loss signal polarity

TLN signal for 3-spot CA and PP methods

activate TLN signal clamp

normal track loss signal polarity

TLN signal derived from central sum signal

disable TLN signal clamp

detector signals on servo outputs

error signals on servo outputs

use internal read power reference I_pr

use LASP input signal as read power

reference

MIR1/2

ALF1/2

MIRN signal based on Q1 to Q6 signals

INA signal based on Q5 + Q6 signals

MIRN signal based on rf signal

INA signal based on rf signal

Table 21: Normalizer analog control parameters set via I²C-bus

Register

IMIR[3:0]

OFR[3:0]

OFW[3:0]

IN1[3:0]

IN2[3:0]

IN3[3:0]

IN4[3:0]

ITW[3:0]

ITR[3:0]

Name # bits Purpose

Step size Min

Max

24

Unit

µA

I_MIR

OF_R

OF_w

I_N1

4

current level setting for MIRN signal

1.5

0.5

2

1.5

−4

4

focus error offset for read mode

+3.5

34

focus error offset for write mode

normalizer reference current for FEN signal

normalizer reference current for REN signal

normalizer reference current for XDN signal

normalizer reference current for TLN signal

dropout-concealment threshold value for write mode

dropout-concealment threshold value for read mode

I_N2

10

4

10

4

160

64

I_N3

I_N4

10

0.4

0

150

6.4

I_TW

I_TR

0.4

6.4

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7.12 ALFA

Preprocessor IC for CD and DVD rewritable

7.12.1 ALFA measurement circuit for running OPC

A detailed block diagram of ALFA is shown in Figure 21.

SQRT

INA

I

LASP

AN

alfa-mon

ALFA

1/7

SLASP

001aab189

I

ref(ALFA)

Fig 21. ALFA block.

The ALFA block measures the ALFA parameter to produce an error signal for use in the

running-OPC control loop of a phase change media writer. For phase change media, the

laser power incident at the recording layer is calculated, and is derived from the reﬂection

signal (’reﬂection measurement’). Two methods for measuring the ALFA parameter are

implemented. Both methods are selected by bit ALF1/2, and are deﬁned below.

7.12.1.1 Phase change media

The ALFA measurement is either based on central spot detection (bit ALF1/2 = 0) or on

satellite spot detection (bit ALF1/2 = 1). In the former case, sampling during the erase

period of rf-norm takes place using RS in the CANORM block; in the latter case sampling

is implemented in the input circuit.

For phase change media the alfa signal produced is either proportional to ‘P × R’ or to

‘P√R’, where P is the optical power and R is the reﬂection. These quantities are measured

in the laser power incident on the recording layer. There are two methods deﬁned.

The ﬁrst method for phase change media (bit ALF1/2 = 1) uses the signals from the

satellite spots to measure the disc reﬂection. The reﬂection signal is the satellite sum

signal satsum, normalized to the sampled power signal SLASP. If bit SQRT = 1, a

square-root operation is applied and the result is multiplied by LASP to give signal alfa-pc.

The second method for phase change media (bit ALF1/2 = 0) uses the signal from the

central spot rather than from satellite spots to measure the disc reﬂection. The reﬂection

signal is the sampled rf-signal srf, normalized on the sampled power signal SLASP.

The switching over between sampled signals rf and satsum, as well as the switching of

sampled signal LASP by bit ALF1/2 is implemented in the CANORM circuit.

The relationship between the various signals used to produce the ALFA signal for both

states of bit SQRT is shown in Equation 5 and Equation 6.

For SQRT = 0:

I_AN

------------------------- -----------------

I_{ref (ALFA)}SLASP

INA

ALFA =

×

× LASP

(5)

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Preprocessor IC for CD and DVD rewritable

For SQRT = 1:

I_AN

INA

ALFA =

×

----------------- × LASP

SLASP

(6)

-------------------------

I_{ref (ALFA)}

The ﬁnal transfer functions for the ALFA block, including the CANORM block, are given in

Table 22. LASP (sampled) is the optionally sampled LASP signal in the CANORM block

(see also Figure 20).

Table 22: ALFA signal

Bit ALF1/2

Bit SQRT

Signal ALFA

1

0

I_AN

------------------------- ---------------------------------------------------

I_{ref (ALFA)}8 × LASP(sampled)

satsum

ALFA =

×

× LASP

1

0

1

0

1

I_AN

satsum

×

-------------------------------------------------- × LASP

8 × LASP(sampled)

-------------------------

I_{ref (ALFA)}

I_AN

srf

×

× LASP

------------------------- ---------------------------------------------------

I_{ref (ALFA)}4 × LASP(sampled)

I_AN

srf

-------------------------------------------------- × LASP

4 × LASP(sampled)

×

-------------------------

I_{ref (ALFA)}

7.12.1.2 ALFA circuit general

The ALFA block is enabled by setting bit ENALF to logic 1. When bit ENALF = 0, the ALFA

output current remains at zero and the circuit is powered down to save power. Signal

ALFA is also automatically switched off in read mode when bit r/w = 1. A copy of signal

ALFA (alfa-mon) output current is routed to the MON block for test purposes. The polarity

of the ALFA output signal current is negative, i.e. the current is sourced by TZA1047.

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7.13 BETA

Preprocessor IC for CD and DVD rewritable

The BETA block delivers signals that are used in the write power calibration procedure at

disc start-up. A detailed block diagram of the BETA block is shown in Figure 22.

I

BS

BCTL

+

PEAK

DETECTOR

V

A1

BETA

−

BCTL

LPF

rf-beta1

rf-beta2

CA1

CALF

A2

BCTL

CCALF

+

−

PEAK

DETECTOR

mgw493

CA2

Fig 22. BETA block.

The BETA circuit uses the input signal rf-beta from the RF Ampliﬁer to produce the RF

average level output signal CALF and the RF top and bottom peak level output signals A1

and A2. The relationship between the various BETA block signals are given by equation

Equation 7, Equation 8 and Equation 9, where rf = rf-beta1 = rf-beta2.

LPF(rf)

I_BS

CALF =

× V

(7)

(8)

(9)

--------------------

BETA

[rf – LPF(rf )]

A1 =

A2 =

^peak× V

------------------------------------------------

BETA

I_BS

[(LPF(rf) – rf )]

^peak× V

---------------------------------------------------

BETA

I_BS

The DC gain (in read mode) between signals (RFP to RFN) and signals A1, A2 and CALF

is given by:

V_BETA

G_BETA

=

× G

-------------------------------

RFR

I_BS× R_rf× 2

The gain can be controlled by parameter IBS. The typical value of V_BETAis 2.5 V and

value I_BS= 5 × (1 + I_BS) µA. Furthermore R_RF= 2.5 kΩ, resulting in G_BETA= 100/(1 + I_BS).

Both the peak detector time constant and the CALF low-pass ﬁlter can be adjusted to the

disk speed by parameter BCTL[2:0]. The seven different time constant settings for the

low-pass ﬁlter allow its frequency range f_LPFto be set from 500 Hz to 32 kHz.

To save power, the BETA block and its DAC can be switched off completely by setting

parameter BCTL[2:0] to 111. If the BETA block and its DAC are switched off, the −3 dB

frequency and time constant will not be deﬁned.

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Preprocessor IC for CD and DVD rewritable

A graphical representation of the BETA measurement is shown in Figure 23.

EFM

signal

A1

A2

A1

A2

CALF

P < P_opt

P > P_opt

mce534

P = instantaneous laser power.

P_opt= optimum laser write power setting.

Fig 23. BETA measurement.

7.14 Monitor block

The MON block is intended for application tests and is never used during normal

operation. It converts two bipolar current input signals to two bipolar (w.r.t 0.5V_DD) voltage

mode outputs. The two current input signals can be selected from various internal

currents by I²C-bus control word MSEL[7:0]. The conversion resistance from current to

voltage is typically 80 kΩ. The bandwidth of the monitor circuit is 100 kHz. The monitor

block is speciﬁed for an external load of 10 pF and 10 kΩ to GND.

Table 23 shows the MSEL[7:0] values for selecting the two input currents to be converted

and sent to monitor outputs MON1 and MON2.

Table 23: Monitor selection

MSEL7 MSEL6 MSEL5 MSEL4 MON2 MSEL3 MSEL2 MSEL1 MSEL0 MON1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

REN

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

REN

TLN

FEN

MIRN

ALFA/7

XDN

MIRN

ALFA/7

XDN

CAN

res.

Q1/10

Q2/10

Q3/10

Q4/10

Q5/10

Q1/10

Q2/10

Q3/10

Q4/10

Q5/10

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Preprocessor IC for CD and DVD rewritable

Table 23: Monitor selection …continued

MSEL7 MSEL6 MSEL5 MSEL4 MON2 MSEL3 MSEL2 MSEL1 MSEL0 MON1

1

0

1

0

1

Q6/10

res.

1

0

1

0

1

Q6/10

res.

The selection tables for MON1 and MON2 are identical so each signal can be sent to

either output. Selecting the same signal for both monitor outputs (bits

MSEL[7:4] = MSEL[3:0]) switches off the MON block, which reduces the power dissipation

during normal operation.

7.15 I²C-bus interface and registers

7.15.1 General description

Most functions in the TZA1047 are controlled via an I²C-bus interface conforming to the

fast-mode speciﬁcation, allowing data transfers of up to 400 kHz. The write address of the

TZA1047 is 34h; this is also the write address of the TZA1039.

There are 52 read/write data registers. The register that is written to is determined by

sub-address bits 4 to 0 which is in the ﬁrst 8-bit word that is transmitted after the device

address. Bit 7 of the sub-address controls the auto-incrementing of the sub-address:

bit 7 = 0 enables auto-incrementing and wrap-around, bit 7 = 1 disables

auto-incrementing so that the same register is written to each time. Examples of valid

write transmissions are shown in Figure 24.

write one

register:

START

BIT

ADDRESS

34h

SUB-ADDRESS

00h

DATA

00h

STOP

BIT

write with

auto-increment:

START ADDRESS SUB-ADDRESS DATA

BIT 34h 00h 00h

DATA

01h

DATA

STOP

BIT

write with

wrap-around:

START ADDRESS SUB-ADDRESS DATA

BIT 34h 31h 31h

DATA

00h

DATA

01h

DATA

STOP

BIT

write without

auto-increment:

START ADDRESS SUB-ADDRESS DATA

BIT 34h 85h 05h

DATA

05h

DATA

05h

STOP

BIT

001aab425

Fig 24. Examples of valid write transmissions.

TZA1047 also supports read back of register data via the I²C-bus. It does not generate

any data itself. The only possibility is to read back previously written data, e.g. to check

the connections to the device or to check the registers after start-up. Read-back mode is

selected by setting the LSB of the device address to logic 1. After sending the device

address, the TZA1047 will start returning register data starting at the last written

address. Auto-increment and wrap-around are supported in the same way as for write.

Before starting read back it is good practice to ﬁrst initialize the starting address by issuing

a write command.

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Preprocessor IC for CD and DVD rewritable

Examples of valid read transmissions are shown in Figure 25.

READ-BACK

ADDRESS

35h

read one

register:

START ADDRESS SUB-ADDRESS STOP START

BIT 34h 00h BIT BIT

DATA STOP

00h BIT

READ-BACK

ADDRESS

35h

read with

auto-increment:

START ADDRESS SUB-ADDRESS STOP START

BIT 34h 00h BIT BIT

DATA DATA DATA STOP

00h 01h BIT

READ-BACK

ADDRESS

35h

read with

auto-increment

wrap-around:

START ADDRESS SUB-ADDRESS STOP START

BIT 34h 31h BIT BIT

DATA DATA DATA DATA STOP

31h 00h 01h BIT

READ-BACK

ADDRESS

35h

read without

auto-increment:

START ADDRESS SUB-ADDRESS STOP START

BIT 34h 85h BIT BIT

DATA DATA DATA DATA STOP

05h

BIT

001aab426

Fig 25. Examples of valid read transmissions.

7.15.2 Power-on reset

The TZA1047 is equipped with a Power-on reset circuit to avoid unwanted situations at

start-up. This will reset some, but not all, registers to a predeﬁned state. Only those

registers that could cause damage or unwanted states are initialized, all other register bits

should be initialized by the controller prior to operation; they will contain random data after

start-up.

The states of the relevant bits are given below:

STBY = 1; EFMTST = 0.

It is decided not to reset RST, ENRS, ENRW and SMPLON. To assure proper operation of

the sample signals without running EFMTIM these signals need to be set via I²C-bus ﬁrst.

Reason not to do this is to limit the complexity of the change to I²C-bus FSB.

The Power-on reset circuit monitors the supply voltage between GNDD and V_DDD. Reset

occurs when the supply voltage is less than 3.3 V.

The registers are deﬁned in Table 24.

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

7.16 Fast serial bus and registers

7.16.1 Fast serial bus description

The fast serial bus interface has three lines: a data line SIDA, a clock line SICL and a

strobe line SILD. The bus circuitry consists of a serial input shift register and several

registers that store the data. During a transmission the data is ﬁrst clocked into the shift

register. On the rising edge of SILD the contents of the input register are copied into the

addressed register. From that moment the programmed settings become effective. As

long as SILD is HIGH, the TZA1047 will not respond to SIDA and SICL. Examples of

one-word and two-word transmissions are shown in Figure 26 and Figure 27.

7.16.2 Serial bus control timing

SICL

t

LOW

HIGH

t

SU;STA

t

T

HD;DAT

CLK

t

SU;DAT

SIDA

SILD

D0

A3

t

SU;LD

mce536

Fig 26. One-word transmission.

SICL

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 A0 A1 A2 A3

D0 D1 D2 D3 D4

A1 A2 A3

SIDA

SILD

t

HIGH;LD

mce537

Fig 27. Example of a two-word transmission.

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TZA1047

Philips Semiconductors

7.16.3 Operation

Preprocessor IC for CD and DVD rewritable

The fast serial bus is used to program those registers that require a fast update rate: GRF

(RF path VGA), DCRF (RF path DC compensation, used as a quasi AC-coupling) and

GPP (P-P Processor Ampliﬁer gain). These three parameters can be controlled in

closed-loop mode by the codec IC to achieve AGC for both the RF path and the push-pull

path. The I²C-bus is not fast enough to allow this type of operation. The FSB interface will

support clock speeds of up to 16 MHz.

There is no power-on reset function in the TZA1047 fast serial bus interface. Before

start-up, the registers will contain random data. Therefore, to ensure correct operation, all

registers must be written to at least once after start-up.

7.16.4 Fast serial bus control registers

Table 25: Fast serial bus register layout

ADDR.

[3:0]

D11

D10 D9 D8 D7

D6

D5

D4

D3

D2

D1

D0

0011

0100

0101

1100

res^[1]

res

res res GRF[3] GRF[2] GRF[1] GRF[0] res

res

res res res

res

DCRF[5] DCRF[4] DCRF[3] DCRF[2] DCRF[1] DCRF[0]

res

RDCRF PDCRF

res

GPP[3] GPP[2] GPP[1] GPP[0]

[1] res = reserved.

The FSB control register addresses are backwards compatible with the TZA1031 and

TZA1039 devices.

8. Limiting values

Table 26: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

−0.5

0

Max

Unit

supply voltage

+5.5

V

V_i

input voltage

V_DD+ 0.5 V

T_amb

T_stg

ambient temperature

storage temperature

70

°C

−55

−2000

+125

+2000

°C

[1]

[2]

V_esd

electrostatic discharge voltage human body

model

V

machine

model

−150

+150

V

[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.

[2] Equivalent to discharging a 200 pF capacitor via a 2.5 mH series inductor.

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Preprocessor IC for CD and DVD rewritable

9. Characteristics

Table 27: Characteristics

Symbol

Input circuit signal range

V_iinput signal

Parameter

Conditions

Min

Typ

Max

Unit

[1]

pins VIA to VIH (versions M1A,

M1B and M2)

V

_REF− 0.0

_REF− 0.05

-

V_REF+ 1

V

pins VIA to VIH (version M3)

V

Input circuit ﬁxed parameters

Z_o(VREF)

external output

impedance of pin

VREF

-

40

Ω

I_o(VREF)

output current

−0.5

+25

mA

capability of pin VREF

Input circuit programmable parameters

Z_i(seg)

G_(seg)

V_ref

segment signal input LDSEG[1:0] = 00

112

225

450

10

150

300

600

-

200

400

800

-

Ω

impedance (VIA to

VIH with respect to

pin VREF)

LDSEG[1:0] = 01

LDSEG[1:0] = 10

LDSEG[1:0] = 11

GSEG[1:0] = 00

GSEG[1:0] = 01

GSEG[1:0] = 10

GSEG[1:0] = 11

Ω

kΩ

gain of segment

signal (VIA to VIH) to

DPD

0.45

0.9

0.5

1.0

2.0

4.0

1.3

2.8

0.55

1.1

1.8

2.2

3.6

4.4

reference voltage for VSEG[3:0] = 0000

1.17

2.52

1.43

3.08

V

segment and RF

inputs

VSEG[3:0] = 1111;

V_REF= 1.3 + 0.1 × VSEG

Distributor ﬁxed parameters

R_FTC

conversion resistance

for signals to FTC

17

20

23

kΩ

R_PP

conversion resistance

for L and R signals to

the P-P processor

R_Q

conversion resistance

for Q signals

4

-

5

-

6

4

kΩ

%

∆f_servo

f_servo

/

matching error LPF1

between channels

∆Q_i/Q₁₂₃₄

matching error

Q₁₂₃₄= ΣQ_i/4 (i = 1 to 4);

-

%

between signals Q1 to input = 0.05 V to 1.0 V;

Q4

V_A= V_B= V_C= V_D; SMPLON = 0;

CALSAT = 0; G_CAL= 1.0 V

∆Q_i/Q₅₆

matching error

between signals Q5

and Q6

Q₅₆= ΣQ_i/2 (i = 5 and 6);

input = 0.05 V to 1.0 V;

V_E= V_F= V_H= V_G; SMPLON = 0;

CALSAT = 0; G_CAL= 1.0; DPD = 0;

GRAT = 0; AT[7:0] = 128

-

5

%

B_LR

−3 dB bandwidth of

signals L and R

SMPLON = 0

SMPLON = 1

90

2

-

MHz

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Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

B_FTC

−3 dB bandwidth of

4

-

MHz

FTC input signals

I_PPOFF

R/L common mode

offset current

TZA1047/M1A and M1B

TZA1047M2

-

0

4

-

µA

Distributor programmable parameters

γ

grating ratio factor

GRAT = 0; γ = 0.5 + 0.0117 × AT

AT[7:0] = 00h

-

0.5

3.5

-

AT[7:0] = FFh

GRAT = 1; γ = 2.0 + 0.0117 × AT

AT[7:0] = 00h

-

2.0

5.0

-

AT[7:0] = FFh

I_OO(RL)

R/L offset current

I_RLOFF= 0.79 µA × RLOFF

RLOFF[5:0] = 00h

-

0

-

µA

RLOFF[5:0] = 3Fh

45

50

55

I_O(A-H)

segment signals A to r/w = 0;

H offset current

I_Oi= (−10 + W_iO× 0.66) µA;

i = A to H

r/w = 1;

I_Oi= (−10 + R_iO× 0.66) µA;

i = A to H

[1]

control register = 00h

control register = 1Fh

-

−10

10

-

µA

∆I_OO(A-H)

segment signals A to

H offset current step

size

0.66

G_cal

segment calibration

signal gain

GCAL[1:0] = 00

GCAL[1:0] = 01

GCAL[1:0] = 10

GCAL[1:0] = 11

BWSER = 0

0.45

0.5

1.0

2.0

4.0

60

0.55

0.9

1.1

1.8

2.2

3.6

4.4

B_LPF1

−3 dB bandwidth of

50

70

kHz

MHz

LPF1 (Q signals)

BWSER = 1

170

200

40

230

B_LPF2

−3 dB bandwidth of

LPF2 (L and R

signals)

BWPP1[2:0] = 000

BWPP1[2:0] = 001

BWPP1[2:0] = 010

BWPP1[2:0] = 011

BWPP1[2:0] = 100

BWPP1[2:0] = 101

BWPP1[2:0] = 11X

BWPP2[1:0] = 00

BWPP2[1:0] = 01

BWPP2[1:0] = 10

BWPP2[1:0] = 11

-

80

-

160

320

640

1300

-

> 65000

B_LPF3

−3 dB bandwidth of

LPF3 (P-P signals)

-

15

-

30

-

60

> 65

-

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Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

RF ampliﬁer signal range

[2]

V_i(dif)

V_i(se)

V_i(ref)

input voltage

differential inputs

(RFPIN, RFNIN)

differential

0

-

2

V

single-ended

1.0

V

_DD− 1

input voltage

single-ended inputs

(WRF, RRF)

1.0

-

V

RF voltage reference DRVON = 1

input (RFREF)

1.0

-

2.5

V

V_RFa(max)

V_RFb(max)

V_o(dif)(RF)

maximum voltage rf_ar/w = 0

-

2

V

maximum voltage rf_br/w = 1

-

0.6

+1

+2

RF differential output G_RF= 8 dB; HA = 0; ENNF = 1

−1

−2

voltage (RFP to RFN)

G_RF= 8 dB; HA = 1; ENNF = 0;

V_RFREF= 2 V

RF ampliﬁer ﬁxed parameters

R_rf

RF V-to-I conversion

resistance

2.12

2.5

2.88

kΩ

B_RF

−1 dB bandwidth of

C_L= 2 pF × 10 pF; ENEQ = 0;

signals RFP and RFN ENNF = 0

5X = 0

100

-

MHz

5X = 1

50

-

α

τ

α-equalizer parameter ENEQ = 1

τ-equalizer parameter ENEQ = 1

k-equalizer parameter ENEQ = 1; KEQ = 0

ENEQ = 1; KEQ = 1

1.25

1.31

4.0

6.0

-

k

-

∆t_d(rf)

RF delay variation

100 kHz < f < 0.7 × f_0RF

;

-

0.05

ns

BWRF[6:0] = 7Fh; f_0RF= 180 MHz;

ENEQ = 1; ENNF = 0

||H₁| − |H_n||

||H₁| − |H_e||

Z_i(RFREF)

∆V_CM

noise ﬁlter amplitude 100 kHz < f < f₀

error

-

1.0

1.5

-

dB

kΩ

mV

equalizer amplitude

error

100 kHz < f < f₀

-

RFREF input

impedance

100

-

offset of

V_rfa= 0 V

80

(V_RFP+ V_RFN)/2

compared to RFREF

V_OO(RF)

∆V_OO(RF)

∆I_OO(RF)

Z_o(RF)

RF output offset

voltage |V_RFP− V_RFN

DC_RF= 0; G_RFR= G_RFW= 0 dB;

G_RF= 8 dB; zero input signal

-

80

mV

µA

Ω

|

variation of RF output |∆T| = 20 °C; |∆V_DD| = 0.2 V

offset voltage

0.5

0.6

70

variation of RF output |∆T| = 20 °C; |∆V_DD| = 0.2 V

current offset

RF output impedance pins RFP and RFN

9397 750 14664

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TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_n(o)(RF)

effective RF output

noise voltage

ENEQ = 0; ENNF = 1;

BWRF[6:0] = 7Fh; r/w = 1;

G_RF= 0 dB

HA = 0

-

2.0

4.0

mV

HA = 1

SR_RF

differential slew rate

for RF output

maximum bandwidth

(BWRF[6:0] = FFh); C_L< 10 pF;

5X = 0

HA = 0

HA = 1

200

400

-

V/µs

C_L< 10 pF; 5X = 1

HA = 0

50

-

V/µs

HA = 1

100

RF ampliﬁer programmable parameters

R_i(RF)

RF input termination

resistance

LDRF[1:0] = 00

56

75

150

300

-

94

188

375

-

Ω

LDRF[1:0] = 01

112

225

5

Ω

LDRF[1:0] = 10

Ω

LDRF[1:0] = 11

kΩ

V_Octrl(RF)

RF offset control

voltage

OFFRF = (−95 + 3 × OFFRF) mV

r/w = 1; OFFRFR[5:0] = 00h

r/w = 0; OFFRFW[5:0] = 00h

r/w = 1; OFFRFR[5:0] = 3Fh

r/w = 0; OFFRFW[5:0] = 3Fh

∆OFFRF = 1 or ∆OFFRFW = 1

−105

75

-

−95

95

3

+75

105

-

mV

∆V_Octrl(RF)

RF offset control

voltage step size

f_0(RF)

noise ﬁlter and

equalizer corner

frequency

f₀= (16 + 1.3 × BWRF) MHz

BWRF[6:0] = 00h

BWRF[6:0] = 7Fh

∆BWRF = 1

-

16

-

MHz

180

1.3

∆f_0(RF)

noise ﬁlter and

equalizer corner

frequency step size

DC_RF

RF DC control voltage normal mode (RDCRF = 0)

DCRF[5:0] = 0h

-

0

-

mV

DCRF[5:0] = 63h; PDCRF = 0

DCRF[5:0] = 63h; PDCRF = 1

OPC mode (RDCRF = 1)

500

−500

630

−630

700

−700

DCRF[5:0] = 0h

-

0

-

mV

DCRF[5:0] = 63h; PDCRF = 0

DCRF[5:0] = 63h; PDCRF = 1

RF DC control voltage ∆DCRF = 1; RDCRF = 0

250

315

−315

10

5

350

−250

−350

∆DC_RF

-

step size

∆DCRF = 1; RDCRF = 1

9397 750 14664

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51 of 69

TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

G_RFR

RF path scaling

ampliﬁer gain in read

mode

G_RFR= (−10 + 2 × GRFR) dB

GRFR[3:0] = 0000

GRFR[3:0] = 1111

−12

−10

−8

dB

18

20

22

G_RFW

RF path scaling

ampliﬁer gain in write

mode

G

_RFW= (−10 + 2 × GRFW) dB

GRFW[3:0] = 0000

−12

18

-

−10

20

2

−8

22

-

dB

GRFW[3:0] = 1111

∆G_RFR

∆G_RFW

G_RF

RF path gain step size ∆GRFR = 1

in read mode

RF path gain step size ∆GRFW = 1

in write mode

-

2

-

dB

RF path VGA gain

G_RF= (−4 + 0.8 × GRF) dB

HA = 0; GRF[3:0] = 0000

HA = 0; GRF[3:0] = 1111

HA = 1; GRF[3:0] = 0000

HA = 1; GRF[3:0] = 1111

∆GRF = 1

−6

6

−4

8

−2

10

22

-

dB

6

8

18

-

20

0.8

∆G_RF

RF path VGA gain

step size

V_RRF, V_WRFsingle-ended RF path V_RRF= 0.9 + 0.16 × VRRF;

reference voltage

V_WRF= 0.9 + 0.16 × VWRF

VRRF[3:0] = 0000;

VWRF[3:0] = 0000

0.76

2.8

-

0.9

1.1

3.8

-

V

VRRF[3:0] = 1111;

VWRF[3:0] = 1111

3.3

∆V_RRF

,

reference voltage step ∆V_RRF= 1; ∆V_WRF= 1

0.16

∆V_WRF

size

DPD signal range

V_IU

DC input voltage level DPD = 1

for signals VUA to

VUD

0.14

0.1

-

1.0

V

V_i(p-p)

input voltage for

DPD = 1

signals VUA to VUD

(peak-to-peak value)

DPD ﬁxed parameters

B_HPF

−3 dB bandwidth of

high-pass ﬁlter

-

100

3

-

kHz

LL

lead length of lead-lag

ﬁlter

k_DTD

B_LPF2

DTD phase detector

sensitivity

1

−3 dB bandwidth of

100

kHz

low-pass ﬁlter LPF2

I_OB

I_OO

output bias current

output offset current

7.9

-

8.8

-

9.7

1

µA

zero phase difference at input;

signals VUA to VUD > 50 mV;

I_N= 3

9397 750 14664

Product data sheet

Rev. 02 — 1 June 2005

52 of 69

TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DPD programmable parameters

B_LPF1

f_start(LL)

t_d(DTD)

I_N

−3 dB bandwidth of

LPF1, normal mode

(signals VUA to VUD)

TSTDPD2 = 0

FDPD[1:0] = 00

FDPD[1:0] = 01

FDPD[1:0] = 10

FDPD[1:0] = 11

-

10

50

120

-

MHz

-

160

lead-lag network start TSTDPD2 = 0

frequency, normal

mode (signals VUA to

FLL[1:0] = 01

VUD)

FLL[1:0] = 00

-

1

-

MHz

ns

5

FLL[1:0] = 10

12

16

30

15

7.5

3.8

1.9

FLL[1:0] = 11

DTD circuit delay

parameter

DL[2:0] = 000

DL[2:0] = 001

DL[2:0] = 010

DL[2:0] = 011

DL[2:0] = 100

I_N= [2.5 × (IN + 1)] µA

IN[3:0] = 0000

IN[3:0] = 1111

∆IN[3:0] = 1

ns

DPD normalization

current

-

2.5

40

-

µA

∆I_N

DPD normalization

current step size

2.5

I_T

DPD dropout

concealment

threshold current

I_T= [1.7 × (IT + 1)] µA

IT[3:0] = 0000

IT[3:0] = 1111

∆IT[3:0] = 1

-

1.7

-

µA

27.2

1.7

∆I_T

DPD dropout

concealment

threshold current step

size

FTC circuit signal range

I_i(FAD,FBC)input current from

FTCON = 1

0

-

100

200

µA

central segments (AD

and BC)

I_i(FAD)

I_i(FBC)

+

sum current of central FTCON = 1

segments

I_i(FE)

input current of

segments FE

TZA1047/M1A; FTCON = 1

0

-

12.5

50

µA

TZA1047/M1B; M2; FTCON = 1

FTCON = 1

I_i(FF-FH)

input current of

segments F to H

50

I_i(FE+FG),

combined input

current of satellite

segments

FTCON = 1

0

-

100

µA

(FF+FH)

I_i(FE+FF),

combined input

current of satellite

segments

(FG+FH)

9397 750 14664

Product data sheet

Rev. 02 — 1 June 2005

53 of 69

TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_I

DC input current from FTCON = 1; DPD = 1

DPD

7

-

9

µA

I_i(p-p)

input current from

DPD (peak-to-peak

value)

FTCON = 1; DPD = 1

3

-

15

µA

V_o(FTC)

output voltage

FTCSL = 1

FTCSL = 0

0

-

3.3

-

V

V_FTC(DC)

output DC voltage

level

2.0

V_o(FTC)(p-p)voltage output

(peak-to-peak value)

FTCSL = 0

1

-

V

V_OL(FTC)

V_OH(FTC)

V_CFTC

LOW-level output

voltage

FTCSL = 1; I_L= 1 mA

0

-

0.6

3.3

-

HIGH-level output

voltage

2.7

-

voltage on pin CFTC

1.6

FTC circuit ﬁxed parameters

Q_FTC

FTC ﬁlter quality

factor

-

1

-

||H₁| − |H_t||

B_HPF

FTC ﬁlter amplitude

error

100 kHz < f < 2 × f_0FTC

1.5

1.2

1

dB

−3 dB bandwidth of

the high-pass ﬁlter

C_FTC= 47 nF to ground

-

kHz

ms

t_su(FTC)

start-up time after

FTCON rising edge

-

FTC circuit programmable parameters

γ

grating ratio factor

γ = 0.5 + 0.0117 × AT; GRAT = 0

AT[7:0] = 00h

-

0.5

3.5

-

AT[7:0] = FFh

γ = 2.0 + 0.0117 × AT; GRAT = 1

AT[7:0] = 00h

-

2.0

5.0

6

-

AT[7:0] = FFh

-

R_FTCOUT

I-to-V conversion

resistance

GFTC[1:0] = 00

-

kΩ

GFTC[1:0] = 01

-

12

24

48

0.25

0.5

1.0

-

kΩ

GFTC[1:0] = 10

-

kΩ

GFTC[1:0] = 11

-

kΩ

f_0FTC

FTC ﬁlter corner

frequency

FTCF[1:0] = 00

-

MHz

FTCF[1:0] = 01

-

FTCF[1:0] = 10

-

FTCF[1:0] = 11

2.5

P-P processor signal range

I_i(PPN)

I_i(PPN)(AV)

V_o

input current

signals L and R

20

40

0.6

-

200

100

µA

V

average input current signals L and R

output voltage at pin

PPNO

V_DD− 0.6

9397 750 14664

Product data sheet

Rev. 02 — 1 June 2005

54 of 69

TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

P-P ampliﬁer ﬁxed parameters

V_O

output voltage at pin

PPNO

I_i(PPN)= 0 A; no input signal

0.5V_DD− 0.4 0.5V_DD0.5V_DD+ 0.4 V

z_O

output impedance at

pin PPNO

-

130

-

Ω

R_PPOUT

SR_PPNO

V_OO(PPNO)

V_ctrl(ub)

I-to-V conversion

resistance

11

100

-

14

-

17

-

kΩ

V/µs

V

slew rate at output pin BWPP[2:0] = 1XX; C_L= 5 pF

PPNO

offset voltage at

output pin PPNO

L = R; G_pp= 0 dB

-

0.4

-

unbalance control

voltage range

0.65

-

V

P-P ampliﬁer programmable parameters

× IPPN

I_PPN= I_{0, PPN}× 10^{0.05 × K}

I_PPN(ref)

I_PPNscaling current

reference

-

120

1.7

-

µA

PPN

I_PPN= I_{0, PPN}× 10^{0.05 × K}

k_PPN

I_PPNscaling current

factor

dB

G_PP

voltage gain

GPP[3:0] = 0000

GPP[3:0] = 1111

-

−3

9

-

dB

µs

-

∆G_PP

voltage gain step size ∆GPP = 1

-

0.8

150

75

37.5

-

τ_PP

integration time

constant of PPN

balancer

TBAL[1:0] = 00

-

TBAL[1:0] = 01

TBAL[1:0] = 10

TBAL[1:0] = 11

BWPP[2:0] = 000

BWPP[2:0] = 001

BWPP[2:0] = 010

BWPP[2:0] = 011

-

[3]

-

B_PP

output bandwidth

-

2

MHz

-

4

-

8

-

16

-

BWPP[2:0] = 1XX (versions M1A,

M1B and M2)

24

BWPP[2:0] = 1XX (version M3)

30

0

-

MHz

EFMTIM signal range

I_i(EFM)

input current on pins

5000

µA

REF/ECN, RS/ECP,

TH1/EDN and

TH2/EDP

I_i(dif)H

I_i(dif)L

differential input

current for HIGH level

I_P− I_Nor I_sig− I_REF

330

−330

-

1800

5000

µA

differential input

current for LOW level

−1800 −5000

I_i(dif)(th)

differential input

0

-

current threshold level

9397 750 14664

Product data sheet

Rev. 02 — 1 June 2005

55 of 69

TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_r(in)(se)

rise time of

EFMINT = 0; 12× DVD

-

1

ns

single-ended input

signals

t_r(in)(dif)

rise time of differential EFMINT = 1; 4× DVD

input signals

-

2

-

ns

EFMTIM ﬁxed parameters

R_i(EFM)

input resistance to

70

Ω

GND on pins

REF/ECN, RS/ECP,

TH1/EDN, TH2/EDP

C_i(EFM)

t_su(EFM)

t_h(EFM)

t_d(EFM)

input capacitance

set-up time

-

6

2

-

pF

ns

rising edge; EFMINT = 1

EFMINT = 1

-

hold time

2

-

propagation delay of

EFM data to sampling

signals

3

-

t_d1(EFM)

t_d2(EFM)

t_d3

propagation delay of

EFM data to r/w

EFMINT = 1

-

20

ns

propagation delay of

EFM data to TH1

EFMINT = 1

2.8

5.0

7.2

1.5

0.5

delay TH1, TH2, RS

to sampling point

EFMINT = 0

-

∆t_d3

delay variation TH1,

EFMINT = 0; ∆T = 40 °C;

TH2, RS to sampling ∆V_DD= 0.5 V

point

∆t_TH1,TH2

delay difference

between TH1 and

TH2

-

0.15

ns

f_EFM

EFM clock frequency V_DD> 4.5 V

V_DD> 5.0 V

140

-

MHz

V

160

-

V_O(EFM)H

HIGH-level output

voltage at pins

I < 12 mA

0.8V_DD

V_DD

RWOUT and TIMOUT

V_O(EFM)L

LOW-level output

voltage at pins

I < 12 mA

0

-

0.2V_DD

V

RWOUT and TIMOUT

Normalizer signal range

I_i(Qn)

servo input current on Q/NE = 0; operating

1

0

20

0

5

0

-

110

12

µA

V

pins Q1 to Q6

Q/NE = 1; operating

-

I_(RF-NORM)

RF to Normalizer

current

r/w = 1; operating

-

200

800

400

100

15

r/w = 0; RS = 0; operating

r/w = 0; RS = 1; operating

-

I_i(LASP)

LASP control current r/w = 0

-

input

r/w = 1

-

V_i(LASP)

LASP input voltage

I_i(LASP)= 100 µA

1.7

-

9397 750 14664

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Rev. 02 — 1 June 2005

56 of 69

TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Normalizer ﬁxed parameters

f_LPF1

f_LPF2

−3 dB frequency of

LPF1 in RAD

C_CMPP= 100 nF

-

1.0

-

kHz

−3 dB frequency of

LPF2 in CANORM

BWRS = 0

BWRS = 1

48

96

-

60

72

144

-

kHz

µA

120

10

I_ref(CAN)

I_ref1

CAN reference

current

MIRN and CAN

reference current

-

200

-

µA

I_ref(PR)

read power reference

current

3.50

I_clamp

TLN clamp current

9

-

10

-

11

2

µA

µs

t_rel(clamp)

TLN clamp release

time

after clamping

∆I/(I1 + I2) normalization error

I1 = I2; Q_n> 1 µA

for FEN and REN

for TLN

-

3

%

-

15

4

%

τ_d

RS switch delay

-

ns

kΩ

R_i(LASP)

LASP input

impedance

2

-

V_o(S),V_o(D)

servo output voltage

S1 and S2, D1 to D4; operating

operating

1.2

40

-

0.5V_DD

800

V

ALFA signal range

I_i(RF)(ALFA)RF input signal for

ALFA

ALFA ﬁxed parameters

I_ref(ALFA)reference current for

normalization

µA

-

10

-

µA

%

∆α/α

variation of ALFA with ∆T = 40 °C

-

4

die temperature

I_o(ALFA)

ALFA output current

V_o(ALFA)= 0 V

0

-

100

µA

ALFA programmable parameters

I_AN

ALFA normalization

current

IAN[1:0] = 00

IAN[1:0] = 01

IAN[1:0] = 10

IAN[1:0] = 11

-

10

20

30

40

-

µA

BETA signal range

I_i(RF)(BETA)RF input signal for

BETA

BETA ﬁxed parameters

V_o(BETA)A1, A2 and CALF

operating

V_DD= 5 V

0

-

200

µA

0

-

3.3

V

output voltage

Z_o(BETA)

A1, A2 and CALF

output impedance

300

Ω

9397 750 14664

Product data sheet

Rev. 02 — 1 June 2005

57 of 69

TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[4]

V_A1/V_A2

matching of A1 and

A2

input conditions set for A1 = A2:

0.85

1.0

1.15

I_p1= I_p2= 8 µA − 40 µA;

I₀= (100 − I_p1) µA

V_A1/V_CALF

matching of A1 and

CALF

input conditions set for A1 = CALF:

0.8

1.0

1.2

5

I_p1= I_p2= 8 µA − 40 µA;

I₀= I_p1µA

∆V_o(BETA)

V_o(BETA)

/

variation of A1, A2

and CALF with

temperature

T_die= 20 °C to 120 °C; ∆T = 10 °C;

∆V_DD= 5 %

-

%

(V_A1)₀/

V_CALF

A1/CALF for DC input

V_RFP− V_RFN= 0.5 V; DC;

2

GRFR[3:0] = 5h (0 dB);

ORF[4:0] = 32h (I₀= 100 µA)

(V_A2)₀/

V_CALF

A2/CALF for DC input

V_RFP− V_RFN= 0.5 V; DC;

2

GRFR[3:0] = 5h (0 dB),

ORF[4:0] = 32h (I₀= 100 µA)

BETA programmable parameters

f_LPF

−3 dB frequency of

f_LPF= (0.5 × 2^BCTL) kHz;

CALF low-pass ﬁlter

C

_CCALF= 27 nF to ground

BCTL[2:0] = 000

BCTL[2:0] = 001

BCTL[2:0] = 010

BCTL[2:0] = 011

BCTL[2:0] = 100

BCTL[2:0] = 101

BCTL[2:0] = 110

BCTL[2:0] = 111

-

0.5

1

-

kHz

2

4

8

16

32

-

[5]

τ_peak

time constant of A1

and A2 peak

detectors

τ_peak= (500 × 2^BCTL) µs;

C

_CA1= C_CA2= 10 nF to ground

BCTL[2:0] = 000

BCTL[2:0] = 001

BCTL[2:0] = 010

BCTL[2:0] = 011

BCTL[2:0] = 100

BCTL[2:0] = 101

BCTL[2:0] = 110

BCTL[2:0] = 111

-

500

250

125

62.5

31.3

15.6

7.81

-

µs

[5]

I_BS

A1, A2 and CALF

output scaling current

IBS[4:0] = 00000

IBS[4:0] = 11111

∆IBS = 1

5

µA

160

5

∆I_BS

A1, A2 and CALF

output scaling current

step size

G_BETA

gain from RFP and

RFN to CALF, A1 and

A2

G_BETA= 100/(1 + IBS)

IBS[4:0] = 00h

-

100

-

IBS[4:0] = 1Fh

3.125

9397 750 14664

Product data sheet

Rev. 02 — 1 June 2005

58 of 69

TZA1047

Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Monitor ﬁxed parameters

V_o(MON)

monitor output voltage R_L= 10 kΩ; C_L= 10 pF

0.7

-

V

_DD− 0.7

V

V_ref(MON)

monitor voltage

reference level

I_i= 0 A

0.5V_DD− 0.1 0.5V_DD0.5V_DD+ 0.1 V

R_o(MON)

monitor output

conversion resistance

-

85

-

kΩ

∆R_o(MON)

/

variation of

20 °C < T_die< 120 °C

10

%

R_o(MON)

conversion resistance

with temperature

B_(MON)

monitor circuit −3 dB

bandwidth

100

-

kHz

R_O(MON)

output resistance on

pins MON1 and

MON2

120

Ω

I²C-bus interface signal range

V_IL

V_IH

V_OL

I_OL

I_i(n)

LOW-level input

voltage

pins SCL and SDA

pin SDA; I_OL= 3 mA

pin SDA

−0.5

2.1

0

-

1.0

V

HIGH-level input

voltage

V_DD+ 0.5

0.4

V

LOW-level output

voltage

V

LOW-level output

current

-

6

mA

nA

input current on pins

SDA and SCL

−100

+100

Fast serial bus signal range

V_i(logic)

logic input voltage

compatibility

2.7

2.1

-

3.3

5.5

-

V

V_IH

HIGH-level input

voltage

-

V_IL

LOW-level input

voltage

1.0

Fast serial bus ﬁxed parameters

V_OH(SROUT)HIGH-level output

voltage on pin SROUT

SERTST = 1; I < 1 mA

0.8V_DD

-

V_DD

V

V_OL(SROUT)LOW-level output

voltage on pin SROUT

SERTST = 1; I < 1 mA

0

-

0.2V_DD

150

V

I_IH(SERTST)

HIGH-level input

internal pull-down resistor of 50 kΩ

µA

nA

current pin SERTST

I_i(n)

input current on pins

SIDA, SICL and SILD

-

100

t_SU;STA

t_SU;DAT

t_HD;DAT

t_HIGH

start set-up time

data set-up time

data hold time

0

-

ns

20

clock HIGH time

clock LOW time

t_LOW

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Preprocessor IC for CD and DVD rewritable

Table 27: Characteristics …continued

Symbol

T_CLK

Parameter

Conditions

Min

60

Typ

Max

Unit

ns

clock period

-

t_SU;LD

set-up time load pulse

load pulse HIGH time

45

ns

t_HIGH;LD

20

ns

[1] With the M1A, M1B and M2 versions negative segment input offset voltages, on pins VIA to VIH, are clipped to zero current internally

and hence cannot be compensated with IOA to IOH. With the M3 version negative input offset voltages are not clipped and can,

therefore, be compensated.

[2] To allow the maximum differential input voltage range requires a V_REFvalue greater than 2 V.

[3] Invalid bit combination; do not use.

[4] The input for the BETA circuit will be described in terms of a test signal, which is similar, but not identical, to the actual EFM signal used

in the application. The AC part of the test signal is a clipped sinusoidal signal with period (10T) 2^-Nand ﬂat top/bottom of (T/2) 2^-N, with

N = 0 to 5 and T = 231 ns. It has a positive peak level I_p1= {rf − LPF(rf)}_peakand a negative peak level I_p2= {LPF(rf) − rf}_peak, which are

equal for the test version. The AC part is superimposed on a DC-level I₀. Furthermore IBS[4:0] =19h, r/w = 1.

[5] To save power, the BETA block and its DAC can be switched off completely by setting parameter BCTL[2:0] to 111. If the BETA block and

its DAC are switched off, the −3 dB frequency and time constant will not be deﬁned.

10. Application information

10.1 Application circuit

Figure 28 shows an application diagram and the essential external components and basic

connections for use with PNX7850 (Centaurus1) and PNX7860 (Centaurus2) decoder

ICs. Changes may be made to the circuit to suit the system architecture.

When using TZA1047 versions M1A, M1B and M2 in applications using the Philips

PAEDIC based OPU (with current outputs), the input channels must have 15 kΩ pull-up

resistors connected to the 3.3 V supply line. These resistors are added so that negative

offsets do not appear on the TZA1047 inputs; see Table 27.

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Several external components and connections are required for the proper operation of

TZA1047, regardless of the application. These components are listed in Table 28.

Table 28: TZA1047 external components

Pin name Pin number Connect to

Comments

SERTST

CFTC

CA1

28

35

38

39

40

41

43

leave open

for test purposes only

47 nF to GND

10 nF to GND

27 nF to GND

47 kΩ to GND

100 nF to GND

short to GND

leave open

can be left unconnected if BETA function not used

CA2

CCALF

RREF

CMPP

IDDQTST 53

SROUT 57

for test purposes only

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11. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v M

D

A

e

w M

b

p

D

B

H

v M

B

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 29. Package outline SOT314-2 (LQFP64)

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12. Packing information

When using reﬂow soldering it is recommended that the Dry Packing instructions in the

Quality Reference Pocketbook are followed. The pocketbook can be ordered using the

code 9398 510 34011.

13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

13.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

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Preprocessor IC for CD and DVD rewritable

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

13.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

13.5 Package related soldering information

Table 29: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

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Preprocessor IC for CD and DVD rewritable

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

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Preprocessor IC for CD and DVD rewritable

14. Revision history

Table 30: Revision history

Document ID

TZA1047_2

Modiﬁcations:

TZA1047_1

Release date Data sheet status

20050601 Product data sheet

• TZA1047HL/M3 added to data sheet

20040816 Product data sheet

Change notice Doc. number

Supersedes

-

9397 750 14664 TZA1047_1

-

9397 750 13329

-

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Preprocessor IC for CD and DVD rewritable

15. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Deﬁnitions

17. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

18. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 14664

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Rev. 02 — 1 June 2005

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Philips Semiconductors

Preprocessor IC for CD and DVD rewritable

19. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.11.4

7.11.5

Radial servo signal block (normalizer

sub-block). . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Track loss servo signal block (normalizer

sub-block). . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

CA signal block (normalizer sub-block) . . . . . 35

Output current polarities. . . . . . . . . . . . . . . . . 36

Normalizer block I²C-bus control signal

overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

ALFA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

ALFA measurement circuit for running OPC . 38

7.11.6

7.11.7

7.11.8

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.12

7.12.1

7

7.1

7.2

7.3

7.4

7.5

Functional description . . . . . . . . . . . . . . . . . . . 8

Detector layout . . . . . . . . . . . . . . . . . . . . . . . . . 8

Supported servo modes . . . . . . . . . . . . . . . . . . 9

Diagram conventions . . . . . . . . . . . . . . . . . . . . 9

Input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Distributor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Signals Q1 to Q6 . . . . . . . . . . . . . . . . . . . . . . 12

Signal Q_s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

FTC circuit signals . . . . . . . . . . . . . . . . . . . . . 13

Signals L and R . . . . . . . . . . . . . . . . . . . . . . . 13

RF ampliﬁer . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Input section . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Differential data path. . . . . . . . . . . . . . . . . . . . 15

Single-ended current path . . . . . . . . . . . . . . . 17

DPD circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

FTC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Push-pull processor . . . . . . . . . . . . . . . . . . . . 21

Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

EFMTIM Timing . . . . . . . . . . . . . . . . . . . . . . . 23

Input signals . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Signal generation in internal mode. . . . . . . . . 24

7.12.1.1 Phase change media . . . . . . . . . . . . . . . . . . . 38

7.12.1.2 ALFA circuit general . . . . . . . . . . . . . . . . . . . . 39

7.13

7.14

7.15

7.15.1

7.15.2

7.15.3

7.16

7.16.1

7.16.2

7.16.3

7.16.4

BETA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Monitor block . . . . . . . . . . . . . . . . . . . . . . . . . 41

I²C-bus interface and registers. . . . . . . . . . . . 42

General description . . . . . . . . . . . . . . . . . . . . 42

Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 43

Register deﬁnition . . . . . . . . . . . . . . . . . . . . . 44

Fast serial bus and registers . . . . . . . . . . . . . 46

Fast serial bus description . . . . . . . . . . . . . . . 46

Serial bus control timing. . . . . . . . . . . . . . . . . 46

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Fast serial bus control registers . . . . . . . . . . . 47

7.5.1

7.5.2

7.5.3

7.5.4

7.6

7.6.1

7.6.2

7.6.3

7.7

7.7.1

7.8

7.9

7.9.1

7.10

7.10.1

7.10.2

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 47

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48

Application information . . . . . . . . . . . . . . . . . 60

Application circuit . . . . . . . . . . . . . . . . . . . . . . 60

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 63

Packing information . . . . . . . . . . . . . . . . . . . . 64

9

10

10.1

11

12

13

13.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 64

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 64

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 65

Package related soldering information. . . . . . 65

7.10.2.1 r/w signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.10.2.2 TH1 and TH2 . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.10.2.3 Signal RS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.10.3

7.10.4

7.10.5

7.10.6

7.10.6.1 RWOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.10.6.2 TIMOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.10.6.3 Bit RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.10.6.4 Bit EFMTST . . . . . . . . . . . . . . . . . . . . . . . . . . 29

13.2

13.3

13.4

13.5

Enabling bits . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Signal generation in external mode . . . . . . . . 28

Timing parameters . . . . . . . . . . . . . . . . . . . . . 28

Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . 28

14

15

16

17

18

Revision history . . . . . . . . . . . . . . . . . . . . . . . 67

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 68

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Contact information . . . . . . . . . . . . . . . . . . . . 68

7.11

7.11.1

7.11.2

Normalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Auxiliary block. . . . . . . . . . . . . . . . . . . . . . . . . 31

Dropout concealment block (normalizer

sub-block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Focus servo signal block (normalizer

7.11.3

sub-block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 1 June 2005

Document number: 9397 750 14664

Published in The Netherlands


型号：	TZA1047HL/M2
厂家：	NXP
描述：	IC SPECIALTY CONSUMER CIRCUIT, PQFP64, 10 X 10 MM, 1.4 MM HEIGHT, PLASTIC, MS-026, SOT314-2, LQFP-64, Consumer IC:Other 商用集成电路
文件：	总69页 (文件大小：324K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TZA1047HL/M2 [NXP]

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