TZA3012HW_技术文档

TZA3012HW

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

Rev. 01 — 15 December 2005

Product data sheet

1. General description

The TZA3012HW is a fully integrated optical network receiver containing a dual limiter,

data and clock recovery and demultiplexer with demultiplexing ratios of 1 : 16, 1 : 10, 1 : 8,

or 1 : 4.

The A-rate feature allows the IC to operate at any bit rate between 30 Mbit/s and

3.2 Gbit/s using a single reference frequency. The receiver supports loop modes with

serial clock and data inputs and outputs. All clock signals are generated using a fractional

N synthesizer with 10 Hz resolution giving a true, continuous rate operation. For full

conﬁguration ﬂexibility, the receiver can be conﬁgured by pin or via the I²C-bus.

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken

during transport and handling.

2. Features

2.1 General

■ Single 3.3 V supply voltage

■ I²C-bus and pin conﬁgured ﬁber-optic receiver

2.2 Dual limiter

■ Dual limiting input with 12 mV sensitivity

■ Received Signal Strength Indicator (RSSI)

■ Loss-Of-Signal (LOS) indicator with threshold adjust

■ Differential overvoltage protection

2.3 Data and clock recovery

■ Supports SHD/SONET bit rates at 155.52 Mbit/s, 622.08 Mbit/s, 2488.32 Mbit/s and

2666.06 Mbit/s (STM16/OC48 + FEC)

■ Supports Gigabit Ethernet at 1250 Mbit/s and 3125 Mbit/s

■ Supports Fiber Channel at 1062.5 Mbit/s and 2125 Mbit/s

■ ITU-T compliant jitter tolerance

■ Frequency lock indicator

■ Stable clock signal when input data absent

■ Outputs for recovered data and clock loop mode

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

2.4 Demultiplexer

■ Demultiplexing ratios of 1 : 16, 1 : 10, 1 : 8 or 1 : 4

■ Low Voltage Positive Emitter Coupled Logic (LVPECL) or Common Mode Logic (CML)

demultiplexer outputs

■ Parity bit generation

■ Loop mode inputs to demultiplexer

2.5 Additional features with I²C-bus

■ A-rate supports any bit rate from 30 Mbit/s to 3.2 Gbit/s with one reference frequency

■ Programmable frequency resolution of 10 Hz

■ Four reference frequency ranges

■ Adjustable swing of data, clock and parallel outputs

■ Programmable polarity of all RF I/Os

■ Exchangeable pin designations of RF clock with data for all I/Os for optimum

connectivity

■ Reversible pin designations of parallel data bus bits for optimum connectivity

■ Slice level adjustment to improve Bit Error Rate (BER)

■ Mute function for a forced logic 0 output state

■ Programmable parity

3. Applications

■ Any optical transmission system with bit rates between 30 Mbit/s and 3.2 Gbit/s

■ Physical interface IC in receive channels

■ Transponder applications

■ Dense Wavelength Division Multiplexing (DWDM) systems

4. Ordering information

Table 1:

Ordering information

Type number Package

Name

Description

Version

TZA3012HW HTQFP100 plastic thermal enhanced thin quad ﬂat package;

SOT638-1

100 leads; body 14 × 14 × 1 mm; exposed die pad

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

2 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

5. Block diagram

CLOOP

DLOOPQ CLOOPQ

DLOOP ENLINQ

DMXR0

DMXR1

LOS1

5

RSSI1

87 88 84 85

91

30 31

6

7

38

39

PARITY

PARITYQ

LOSTH1

LOS

44, 46, 48, 53

55, 57, 59, 61,

64, 66, 68, 70

72, 77, 79, 81

RSSI

LIM

12

9

INSEL

IN1

PARITY

GENERATOR

AND

TZA3012HW

c

16

D00

to D15

DMX

1 : 4

1 : 8

1 : 10

1 : 16

d

10

BUS SWAP

IN1Q

16

45, 47, 49, 54

56, 58, 60, 62,

65, 67, 69, 71

73, 78, 80, 82

SWITCH

PHASE

DETECTOR

2

d

c

16

17

IN2

D00Q

to D15Q

LIM

IN2Q

41

42

2

POCLK

POCLKQ

LPF

2

94

95

RSSI

COUT

LOS

COUTQ

FREQUENCY

WINDOW DETECTOR

19

LOSTH2

97

98

DOUT

24

23

SCL(DR2)

SDA(DR1)

DOUTQ

2

I C-BUS

22

4

92

INTERRUPT

CONTROLLER

INT

n.c.

CS(DR0)

UI

36, 37

28, 29

14

2

i.c.

1, 35, 40, 43, 51

75, 76, 83, 86,

89, 93, 96, 99

RREF

26, 50, 52,

63, 74, 100

8, 11,

15, 18

20

21 13 33 34 27

2

3

90

32

25

001aad377

13

V

4

RSSI2

LOS2

CREFQ

CREF

WINSIZE INWINDOW

PRSCLOQ

V

DD

V

CCA

V

EE

PRSCLO

CCD

CCO

ENLOUTQ

LIM = Limiting ampliﬁer

RSSI = Received signal strength indicator

LOS = Loss-of-signal detector

LPF = Low-pass ﬁlter

DMX = Demultiplexer

Fig 1. Block diagram

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

3 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

6. Pinning information

6.1 Pinning

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

CCD

EE

2

PRSCLO

PRSCLOQ

UI

3

D12Q

D12

4

5

LOS1

D11Q

D11

6

RSSI1

7

LOSTH1

D10Q

D10

8

V

CCA

9

IN1

D09Q

D09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

INQ1

V

D08Q

D08

CCA

INSEL

WINSIZE

RREF

TZA3012HW

V

EE

D07Q

D07

V

CCA

IN2

D06Q

D06

IN2Q

V

D05Q

D05

CCA

LOSTH2

RSSI2

D04Q

D04

LOS2

CS/DR0

SDA/DR1

SCL/DR2

D03Q

D03

V

EE

V

DD

CCD

001aad378

Fig 2. Pin conﬁguration

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

4 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

6.2 Pin description

Table 2:

Symbol

V_CCD

Pin description

1

Description

supply voltage (digital signal part)

PRSCLO

PRSCLOQ

UI

2

prescaler output

3

prescaler inverted output

4

user interface select input

LOS1

5

ﬁrst input channel loss-of-signal output

ﬁrst input channel received signal strength indicator output

ﬁrst input channel loss-of-signal threshold input

supply voltage (analog part)

RSSI1

LOSTH1

V_CCA

6

7

8

IN1

9

ﬁrst channel input

IN1Q

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

ﬁrst channel inverted input

V_CCA

supply voltage (analog part)

INSEL

WINSIZE

RREF

V_CCA

input selector

wide and narrow frequency detect window select input

reference resistor input

supply voltage (analog part)

IN2

second channel input

IN2Q

second channel inverted input

supply voltage (analog part)

V_CCA

LOSTH2

RSSI2

LOS2

second input channel loss-of-signal threshold input

second input channel received signal strength indicator output

second input channel loss-of-signal output

chip select input or data rate select input 2

I²C-bus serial data input and output or data rate select input 1

I²C-bus serial clock input or data rate select input 2

supply voltage (digital controller part)

ground

CS/DR0

SDA/DR1

SCL/DR2

V_DD

V_EE

INWINDOW

i.c.

frequency window detector output

internally connected; leave open

demultiplexing ratio select 0

i.c.

DMXR0

DMXR1

V_CCO

demultiplexing ratio select 1

supply voltage (clock generator part)

reference clock input

CREF

CREFQ

V_CCD

reference clock inverted input

supply voltage (digital signal part)

not connected

n.c.

not connected

PARITY

PARITYQ

parity output

parity inverted output

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

5 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

Table 2:

Symbol

V_CCD

POCLK

POCLKQ

V_CCD

D00

Pin description …continued

Description

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

supply voltage (digital signal part)

parallel clock output

parallel clock inverted output

supply voltage (digital signal part)

parallel data 00 output

D00Q

D01

parallel data 00 inverted output

parallel data 01 output

D01Q

D02

parallel data 01 inverted output

parallel data 02 output

D02Q

V_EE

parallel data 02 inverted output

ground

V_CCD

V_EE

supply voltage (digital signal part)

ground

D03

parallel data 03 output

D03Q

D04

parallel data 03 inverted output

parallel data 04 output

D04Q

D05

parallel data 04 inverted output

parallel data 05 output

D05Q

D06

parallel data 05 inverted output

parallel data 06 output

D06Q

D07

parallel data 06 inverted output

parallel data 07 output

D07Q

V_EE

parallel data 07 inverted output

ground

D08

parallel data 08 output

D08Q

D09

parallel data 08 inverted output

parallel data 09 output

D09Q

D10

parallel data 09 inverted output

parallel data 10 output

D10Q

D11

parallel data 10 inverted output

parallel data 11 output

D11Q

D12

parallel data 11 inverted output

parallel data 12 output

D12Q

V_EE

parallel data 12 inverted output

ground

V_CCD

D13

supply voltage (digital signal part)

parallel data 13 output

D13Q

D14

parallel data 13 inverted output

parallel data 14 output

D14Q

parallel data 14 inverted output

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

6 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

Table 2:

Symbol

D15

Pin description …continued

Description

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

parallel data 15 output

D15Q

parallel data 15 inverted output

supply voltage (digital signal part)

loop mode clock input

V_CCD

CLOOP

CLOOPQ

V_CCD

loop mode clock inverted input

supply voltage (digital signal part)

loop mode data input

DLOOP

DLOOPQ

V_CCD

loop mode data inverted input

supply voltage (digital signal part)

line loop back enable input (active LOW)

diagnostic loop back enable input (active LOW)

interrupt output

ENLOUTQ

ENLINQ

INT

V_CCD

supply voltage (digital signal part)

recovered clock output

COUT

COUTQ

V_CCD

recovered clock inverted output

supply voltage (digital signal part)

recovered data output

DOUT

DOUTQ

V_CCD

recovered data inverted output

supply voltage (digital signal part)

ground

V_EE

die pad common ground plane

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

7 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

7. Limiting values

Table 3:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

+3.6

Unit

V

V_CCA

V_CCD

V_CCO

V_DD

analog supply voltage

−0.5

digital supply voltage

oscillator supply voltage

supply voltage

V

V_n

voltage on pin n

D00 to D15, D00Q to D15Q,

POCLK, POCLKQ, PARITY,

PARITYQ, PRSCLO and

PRSCLOQ

V_CC− 2.5 V_CC+ 0.5 V

LOSTH1, LOSTH2 and RREF

RSSI1 and RSSI2

−0.5

V_CC+ 0.5 V

UI, INSEL, WINSIZE, CS, SDA,

SCL, DMXR0, DMXR1, ENLOUTQ

and ENLINQ

LOS1, LOS2 and INWINDOW

INT

−0.5

V

_CC+ 0.5 V

V

I_I(n)

input current on pin n

IN1, IN1Q, IN2 and IN2Q

−30

−20

+30

+20

mA

CREF, CREFQ, CLOOP, CLOOPQ,

DLOOP and DLOOPQ

INT

−2

−40

-

+2

mA

°C

T_amb

T_j

ambient temperature

junction temperature

storage temperature

+85

+125

+150

T_stg

−65

8. Thermal characteristics

Table 4:

Thermal characteristics

Symbol Parameter

Conditions

Typ

Unit

[1] [2]

R_th(j-a)

thermal resistance from junction to

ambient

16

K/W

[1] In compliance with JEDEC standards JESD 51-5 and JESD 51-7.

[2] Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the

second and fourth layer in the PCB.

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

8 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

9. Characteristics

Table 5:

Default measurement settings

All measurements are done with the default settings.

Parameter

Pin conﬁgured mode

STM16/OC48

UI = LOW

DR0 = LOW, DR1 = HIGH, DR2 = LOW

INSEL = HIGH

Limiter 1 active

Detect window 1000 ppm

Disabled DOUT and COUT

Disabled DLOOP and CLOOP

DMX ratio = 1 : 16

WINSIZE = HIGH

ENLOUTQ = HIGH

ENLINQ = HIGH

DMXR0 = HIGH, DMXR1 = HIGH

CREF and CREFQ = 19.44 MHz

LOSTH2 = not connected

not connected

Reference frequency

LOS2 switched off

D00 to D15 and D00Q to D15Q

PARITY, PARITYQ

not connected

POCLK, POCLKQ

not connected

PRSCLO and PRSCLOQ

not connected

Table 6:

Supply characteristics

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies: pins V_CCA, V_CCD, V_CCO

V_CC

supply voltage

3.14

15

3.30

20

3.47

27

V

I_CCA

I_CCD

I_CCO

I_CC(tot)

analog supply current

digital supply current

oscillator supply current

total supply current

mA

270

20

350

25

450

33

[1]

305

395

511

Digital controller: pins V_DD

V_DD

supply voltage

supply current

3.14

0

3.30

0

3.47

1

V

I_DD

mA

General

P_tot

[1]

total power dissipation

0.96

1.17

1.3

1.77

1.26

W

V

Reference: pin RREF

V_refreference voltage

10 kΩ to 20 kΩ to V_EE

1.21

[1] The total supply current and power dissipation are dependent on the IC setups such as swing and loop modes and termination

conditions.

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

9 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

Table 7:

Logic control input and output characteristics

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

CMOS input: pins UI, DR0, DR1, DR2, INSEL, WINSIZE, DMXR0, DMXR1, ENLOUTQ and ENLINQ

V_IL

V_IH

I_IL

LOW-state input voltage

HIGH-state input voltage

LOW-state input current

HIGH-state input current

-

0.2V_CC

V

0.8V_CC

−200

-

V

V_IL= 0 V

V_IH= V_CC

-

µA

I_IH

10

CMOS output: INWINDOW and INT

V_OL

V_OH

LOW-state output voltage

HIGH-state output voltage

I_OL= 1 mA

0

-

0.2

V

I_OH= −0.5 mA

V_CC

0.2

−

V_CC

Open-drain output: pin INT

V_OL

I_OH

LOW-state output voltage

HIGH-state output current

I_OL= 1 mA

V_OH= V_CC

0

-

0.2

10

V

µA

Table 8:

RF input, RSSI and LOS characteristics

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

RF input: pins IN1, INQ1, IN2 and INQ2

[1]

[2]

V_i(p-p)

peak-to-peak input voltage

lower slice level voltage

single-ended

12

-

500

mV

Ω

V_sl(lower)

−50

+50

100

60

-

V_sl(upper)upper slice level voltage

Z_iinput impedance

-

differential

80

-

120

-

α_isol(ch-ch)isolation between channels

dB

RSSI circuit

V_i(sens)

input sensitivity voltage

V_i= 5 mV to 500 mV (p-p)

15

17

20

mV/dB

Output: pins RSSI1 and RSSI2

V_O

output voltage

V_i= 32 mV (p-p);

580

680

-

780

mV

PRBS = (2³¹− 1)

∆V_O

output voltage variation

input 30 Mbit/s to 3200 Mbit/s;

PRBS = (2³¹− 1); V_CC= 3.14 V

to 3.47 V; ∆T_amb= 120 °C

−50

+50

I_O(source)output source current

-

1

mA

Ω

I_O(sink)

Z_o

output sink current

output impedance

-

0.4

10

1

LOS detector

LOS circuit

[3]

V_hys(i)

t_as

input hysteresis voltage

-

3

-

dB

µs

assert time

∆V_i(p-p)= 3 dB

5

t_das

de-assert time

-

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

10 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

Table 8:

RF input, RSSI and LOS characteristics …continued

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

CMOS output: pins LOS1 and LOS2

V_OL

V_OH

LOW-state output voltage

HIGH-state output voltage

I_OL= 1 mA

0

-

0.2

V

I_OH= −0.5 mA

V_CC

0.2

−

V_CC

[1] The RF input is protected against a differential overvoltage; the maximum input current is 30 mA. It is assumed that both inputs carry a

complementary signal of the speciﬁed peak-to-peak value.

[2] The slice level is adjustable in 256 steps controlled by I²C-bus registers LIMSLICE1 (address C0h) and LIMSLICE2 (address C1h).

[3] The hysteresis is adjustable in 8 steps controlled by bits HYS1 and HYS2 in I²C-bus registers LIMLOS1CNF (address BDh) and

LIMLOS2CNF (address BFh).

Table 9:

Clock and PLL characteristics

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Reference input frequency: pins CREF and CREFQ

V_i(p-p)

V_I

peak-to-peak input voltage

input voltage

single-ended

50

-

1000

mV

V

V_CC

1

−

V_CC+

0.25

Z_i

input impedance

single-ended to V_CC

R = 1, 2, 4 or 8

40

50

60

Ω

f_i(ref)

∆f_i(ref)

reference input frequency

reference input frequency accuracy

18R

−20

19.4R 21R

MHz

ppm

SDH/SONET requirement

-

+20

PLL characteristics

t_acq

acquisition time

30 Mbit/s

-

200

10

-

µs

ms

µs

bit

t_acq(pc)

t_acq(oc)

TDR_max

power cycle acquisition time

octave change acquisition time

maximum transitionless data run

-

1000

Table 10: Serial input and output characteristics

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ Max

Unit

Serial input: pins CLOOP, CLOOPQ, DLOOP and DLOOPQ

V_i(p-p)

V_I

peak-to-peak input voltage

input voltage

single-ended

50

-

100

mV

V_CC− 1 -

V

_CC+ 0.25 V

Z_i

input impedance

delay time

single-ended to V_CC

40

50

60

Ω

t_d

data DLOOP and DLOOPQ to

clock CLOOP and CLOOPQ;

between differential crossovers

referenced to negative clock edge

260

340 400

ps

t_su

t_h

setup time

see Figure 3

15

40

30

50

60

ps

%

hold time

δ_clk

clock duty cycle

clock CLOOP and CLOOPQ;

between differential crossovers

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

11 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

Table 10: Serial input and output characteristics …continued

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ Max

Unit

Serial output: pins COUT, COUTQ, DOUT and DOUTQ

[1]

V_o(p-p)

peak-to-peak output voltage

single-ended with 50 Ω external

50

80

110

mV

load; ENLOUTQ = LOW

Z_o

t_r

output impedance

rise time

single-ended to V_CC

20 % to 80 %

80

-

100 120

Ω

100

-

ps

t_f

fall time

80 % to 20 %

-

t_d

delay time

data DOUT and DOUTQ to clock

COUT and COUTQ; between

differential crossovers referenced

to negative clock edge

80

140 200

δ_clk

clock duty cycle

COUT and COUTQ; between

differential crossovers

40

50

60

%

[1] The output swing is adjustable in 16 steps controlled by bits RFS in I²C-bus register CBh.

CLOOP

t

d

t

su

h

DLOOP

mbl554

The timing is measured from the crossover point of the clock input signal to the crossover point

of the data input.

Fig 3. Loop mode input timing

Table 11: Parallel outputs characteristics

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Parallel output: pins D00 to D15, D00Q to D15Q, PARITY, PARITYQ, POCLK, POCLKQ, PRSCLO and PRSCLOQ

CML mode

[1]

V_o(p-p)

peak-to-peak output voltage

single-ended with 50 Ω

external load to V_CC

650

800

1000

mV

;

AC-coupled or DC-coupled

single-ended to V_CC

20 % to 80 %

Z_o

output impedance

rise time

70

200

-

95

250

-

110

350

400

Ω

t_r

ps

t_f

fall time

80 % to 20 %

ps

f_bit(par)

parallel bit rate

Mbit/s

LVPECL mode

V_OH

V_OL

HIGH-state output voltage

LOW-state output voltage

50 Ω termination to V_CC− 2 V

V

_CC− 1.2 V_CC− 1.0 V_CC− 0.9 V

_CC− 2.0 V_CC− 1.9 V_CC− 1.7 V

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

12 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

Table 11: Parallel outputs characteristics …continued

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[1]

V_o(p-p)

peak-to-peak output voltage

LVPECL ﬂoating; single-ended

700

900

1150

mV

with 50 Ω external load to V_CC

;

AC-coupled or DC-coupled

t_r

rise time

20 % to 80 %

80 % to 20 %

300

-

350

-

400

ps

t_f

fall time

ps

f_bit(par)

Timing

t_d

parallel bit rate

Mbit/s

[2]

delay time

referenced to negative clock

edge

data D00 to D15 to clock POCLK

data D06 to D09 to clock POCLK

clock duty cycle

DMX = 1 : 16, 1 : 10, 1 : 8

DMX = 1 : 4

−100

150

40

+100

180

50

+250

250

60

ps

%

δ_clk

POCLK and POCLKQ;

between differential crossovers

[2]

t_sk(o)

output skew time

between channels

data D00 to data Dn

DMX = 1 : 16, 1 : 10, 1 : 8

DMX = 1 : 4

-

200

50

ps

data D06 to D09 to clock POCLK

[1] The output swing is adjustable in 16 steps controlled by bits MFS in I²C-bus register IOCNF3 (address C8h). In standard LVPECL mode

only swing = 12 (default) should be used.

[2] With 50 % duty cycle.

Table 12: Jitter tolerance characteristics

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[1]

[2]

t_{jit(tol)(p-p)}peak-to-peak jitter tolerance

ITU-T G.958; PRBS = (2³¹− 1)

STM1/OC3 mode

f = 6.5 kHz

3

10

-

f = 65 kHz

0.3

1.0

0.5

f = 1 MHz

[3]

[4]

STM4/OC12 mode

f = 25 kHz

3

10

-

f = 250 kHz

0.3

1.0

0.5

f = 5 MHz

STM16/OC48 mode

f = 100 kHz

3

10

-

f = 1 MHz

0.3

1.0

0.5

f = 20 MHz

[1] The peak-to-peak jitter tolerance is expressed as a ratio of the Unit Interval (UI):

UI(max) – UI(min)

t _{jit(tol)(p – p)}

=

--------------------------------------------------

UI(nom)

[2] The minimum value of the peak-to-peak jitter tolerance is 0.25 for T_amb= −40 °C to 0 °C at f = 65 kHz and 1 MHz.

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

13 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

[3] The minimum value of the peak-to-peak jitter tolerance is 0.25 for T_amb= −40 °C to 0 °C at f = 250 kHz and 5 MHz.

[4] The minimum value of the peak-to-peak jitter tolerance is 0.25 for T_amb= −40 °C to 0 °C at f = 1 MHz and 20 MHz.

Table 13: I²C-bus characteristics

V_CC= 3.14 V to 3.47 V; T_amb= −40 °C to +85 °C; R_th(j-a)≤ 16 K/W; all characteristics are speciﬁed for the default settings; all

voltages are referenced to ground; positive currents ﬂow into the device; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

DC characteristics: pins SCL and SDA

V_IL

V_IH

V_hys

V_OL1

I_i

LOW level input voltage

-

0.2V_CC

V

HIGH level input voltage

0.8V_CC

-

V

hysteresis of Schmitt trigger inputs

LOW level output voltage

0.05V_CC

-

V

SDA open-drain; I_OL= 3 mA

0

0.4

+10

10

400

-

V

input current each I/O pin

−10

µA

pF

V

C_i

capacitance for each I/O pin

capacitive load for each bus line

noise margin at the LOW-level

noise margin at the HIGH-level

-

C_b

-

V_nL

V_nH

0.1V_CC

0.2V_CC

-

V

Timing (standard mode): pins SCL and SDA

f_SCL

SCL clock frequency

-

100

kHz

µs

t_LOW

LOW period of the SCL clock

hold time (repeated) START condition

HIGH period of the SCL clock

1.3

0.6

-

t_HD;STA

t_HIGH

t_SU;STA

µs

set-up time for a repeated START

condition

µs

t_HD;DAT

t_SU;DAT

t_SU;STO

t_r

data hold time

0

-

0.9

µs

ns

µs

ns

µs

data set-up time

100

0.6

20

1.3

-

setup time for STOP condition

rise time of both SDA and SCL signals

fall time of both SDA and SCL signals

-

300

-

t_f

t_BUF

bus free time between a STOP and

START condition

t_SP

pulse width of spikes that must be

suppressed by the input ﬁlter

0

-

50

ns

SDA

SCL

t

f

t

SU;DAT

t

r

t

LOW

f

r

HD;STA

SP

BUF

t

HD;STA

SU;STA

SU;STO

t

HIGH

HD;DAT

P

S

Sr

msc610

Fig 4. I²C-bus timing

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

14 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

10. Package outline

HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads;

body 14 x 14 x 1 mm; exposed die pad

SOT638-1

c

y

exposed die pad side

X

D

h

A

75

51

50

76

Z

E

e

H

E

(A )

3

A

h

2

A

1

w M

p

θ

b

L

p

pin 1 index

L

detail X

26

100

1

25

w M

Z

v

M

A

B

D

b

p

e

D

B

H

D

0

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

θ

UNIT

A

b

c

D

E

e

H

L

p

v

w

y

Z

1

2

3

p

h

D

E

D

E

max.

0.15 1.05

0.05 0.95

0.27 0.20 14.1 7.1 14.1 7.1

0.17 0.09 13.9 6.1 13.9 6.1

16.15 16.15

15.85 15.85

0.75

0.45

1.15 1.15

0.85 0.85

7°

0°

mm

1.2

0.25

0.5

1

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-04-07

05-02-02

SOT638-1

MS-026

Fig 5. Package outline SOT638-1 (HTQFP100)

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

15 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

11. Revision history

Table 14: Revision history

Document ID

Release date

Data sheet status

Change notice

Doc. number

Supersedes

TZA3012HW_1

20051215

Product data sheet

-

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

16 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

12. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

13. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

makes no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

15. Trademarks

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.

A-Rate — is a trademark of Koninklijke Philips Electronics N.V.

14. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

16. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

TZA3012HW_1

Product data sheet

Rev. 01 — 15 December 2005

17 of 18

TZA3012HW

Philips Semiconductors

30 Mbit/s up to 3.2 Gbit/s A-Rate ﬁber-optic receiver

17. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Dual limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Data and clock recovery . . . . . . . . . . . . . . . . . . 1

Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Additional features with I²C-bus . . . . . . . . . . . . 2

2.1

2.2

2.3

2.4

2.5

3

4

5

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal characteristics. . . . . . . . . . . . . . . . . . . 8

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 9

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Contact information . . . . . . . . . . . . . . . . . . . . 17

8

9

10

11

12

13

14

15

16

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 15 December 2005

Document number: TZA3012HW_1

Published in The Netherlands


型号：	TZA3012HW
厂家：	NXP
描述：	30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 30 Mbit / s的高达3.2 Gbit / s的速率连接的BER光接收器
文件：	总18页 (文件大小：100K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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