UDA1320A [NXP]
Low-cost stereo filter DAC; 低价位立体声DAC过滤器
| 型号： | UDA1320A |
| 厂家： | 
NXP |
| 描述： | Low-cost stereo filter DAC |
| 文件： | 总20页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
UDA1320ATS
Low-cost stereo filter DAC
Preliminary specification
2000 Jan 10
Supersedes data of 1999 Oct 11
File under Integrated Circuits, IC01
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
CONTENTS
1
FEATURES
1.1
1.2
1.3
1.4
General
Multiple format input interface
DAC digital sound processing
Advanced audio configuration
2
3
4
5
6
7
8
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
System clock
Application modes
Multiple format input interface
Static pin mode
Pin compatibility
Interpolation filter (DAC)
Noise shaper
Filter-Stream DAC
9
L3 INTERFACE DESCRIPTION
9.1
9.2
9.3
The L3 interface
Data transfer mode
Programming the features
10
11
12
13
14
15
LIMITING VALUES
HANDLING
QUALITY SPECIFICATION
THERMAL CHARACTERISTICS
DC CHARACTERISTICS
AC CHARACTERISTICS
15.1
15.2
Analog
Digital
16
17
18
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
18.1
18.2
18.3
18.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
19
20
DEFINITIONS
LIFE SUPPORT APPLICATIONS
2000 Jan 10
2
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
1
FEATURES
General
1.1
• Low power consumption.
• 2.7 to 3.6 V power supply.
• Selectable control via L3 microcontroller interface or via
static pin control.
• 256, 384 and 512fs system clock (fsys), selectable via
the L3 interface or 256 and 384fs clock mode via static
pin control
2
APPLICATIONS
• supports sampling frequencies from 16kHz to 48kHz.
• Portable digital audio equipment, see Fig.8.
• Set-top boxes
• Integrated digital filter plus non inverting DAC
Digital-to-Analog Converter (DAC).
• Easy application and no analog post filtering required for
DAC.
3
GENERAL DESCRIPTION
The UDA1320ATS/N2 is a single-chip non inverting stereo
DAC employing bitstream conversion techniques. The low
power consumption and low voltage requirements make
the device eminently suitable for use in digital audio
equipment which incorporates playback functions.
• Slave mode only applications.
• Small package size (SSOP16).
1.2
Multiple format input interface
• I2S-bus, MSB-justified and LSB-justified 16,18 and 20
bits format compatible (in L3-mode).
The UDA1320ATS/N2 supports the I2S-bus data format
with word lengths of up to 20 bits, the MSB-justified data
format with word lengths of up to 20 bits and the
LSB-justified serial data format with word lengths of 16,
18 and 20 bits.
• I2S-bus and LSB-justified 16,18 and 20 bits format
compatible in static mode.
• 1fs input format data rate.
The UDA1320ATS/N2 can be used in two modes, either
L3-mode or static pin mode.
1.3
DAC digital sound processing
• Digital logarithmic volume control via L3.
In the L3-mode, all digital sound processing features must
be controlled via the L3 interface, including the selection of
the system clock setting.
• Digital de-emphasis for 32, 44.1 and 48 kHz fs via
L3 or 44.1 kHz fs via static pin control.
In the two static-modes, the UDA1320ATS/N2 can be
operated in the 256fs and 384fs system clock mode. The
mute, de-emphasis for 44.1 kHz and 4 digital input formats
(I2S and 16, 18, 20 bits LSB formats) can be selected via
static pins. The L3 interface cannot be used in this
application mode, also, volume control is not available in
this mode.
• Soft mute via static pin control or via L3 interface.
1.4
Advanced audio configuration
• Stereo line output (under L3 volume control)
• High linearity, wide dynamic range, low distortion.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
UDA1320ATS
SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
2000 Jan 10
3
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
5
QUICK REFERENCE DATA
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA
VDDD
IDDA
analog supply voltage
digital supply voltage
DAC supply current
digital supply current
ambient temperature
2.7
3.3
3.6
V
V
2.7
−
3.3
6.5
3.0
−
3.6
−
mA
mA
°C
IDDD
Tamb
−
−
−40
+85
DAC
Vo(rms)
output voltage (RMS value)
note 1, 2
−
1.0
−90
−38
100
100
−
−
V
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio
at 0 dB
−
−85
−35
95
−
dB
dB
dB
dB
°C
at −60 dB; A-weighted
code = 0; A-weighted
−
S/N
αcs
signal-to-noise ratio
channel separation
ambient temperature
−
−
Tamb
−40
+85
Notes
1. the output voltage has been changed with respect to the UDA1320TZ/N1.
2. the output voltage scales linearly with the power supply voltage.
6
BLOCK DIAGRAM
V
V
SSD
5
DDD
4
7
APPSEL
1
2
3
11
BCK
WS
APPL0
APPL1
APPL2
APPL3
CONTROL
INTERFACE
10
9
DIGITAL INTERFACE
DATAI
8
VOLUME/MUTE/DE-EMPHASIS
INTERPOLATION FILTER
NOISE SHAPER
UDA1320A
6
SYSCLK
16
DAC
DAC
14
V
V
O(L)
O(R)
13
15
12
MGM816
V
V
V
REF(DAC)
DDA
SSA
Fig.1 Block diagram.
2000 Jan 10
4
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
7
PINNING
8
FUNCTIONAL DESCRIPTION
System clock
8.1
SYMBOL PIN
DESCRIPTION
The UDA1320ATS/N2 operates in slave mode only. This
means in all applications the system devices must provide
the system clock. The system frequency is selectable and
depends on the mode of operation.
BCK
1
2
3
4
5
6
7
8
9
bit clock
WS
word select
DATAI
VDDD
data input
digital power supply
digital ground
The options are 256fs, 384fs and 512fs for the L3 mode
and 256fs plus 384fs for the static mode. The system clock
must be locked in frequency to the digital interface input
signals.
VSSD
SYSCLK
APPSEL
APPL3
APPL2
APPL1
APPL0
VREF(DAC)
VDDA
system clock: 256fs, 384fs, 512fs
application mode select
application pin 3
application pin 2
The UDA1320ATS/N2 supports sampling frequencies
from 16kHz up to 48kHz
10 application pin 1
11 application pin 0
12 DAC reference voltage
13 analog supply voltage
14 left output voltage
15 analog ground
8.2
Application modes
The application mode can be set with the tri-value
APPSEL pin, to L3 mode (APPSEL = VSSD) or to either of
two static modes (APPSEL = 0.5VDDD or
APPSEL = VDDD). See Table 1 for APPL0 to APPL3 pin
functions (active = HIGH).
VO(L)
VSSA
VO(R)
16 right output voltage
Table 1 Selection modes via APPSEL (note 1)
APPSEL
PIN
0.5VDDD
(384fs)
VDDD
(256fs)
VSSD
handbook, halfpage
BCK
WS
1
2
3
4
5
6
7
8
16
15
14
13
12
V
V
V
V
V
O(R)
APPL0 TEST
MUTE
MUTE
SSA
APPL1 L3CLOCK
APPL2 L3MODE
APPL3 L3DATA
DEEM
SF0
DEEM
SF0
DATAI
O(L)
SF1
SF1
V
DDD
DDA
UDA1320A
V
SSD
REF(DAC)
For example, in static pin control mode, the output signal
can be soft muted by setting APPL0 HIGH. De-emphasis
can be switched on for 44.1 kHz by setting APPL1 HIGH.
APPL1 LOW will disable de-emphasis.
SYSCLK
APPSEL
APPL3
11 APPL0
10 APPL1
9
APPL2
Note that when L3 interface is used, an L3 initialisation
must be done when the IC is powered up!
MGM817
In L3 mode pin APPL0 must be set to LOW.
Fig.2 Pin configuration.
2000 Jan 10
5
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
8.3
Multiple format input interface
IMPORTANT: UDA1320ATS/N2 differs from the
UDA1320TZ/N1 with respect to:
L3 mode:
•
•
in the static mode 384fs is supported instead of 512fs.
• I2S-bus with data word length of up to 20 bits
the output voltage of the DAC. In the UDA1320TZ/N1
this is 800mVrms at 3.0V, now it is 1Vrms at 3.3V power
supply
• MSB-justified format with data word length up to 20 bits
• LSB-justified format with data word length of 16,
18 or 20 bits.
8.6
Interpolation filter (DAC)
8.4
Static pin mode
The digital filter interpolates from 1 to 128fs by cascading
a recursive filter and a FIR filter, see Table 3.
The UDA1320ATS/N2 supports the following data input
name formats in the static pin mode (via SF0 and SF1):
• I2S bus with data word length of up to 20 bits
Table 3 Interpolation filter characteristics
• LSB-justified format with data word length of 16,
18 or 20 bits.
ITEM
CONDITION
VALUE (dB)
Pass-band ripple
Stop band
0 to 0.45fs
>0.55fs
±0.1
−50
108
See Table 2, for the static pin codes of the 4 formats,
selectable via SF0 and SF1.
Dynamic range
0 to 0.45fs
The UDA1320ATS/N2 also accepts double speed data for
double speed data monitoring purposes.
8.7
Noise shaper
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter-Stream DAC (FSDAC).
Table 2 Input format selection using SF0 and SF1
FORMAT
SF0
SF1
I2S
0
0
1
1
0
1
0
1
LSB-justified 16 bits
LSB-justified 18 bits
LSB-justified 20 bits
8.8
Filter-Stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to be
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed. The WS signal
must have 50% duty-factor for all LSB-justified modes.
For BCK and WS holds that the BCK frequency must be
equal or smaller then 64 times WS, or fBCK =< 64*fWS in
both L3 and static mode.
8.5
Pin compatibility
In L3 interface mode the UDA1320ATS/N2 can be used on
boards that are designed for the UDA1322. The software
for UDA1322 can be used for the UDA1320ATS/N2 to
control de-emphasis, volume control and mute and also
the status settings like system clock setting and input data
format.
The output voltage of the FSDAC scales linearly with the
power supply voltage.
2000 Jan 10
6
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WS
BCK
LEFT
3
RIGHT
3
1
2
≥8
1
2
≥8
DATAI
MSB B2
LSB MSB B2
LSB MSB
2
INPUT FORMAT I S-BUS
WS
BCK
LEFT
RIGHT
1
2
3
≥8
1
2
3
≥8
DATAI
MSB B2
LSB MSB B2
LSB MSB B2
MSB-JUSTIFIED FORMAT
WS
RIGHT
LEFT
16
15
2
1
16
15
2
1
BCK
DATAI
MSB B2
B15 LSB
MSB B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
WS
RIGHT
17
LEFT
18
17
16
15
2
1
18
16
15
2
1
BCK
DATAI
LSB
LSB
MSB B2
B3
B4
B17
MSB B2
B3
B4
B17
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
18
RIGHT
17 16
20
19
17
16
15
2
1
20
19
18
15
2
1
BCK
LSB
LSB
DATAI
MSB B2
B3
B4
B5
B6
B19
MSB B2
B3
B4
B5
B6
B19
MBK071
LSB-JUSTIFIED FORMAT 20 BITS
Fig.3 Serial interface; input format I2S-bus.
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
9
L3 INTERFACE DESCRIPTION
The L3 interface
Data transfer can only be in one direction, consisting of
input to the UDA1320ATS/N2 to program sound
processing and other functional features.
9.1
The following system and digital sound processing
features can be controlled in the microcontroller mode of
the UDA1320ATS/N2:
Data bits 7 to 2 represent a 6-bit device address, bit 7
being the MSB. The address of the UDA1320ATS/N2 is
000101 (bit 7 to bit 2). If the UDA1320ATS/N2 receives a
different address, it will deselect its microcontroller
interface logic.
• System clock frequency
• Data input format
• De-emphasis for 32 kHz, 44.1 kHz and 48 kHz
• Volume
9.2
Data transfer mode
The selected address remains active during subsequent
data transfers until the UDA1320ATS/N2 receives a new
address command. The fundamental timing of data
transfers is essentially the same as in the address mode,
see Fig.6. The maximum input clock and data rate is 64 fs.
All transfers are by 8-bit bytes. Data will be stored in the
UDA1320ATS/N2 after reception of a complete byte. See
Fig.5 for a multi-byte transfer.
• Soft mute.
The exchange of data and control information between the
microcontroller and the UDA1320ATS/N2 is accomplished
through a serial hardware interface comprising the
following pins:
• L3DATA
• L3MODE
• L3CLOCK.
Table 4 Selection of data transfer
Information transfer through the microcontroller bus is
organized in accordance with the L3 format, in which two
different modes of operation can be distinguished; address
mode and data transfer mode (see Figs 4 and 6).
BIT 1 BIT 0
TRANSFER
0
0
1
0
1
0
DATA (volume, de-emphasis, mute)
not used
STATUS (system clock frequency,
data input format)
The address mode is required to select a device
communicating via the L3 bus and to define the
destination registers for the data transfer mode.
1
1
not used
L3MODE
t
t
su(L3)A
h(L3)A
t
CLK(L3)L
t
t
t
CLK(L3)H
su(L3)A
h(L3)A
L3CLCK
T
cy(CLK)(L3)
t
t
su(L3)DA
h(L3)DA
BIT 0
BIT 7
L3DATA
MBK072
Fig.4 Timing address mode.
2000 Jan 10
8
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
t
stp(L3)
L3MODE
L3CLK
L3DATA
MBK074
address
data byte #1
data byte #2
address
Fig.5 Multi-byte transfer.
t
t
stp(L3)
stp(L3)
L3MODE
t
CLK(L3)L
t
T
h(L3)D
cy(CLK)L3
t
t
CLK(L3)H
su(L3)D
L3CLCK
t
t
t
h(L3)DA
h(L3)DA
su(L3)DA
L3DATA
write
BIT 0
BIT 7
MBK073
Fig.6 Timing for data transfer mode.
The sound feature values are stored in independent
registers. The first selection of the registers is achieved by
the choice of data type that is transferred (‘STATUS’ or
‘DATA’ transfer). This is performed in the address mode
using bit 1 and bit 0, see Table 4,. The settings that can be
controlled with ‘STATUS’ transfer are given in table 5, and
the settings that can be controlled using ‘DATA’ transfer
are given in table 6.
The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6). The other bits in the data byte
(bit 5 to bit 0) is the value that is placed in the selected
registers.
2000 Jan 10
9
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
Table 5 Data transfer of type ‘status’
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REGISTER SELECTED
System Clock frequency (1 : 0);
0
0
SC1 SC0
IF2
IF1
IF0
0
data Input Format (2 : 0)
1
0
0
0
0
0
0
0
reserved
Table 6 Data transfer of type ‘data’
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REGISTER SELECTED
VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 : 0)
0
0
1
1
0
1
0
1
0
0
0
0
0
0
MT
0
0
0
0
0
0
1
reserved
DE1 DE0
DE-emphasis (1 : 0); MuTe
default setting
0
0
9.3
Programming the features
Volume control: a 6-bit value to program the volume
attenuation (VC5 to VC0), 0 to −∞ dB in steps of 1 dB.
When the data transfer of type ‘STATUS’ is selected, the
features SYSTEM CLOCK FREQUENCY and DATA
INPUT FORMAT can be controlled.
Table 9 Volume settings
VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)
System clock frequency: a 2-bit value to select the used
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
1
1
:
0
1
0
1
:
0
0
external clock frequency.
Table 7 System clock settings
−1
−2
:
SC1
SC0
FUNCTION
512fs
0
0
1
1
0
1
0
1
384fs
1
1
1
1
1
1
1
1
0
1
1
1
−60
−∞
256fs
not used
De-emphasis: a 2-bit value to enable the digital
de-emphasis filter.
Data input format: a 3-bit value to select the data format.
Table 8 Data input format settings
Table 10 De-emphasis settings
DE1
DE0
FUNCTION
no de-emphasis
IF2
IF1
IF0
FUNCTION
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I2S bus
de-emphasis, 32 kHz
de-emphasis, 44.1 kHz
de-emphasis, 48 kHz
LSB-justified, 16 bits
LSB -justified, 18 bits
LSB-justified, 20 bits
MSB-justified
not used
Mute: a 1-bit value to enable the digital mute.
Table 11 Mute setting
not used
not used
MT
FUNCTION
0
1
no muting
muting
When the data transfer of type ‘DATA’ is selected, the
features VOLUME, DE-EMPHASIS and MUTE can be
controlled.
2000 Jan 10
10
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
digital supply voltage
CONDITIONS
MIN.
MAX.
5.0
UNIT
VDDD
VDDA
Txtal(max)
Tstg
note 1
note 1
−
−
−
V
V
analog supply voltage
maximum crystal temperature
storage temperature
5.0
150
°C
°C
°C
V
−65
+125
+85
Tamb
Ves
ambient temperature
electrostatic handling
−40
note 2
note 3
−3000
−300
+3000
+300
V
Notes
1. All supply connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pin 14 which must be specified to
−2500V (MIN) and +2500V (MAX).
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
12 QUALITY SPECIFICATION
In accordance with “SNW-FQ-611-E”. The number of the quality specification can be found in the “Quality Reference
Handbook”. The handbook can be ordered using the code 9397 750 00192.
13 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
190
K/W
2000 Jan 10
11
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
14 DC CHARACTERISTICS
VDDD = VDDA = 3.3 V; Tamb = 25 °C; RL = 5 kΩ. All voltages referenced to ground (pins 5 and 15) unless otherwise
specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNIT
VDDA
VDDD
IDDA
DAC analog supply voltage
digital supply voltage
analog supply current
digital supply current
note 1
2.7
2.7
−
3.3
3.3
6.5
3.0
3.6
3.6
−
V
V
note 1
operation mode
operation mode
mA
mA
IDDD
−
−
Digital input pins
VIH
VIL
ILI
HIGH-level input voltage
0.8VDDD
−
−
−
−
−
−
−
V
LOW-level input voltage
input leakage current
input capacitance
−
0.2VDDD
V
−
1
µA
pF
Ci
−
10
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
−
VDDD + 0.5 V
−0.5
−
V
DAC
Vref
reference voltage
with respect to VSSA
0.45VDDA 0.5VDDA
0.55VDDA
V
Io(max)
maximum output current
(THD + N)/S < 0.1%
−
0.22
−
mA
RL = 5 kΩ
Rout
RL
output resistance
load resistance
load capacitance
−
3
−
0.15
−
2.0
−
Ω
kΩ
pF
CL
note 2
−
50
Notes
1. All supply connections must be made to the same external power supply unit.
2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
2000 Jan 10
12
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
15 AC CHARACTERISTICS
15.1 Analog
VDDD = VDDA = 3.3 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ. All voltages referenced to ground (pins 5 and 15) unless
otherwise specified.
SYMBOL
DAC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vo(rms)
output voltage (RMS value)
unbalance between channels
−
−
−
−
−
−
−
1.0
−
−
V
∆Vo
0.1
−90
−38
100
100
50
dB
dB
dB
dB
dB
dB
(THD + N)/S total harmonic distortion plus at 0 dB
noise-to-signal ratio
−85
-35
95
−
at −60 dB; A-weighted
S/N
signal-to-noise ratio
channel separation
code = 0; A-weighted
αcs
PSRR
power supply ripple rejection
ratio
fripple = 1 kHz;
−
Vripple(p-p) = 100 mV
2000 Jan 10
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
15.2 Digital
VDDD = VDDA = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ. All voltages referenced to ground (pins 5 and 15); unless
otherwise specified.
SYMBOL
Tsys
PARAMETER
system clock cycle
CONDITIONS
fsys = 256fs
fsys = 384fs
sys = 512fs
fsys < 19.2 MHz
sys ≥ 19.2 MHz
fsys < 19.2 MHz
sys ≥ 19.2 MHz
MIN.
78
TYP.
88
MAX.
244
UNIT
ns
52
39
30
40
30
40
59
44
−
162
122
70
ns
f
ns
tCWL
LOW-level system clock pulse width
HIGH-level system clock pulse width
%Tsys
%Tsys
%Tsys
%Tsys
f
−
60
tCWH
−
70
f
−
60
Serial input data timing (see Fig.7)
Tcy(CLK)(bit) bit clock period
300
100
100
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLKH(bit)
tCLKL(bit)
tr
bit clock HIGH time
bit clock LOW time
rise time
−
−
20
20
−
tf
fall time
−
tsu(i)(D)
th(i)(D)
tsu(WS)
th(WS)
data input set-up time
data input hold time
word selection set-up time
word selection hold time
20
0
−
20
10
−
−
Microcontroller interface timing (see Figs 4 and 6)
Tcy(CLK)(L3) L3CLK
500
250
250
190
190
190
190
190
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
tCLK(L3)H
tCLK(L3)L
tsu(L3)A
th(L3)A
L3CLK HIGH period
L3CLK LOW period
L3MODE set-up time
L3MODE hold time
L3MODE set-up time
L3MODE hold time
L3DATA set-up time
addressing mode
addressing mode
data transfer mode
data transfer mode
tsu(L3)D
th(L3)D
tsu(L3)DA
data transfer and
addressing mode
th(L3)DA
tstp(L3)
L3DATA hold time
L3MODE halt time
data transfer and
addressing mode
30
−
−
−
−
ns
ns
190
2000 Jan 10
14
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
WS
t
t
h(WS)
CLKH(bit)
t
su(WS)
t
t
r
f
BCLK
t
CLKH(bit)
t
t
su(i)(D)
h(i)(D)
T
cy(CLK)(bit)
DATAI
MBK075
Fig.7 Serial interface timing.
16 APPLICATION INFORMATION
analog
supply voltage
digital
supply voltage
R2
1 Ω
R3
1 Ω
C1
100 µF
(16 V)
C5
C6
100 nF
(63 V)
100 nF
(63 V)
V
V
V
V
SSA
DDA
SSD
DDD
14
15
13
5
4
R1
SYSCLK
system
clock
6
47 Ω
C2
V
V
R4
O(L)
left
output
100 Ω
BCK
WS
47 µF
(16 V)
1
2
3
7
R5
10 kΩ
DATAI
APPSEL
C3
R6
100 Ω
O(R)
right
output
UDA1320A
47 µF
(16 V)
R7
10 kΩ
16
12
APPL0
APPL1
APPL2
APPL3
11
10
9
V
REF(DAC)
8
C7
C4
47 µF
(16 V)
100 nF
(63 V)
MGM818
Fig.8 Application schematic.
15
2000 Jan 10
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
17 PACKAGE OUTLINE
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
10o
0o
0.15
0.00
1.4
1.2
0.32
0.20
0.25
0.13
5.30
5.10
4.5
4.3
6.6
6.2
0.75
0.45
0.65
0.45
0.48
0.18
mm
1.0
1.5
0.65
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
99-12-27
SOT369-1
MO-152
2000 Jan 10
16
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
18 SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
18.1 Introduction to soldering surface mount
packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
18.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
18.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2000 Jan 10
17
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
18.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
19 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Jan 10
18
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
NOTES
2000 Jan 10
19
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
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Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
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Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/25/02/pp20
Date of release: 2000 Jan 10
Document order number: 9397 750 06675
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