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UDA1321PS/N101 [NXP]

Universal Serial Bus USB Digital-to-Analog Converter DAC; 通用串行总线USB数位类比转换器DAC
UDA1321PS/N101
型号： UDA1321PS/N101
厂家： NXP    NXP
描述：

Universal Serial Bus USB Digital-to-Analog Converter DAC
通用串行总线USB数位类比转换器DAC

转换器
文件： 总44页 (文件大小：283K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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INTEGRATED CIRCUITS  
DATA SHEET  
UDA1321  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
1998 Oct 06  
Preliminary specification  
Supersedes data of 1998 May 12  
File under Integrated Circuits, IC01  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
FEATURES  
General  
Document references  
• “USB Specification”  
• “USB Common Class Specification”  
• Universal Serial Bus (USB) stereo Digital-to-Analog  
Converter (DAC) system with adaptive (5 to 55 kHz)  
20-bits digital-to-analog conversion and filtering  
• “USB Device Class Definition for Audio Devices”  
• “Device Class Definition for Human Interface Devices  
• USB-compliant audio and Human Interface Device  
(HID)”  
(HID)  
• “USB HID Usage Table”.  
• Supports 12 Mbits/s full-speed serial data transmission  
• Supports multiple audio data formats (8, 16 and 24 bits)  
• Supports headphone and line output  
• Fully automatic ‘Plug-and-Play’ operation  
• High linearity  
APPLICATIONS  
• USB monitors  
• USB speakers  
• USB headsets  
• Wide dynamic range  
• USB telephone/answering machines  
• USB links in consumer audio devices.  
• Superior signal-to-noise ratio (typical 95 dB)  
• Low total harmonic distortion (typical 90 dB)  
• 3.3 V power supply  
GENERAL DESCRIPTION  
• Efficient power management  
The UDA1321 is a stereo CMOS digital-to-analog  
bitstream converter designed for USB-compliant audio  
playback devices and multimedia audio  
• Low power consumption  
• On-chip master clock oscillator, only an external crystal  
is required  
applications.The UDA1321 is an adaptive asynchronous  
sink USB audio device with a continuous sampling  
frequency (fs) range from 5 to 55 kHz. It contains a USB  
interface, an embedded microcontroller and an  
Asynchronous Digital-to-Analog Converter (ADAC).  
• Partly programmable USB descriptors and configuration  
via I2C-bus.  
Sound processing  
The USB interface is the interface between the USB, the  
ADAC and the microcontroller. The USB interface consists  
of an analog front-end and a USB processor. The analog  
front-end transforms the differential USB data to a digital  
data stream. The USB processor buffers the input and  
output data from the analog front-end and handles all  
low-level USB protocols. The USB processor selects the  
relevant data from the universal serial bus, performs an  
extensive error detection and separates control  
information (input and output) and audio information (input  
only).  
• Separate digital volume control for left and right channel  
• Soft mute  
• Digital bass and treble tone control  
• External Digital Sound Processor (DSP) option possible  
via standard I2S-bus or Japanese digital I/O format  
• Selectable clipping prevention  
• Selectable Dynamic Bass Boost (DBB)  
• On-chip digital de-emphasis.  
1998 Oct 06  
2
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
The control information becomes accessible at the  
microcontroller. The audio information becomes available  
at the digital I/O output or is fed directly to the ADAC.  
The ADAC consists of FIFO registers, a unique audio  
feature processing DSP, the SFG, digital up-sampling  
filters, a variable hold register, a Noise Shaper (NS) and a  
Filter Stream DAC (FSDAC) with integrated filter and line  
output drivers. The audio information is applied to the  
ADAC via the USB processor or via the digital I/O input.  
The microcontroller handles the high-level USB protocols,  
translates the incoming control requests and manages the  
user interface via General Purpose (GP) pins and an  
I2C-bus.  
An external DSP can be used for adding extra sound  
processing features via the digital I/O-bus.  
The ADAC enables the wide and continuous range of input  
sampling frequencies. By means of a Sample Frequency  
Generator (SFG), the ADAC is able to reconstruct the  
average sample frequency from the incoming audio  
samples. The ADAC also performs the sound processing.  
The UDA1321 supports the standard I2S-bus data input  
format and the LSB-justified serial data input format with  
word lengths of 16, 18 and 20 bits.  
The wide dynamic range of the bitstream conversion  
technique used in the UDA1321 guarantees a high audio  
sound quality.  
QUICK REFERENCE DATA  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
Supplies  
VDD  
supply voltage  
note 1  
note 3  
3.0  
3.3  
3.6  
−
V
IDD(tot)  
IDD(ps)  
total supply current  
−
−
50  
18  
mA  
mA  
supply current in power-save  
mode  
−
Dynamic performance DAC  
total harmonic  
distortion-plus-noise to signal  
ratio  
fs = 44.1 kHz; RL = 5 kΩ  
THD + N  
----------------------  
S
at input signal of 1 kHz (0 dB)  
−
−
−90(2) −80  
0.0032 0.01  
−30(2) −20  
dB  
%
at input signal of 1 kHz (−60 dB) −  
dB  
%
−
3.2  
95  
10  
S/Nbz  
signal-to-noise ratio at bipolar  
zero  
A-weighted at code 0000H  
VDD = 3.3 V  
90  
−
dBA  
Vo(FS)(rms)  
full-scale output voltage  
(RMS value)  
−
0.66  
−
V
General characteristics  
fi(sample) audio sample input frequency  
Tamb operating ambient temperature  
5
0
−
55  
70  
kHz  
25  
°C  
Notes  
1. VDD is the supply voltage on pins VDDA, VDDE, VDDI and VDDX. VSS is the ground on pins VSSA, VSSE, VSSI and VSSX  
.
All VDD and VSS pins must be connected to the same supply or ground respectively.  
2. The audio information from the USB interface is fed directly to the ADAC.  
3. The power-save mode (power management) is not supported in the UDA1321/N101;  
see Chapter “USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)”.  
1998 Oct 06  
3
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
ORDERING INFORMATION  
PACKAGE  
TYPE NUMBER  
NAME  
DESCRIPTION  
VERSION  
UDA1321H/N101  
QFP64  
plastic quad flat package; 64 leads (lead length 1.95 mm);  
SOT319-2  
body 14 × 20 × 2.8 mm  
UDA1321T/N101  
UDA1321PS/N101  
SO28  
plastic small outline package; 28 leads; body width 7.5 mm  
plastic shrink dual in-line package; 32 leads (400 mil)  
SOT136-1  
SOT232-1  
SDIP32  
1998 Oct 06  
4
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
BLOCK DIAGRAM  
D+  
D−  
TC  
SCL  
TEST  
CONTROL  
BLOCK  
ANALOG FRONT-END  
USB-PROCESSOR  
RTCB  
SDA  
EA  
SHTCB  
PSEN  
ALE  
P2.0  
P2.1  
GP4/BCKO  
GP3/WSO  
GP2/DO  
P2.2  
P2.3  
DIGITAL I/O  
GP1/DI  
P2.4  
P2.5  
GP0/BCKI  
GP5/WSI  
MICRO-  
CONTROLLER  
P2.6  
P2.7  
P0.0  
P0.1  
FIFO REGISTERS  
P0.2  
f
s
P0.3  
P0.4  
SAMPLE  
FREQUENCY  
GENERATOR  
AUDIO FEATURE  
PROCESSING DSP  
P0.5  
P0.6  
f
s
P0.7  
UP-SAMPLE FILTERS  
64f  
s
V
DDE  
V
SSE  
V
SSX  
VARIABLE HOLD REGISTER  
V
SSI  
UDA1321H  
UDA1321T  
UDA1321PS  
XTAL1  
XTAL2  
V
128f  
s
DDI  
OSC TIMING  
V
DDO  
V
DDX  
3rd-ORDER  
NOISE SHAPER  
V
SSO  
V
DDA  
V
SSA  
LEFT  
DAC  
RIGHT  
DAC  
VOUTL  
VOUTR  
REFERENCE  
VOLTAGE  
MGM839  
V
ref  
Fig.1 Block diagram.  
5
1998 Oct 06  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
PINNING  
PIN  
QFP64  
PIN  
SDIP32  
PIN  
SO28  
SYMBOL  
I/O  
DESCRIPTION  
GP5/WSI  
SCL  
2
3
29  
30  
25  
26  
I/O general purpose pin 5 or word select input  
I/O serial clock input (I2C-bus)  
SDA  
4
31  
27  
I/O serial data input/output (I2C-bus)  
P0.7  
5
n.a.  
n.a.  
32  
n.a.  
n.a.  
28  
I/O Port 0.7 of the microcontroller  
EA  
6
I/O external access (active LOW)  
GP1/DI  
PSEN  
ALE  
7
I/O general purpose pin 1 or data input  
I/O program store enable (active LOW)  
I/O address latch enable (active HIGH)  
8
n.a.  
n.a.  
1
n.a.  
n.a.  
1
9
GP2/DO  
10  
I/O general purpose pin 2 or data output for extra DSP  
chip  
P2.0  
11  
12  
13  
n.a.  
n.a.  
2
n.a.  
n.a.  
2
I/O Port 2.0 of the microcontroller  
I/O Port 2.1 of the microcontroller  
P2.1  
GP3/WSO  
I/O general purpose pin 3 or master word select output for  
extra DSP chip  
GP4/BCKO  
14  
3
3
I/O general purpose pin 4 or master bit clock output for  
extra DSP chip  
SHTCB  
15  
17  
4
6
4
5
I
shift clock TCB input (active HIGH)  
D−  
I/O negative data line of the differential data bus conform  
to the USB-standard  
P2.2  
P2.3  
D+  
18  
19  
20  
n.a.  
n.a.  
7
n.a.  
n.a.  
6
I/O Port 2.2 of the microcontroller  
I/O Port 2.3 of the microcontroller  
I/O positive data line of the differential data bus conform to  
the USB-standard  
P2.4  
21  
22  
23  
24  
25  
29  
30  
32  
36  
37  
38  
39  
42  
44  
45  
46  
49  
n.a.  
n.a.  
n.a.  
n.a.  
8
n.a.  
n.a.  
n.a.  
n.a.  
7
I/O Port 2.4 of the microcontroller  
I/O Port 2.5 of the microcontroller  
I/O Port 2.6 of the microcontroller  
I/O Port 2.7 of the microcontroller  
P2.5  
P2.6  
P2.7  
VDDI  
−
−
−
−
−
I
digital supply voltage core  
digital ground core  
VSSI  
9
8
VSSE  
VDDE  
VSSX  
XTAL1  
XTAL2  
VDDX  
Vref  
10  
11  
9
digital ground I/O pins  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
digital supply voltage I/O pins  
crystal oscillator ground  
crystal oscillator input 1  
crystal oscillator output 2  
crystal oscillator supply voltage  
reference output voltage  
analog ground  
13  
14  
15  
16  
18  
19  
20  
21  
22  
O
−
O
−
−
O
−
VSSA  
VDDA  
VOUTR  
VSSO  
analog supply voltage  
right channel output voltage  
operational amplifier ground  
1998 Oct 06  
6
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
PIN  
QFP64  
PIN  
SDIP32  
PIN  
SO28  
SYMBOL  
I/O  
DESCRIPTION  
VDDO  
VOUTL  
TC  
51  
53  
55  
56  
57  
58  
59  
60  
61  
23  
24  
20  
21  
−
O
I
operational amplifier supply voltage  
left channel output voltage  
25  
22  
test control input (active HIGH)  
P0.0  
P0.1  
P0.2  
P0.3  
P0.4  
RTCB  
n.a.  
n.a.  
n.a.  
n.a.  
n.a.  
26  
n.a.  
n.a.  
n.a.  
n.a.  
n.a.  
23  
I/O Port 0.0 of the microcontroller  
I/O Port 0.1 of the microcontroller  
I/O Port 0.2 of the microcontroller  
I/O Port 0.3 of the microcontroller  
I/O Port 0.4 of the microcontroller  
I
asynchronous reset input for test control box (active  
HIGH)  
P0.5  
62  
63  
64  
n.a.  
n.a.  
27  
n.a.  
n.a.  
24  
I/O Port 0.5 of the microcontroller  
P0.6  
I/O Port 0.6 of the microcontroller  
GP0/BCKI  
n.c.  
I/O general purpose pin 0 or master bit clock input  
1, 16, 26,  
27, 28, 31,  
33, 34, 35,  
40, 41, 43,  
47, 48, 50,  
52, 54  
5, 12, 17,  
28  
n.a.  
−
not connected  
1998 Oct 06  
7
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
V
n.c.  
GP5/WSI  
SCL  
1
2
3
4
5
6
7
8
9
51  
50  
49  
48  
47  
DDO  
n.c.  
V
SSO  
n.c.  
n.c.  
SDA  
P0.7  
46 VOUTR  
EA  
GP1/DI  
PSEN  
ALE  
V
V
45  
44  
43  
42  
41  
40  
39  
DDA  
SSA  
n.c.  
V
GP2/DO 10  
P2.0 11  
UDA1321H  
REF  
n.c.  
n.c.  
V
P2.1 12  
GP3/WSO 13  
GP4/BCKO 14  
SHTCB 15  
DDX  
38 XTAL2  
37 XTAL1  
V
n.c.  
16  
36  
35  
34  
33  
SSX  
n.c.  
D− 17  
P2.2 18  
P2.3 19  
n.c.  
n.c.  
MGM850  
Fig.2 Pin configuration QFP64.  
8
1998 Oct 06  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
handbook, halfpage  
handbook, halfpage  
GP2/DO  
GP3/WSO  
GP4/BCKO  
SHTCB  
D−  
GP1/DI  
SDA  
1
2
GP2/DO  
GP1/DI  
SDA  
28  
27  
26  
25  
24  
1
2
32  
31  
GP3/WSO  
GP4/BCKO  
SHTCB  
n.c.  
3
SCL  
3
30 SCL  
GP5/WSI  
GP0/BCKI  
4
4
29  
28  
GP5/WSI  
n.c.  
5
5
D+  
6
23 RTCB  
TC  
D−  
6
27 GP0/BCKI  
26 RTCB  
V
22  
21 VOUTL  
7
D+  
7
DDI  
UDA1321T  
V
V
8
8
25  
24  
23  
22  
21  
20  
19  
18  
17  
TC  
DDI  
SSI  
UDA1321PS  
V
V
V
V
9
20  
19  
18  
17  
16  
15  
VOUTL  
9
SSE  
DDO  
SSO  
SSI  
V
V
V
10  
11  
10  
11  
DDO  
DDE  
SSE  
V
V
VOUTR  
V
SSO  
SSX  
DDE  
XTAL1 12  
V
VOUTR  
n.c. 12  
DDA  
V
XTAL2  
V
V
13  
14  
13  
DDA  
SSA  
SSX  
V
V
V
14  
15  
16  
XTAL1  
XTAL2  
SSA  
DDX  
ref  
V
MGM840  
ref  
V
n.c.  
DDX  
MGM841  
Fig.3 Pin configuration SO28.  
Fig.4 Pin configuration SDIP32.  
1998 Oct 06  
9
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
The PSIE is the digital front-end of the USB processor.This  
module recovers the 12 MHz USB clock, detects the USB  
sync word and handles all low-level USB protocols and  
error checking.  
FUNCTIONAL DESCRIPTION  
All bold-faced parameters given in this data sheet  
such as ‘bAlternateSetting’ are part of the USB  
specification as described in “USB Device Class  
Definition for Audio Devices”.  
The MMU is the digital back-end of the USB processor.  
It handles the temporary data storage of all USB packets  
that are received or sent over the bus. Three types of  
packets are defined on the USB. These are:  
The Universal Serial Bus (USB)  
Data and power are transferred via the USB by a 4-wire  
cable. The signalling occurs via two wires and  
point-to-point segments. The signals on each segment are  
differentially driven into a cable of 90 Ω intrinsic  
impedance. The differential receiver features input  
sensitivity of at least 200 mV and sufficient common mode  
rejection.  
• Token packets  
• Data packets  
• Handshake packets.  
The token packet contains information about the  
destination of the data packet. The audio data is  
transferred via an isochronous data sink endpoint and  
consequently no handshaking mechanism is used.  
The MMU also generates a 1 kHz clock that is locked to  
the USB Start-Of-Frame (SOF) token.  
The analog front-end  
The analog front-end is an on-chip generic USB  
transceiver. It is designed to allow voltage levels up to VDD  
from standard or programmable logic to interface with the  
physical layer of the USB. It is capable of receiving and  
transmitting serial data at full speed (12 Mbits/s).  
THE AUDIO SAMPLE REDISTRIBUTION (ASR) MODULE  
The ASR module reads the audio samples from the MMU  
and distributes these samples equidistant over a 1 ms  
frame period. The distributed audio samples are translated  
by the digital I/O module to standard I2S-bus format or  
Japanese digital I/O format. The ASR module generates  
the bit clock and the word select signal of the digital I/O.  
The digital I/O formats the received audio samples to one  
of the four specified serial digital audio formats  
The USB processor  
The USB processor forms the interface between the  
analog front-end, the ADAC and the microcontroller.  
The USB processor consists of:  
• The Philips Serial Interface Engine (PSIE)  
• The Memory Management Unit (MMU)  
(standard I2S-bus, 16, 18 or 20 bits LSB-justified).  
• The Audio Sample Redistribution (ASR) module.  
The microcontroller  
The microcontroller receives the control information  
selected from the USB by the USB processor. It handles  
the high-level USB protocols and the user interfaces.  
THE PHILIPS SERIAL INTERFACE ENGINE AND MEMORY  
MANAGEMENT UNIT (PSIE AND MMU)  
The PSIE and MMU translate the electrical USB signals  
into bytes and signals. Depending upon the USB device  
address and the USB endpoint address, the USB data is  
directed to the correct endpoint buffer on the PSIE and  
MMU interface. The data transfer could be of the bulk,  
isochronous, control or interrupt type. The USB device  
address is configured during the enumeration process.  
The UDA1321 has three endpoints. These are:  
The major task of the software process, that is mapped  
upon the microcontroller, is to control the different modules  
of the UDA1321 in such a way that it behaves as a USB  
device. Therefore the microcontroller:  
• Interprets the USB requests and maps them upon the  
UDA1321 application  
• Controls the internal operation of the UDA1321 and the  
• Control endpoint 0  
digital I/O pins  
• Status interrupt endpoint  
• Isochronous data sink endpoint.  
• Communicates with the external world (EEPROM) using  
the I2C-bus facility and the general purpose I/O pins.  
The amount of bytes per packet on the control endpoint is  
limited by the PSIE and MMU hardware to 8 bytes per  
packet.  
1998 Oct 06  
10  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
The Asynchronous Digital-to-Analog Converter  
(ADAC)  
Table 1 Frequency domains for audio processing  
DOMAIN  
SAMPLE FREQUENCY (kHz)  
The ADAC receives USB audio information from the USB  
processor or from the digital I/O-bus. The ADAC is able to  
reconstruct the sample clock from the rate at which the  
audio samples arrive and handles the audio sound  
processing. After processing, the audio signal is  
up-sampled, noise-shaped and converted to analog output  
voltages capable of driving a line output. The ADAC  
consists of:  
1
2
3
4
5 to 12  
12 to 25  
25 to 40  
40 to 55  
THE NOISE SHAPER  
A 3rd-order noise shaper converts the oversampled data  
to a noise-shaped bitstream for the FSDAC. The in-band  
quantization noise is shifted to frequencies well above the  
audio band.  
• A Sample Frequency Generator (SFG)  
• First-In First-Out (FIFO) registers  
• An audio feature processing DSP  
• Two digital up-sample filters  
• A variable hold register  
THE FILTER STREAM DAC (FSDAC)  
The FSDAC is a semi-digital reconstruction filter that  
converts the 1-bit data stream of the noise shaper to an  
analog output voltage. The filter coefficients are  
implemented as current sources and are summed at  
virtual ground of the output operational amplifier. In this  
way very high signal-to-noise performance and low clock  
jitter sensitivity is achieved. A post filter is not needed  
because of the inherent filter function of the DAC.  
On-board amplifiers convert the FSDAC output current to  
an output voltage signal capable of driving a line output.  
• A digital Noise Shaper (NS)  
• A Filter Stream DAC (FSDAC) with integrated filter and  
line output drivers.  
THE SAMPLE FREQUENCY GENERATOR (SFG)  
The SFG controls the timing signals for the asynchronous  
digital-to-analog conversion. By means of a digital PLL,  
the SFG automatically recovers the applied sampling  
frequency and generates the accurate timing signals for  
the audio feature processing DSP and the up-sample  
filters.  
USB Digital-to-Analog Converter (DAC) descriptors  
In a typical USB environment the USB host has to know  
which kind of devices are connected. For this purpose  
each device contains a number of USB descriptors. These  
descriptors describe, from different points of view (USB  
configuration, USB interface and USB endpoint), the  
capabilities of a device. Each of them can be requested by  
the host. The collection of descriptors is denoted as a  
descriptor map. This descriptor map will be reported to the  
USB host during enumeration and on request.  
FIRST-IN FIRST-OUT (FIFO) REGISTERS  
The FIFO registers are used to store the audio samples  
temporarily coming from the USB processor or from the  
digital I/O input. The use of a FIFO register (in conjunction  
with the SFG) is necessary to remove all jitter present on  
the incoming audio signal.  
THE AUDIO FEATURE PROCESSING DSP  
The full descriptor map is implemented in the firmware  
exploiting the full functionality of the UDA1321. The USB  
descriptors and their most important fields, in relationship  
to the characteristics of the UDA1321 are briefly explained  
below.  
A DSP processes the sound features. The control and  
mapping of the sound features is explained in Section  
“Controlling the USB Digital-to-Analog Converter (DAC)”.  
Depending on the sampling rate (fs) the DSP has four  
frequency domains in which the treble and bass are  
regulated (see Table 1). The domain is chosen  
automatically.  
GENERAL DESCRIPTORS  
The UDA1321 supports one configuration containing a  
control interface, an audio interface and a HID interface.  
The descriptor map that describes this configuration is  
partly fixed and partly programmable.  
THE UP-SAMPLE FILTERS AND VARIABLE HOLD REGISTER  
After the audio feature processing DSP two up-sample  
filters and a variable hold register increase the  
oversampling rate to 128fs.  
1998 Oct 06  
11  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
INPUT TERMINAL  
FEATURE UNIT  
OUTPUT TERMINAL  
FU  
IT  
OT  
MBK530  
Fig.5 Audio function topology.  
The programmable part can be retrieved from one of four  
configuration maps located in the firmware or from an  
I2C-bus EEPROM. At start-up one of four configuration  
maps can be selected depending on the logical  
combination of GP3 and GP0. It is possible to overwrite  
this configuration map with a configuration map loaded  
from an I2C-bus EEPROM.  
Table 2 Audio bandwidth at each audio mode  
AUDIO MODE wMaxPacketSize  
8-bit PCM; mono  
56 (8⁄8 × 1 × 56)  
8-bit PCM; stereo  
16-bit PCM; mono  
16-bit PCM; stereo  
24-bit PCM; mono  
24-bit PCM; stereo  
112 (8⁄8 × 2 × 56)  
112 (16⁄8 × 1 × 56)  
224 (16⁄8 × 2 × 56)  
168 (24⁄8 × 1 × 56)  
336 (24⁄8 × 2 × 56)  
AUDIO DEVICE CLASS SPECIFIC DESCRIPTORS  
The audio device class is partly specified with standard  
descriptors and partly with specific audio device class  
descriptors. The standard descriptors specify the number  
and the type of the interface or endpoint. The UDA1321  
supports 7 different audio modes:  
The maximum number of audio data samples within a USB  
packet arriving on the isochronous sink endpoint is  
restricted by the buffer capacity of this isochronous  
endpoint. The maximum buffer capacity is 336 bytes/ms.  
• 8-bit Pulse Code Modulation (PCM) mono or stereo  
audio data  
For each alternate setting with audio, a maximum  
bandwidth is claimed as indicated in the standard  
isochronous audio data endpoint descriptor  
wMaxPacketSize field. To allow a small overshoot in the  
number of audio samples per packet, the top sample  
frequency of 55 kHz is taken in the calculation of the  
bandwidth for each alternate setting. For each alternate  
setting, with its own isochronous audio data endpoint  
descriptor, wMaxPacketSize field is then defined as  
described in Table 2.  
• 16-bit PCM mono or stereo audio data  
• 24-bit PCM mono or stereo audio data  
• Zero bandwidth mode.  
Each mode is defined as an alternate setting of the audio  
interface, selectable with the standard audio streaming  
interface descriptor bAlternateSetting field.  
The seven alternate settings are described in more detail  
by the specific audio device class descriptors.  
Although in a specific UDA1321 application no endpoint  
control properties can be used upon the isochronous  
adaptive sink endpoint, the descriptors are still necessary  
to inform the host about the definition of this endpoint:  
isochronous, adaptive, sink, continuous sampling  
frequency (at input side of this endpoint) with lower bound  
of 5 kHz and upper bound of 55 kHz.  
The UDA1321 supports the Input Terminal (IT), Output  
Terminal (OT) and the Feature Unit (FU) descriptors.  
The input and output terminals are not controllable via the  
USB. The feature unit provides the basic manipulation of  
the incoming logical channels.  
The audio class specific descriptors can be requested with  
the ‘Get descriptor: configuration request’, which returns  
all the descriptors, except the device descriptor.  
The supported sound features are:  
• Volume control  
• Mute control  
• Treble control  
HUMAN INTERFACE DEVICE SPECIFIC DESCRIPTORS  
• Bass control  
The inputs defined on the UDA1321 are transmitted via the  
USB to the host according to the HID class. The host  
• Bass boost control.  
1998 Oct 06  
12  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
responds with the appropriate settings via the audio device  
class for the audio related parts or via the HID class for the  
HID related inputs and outputs of the UDA1321.  
Controlling the USB Digital-to-Analog Converter  
(DAC)  
This section describes the functionality of the feature unit  
of the UDA1321. The mapping of this functionality onto  
USB descriptors is as implemented in the firmware.  
A HID descriptor is necessary to inform the host about the  
conception of the user interface. The host communicates  
via the HID device driver using either the control pipe or  
the interrupt pipe. The UDA1321 uses USB endpoint 0  
(control pipe) to respond to the HID specific ‘Get/set report  
request’ to receive or transmit data from or to the  
The sound features as defined in the “USB Device Class  
Definition for Audio Devices” are mapped on the UDA1321  
specific feature registers by the microcontroller. These  
specific sound features are:  
UDA1321. The UDA1321 uses the status interrupt  
endpoint as interrupt pipe for polling asynchronous data.  
• Volume control (separate for left and right stereo  
channels, no master channel)  
The UDA1321 is a high-speed device. The maximum  
transaction size is 64 bytes per USB frame and the polling  
rate is defined at a maximum of every 1 ms.  
• Mute control (only master channel)  
• Treble control (only master channel)  
• Bass control (only master channel)  
The host requests the configuration descriptor which  
includes the standard interface descriptor, the HID  
endpoint descriptor and the HID descriptor. The HID  
device driver of the host then requests the report  
descriptor.  
• Dynamic bass boost control (only master channel).  
These specific features can be activated via the host  
(audio device class requests) or via the GP pins (HID plus  
audio device class requests). Via the I2C-bus the user is  
able to download the necessary configuration data for  
different applications (definition of the function of the GP  
pins, with or without digital I/O functionality, etc.).  
The mapping and control of the standard USB audio  
features and UDA1321 specific features is described  
below.  
Report descriptors are composed of pieces of information  
about the device. Each piece of information is called an  
item. All items have a 1-byte prefix that contains the item  
tag, type and size. In the UDA1321 only the short item  
basic type is used.  
The hosts HID device driver will parse the report descriptor  
and the defined items. By examining all of these items, the  
HID class driver is able to determine the size and  
composition of data reports from the device.  
VOLUME CONTROL  
Volume control is possible via the host or via predefined  
GP pins. The setting of 0 dB is always referenced to the  
maximum available volume setting. Table 3 gives the  
mapping of wVolume value (as defined in the “USB  
Device Class Definition for Audio Devices”) upon the  
actual volume setting of the USB DAC. When using the  
UDA1321, the range is 0 down to −60 dB (in steps of 1 dB)  
and −∞ dB. Independant control of ‘left’/’right’ volume is  
possible. It should be noted that wVolume bits B7 to B0  
are not used. Values above 0 dB are returned as 0 dB.  
The volume value at start-up of the device is defined in the  
selected configuration map.  
The main items of the UDA1321 are input and output  
reports. Input reports are sent via the interrupt pipe  
(UDA1321 USB address 3). Input and output reports can  
be requested by the host via the control endpoint (USB  
address 0).  
The UDA1321 supports a maximum of three pushbuttons,  
which represents a certain feature of the UDA1321. If  
pressed by the user the pushbutton will go to its ‘ON’ state,  
if not pressed the pushbutton will go back to its ‘OFF’ state.  
The UDA1321 supports a maximum of two outputs for e.g.  
user LEDs.  
Balance control is possible via the separate volume control  
option of both channels. Therefore the characteristics of  
the balance control are equal to the volume control  
characteristics.  
For more information about the input and output functions  
of the UDA1321 see the application documentation of the  
device.  
1998 Oct 06  
13  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
Table 3 Volume control characteristics; note 1  
wVOLUME  
VOLUME USB SIDE VOLUME USB DAC  
(dB)  
(dB)  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
0
1
1
1
1
1
1
1
1
1
1
...  
1
1
1
1
...  
1
0
1
1
1
1
1
1
1
1
1
1
...  
1
1
1
1
...  
0
0
1
1
1
1
1
1
1
1
1
1
...  
0
0
0
0
...  
0
0
1
1
1
1
1
1
1
1
1
1
...  
0
0
0
0
...  
0
0
1
1
1
1
1
1
1
1
0
0
...  
0
0
0
0
...  
0
0
1
1
1
1
0
0
0
0
1
1
...  
1
1
0
0
...  
0
0
1
1
0
0
1
1
0
0
1
1
...  
0
0
1
1
...  
0
0
1
0
1
0
1
0
1
0
1
0
...  
1
0
1
0
...  
0
0
0
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
...  
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
...  
−59  
−60  
−61  
−62  
...  
−59  
−60  
−∞  
−∞  
...  
−∞  
−∞  
Note  
1. The volume control characteristics of this table are in accordance with the latest Audio Device Class Definition.  
The volume control characteristics of the UDA1321/N101 are slightly different; see Chapter “USB-DAC  
UDA1321/N101 (Firmware sw 2.1.1.7)”  
This amounts to a mute transition of 23 ms at  
fs = 44.1 kHz. When the mute is released, the samples are  
returned to the full level again following a raised cosine  
curve with the same coefficients being used in reversed  
order. The mute, on the master channel is synchronized to  
the sample clock, so that operation always takes place on  
complete samples.  
MUTE CONTROL  
Mute is one of the sound features as defined in the “USB  
Device Class Definition for Audio Devices”. The mute  
control request data bMute controls the position of the  
mute switch. The position can be either on or off. When  
bMute is true the feature unit is muted. When bMute is  
false the feature unit is not muted.  
A mute can be given via the host or by pressing a  
predefined GP pin.  
When the mute is active for the master channel, the value  
of the sample is decreased smoothly to zero following a  
raised cosine curve. There are 32 coefficients used to step  
down the value of the data, each one being used 32 times  
before stepping to the next.  
1998 Oct 06  
14  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
TREBLE CONTROL  
The treble control is available for the master channel of the UDA1321. Treble can be regulated in three modes: minimum,  
flat and maximum mode. The preferred mode is selected at start-up of the device (configuration map). The corner  
frequency is 3000 Hz for the minimum mode and 1500 Hz for the maximum mode. The treble range is from 0 to 6 dB in  
steps of 2 dB. It should be noted that the negative treble values as defined in the “USB Device Class Definition for Audio  
Devices” are not supported by the UDA1321; the 0 dB value is returned as 0 dB. Table 4 gives the mapping of the  
bTreble value upon the actual treble setting of the USB DAC.  
Table 4 Treble control characteristics; note 1  
bTREBLE  
TREBLE USB DAC (dB)  
TREBLE USB  
SIDE (dB)  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
minimum  
flat  
maximum  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.00  
0.25  
0.50  
0.75  
1.00  
1.25  
1.50  
1.75  
2.00  
2.25  
2.50  
2.75  
3.00  
3.25  
...  
0
0
0
2
0
2
4
6
6
6
6
0
0
0
0
0
4
6
6
6
6
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
0
1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
5.25  
...  
7.25  
...  
9.25  
...  
0
31.75  
Note  
1. The 2 dB step is not supported in the UDA1321/N101; see Chapter “USB-DAC UDA1321/N101  
(Firmware sw 2.1.1.7)”.  
1998 Oct 06  
15  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
BASS CONTROL  
The bass control is available for the master channel of the UDA1321. Bass can be regulated in three modes: minimum,  
flat and maximum mode. The preferred mode is selected at start-up of the device (configuration map). The Bass range  
is from 0 to about 14 dB (minimum mode) or about 24 dB (maximum mode) in steps of 2 dB. It should be noted that the  
negative bass values as defined in the “USB Device Class Definition for Audio Devices” are not supported by the  
UDA1321; the 0 dB value is returned as 0 dB. The maximum Bass value which will be reported to the host is always  
24 dB independent of the mode. The maximum mode is the most accurate mode when the Bass values are reported to  
the host. The corner frequency is 100 Hz for the minimum mode and 75 Hz for the maximum mode. Table 5 gives the  
mapping of the bBass value upon the actual bass setting of the USB DAC.  
Table 5 Bass control characteristics  
bBASS  
B4  
BASS USB DAC (dB)  
BASS USB  
SIDE (dB)  
B7  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B6  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B5  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
B2  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
B1  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
B0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
minimum  
flat  
maximum  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.00  
0.25  
0.50  
0.75  
1.00  
1.25  
1.50  
1.75  
2.00  
2.25  
2.50  
2.75  
3.00  
3.25  
...  
0
0
0
1.1  
0
1.7  
2.4  
3.7  
0
0
0
0
0
0
0
0
3.6  
5.4  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
5.25  
...  
7.25  
...  
5.2  
7.4  
9.25  
...  
6.8  
9.4  
11.25  
...  
8.4  
11.3  
13.3  
15.2  
17.3  
13.25  
...  
10.2  
11.9  
13.7  
15.25  
...  
17.25  
...  
1998 Oct 06  
16  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
bBASS  
BASS USB DAC (dB)  
minimum flat maximum  
BASS USB  
SIDE (dB)  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
1
0
0
1
1
0
1
19.25  
...  
13.7  
13.7  
13.7  
13.7  
13.7  
13.7  
13.7  
13.7  
0
0
0
0
0
0
0
0
19.2  
21.2  
23.2  
23.2  
23.2  
23.2  
23.2  
23.2  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
21.25  
...  
23.25  
...  
25.25  
...  
27.25  
...  
29.25  
...  
31.25  
...  
31.75  
DYNAMIC BASS BOOST CONTROL  
Clipping prevention  
Bass boost is one of the sound features as defined in the  
“USB Device Class Definition for Audio Devices”.  
The bass boost control request data bBassBoost controls  
the position of the bass boost switch. The position can be  
either on or off. When bBassBoost is true the bass boost  
is activated. When bBassBoost is false the bass boost is  
off.  
If the maximum of the bass plus volume gives clipping, the  
Bass is reduced. Clipping prevention is selectable via the  
configuration map.  
De-emphasis  
De-emphasis is one of the properties which is not  
supported by the USB. De-emphasis for 44.1 kHz can be  
predefined in the configuration map selected at start-up of  
the UDA1321.  
When clipping prevention is active, the bass is reduced to  
avoid clipping with high volume settings. Bass boost is  
selectable via the configuration map (see Table 6).  
If byte 19H is loaded with 00H, bass boost is not reported  
to the USB host by the device.  
1998 Oct 06  
17  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
3.3 V  
3.3 V  
22 kΩ  
3.3 V  
22 kΩ  
3.3 V  
22 kΩ  
GP0  
GP3  
TR3  
KEY 1  
SW1  
KEY 2  
SW2  
1
2
V
bus  
D1  
1
2
1.5 kΩ  
22 kΩ  
D2  
22 kΩ  
22 kΩ  
USB-B  
connector  
GP5  
TR1  
TR2  
5
1
2
3
4
22 kΩ  
V
bus  
22 Ω  
D−  
D+  
22 Ω  
MGM109  
6
10 nF  
22 pF  
22 pF  
10 nF  
Fig.6 Diode matrix selection.  
After selecting a configuration map the user cannot  
change the chosen settings for the GP pins, internal  
configuration, descriptors, etc.  
Start-up and configuration of the UDA1321  
START-UP OF THE UDA1321  
After power-on, an internal power-on reset signal becomes  
HIGH after a certain RC-time (R = 5 kΩ and C = Cref).  
During 10 ms after power-on reset the UDA1321 has to  
initiate the internal settings. After the power-on reset the  
UDA1321 becomes master of the I2C-bus. The UDA1321  
tries to read the eventually connected EEPROM and if an  
EEPROM is detected, the internal descriptors are  
For more information about the four (vendor specific)  
configuration maps and the diode matrix see the  
application documentation.  
CONFIGURATION OPTIONS OF THE UDA1321 VIA AN I2C-BUS  
EEPROM  
overwritten and the selected port configuration is applied.  
If no EEPROM is detected, the UDA1321 tries to read the  
logical levels of GP3 and GP0. A choice can be made from  
four configuration maps via these two pins.  
If an EEPROM is detected (reading byte 0 as AAH and  
byte 1 as 55H), the UDA1321 will use the configuration  
map in the EEPROM instead of one of four configuration  
maps. The layout of the configuration map is fixed, the  
values (except bytes 0 and 1) are user definable (see  
Table 6). If the user wants to change these values  
(the manufacturers name for instance), this can be  
achieved via the EEPROM code.  
CONFIGURATION SELECTION OF THE UDA1321 VIA A DIODE  
MATRIX  
The UDA1321 uses a configuration map to hold a number  
of specific configurable data on hardware, product,  
component and USB configuration level. At start-up  
without EEPROM, the UDA1321 will scan the logical levels  
of GP3 and GP0. With these two pins it is possible to  
select one of the four possible (vendor specific)  
configuration maps. This selection can be achieved via a  
diode matrix (see Fig.6).  
The communication between the UDA1321 and the  
external I2C-bus device is based on the standard I2C-bus  
protocol given in the Philips specification “The I2C-bus and  
how to use it (including specifications)”, which can be  
ordered using the code 9398 393 40011. The I2C-bus has  
two lines: a clock line SCL and a serial data line SDA  
(see Fig.7).  
1998 Oct 06  
18  
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SDA  
t
t
t
t
t
t
SP  
r
BUF  
LOW  
HD;STA  
f
SCL  
t
t
SU;STO  
HD;STA  
t
t
t
t
SU;DAT  
SU;STA  
HD;DAT  
HIGH  
P
S
P
Sr  
MBC611  
2
ahdnbok,uflapegwidt  
Fig.7 Definition of timing of the I C-bus.  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
Table 6 Control options for the UDA1321 via the EEPROM configuration map; note 1  
BYTE  
(HEX)  
REGISTER  
NAME  
COMMENTS  
BIT  
VALUE  
0
1
2
−
−
recognition pattern; do not change it  
recognition pattern; do not change it  
robust word clock  
AAH  
55H  
ASR control register  
7
0 = off  
1 = on  
serial I2S-bus output format  
6 and 5 00 = I2S-bus  
01 = 16-bit LSB  
10 = 18-bit LSB  
11 = 20-bit LSB  
phase inversion  
4
0 = mono phase inversion off  
1 = mono phase inversion on  
bits per sample modi  
3 and 2 00 = reserved  
01 = 8-bit audio  
10 = 16-bit audio  
11 = 24-bit audio  
audio mode  
1
0
7
0 = mono  
1 = stereo  
ASR register start-up mode  
0 = stop  
1 = go  
3
ADAC mode register 0 selection ADAC mode register  
audio feature mode  
0
6 and 5 00 = flat  
01 = minimum  
10 = minimum  
11 = maximum  
de-emphasis  
4
3
2
1
0
0 = de-emphasis off  
1 = de-emphasis on  
channel manipulation  
synchronous/asynchronous control  
mute control  
0 = L  
1 = L  
L, R  
R, R  
R
L
0 = asynchronous  
1 = synchronous  
0 = no mute  
1 = mute active  
reset ADAC  
0 = no reset ADAC  
1 = reset ADAC  
1998 Oct 06  
20  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
BYTE  
(HEX)  
REGISTER  
NAME  
COMMENTS  
BIT  
VALUE  
4
ADAC mode register 1 selection ADAC mode register  
digital PLL lock speed  
7
1
6 and 5 00 = lock after 512 samples  
01 = lock after 2048 samples  
10 = lock after 4096 samples  
11 = lock after 16384 samples  
digital PLL lock mode  
digital PLL mode  
4
0 = adaptive  
1 = fixed  
3 and 2 00 = adaptive  
01 = fixed state 1  
10 = fixed state 2  
11 = fixed state 3  
serial I2S-bus input format  
1 and 0 00 = I2S-bus  
01 = 16-bit LSB  
10 = 18-bit LSB  
11 = 20-bit LSB  
5
I/O selection register  
clipping  
7
6
5
0 = clipping prevention off  
1 = clipping prevention on  
I2S-bus usage  
0 = no I2S-bus used  
1 = I2S-bus used  
only if I2S-bus is used;  
0 = 4 pins I2S-bus  
1 = 6 pins I2S-bus  
4/6 pins I2S-bus (see Section “The  
general purpose pins (GP0 to GP5)”)  
GP4  
4
3
2
1
0
0 = function 1  
1 = function 2  
(see Tables 7, 8 and 9)  
GP3  
GP2  
GP1  
GP0  
6
7
GP0 Usage Page if HID selected  
GP0 Usage if HID selected  
reserved  
8
9
reserved  
A
B
C
D
E
F
GP3 Usage Page if HID selected  
GP3 Usage if HID selected  
reserved  
reserved  
GP4 Usage Page if HID selected  
GP4 Usage if HID selected  
reserved  
10  
1998 Oct 06  
21  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
BYTE  
(HEX)  
REGISTER  
NAME  
COMMENTS  
BIT  
VALUE  
11  
GP1 and GP2 outputs reserved  
7
6
5
definition register  
reserved  
application GP2 function 2  
application GP1 function 2  
0 = HID output 2  
1 = LED output 2 (activated  
when DBB is active)  
4
0 = HID output 1  
1 = LED output 1 (activated  
when mute is active)  
polarity GP2 function 1  
3
2
1
0
normal or inversed output  
functionality:  
0 = according Table 7  
1 = inversed  
polarity GP1 function 1  
polarity GP2 function 2  
polarity GP1 function 2  
12  
13  
14  
15  
16  
GP1 Usage Page if HID selected  
GP1 Usage if HID selected  
GP2 Usage Page if HID selected  
GP2 Usage if HID selected  
time between releasing standby and  
enabling the audio output; steps of  
20 ms  
17  
18  
time between ‘no isochronous data  
present’ and activating the mute  
output; steps of 1 s (only applicable for  
function 1, no digital I/O  
communication)  
time between activating the mute  
output and activating the standby  
output; steps of 5 s (only applicable for  
function 1, no digital I/O  
communication); when filled-in with  
zero, standby will not be activated  
19  
default bass boost value on top of  
Bass USB DAC for Dynamic Bass  
Boost (DBB); see Table 5  
bass boost = register value; if  
bass boost + Bass USB DAC  
is larger then the maximum  
value of Table 5, the maximum  
value is used (no bass boost  
in flat mode)  
1A  
1B  
1C  
1D  
1E  
1F  
20  
default volume value of USB DAC  
idVendor high byte  
idVendor low byte  
volume = −register value  
idProduct high byte  
idProduct low byte  
bmAttributes  
maximum power steps of 2 mA with  
maximum 500 mA  
1998 Oct 06  
22  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
BYTE  
(HEX)  
REGISTER  
NAME  
COMMENTS  
BIT  
VALUE  
21  
22  
23  
24  
25  
26  
27  
28  
wTerminalType high byte  
wTerminalType low byte  
pointer language string  
pointer manufacturer string  
pointer product string  
pointer serial number  
32  
36  
46  
54  
32  
36  
46  
54  
language string  
−
−
−
manufacturer string  
product string  
serial number; note 2  
Notes  
1. An extensive description of the USB control options is available in the “USB Device Class Definition for Audio  
Devices”.  
2. The serial number is only supported in the external configuration map and not in the four internal configuration maps.  
The general purpose pins (GP0 to GP5)  
The UDA1321 has 6 General Purpose (GP) pins; these are pins GP0 to GP5. These can be used either for digital I/O  
functions or for general purposes. The configurations presented are as implemented in the standard firmware.  
There are basically three port configurations:  
• No digital I/O communication  
• 4-pins digital I/O communication  
• 6-pins digital I/O communication.  
These port configurations can be selected via the configuration map at start-up of the UDA1321.  
The user can make a selection between two functions for each of the pins GP0 to GP4 (see byte 5 in Table 6), except if  
digital I/O communication is selected (see Tables 7, 8 and 9).  
1998 Oct 06  
23  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
Table 7 No digital I/O communication  
PIN  
INPUT/OUTPUT  
FUNCTION 1  
FUNCTION 2  
GP5  
GP4  
GP3  
GP0  
GP2  
GP1  
output; not programmable; note 2  
inputs; programmable; note 1  
connect/disconnect  
alarm mute; note 3  
HID input 2  
connect/disconnect  
HID input 3  
HID input 2  
HID input 1  
HID input 1  
outputs; programmable  
standby; note 4  
mute; note 5  
HID/LED output 2; note 6  
HID/LED output 1; note 6  
Notes  
1. The input pins must have a pull-up resistor.  
2. Connect/disconnect: holds the USB ‘disconnected’ as long as the initialization is not finished.  
3. Alarm mute: input to switch the sound off; specially used if the USB host program does not respond to the control.This  
pin acts directly on the sound and passes the mute to the USB host.  
4. Standby is switched on (output becomes LOW) after a programmable time if mute is active (see Byte 18 of Table 6).  
5. Mute is switched on (output becomes LOW) after a programmable time if the isochronous data flow is interrupted  
(see Byte 17 of Table 6).  
6. For selection between HID/LED application see configuration map byte 11 (output is active HIGH).  
Table 8 4-pins digital I/O communication  
PIN  
INPUT/OUTPUT  
FUNCTION 1  
FUNCTION 2  
GP5  
GP4  
GP3  
GP2  
GP1  
GP0  
output; not programmable; note 1  
digital I/O-bus  
connect/disconnect  
connect/disconnect  
BCKO  
WSO  
DO  
BCKO  
WSO  
DO  
DI  
DI  
input; programmable  
HID input 1  
alarm mute; note 2  
Notes  
1. Connect/disconnect: holds the USB ‘disconnected’ as long as the initialization is not finished.  
2. Alarm mute: input to switch the sound off; specially used if the USB host program does not respond to the control.  
This pin acts directly on the sound and passes the mute to the USB host.  
1998 Oct 06  
24  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
Table 9 6-pins digital I/O communication  
PIN  
INPUT/OUTPUT  
digital I/O-bus  
FUNCTION  
GP5  
GP4  
GP3  
GP2  
GP1  
GP0  
WSI  
BCKO  
WSO  
DO  
DI  
BCKI  
Filter characteristics  
The overall filter characteristic of the UDA1321 in flat mode is given in Fig.8. The overall filter characteristic of the  
UDA1321 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC  
(fs = 44.1 kHz).  
DSP extension port  
An external DSP can be used for adding extra sound processing features via the digital I/O-bus. The UDA1321 supports  
the standard I2S-bus data protocol and the LSB-justified serial data input format with word lengths of 16, 18 and 20 bits.  
Using the 4-pins digital I/O-bus the UDA1321 device acts as a master, controlling the BCK and WS signals. The period  
of the WS signal is determined by the number of samples in the 1 ms frame of the USB. This implies that the WS signal  
does not have a constant period time, but is jittery. Using the 6-pins digital I/O-bus GP2, GP3 and GP4 are the output  
pins (master) and GP0, GP1 and GP5 are the input pins (slave).  
For characteristic timing of the I2S-bus input interface see Figs 9 and 10.  
1998 Oct 06  
25  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
MGM110  
−0  
−20  
volume  
(dB)  
−40  
−60  
−80  
−100  
−120  
−140  
−160  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
f (kHz)  
Fig.8 Overall filter characteristics of the UDA1321.  
LEFT  
WS  
RIGHT  
t
s;WS  
t
h;WS  
t
t
BCK(H)  
BCK(L)  
t
t
f
r
BCK  
T
t
cy  
s;DAT  
t
h;DAT  
DATA  
LSB  
MSB  
MGK003  
Fig.9 Timing of digital I/O input signals.  
26  
1998 Oct 06  
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ahdnbok,uflapegwidt  
WS  
BCK  
LEFT  
3
RIGHT  
3
1
2
>=8  
1
2
>=8  
DATA  
MSB B2  
LSB MSB B2  
LSB MSB  
2
INPUT FORMAT I S-BUS  
WS  
RIGHT  
LEFT  
16  
15  
2
1
16  
15  
2
1
BCK  
DATA  
MSB B2  
B15 LSB  
LSB-JUSTIFIED FORMAT 16 BITS  
MSB B2  
B15 LSB  
WS  
RIGHT  
17  
LEFT  
18  
17  
16  
15  
2
1
18  
16  
15  
2
1
BCK  
DATA  
LSB  
LSB  
MSB B2  
B3  
B4  
B17  
MSB B2  
B3  
B4  
B17  
LSB-JUSTIFIED FORMAT 18 BITS  
WS  
LEFT  
18  
RIGHT  
17 16  
20  
19  
17  
16  
15  
2
1
20  
19  
18  
15  
2
1
BCK  
LSB  
LSB  
DATA  
MSB B2  
B3  
B4  
B5  
B6  
B19  
MSB B2  
B3  
B4  
B5  
B6  
B19  
MGK002  
LSB-JUSTIFIED FORMAT 20 BITS  
Fig.10 Input formats.  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
All digital I/Os  
VI/O  
IO  
DC input/output voltage range  
output current  
−0.5  
−
−
VDD  
V
−
4
mA  
Temperature  
Tj  
junction temperature  
0
−
−
125  
+150  
70  
°C  
°C  
°C  
Tstg  
Tamb  
storage temperature  
−55  
0
operating ambient temperature  
25  
Electrostatic handling  
Ves  
electrostatic handling  
note 1  
note 2  
−3000  
−300  
−
−
+3000  
+300  
V
V
Notes  
1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.  
2. Equivalent to discharging a 200 pF capacitor through a 2.5 µH series inductor and a 25 Ω resistor.  
For pin VDDO the electrostatic handling is limited to 250 V.  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
in free air  
VALUE  
UNIT  
Rth(j-a)  
thermal resistance from junction to ambient  
QFP64  
SDIP32  
SO28  
48  
57  
65  
K/W  
K/W  
K/W  
1998 Oct 06  
28  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
PARAMETER  
MIN.  
3.0  
TYP.  
3.3  
MAX.  
3.6  
UNIT  
VDD  
VI  
supply voltage  
V
V
V
DC input voltage for D+ and D−  
0.0  
0.0  
−
−
VDD  
VDD  
VI/O  
DC input voltage for the digital I/Os  
DC CHARACTERISTICS  
DD = 3.3 V; VSS = 0 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified.  
V
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Supplies  
VDDE  
VDDI  
VDDA  
VDDO  
VDDX  
IDDE  
IDDI  
digital supply voltage I/O pins  
digital supply voltage core  
analog supply voltage  
3.0  
3.3  
3.6  
3.6  
3.6  
3.6  
3.6  
−
V
3.0  
3.0  
3.0  
3.0  
−
3.3  
3.3  
3.3  
3.3  
3
V
V
operational amplifier supply voltage  
crystal oscillator supply voltage  
digital supply current I/O pins  
digital supply current core  
analog supply current  
V
V
note 1  
mA  
mA  
mA  
mA  
mA  
mW  
mW  
−
36  
−
IDDA  
IDDO  
IDDX  
Ptot  
−
4.2  
4.0  
2.1  
165  
60  
−
operational amplifier supply current  
crystal oscillator supply current  
total power dissipation  
−
−
−
15.0(2)  
−
−
Ptot(ps)  
total power dissipation in  
power-save mode  
note 3  
−
−
Inputs/outputs D+ and D−  
VI  
static DC input voltage  
−0.5  
−
−
−
−
VDDI  
VDDI  
0.3  
V
VOH  
VOL  
ILO  
static DC output voltage HIGH  
static DC output voltage LOW  
RL = 15 kΩ to ground 2.8  
V
RL = 1.5 kΩ to 3.6 V  
−
−
V
high impedance state data line  
output leakage current  
10  
µA  
∆VI(dif)  
differential input sensitivity  
0.2  
0.8  
0.8  
−
−
−
−
V
V
V
VCM(dif)  
VSE(RX)th  
differential common mode voltage  
2.5  
2.0  
single-ended receiver threshold  
voltage  
CI(TRX)  
transceiver input capacitance  
pin to ground  
−
−
20  
pF  
Digital inputs/outputs  
VIL  
VIH  
VOL  
VOH  
ILI  
LOW-level input voltage  
−
−
−
−
0.3VDDI  
V
HIGH-level input voltage  
LOW-level output voltage  
HIGH-level output voltage  
input leakage current  
input capacitance  
0.7VDDI  
VDDI  
0.4  
−
V
−
V
V
−
−
DDI − 0.4 −  
V
−
−
1
µA  
pF  
Ci  
pin to ground  
5
1998 Oct 06  
29  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Filter stream DAC  
Vref  
reference voltage  
−
−
−
0.5VDDA  
0.5VDDA  
11  
−
−
−
V
Vo(cm)  
Ro  
common mode output voltage  
V
output resistance at pins VOUTL  
and VOUTR  
Ω
Ro(L)  
Co(L)  
output load resistance  
output load capacitance  
2.0  
−
−
−
kΩ  
−
50  
pF  
Notes  
1. This value depends strongly on the application. The specified value is the typical value obtained using the application  
as given in Fig.12.  
2. At start-up of the oscillator.  
3. The power-save mode (power management) is not supported in the UDA1321/N101;  
see Chapter “USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)”.  
1998 Oct 06  
30  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
AC CHARACTERISTICS  
VDD = 3.3 V; VSS = 0 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Driver characteristics D+ and D− (full-speed mode)  
tr  
rise time  
CL = 50 pF  
4
−
−
−
−
−
20  
ns  
tf  
fall time  
CL = 50 pF  
4
20  
ns  
%
V
trf(m)  
Vcr  
matching rise/fall time (tr/tf)  
output signal crossover voltage  
driver output resistance  
90  
110  
2.0  
43  
1.3  
28  
R(o)driver  
steady-state drive  
Ω
Data source timings D+ and D− (full-speed mode)  
fi(sample)  
ffs(D)  
tfr  
audio sample input frequency  
full-speed data rate  
frame interval  
5
−
55  
kHz  
Mbits/s  
ms  
11.97  
0.9995  
−3.5  
12.00  
12.03  
1.0000 1.0005  
tJ1(dif)  
source differential jitter to next  
transition  
0.0  
+3.5  
ns  
tJ2(dif)  
source differential jitter for paired  
transitions  
−4.0  
0.0  
+4.0  
ns  
tW(EOP)  
tEOP(dif)  
tJR1  
source End Of Packet (EOP) width  
differential to EOP transition skew  
160  
−
175  
ns  
ns  
ns  
−2.0  
−18.5  
−
+5.0  
+18.5  
receiver data jitter tolerance to next  
transition  
0.0  
tJR2  
receiver data jitter tolerance for  
paired transitions  
−9.0  
40  
0.0  
−
+9.0  
−
ns  
ns  
ns  
tEOPR1  
tEOPR2  
EOP width at receiver must reject as  
EOP  
EOP width at receiver must accept  
as EOP  
82  
−
−
Serial input/output data timing; see Fig.9  
fclk(sys)  
fi(WS)  
tr  
system clock frequency  
word select input frequency  
rise time  
−
12  
−
−
−
−
−
−
−
−
−
−
MHz  
kHz  
ns  
5
55  
20  
20  
−
−
tf  
fall time  
−
ns  
tBCK(H)  
tBCK(L)  
ts;DAT  
th;DAT  
ts;WS  
th;WS  
bit clock HIGH time  
bit clock LOW time  
data set-up time  
55  
55  
10  
20  
20  
10  
ns  
−
ns  
−
ns  
data hold time  
−
ns  
word select set-up time  
word select hold time  
−
ns  
−
ns  
1998 Oct 06  
31  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
SDA and SCL lines (standard I2C-bus); see Fig.7  
fSCL  
tBUF  
SCL clock frequency  
0
−
−
100  
kHz  
bus free time between a STOP  
and START condition  
4.7  
−
µs  
tHD;STA  
hold time (repeated) START  
condition  
4.0  
−
−
µs  
tLOW  
SCL LOW time  
SCL HIGH time  
4.7  
4.0  
4.7  
−
−
−
−
−
−
µs  
µs  
µs  
tHIGH  
tSU;STA  
set-up time for a repeated START  
condition  
tSU;STO  
tHD;DAT  
tSU;DAT  
tr  
set-up time for a STOP condition  
data hold time  
4.0  
5.0  
250  
−
−
−
−
−
−
µs  
µs  
ns  
ns  
0.9  
−
data set-up time  
rise time of both SDA and SCL  
signals  
1000  
tf  
fall time of both SDA and SCL  
signals  
−
−
−
−
300  
400  
ns  
CL(bus)  
load capacitance for each bus line  
pF  
Oscillator; note 1  
fosc  
oscillator frequency  
−
48  
−
MHz  
%
δ
duty factor  
−
50  
−
gm  
transconductance  
13.5  
450  
10  
23.0  
700  
11  
30.5  
1450  
12  
mS  
Ω
Ro  
output resistance  
Ci(XTAL1)  
Ci(XTAL2)  
Istart  
parasitic input capacitance at XTAL1  
parasitic input capacitance at XTAL2  
start current  
pF  
4.5  
4.3  
5.0  
8.8  
5.5  
15.0  
pF  
mA  
Power-on reset  
tsu(POR)  
power-on reset set-up time  
notes 2 and 3  
5Cref  
−
−
ms  
Filter Stream DAC (FSDAC)  
RES  
resolution  
16  
−
−
−
bits  
V
Vo(FS)(rms)  
full-scale output voltage  
(RMS value)  
VDD = 3.3 V  
−
0.66  
SVRR  
supply voltage ripple rejection of  
fripple = 1 kHz;  
−
60  
−
dB  
VDDA and VDDO  
Vripple(p-p) = 0.1 V  
∆Vo  
channel unbalance  
maximum volume  
−
−
0.03  
95  
−
−
dB  
dB  
αct  
crosstalk between channels  
RL = 5 kΩ  
1998 Oct 06  
32  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
(THD + N)/S total harmonic distortion-plus-noise fs = 44.1 kHz;  
to signal ratio  
RL = 5 kΩ  
at input signal of  
1 kHz (0 dB)  
−
−90(4)  
−80  
dB  
−
0.0032 0.01  
%
at input signal of  
1 kHz (−60 dB)  
−
−30(4)  
−20  
10  
−
dB  
%
−
3.2  
S/Nbz  
signal-to-noise ratio at bipolar zero  
A-weighted at  
code 0000H  
90  
95  
dBA  
Notes  
1. A 3rd overtone crystal of 48 MHz must be used in combination with a filter connected to the oscillator output (XTAL2),  
(L = 1.5 µH ±10%; C = 10 nF ±10%). The series resistance of the crystal must be below 60 Ω. Cxtal1 = 4.7 pF ±10%;  
Cxtal2 = 12 pF ±10%).  
2. Strongly depends on the external decoupling capacitor connected to Vref.  
3. Use for calculation of the power-on reset set-up time the Cref value in µF.  
4. The audio information from the USB interface is fed directly to the ADAC.  
APPLICATION INFORMATION  
The UDA1321 is designed to be used as a self-powered device.  
The I2C-bus EEPROM is optional and can be used e.g. to program your own Vendor ID and Product ID. In order to help  
customers with defining there own configuration map, a special program called ‘Configuration map editor’ has been  
developed. It is available from your local Philips Semiconductors Field Application Engineer.  
More information about the firmware, descriptors and configurations can be obtained from several application notes.  
1998 Oct 06  
33  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
USB-DAC UDA1321/N101 (FIRMWARE SW 2.1.1.7)  
The following items are different for the UDA1321/N101 compared to the general content of this data sheet:  
• Volume control  
• Treble control  
• Power management.  
Table 10 Volume control characteristics  
wVOLUME  
VOLUME USB SIDE VOLUME USB DAC  
(dB)  
(dB)  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
0
1
1
1
1
1
1
1
1
1
1
...  
1
1
1
1
1
...  
1
0
1
1
1
1
1
1
1
1
1
1
...  
1
1
1
1
1
...  
0
0
1
1
1
1
1
1
1
1
1
1
...  
0
0
0
0
0
...  
0
0
1
1
1
1
1
1
1
1
1
1
...  
0
0
0
0
0
...  
0
0
1
1
1
1
1
1
1
1
0
0
...  
0
0
0
0
0
...  
0
0
1
1
1
1
0
0
0
0
1
1
...  
1
1
0
0
0
...  
0
0
1
1
0
0
1
1
0
0
1
1
...  
0
0
1
1
0
...  
0
0
1
0
1
0
1
0
1
0
1
0
...  
1
0
1
0
1
...  
0
0
0
0
0
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
...  
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
...  
−58  
−59  
−60  
−61  
−62  
...  
−58  
−59  
−60  
−∞  
−∞  
...  
−∞  
−∞  
The treble control is available for the master channel of the UDA1321. Treble can be regulated in three modes: minimum,  
flat and maximum mode. The preferred mode is selected via the configuration map. The corner frequency is 3000 Hz for  
the minimum mode and 1500 Hz for the maximum mode. The treble range is from 0 to 6 dB (discrete steps  
0, 4 and 6 dB). It should be noted that the negative treble values as defined in the “USB Device Class Definition for Audio  
Devices” are not supported by the UDA1321; the 0 dB value is returned as 0 dB. Table 4 gives the mapping of the  
bTreble value upon the actual treble setting of the USB DAC.  
1998 Oct 06  
34  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
Table 11 Treble control characteristics  
bTREBLE  
TREBLE USB DAC (dB)  
minimum flat maximum  
TREBLE USB  
SIDE (dB)  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.00  
0.25  
0.50  
0.75  
1.00  
1.25  
1.50  
1.75  
2.00  
2.25  
2.50  
2.75  
3.00  
3.25  
...  
0
0
0
4
4
0
6
6
6
6
6
0
0
0
0
0
6
6
6
6
6
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
0
1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
5.25  
...  
7.25  
...  
9.25  
...  
31.75  
The power saving mode is not supported (no power management).  
The content of the four internal configuration maps is written in the ‘sw 2.1.1.7 configuration maps’ document. This  
document is available at your local Philips Semiconductors Field Application Engineer.  
1998 Oct 06  
35  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
APPLICATION DIAGRAM  
+V  
A
R15  
1 Ω  
C8  
47 µF  
(16 V)  
C14  
100 nF  
(63 V)  
V
V
DDA  
SSA  
44  
45  
GP0/BCKI  
BCK  
WS  
DI  
64  
2
digital  
input  
GP5/WSI  
GP1/DI  
7
+V  
C
P5  
L9  
R9  
1.5 kΩ  
1
2
3
4
8
1
2
3
4
R14  
D−  
D+  
7
6
5
17  
20  
22 Ω  
R13  
22 Ω  
C26  
10 nF  
(50 V)  
C4  
22 pF  
(63 V)  
C5  
22 pF  
(63 V)  
C27  
10 nF  
(50 V)  
L10  
1.5 µH  
C7  
XTAL2  
38  
10 nF  
(63 V)  
UDA1321H  
C6  
12 pF  
(63 V)  
X1  
48 MHz  
C13  
XTAL1  
37  
4.7 pF  
(50 V)  
L15  
(1)  
(2)  
V
+V  
A(ext)  
A
C
D
BLM32A07  
L14  
+V  
+V  
BLM32A07  
L16  
V
D(ext)  
BLM32A07  
C1  
C2  
C3  
100 µF  
(16 V)  
100 µF  
(16 V)  
100 µF  
(16 V)  
GND  
29  
25  
30  
32  
V
V
V
V
DDE  
SSI  
C16  
DDI  
SSE  
C18  
100 nF  
(63 V)  
100 nF  
(63 V)  
L11  
BLM32A07  
L12  
BLM32A07  
C17  
C15  
(1) BLM32A07.  
(2) VD(ext) can be connected to 5 V max. (5 V tolerant I/O).  
100 nF  
(63 V)  
100 nF  
(63 V)  
1 Ω  
R16  
1 Ω  
R17  
MGM842  
+V  
+V  
C
D
Fig.11 Application diagram QFP64 (continued in Fig.12).  
36  
1998 Oct 06  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
P0.0  
P0.1  
P0.2  
P0.3  
P0.4  
P0.5  
P0.6  
P0.7  
ALE  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
LE  
OE  
Q7  
Q6  
Q5  
Q4  
Q3  
Q2  
Q1  
A0  
A1  
A2  
A3  
A4  
A5  
O0  
11  
56  
57  
58  
59  
60  
62  
63  
5
18  
17  
14  
13  
8
19  
16  
15  
12  
9
10  
9
O1  
12  
O2  
13  
8
O3  
7
15  
O4  
16  
6
D3  
O5  
17  
5
7
6
74HCT373D  
O6  
18  
A6  
A7  
A8  
4
5
4
Q0  
V
O7  
19  
3
2
3
CC  
D2  
EEPM27128  
9
11  
1
20  
+V  
25  
D
A9  
A10  
A11  
A12  
A13  
OE  
100 nF  
(50 V)  
C24  
GND  
24  
21  
23  
2
V
CC  
+V  
10  
28  
14  
D
100 nF  
(50 V)  
C25  
GND  
P2.0  
P2.1  
P2.2  
P2.3  
P2.4  
P2.5  
PSEN  
EA  
11  
12  
18  
19  
21  
22  
8
26  
22  
20  
27  
1
CE  
PGM  
V
PP  
+V  
D
3
6
R20  
+V  
D
R8  
(internal ROM  
external ROM)  
1 Ω  
+V  
D
V
4.7 kΩ  
A0  
A1  
A2  
SS  
DD  
C23  
100 nF  
(63 V)  
1
8
7
6
5
+VD  
2
PTC  
SCL  
SDA  
J1  
2
3
4
D4  
UDA1321H  
PCX8582X-2  
R6  
10 kΩ  
R7  
10 kΩ  
1
V
P8  
SDA  
1
2
4
3
SDA  
SCL  
(I2C-bus)  
SCL  
V
REF  
42  
C22  
100 nF  
(63 V)  
C12  
47 µF  
(16 V)  
C10  
47 µF  
(16 V)  
VOUTR  
VOUTL  
46  
53  
audio  
output  
C11  
47 µF  
(16 V)  
GP4/BCKO  
GP3/WSO  
GP2/DO  
14  
13  
10  
BCK  
digital  
output  
WS  
DO  
RTCB  
TC  
61  
55  
15  
SHTCB  
49  
51  
36  
39  
V
V
V
V
DDX  
SSO  
C19  
DDO  
SSX  
C21  
100 nF  
(63 V)  
100 nF  
(63 V)  
L13  
BLM32A07  
C9  
C28  
47 µF  
(16 V)  
100 nF  
(63 V)  
1 Ω  
R18  
1 Ω  
R19  
MGM843  
+V  
+V  
C
A
(1) BLM32A07.  
Fig.12 Application diagram QFP64 (continued from Fig.11).  
37  
1998 Oct 06  
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  g
+3.3 V  
1 Ω  
+3.3 V  
1 Ω  
1 Ω  
1 Ω  
100 µF  
V
A0  
A1  
A2  
DD  
1
2
8
7
PTC  
SCL  
SDA  
100 nF  
100 nF  
100 nF  
100 nF  
100 nF  
100 nF  
100 nF  
PCX8582X-2  
(1)  
(1)  
(1)  
V
3
6
+3.3 V  
V
SS  
4
5
V
V
V
V
V
SSI  
DDI  
SSE  
DDE  
SSX  
DDX  
10  
10  
kΩ  
kΩ  
8
(9)  
7
(8)  
9
(10)  
10  
(11)  
11  
(13)  
14  
(16)  
SDA  
SCL  
GP0/BCKI  
GP5/WSI  
GP1/DI  
(31) 27  
(30) 26  
24 (27)  
25 (29)  
28 (32)  
BCK  
WS  
DI  
(I2C-bus)  
digital  
input  
V
ref  
(18) 15  
100  
nF  
4.7  
µF  
L6  
+3.3 V  
X4  
8
7
6
5
1
2
3
4
1
2
3
4
1.5  
kΩ  
VOUTL  
VOUTR  
(24) 21  
(21) 18  
LEFT  
22 Ω  
22 Ω  
D−  
D+  
5 (6)  
6 (7)  
47 µF  
47 µF  
10  
nF  
22  
pF  
22  
pF  
RIGHT  
UDA1321T  
(UDA1321PS)  
V
10 nF  
DDO  
+3.3 V  
(23) 20  
(22)19  
(20) 17  
(19) 16  
1 Ω  
1 Ω  
100 nF  
V
XTAL2  
SSO  
13 (15)  
1.5 µH  
10 nF  
12 pF  
V
DDA  
+3.3 V  
100 nF  
V
SSA  
48 MHz  
GP4/BCKO  
GP3/WSO  
GP2/DO  
(3) 3  
(2) 2  
(1) 1  
BCK  
WS  
DO  
XTAL1  
digital  
output  
12 (14)  
4.7 pF  
RTCB  
TC  
(26) 23  
(25) 22  
(4) 4  
SHTCB  
Pin numbers in parenthesis represent the UDA1321PS.  
(1) BLM32A07.  
MGM844  
Fig.13 Application diagram SO28 and SDIP32.  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
PACKAGE OUTLINES  
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm  
SOT319-2  
y
X
A
51  
33  
52  
32  
Z
E
e
A
2
H
A
E
(A )  
3
E
A
1
θ
w M  
p
pin 1 index  
L
p
b
L
20  
64  
detail X  
1
19  
w M  
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.25 2.90  
0.05 2.65  
0.50 0.25 20.1 14.1  
0.35 0.14 19.9 13.9  
24.2 18.2  
23.6 17.6  
1.0  
0.6  
1.2  
0.8  
1.2  
0.8  
mm  
3.20  
0.25  
1
1.95  
0.2  
0.2  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-02-04  
97-08-01  
SOT319-2  
1998 Oct 06  
39  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
SO28: plastic small outline package; 28 leads; body width 7.5 mm  
SOT136-1  
D
E
A
X
c
y
H
v
M
A
E
Z
28  
15  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
14  
w
detail X  
e
M
b
p
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
max.  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30  
0.10  
2.45  
2.25  
0.49  
0.36  
0.32  
0.23  
18.1  
17.7  
7.6  
7.4  
10.65  
10.00  
1.1  
0.4  
1.1  
1.0  
0.9  
0.4  
mm  
2.65  
1.27  
0.050  
1.4  
0.25  
0.01  
0.25  
0.1  
0.25  
0.01  
8o  
0o  
0.012 0.096  
0.004 0.089  
0.019 0.013 0.71  
0.014 0.009 0.69  
0.30  
0.29  
0.419  
0.394  
0.043 0.043  
0.016 0.039  
0.035  
0.016  
inches 0.10  
0.055  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-01-24  
97-05-22  
SOT136-1  
075E06  
MS-013AE  
1998 Oct 06  
40  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)  
SOT232-1  
D
M
E
A
2
A
A
L
1
c
(e )  
w M  
e
Z
1
b
1
M
H
b
32  
17  
pin 1 index  
E
1
16  
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
max.  
A
A
2
max.  
(1)  
(1)  
Z
1
w
UNIT  
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.  
max.  
1.3  
0.8  
0.53  
0.40  
0.32  
0.23  
29.4  
28.5  
9.1  
8.7  
3.2  
2.8  
10.7  
10.2  
12.2  
10.5  
mm  
4.7  
0.51  
3.8  
1.778  
10.16  
0.18  
1.6  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
92-11-17  
95-02-04  
SOT232-1  
1998 Oct 06  
41  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
For details, refer to the Drypack information in the  
“Data Handbook IC26; Integrated Circuit Packages;  
Section: Packing Methods”.  
SOLDERING  
Introduction  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mounted components are mixed  
on one printed-circuit board. However, wave soldering is  
not always suitable for surface mounted ICs, or for  
printed-circuits with high population densities. In these  
situations reflow soldering is often used.  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
Several methods exist for reflowing; for example,  
infrared/convection heating in a conveyor type oven.  
Throughput times (preheating, soldering and cooling) vary  
between 50 and 300 seconds depending on heating  
method. Typical reflow peak temperatures range from  
215 to 250 °C.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(order code 9398 652 90011).  
WAVE SOLDERING  
SDIP  
QFP  
SOLDERING BY DIPPING OR BY WAVE  
Wave soldering is not recommended for QFP packages.  
This is because of the likelihood of solder bridging due to  
closely-spaced leads and the possibility of incomplete  
solder penetration in multi-lead devices.  
The maximum permissible temperature of the solder is  
260 °C; solder at this temperature must not be in contact  
with the joint for more than 5 seconds. The total contact  
time of successive solder waves must not exceed  
5 seconds.  
CAUTION  
The device may be mounted up to the seating plane, but  
the temperature of the plastic body must not exceed the  
specified maximum storage temperature (Tstg max). If the  
printed-circuit board has been pre-heated, forced cooling  
may be necessary immediately after soldering to keep the  
temperature within the permissible limit.  
Wave soldering is NOT applicable for all QFP  
packages with a pitch (e) equal or less than 0.5 mm.  
If wave soldering cannot be avoided, for QFP  
packages with a pitch (e) larger than 0.5 mm, the  
following conditions must be observed:  
REPAIRING SOLDERED JOINTS  
• A double-wave (a turbulent wave with high upward  
pressure followed by a smooth laminar wave)  
soldering technique should be used.  
Apply a low voltage soldering iron (less than 24 V) to the  
lead(s) of the package, below the seating plane or not  
more than 2 mm above it. If the temperature of the  
soldering iron bit is less than 300 °C it may remain in  
contact for up to 10 seconds. If the bit temperature is  
between 300 and 400 °C, contact may be up to 5 seconds.  
• The footprint must be at an angle of 45° to the board  
direction and must incorporate solder thieves  
downstream and at the side corners.  
SO  
QFP and SO  
Wave soldering techniques can be used for all SO  
packages if the following conditions are observed:  
REFLOW SOLDERING  
• A double-wave (a turbulent wave with high upward  
pressure followed by a smooth laminar wave) soldering  
technique should be used.  
Reflow soldering techniques are suitable for all QFP and  
SO packages.  
The choice of heating method may be influenced by larger  
plastic QFP packages (44 leads, or more). If infrared or  
vapour phase heating is used and the large packages are  
not absolutely dry (less than 0.1% moisture content by  
weight), vaporization of the small amount of moisture in  
them can cause cracking of the plastic body.  
• The longitudinal axis of the package footprint must be  
parallel to the solder flow.  
• The package footprint must incorporate solder thieves at  
the downstream end.  
1998 Oct 06  
42  
Philips Semiconductors  
Preliminary specification  
Universal Serial Bus (USB)  
Digital-to-Analog Converter (DAC)  
UDA1321  
Method (QFP and SO)  
REPAIRING SOLDERED JOINTS  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Fix the component by first soldering two diagonally-  
opposite end leads. Use only a low voltage soldering iron  
(less than 24 V) applied to the flat part of the lead. Contact  
time must be limited to 10 seconds at up to 300 °C. When  
using a dedicated tool, all other leads can be soldered in  
one operation within 2 to 5 seconds between  
270 and 320 °C.  
Maximum permissible solder temperature is 260 °C, and  
maximum duration of package immersion in solder is  
10 seconds, if cooled to less than 150 °C within  
6 seconds. Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
PURCHASE OF PHILIPS I2C COMPONENTS  
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the  
components in the I2C system provided the system conforms to the I2C specification defined by  
Philips. This specification can be ordered using the code 9398 393 40011.  
1998 Oct 06  
43  
Philips Semiconductors – a worldwide company  
Argentina: see South America  
Middle East: see Italy  
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,  
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,  
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466  
Tel. +31 40 27 82785, Fax. +31 40 27 88399  
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,  
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,  
Fax. +43 160 101 1210  
Tel. +64 9 849 4160, Fax. +64 9 849 7811  
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,  
Norway: Box 1, Manglerud 0612, OSLO,  
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773  
Tel. +47 22 74 8000, Fax. +47 22 74 8341  
Belgium: see The Netherlands  
Brazil: see South America  
Pakistan: see Singapore  
Philippines: Philips Semiconductors Philippines Inc.,  
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,  
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474  
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,  
51 James Bourchier Blvd., 1407 SOFIA,  
Tel. +359 2 689 211, Fax. +359 2 689 102  
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,  
Tel. +48 22 612 2831, Fax. +48 22 612 2327  
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,  
Tel. +1 800 234 7381  
Portugal: see Spain  
Romania: see Italy  
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,  
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,  
Tel. +852 2319 7888, Fax. +852 2319 7700  
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,  
Tel. +7 095 755 6918, Fax. +7 095 755 6919  
Colombia: see South America  
Czech Republic: see Austria  
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,  
Tel. +65 350 2538, Fax. +65 251 6500  
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,  
Tel. +45 32 88 2636, Fax. +45 31 57 0044  
Slovakia: see Austria  
Slovenia: see Italy  
Finland: Sinikalliontie 3, FIN-02630 ESPOO,  
Tel. +358 9 615800, Fax. +358 9 61580920  
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,  
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,  
Tel. +27 11 470 5911, Fax. +27 11 470 5494  
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,  
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427  
South America: Al. Vicente Pinzon, 173, 6th floor,  
04547-130 SÃO PAULO, SP, Brazil,  
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,  
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300  
Tel. +55 11 821 2333, Fax. +55 11 821 2382  
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,  
Spain: Balmes 22, 08007 BARCELONA,  
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240  
Tel. +34 93 301 6312, Fax. +34 93 301 4107  
Hungary: see Austria  
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,  
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2741 Fax. +41 1 488 3263  
Indonesia: PT Philips Development Corporation, Semiconductors Division,  
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,  
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080  
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,  
Tel. +66 2 745 4090, Fax. +66 2 398 0793  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
Tel. +90 212 279 2770, Fax. +90 212 282 6707  
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557  
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461  
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077  
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421  
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,  
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. +82 2 709 1412, Fax. +82 2 709 1415  
Tel. +1 800 234 7381  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Uruguay: see South America  
Vietnam: see Singapore  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Tel. +381 11 625 344, Fax.+381 11 635 777  
For all other countries apply to: Philips Semiconductors,  
Internet: http://www.semiconductors.philips.com  
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,  
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
© Philips Electronics N.V. 1998  
SCA60  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
545102/750/04/pp44  
Date of release: 1998 Oct 06  
Document order number: 9397 750 04262  

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