UDA1324TS [NXP]
Ultra low-voltage stereo filter DAC; 超低电压的立体声DAC，滤波器
| 型号： | UDA1324TS |
| 厂家： | 
NXP |
| 描述： | Ultra low-voltage stereo filter DAC |
| 文件： | 总20页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
UDA1324TS
Ultra low-voltage stereo filter DAC
Preliminary specification
2000 Jan 20
Supersedes data of 1999 Oct 12
File under Integrated Circuits, IC01
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
FEATURES
General
• Low power consumption
• Ultra low power supply voltage from 1.9 to 2.7 V
• Selectable control via L3 microcontroller interface or via
static pin control
• System clock frequencies of 256fs, 384fs and 512fs
selectable via L3 interface or 256fs and 384fs via static
pin control
APPLICATIONS
• Supports sampling frequencies (fs) from 16 to 48 kHz
• Portable digital audio equipment.
• Integrated digital filter plus non inverting
Digital-to-Analog Converter (DAC)
GENERAL DESCRIPTION
• No analog post filtering required for DAC
• Slave mode only applications
• Easy application
The UDA1324TS is a single-chip stereo DAC employing
bitstream conversion techniques. The ultra low-voltage
requirements make the device eminently suitable for use
in portable digital audio equipment which incorporates
playback functions.
• Small package size (SSOP16).
Multiple format input interface
The UDA1324TS supports the I2S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB-justified
serial data format with word lengths of 16, 18 and 20 bits.
• L3 mode: I2S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible
• Static pin mode: I2S-bus or LSB-justified
16, 18 and 20 bits format compatible
The UDA1324TS can be used in two modes: L3 mode or
static pin mode.
• 1fs input format data rate.
DAC digital sound processing
In the L3 mode, all digital sound processing features must
be controlled via the L3 interface, including the selection of
the system clock setting.
• Digital logarithmic volume control in L3 mode
• Digital de-emphasis selection for 32, 44.1 and 48 kHz
sampling frequencies in L3 mode or 44.1 kHz sampling
frequency in static pin mode
In the two static modes, the UDA1324TS can be operated
in the 256fs and 384fs system clock mode. Muting,
de-emphasis for 44.1 kHz and four digital input formats
(I2S-bus or LSB-justified 16, 18 and 20 bits) can be
selected via static pins. The L3 interface cannot be used in
this application mode, so volume control is not available in
this mode.
• Soft mute control in static pin mode or in L3 mode.
Advanced audio configuration
• Stereo line output (volume control in L3 mode)
• High linearity, wide dynamic range and low distortion.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
plastic shrink small outline package; 16 leads; body width 4.4 mm
VERSION
UDA1324TS
SSOP16
SOT369-1
2000 Jan 20
2
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
QUICK REFERENCE DATA
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
VDDA
VDDD
IDDA
analog supply voltage
1.9
2.0
2.0
3.0
1.5
2.7
2.7
−
V
digital supply voltage
analog supply current
digital supply current
1.9
−
V
VDDA = 2.0 V
mA
mA
IDDD
VDDD = 2.0 V
−
−
DAC; note 1
Vo(rms)
output voltage (RMS value)
note 2
−
500
−83
−36
97
−
mV
dB
dB
dB
dB
°C
(THD + N)/S
total harmonic distortion-plus-noise to at 0 dB
signal ratio
−
−78
−
at −60 dB; A-weighted
−
S/N
αcs
signal-to-noise ratio
channel separation
ambient temperature
code = 0; A-weighted
−
−
−
100
−
−
Tamb
−40
+70
Notes
1. The analog performance figures are measured at 2.0 V supply voltage.
2. The DAC output voltage scales linearly with the power supply voltage.
BLOCK DIAGRAM
V
V
SSD
5
DDD
4
7
APPSEL
APPL0
APPL1
APPL2
APPL3
1
2
3
11
BCK
WS
CONTROL
INTERFACE
10
9
DIGITAL INTERFACE
DATAI
8
VOLUME/MUTE/DE-EMPHASIS
INTERPOLATION FILTER
NOISE SHAPER
UDA1324TS
6
SYSCLK
16
DAC
DAC
14
VOUTR
VOUTL
13
15
12
MBK770
V
V
V
ref(DAC)
DDA
SSA
Fig.1 Block diagram.
3
2000 Jan 20
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
PINNING
FUNCTIONAL DESCRIPTION
System clock
SYMBOL
BCK
PIN
DESCRIPTION
bit clock input
The UDA1324TS operates in the slave mode only.
Therefore, in all applications the system devices must
provide the system clock. The system frequency (fsys) is
selectable and depends on the application mode.
The options are: 256fs, 384fs and 512fs for the L3 mode
and 256fs or 384fs for the static pin mode. The system
clock must be locked in frequency to the digital interface
input signals.
1
2
3
4
5
6
WS
word select input
data input
DATAI
VDDD
digital supply voltage
digital ground
VSSD
SYSCLK
system clock input: 256fs, 384fs
and 512fs
The UDA1324TS supports sampling frequencies (fs) from
16 to 48 kHz.
APPSEL
APPL3
APPL2
APPL1
APPL0
Vref(DAC)
VDDA
7
8
9
application mode select input
application input pin 3
Application modes
application input pin 2
10 application input pin 1
11 application input pin 0
12 DAC reference voltage
13 analog supply voltage for DAC
14 left channel output
The application mode can be set with the three-level
pin APPSEL (see Table 1):
• L3 mode
• Static pin mode with fsys = 384fs
• Static pin mode with fsys = 256fs.
VOUTL
VSSA
15 analog ground for DAC
16 right channel output
Table 1 Selecting application mode and system clock
VOUTR
frequency via pin APPSEL
VOLTAGE ON
PIN APPSEL
MODE
L3 mode
fsys
VSSD
0.5VDDD
VDDD
256fs, 384fs or 512fs
384fs
256fs
static pin mode
handbook, halfpage
BCK
WS
1
2
3
4
5
6
7
8
16
15
VOUTR
V
SSA
The function of an application input pin (active HIGH)
depends on the application mode (see Table 2).
DATAI
14 VOUTL
V
V
V
13
12
DDD
DDA
Table 2 Functions of application input pins
UDA1324TS
V
SSD
ref(DAC)
FUNCTION
PIN
SYSCLK
APPSEL
APPL3
11 APPL0
10 APPL1
L3 MODE
STATIC PIN MODE
APPL0
APPL1
APPL2
APPL3
TEST
MUTE
DEEM
SF0
9
APPL2
L3CLOCK
L3MODE
L3DATA
MBK769
SF1
For example, in the static pin mode the output signal can
be soft muted by setting pin APPL0 to HIGH.
De-emphasis can be switched on for 44.1 kHz by setting
pin APPL1 to HIGH; setting pin APPL1 to LOW will disable
de-emphasis.
Fig.2 Pin configuration.
2000 Jan 20
4
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
In the L3 mode, pin APPL0 must be set to LOW. It should
be noted that when the L3 mode is used, an initialization
must be performed when the IC is powered-up.
Interpolation filter
The digital filter interpolates from 1fs to 128fs by cascading
a recursive filter and a FIR filter (see Table 4).
Digital interface
Table 4 Interpolation filter characteristics
DATA FORMATS
ITEM
CONDITION
VALUE (dB)
The digital interface of the UDA1324TS supports multiple
format inputs (see Fig.3).
Pass-band ripple
Stop band
0 to 0.45fs
>0.55fs
±0.1
−50
108
Left and right data-channel words are time multiplexed.
Dynamic range
0 to 0.45fs
The WS signal must have a 50% duty factor for all
LSB-justified formats.
Noise shaper
The BCK clock can be up to 64fs, or in other words the
BCK frequency is 64 times the Word Select (WS)
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream Digital-to-Analog Converter (FSDAC).
frequency or less: fBCK ≤ 64 × fWS
.
Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital
interface.
Filter stream DAC
The UDA1324TS also accepts double speed data for
double speed data monitoring purposes.
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
L3 MODE
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage capable of driving a line output.
• I2S-bus format with data word length of up to 20 bits
• MSB-justified format with data word length up to 20 bits
• LSB-justified format with data word length of
16, 18 or 20 bits.
STATIC PIN MODE
• I2S-bus format with data word length of up to 20 bits
The output voltage of the FSDAC scales linearly with the
power supply voltage.
• LSB-justified format with data word length of
16, 18 or 20 bits.
These four formats are selectable via the static pin codes
SF0 and SF1 (see Table 3).
Table 3 Input format selection using SF0 and SF1
FORMAT
SF0
SF1
I2S-bus
0
0
1
1
0
1
0
1
LSB-justified 16 bits
LSB-justified 18 bits
LSB-justified 20 bits
2000 Jan 20
5
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a
RIGHT
LEFT
WS
1
2
3
> = 8
1
2
3
> = 8
BCK
DATA
MSB B2
MSB B2
MSB
2
I S-BUS FORMAT
WS
LEFT
RIGHT
3
1
2
3
> = 8
1
2
> = 8
BCK
DATA
MSB
B2
LSB MSB
B2
LSB MSB
B2
MSB-JUSTIFIED FORMAT
WS
LEFT
RIGHT
16
15
2
1
16
15
2
1
BCK
DATA
MSB B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
MSB B2
B15 LSB
WS
LEFT
RIGHT
18
17
16
15
2
1
18
17
16
15
2
1
BCK
DATA
B17 LSB
B17 LSB
MSB B2
B3
B4
MSB B2
B3
B4
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
20
RIGHT
20
19
18
17
16
15
2
1
19
18
17
16
15
2
1
BCK
DATA
B19 LSB
B19 LSB
MSB B2
B3
B4
B5
B6
MSB B2
B3
B4
B5
B6
LSB-JUSTIFIED FORMAT 20 BITS
WS
LEFT
RIGHT
24
23
22
21
20
19
18
17
16
15
2
1
24
23
22
21
20
19
18
17
16
15
2
1
BCK
DATA
MSB B2
B3
B4
B5
B6
B7
B8
B9 B10
B23 LSB
MSB B2
B3
B4
B5
B6
B7
B8
B9 B10
B23 LSB
MBL121
LSB-JUSTIFIED FORMAT 24 BITS
Fig.3 Digital interface input data formats.
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
L3 INTERFACE
The fundamental timing of data transfers (see Fig.5) is
essentially the same as the address mode. The maximum
input clock frequency and data rate is 64fs.
The following system and digital sound processing
features can be controlled in the L3 mode of the
UDA1324TS:
Data transfer can only be in one direction, consisting of
input to the UDA1324TS to program sound processing and
other functional features. All data transfers are by 8-bit
bytes. Data will be stored in the UDA1324TS after
reception of a complete byte.
• System clock frequency
• Data input format
• De-emphasis for 32, 44.1 and 48 kHz
• Volume
A multi-byte transfer is illustrated in Fig.6.
• Soft mute.
Registers
The exchange of data and control information between the
microcontroller and the UDA1324TS is accomplished
The sound processing and other feature values are stored
through a serial interface comprising the following signals: in independent registers. The first selection of the registers
is achieved by the choice of data type that is transferred.
This is performed in the address mode using bit 1 and bit 0
(see Table 5).
• L3DATA
• L3MODE
• L3CLOCK.
Table 5 Selection of data transfer
Information transfer through the microcontroller bus is
organized in accordance with the L3 interface format, in
which two different modes of operation can be
distinguished: address mode and data transfer mode.
BIT 1 BIT 0
TRANSFER
0
0
1
0
1
0
data (volume, de-emphasis, mute)
not used
Address mode
status (system clock frequency,
data input format)
The address mode (see Fig.4) is required to select a
device communicating via the L3 interface and to define
the destination registers for the data transfer mode.
1
1
not used
The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6). The other bits in the data byte
(bit 5 to bit 0) represent the value that is placed in the
selected registers.
Data bits 7 to 2 represent a 6-bit device address where
bit 7 is the MSB. The address of the UDA1324TS is
000101 (bit 7 to bit 2). If the UDA1324TS receives a
different address, it will deselect its microcontroller
interface logic.
The ‘status’ settings are given in Table 6 and the ‘data’
settings are given in Table 7.
Data transfer mode
The selected address remains active during subsequent
data transfers until the UDA1324TS receives a new
address command.
2000 Jan 20
7
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
L3MODE
t
t
su(L3)A
h(L3)A
t
CLK(L3)L
t
t
t
CLK(L3)H
su(L3)A
h(L3)A
L3CLOCK
T
cy(CLK)(L3)
t
t
h(L3)DA
su(L3)DA
BIT 0
BIT 7
L3DATA
MGL723
Fig.4 Timing address mode.
t
t
stp(L3)
stp(L3)
L3MODE
t
CLK(L3)L
t
T
h(L3)D
cy(CLK)L3
t
t
CLK(L3)H
su(L3)D
L3CLOCK
t
t
h(L3)DA
su(L3)DA
L3DATA
WRITE
BIT 0
BIT 7
MGL882
Fig.5 Timing data transfer mode.
2000 Jan 20
8
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
t
stp(L3)
L3MODE
L3CLOCK
L3DATA
MGL725
address
data byte #1
data byte #2
address
Fig.6 Multibyte data transfer.
Programming the features
When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format
can be controlled.
Table 6 Data transfer of type ‘status’
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REGISTER SELECTED
0
0
SC1
SC0
IF2
IF1
IF0
0
SC = system clock frequency (2 bits); see Table 8
IF = data input format (3 bits); see Table 9
not used
1
0
0
0
0
0
0
0
When the data transfer of type ‘data’ is selected, the features for volume, de-emphasis and mute can be controlled.
Table 7 Data transfer of type ‘data’
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REGISTER SELECTED
0
0
1
0
1
0
VC5
0
VC4
0
VC3
0
VC2
0
VC1
0
VC0 VC = volume control (6 bits); see Table 11
0
0
not used
0
DE1
DE0
MT
0
DE = de-emphasis (2 bits); see Table 10
MT = mute (1 bit); see Table 12
default setting
1
1
0
0
0
0
0
1
2000 Jan 20
9
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
SYSTEM CLOCK FREQUENCY
VOLUME CONTROL
The system clock frequency is a 2-bit value to select the
external clock frequency.
The volume control is a 6-bit value to program the volume
attenuation from 0 to −60 dB and −∞ dB in steps of 1 dB.
Table 8 System clock settings
Table 11 Volume settings
SC1 SC0
FUNCTION
VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)
0
0
1
1
0
1
0
1
512fs
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
1
1
:
0
1
0
1
:
0
0
384fs
256fs
−1
−2
:
not used
DATA FORMAT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
−51
−52
−54
The data format is a 3-bit value to select the used data
format.
Table 9 Data input format settings
IF2
IF1
IF0
FORMAT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I2S-bus
LSB-justified 16 bits
LSB-justified 18 bits
LSB-justified 20 bits
MSB-justified
not used
−57
−60
−∞
not used
not used
MUTE
DE-EMPHASIS
Mute is a 1-bit value to enable the digital mute.
De-emphasis is a 2-bit value to enable the digital
de-emphasis filter.
Table 12 Mute setting
MT
FUNCTION
Table 10 De-emphasis settings
0
1
no muting
muting
DE1
DE0
FUNCTION
no de-emphasis
0
0
1
1
0
1
0
1
de-emphasis, 32 kHz
de-emphasis, 44.1 kHz
de-emphasis, 48 kHz
2000 Jan 20
10
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
5.0
UNIT
VDDD
VDDA
Txtal(max)
Tstg
digital supply voltage
note 1
note 1
−
−
−
V
analog supply voltage
maximum crystal temperature
storage temperature
5.0
V
150
°C
°C
°C
V
−65
+125
+85
Tamb
Ves
ambient temperature
−40
electrostatic handling voltage
note 2
note 3
note 4
−3000
−300
+3000
+300
V
Isc(DAC)
short-circuit current of DAC
output short-circuited to VSSA(DAC)
output short-circuited to VDDA(DAC)
−
−
450
300
mA
mA
Notes
1. All supply connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pin 14 which can withstand ESD
pulses of −2500 to +2500 V.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
4. Short-circuit test at Tamb = 0 °C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
thermal resistance from junction to ambient
190
K/W
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611-E”.
DC CHARACTERISTICS
VDDD = VDDA = 2.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD); unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
VDDD
IDDA
analog supply voltage
digital supply voltage
analog supply current
digital supply current
note 1
1.9
1.9
−
2.0
2.0
3.0
1.5
2.7
V
note 1
2.7
−
V
operating
operating
mA
mA
IDDD
−
−
2000 Jan 20
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3
VIH
VIL
ILI
HIGH-level input voltage
LOW-level input voltage
input leakage current
input capacitance
0.8VDDD
−
−
−
−
−
V
−
−
−
0.2VDDD
V
1
µA
pF
CI
10
Three-level input: pin APPSEL
VIH
VIM
VIL
HIGH-level input voltage
0.8VDDD
0.3VDDD
−0.5
−
−
−
VDDD + 0.5 V
MIDDLE-level input voltage
LOW-level input voltage
0.7VDDD
0.2VDDD
V
V
DAC
Vref(DAC)
Io(max)
reference voltage
referenced to VSSA
0.45VDDA 0.5VDDA
0.55VDDA
V
maximum output current
(THD + N)/S < 0.1%;
−
0.16
−
mA
RL = 5 kΩ
RO
RL
CL
output resistance
load resistance
load capacitance
−
3
−
0.15
−
2.0
−
Ω
kΩ
pF
note 2
−
50
Notes
1. All supply connections must be made to the same external power supply unit.
2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
AC CHARACTERISTICS
VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
DAC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vo(rms)
output voltage (RMS value)
−
−
500
−
−
mV
∆Vo
unbalance voltage between
channels
0.1
dB
(THD + N)/S total harmonic
distortion-plus-noise to
at 0 dB
−
−
−83
−36
−78
dB
dB
at −60 dB; A-weighted
−
signal ratio
S/N
signal-to-noise ratio
channel separation
code = 0; A-weighted
−
−
−
97
−
−
−
dB
dB
dB
αcs
100
50
PSRR
power supply ripple rejection
ratio
fripple = 1 kHz;
Vripple = 100 mV (p-p)
2000 Jan 20
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
TIMING
VDDD = VDDA = 1.9 to 2.7 V; Tamb = −40 to +85 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock (see Fig.7)
Tsys
system clock cycle time
fsys = 256fs
78
88
244
ns
f
sys = 384fs
sys = 512fs
52
59
44
−
162
122
ns
ns
f
39
tCWL
LOW-level system clock pulse width
HIGH-level system clock pulse width
fsys < 19.2 MHz
sys ≥ 19.2 MHz
fsys < 19.2 MHz
sys ≥ 19.2 MHz
0.3Tsys
0.4Tsys
0.3Tsys
0.4Tsys
0.7Tsys ns
0.6Tsys ns
0.7Tsys ns
0.6Tsys ns
f
−
tCWH
−
f
−
Digital interface with I2S-bus (see Fig.8)
Tcy(BCK)
tBCKH
tBCKL
tr
bit clock cycle time
bit clock HIGH time
bit clock LOW time
rise time
300
100
100
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
20
20
−
tf
fall time
−
tsu(DATAI)
th(DATAI)
tsu(WS)
th(WS)
data input set-up time
data input hold time
word select set-up time
word select hold time
20
0
−
20
10
−
−
Control L3 interface (see Figs 4 and 5)
Tcy(CLK)L3
tCLK(L3)H
tCLK(L3)L
tsu(L3)A
L3CLOCK cycle time
500
250
250
190
190
190
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
L3CLOCK HIGH time
L3CLOCK LOW time
L3MODE set-up time for address mode
L3MODE hold time for address mode
th(L3)A
tsu(L3)D
L3MODE set-up time for data transfer
mode
th(L3)D
L3MODE hold time for data transfer
mode
190
190
30
−
−
−
−
−
−
−
−
ns
ns
ns
ns
tsu(L3)DA
th(L3)DA
tstp(L3)
L3DATA set-up time for data transfer and
address mode
L3DATA hold time for data transfer and
address mode
L3MODE stop time for data transfer
mode
190
2000 Jan 20
13
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
t
CWH
MGR984
t
CWL
T
sys
Fig.7 System clock timing.
WS
t
h(WS)
t
BCKH
t
su(WS)
t
t
f
r
BCK
t
su(DATAI)
t
BCKL
T
t
cy(BCK)
h(DATAI)
DATAI
MGL880
Fig.8 I2S-bus timing.
2000 Jan 20
14
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
APPLICATION INFORMATION
analog
digital
supply voltage
supply voltage
R2
1 Ω
R3
1 Ω
C1
100 µF
(16 V)
C5
C6
100 nF
(63 V)
100 nF
(63 V)
V
V
V
V
SSA
DDA
SSD
DDD
14
15
13
5
4
R1
SYSCLK
system
clock
6
47 Ω
C2
R4
VOUTL
left
output
100 Ω
BCK
WS
47 µF
(16 V)
1
2
3
7
R5
10 kΩ
DATAI
APPSEL
C3
R6
100 Ω
R7
10 kΩ
VOUTR
right
output
16
12
UDA1324TS
47 µF
(16 V)
APPL0
APPL1
APPL2
APPL3
11
10
9
V
ref(DAC)
8
C7
C4
100 nF
(63 V)
47 µF
(16 V)
MBK771
Fig.9 Application diagram.
2000 Jan 20
15
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
PACKAGE OUTLINE
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
10o
0o
0.15
0.00
1.4
1.2
0.32
0.20
0.25
0.13
5.30
5.10
4.5
4.3
6.6
6.2
0.75
0.45
0.65
0.45
0.48
0.18
mm
1.0
1.5
0.65
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
99-12-27
SOT369-1
MO-152
2000 Jan 20
16
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Jan 20
17
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Jan 20
18
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
NOTES
2000 Jan 20
19
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69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/25/03/pp20
Date of release: 2000 Jan 20
Document order number: 9397 750 06676
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