UJA1069TW_技术文档

UJA1069

LIN fail-safe system basis chip

Rev. 02 — 5 March 2007

Preliminary data sheet

1. General description

The UJA1069 fail-safe System Basis Chip (SBC) replaces basic discrete components

which are common in every Electronic Control Unit (ECU) with a Local Interconnect

Network (LIN) interface. The fail-safe SBC supports all networking applications which

control various power and sensor peripherals by using LIN as a local sub-bus. The

fail-safe SBC contains the following integrated devices:

• LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3

• Advanced independant watchdog

• Dedicated voltage regulator for microcontroller

• Serial peripheral interface (full duplex)

• Local wake-up input port

• Inhibit/limp-home output port

In addition to the advantages of integrating these common ECU functions in a single

package, the fail-safe SBC offers an intelligent combination of system-speciﬁc functions

such as:

• Advanced low-power concept

• Safe and controlled system start-up behavior

• Advanced fail-safe system behavior that prevents any conceivable deadlock

• Detailed status reporting on system and sub-system levels

The UJA1069 is designed to be used in combination with a microcontroller and a LIN

controller. The fail-safe SBC ensures that the microcontroller is always started up in a

deﬁned manner. In failure situations the fail-safe SBC will maintain the microcontroller

function for as long as possible, to provide full monitoring and software driven fall-back

operation.

The UJA1069 is designed for 14 V single power supply architectures and for 14 V and

42 V dual power supply architectures.

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

2. Features

2.1 General

I Contains a full set of LIN ECU functions:

N LIN transceiver

N Voltage regulator for the microcontroller (3.0 V, 3.3 V or 5.0 V)

N Enhanced window watchdog with on-chip oscillator

N Serial Peripheral Interface (SPI) for the microcontroller

N ECU power management system

N Fully integrated autonomous fail-safe system

I Designed for automotive applications:

N Supports 14 V and 42 V architectures

N Excellent ElectroMagnetic Compatibility (EMC) performance

N ±8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for

off-board pins

N ±4 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins

N ±60 V short-circuit proof LIN-bus pin

N Battery and LIN-bus pins are protected against transients in accordance with

ISO 7637-3

N Very low sleep current

I Supports remote ﬂash programming via the LIN-bus

I Available in:

N Small 6.4 mm × 7.8 mm HTSSOP24 package with low thermal resistance

N Small 8 mm × 11 mm HTSSOP32 package with low thermal resistance

2.2 LIN transceiver

I LIN 2.0 and SAE J2602 compliant LIN transceiver

I Enhanced error signalling and reporting

I Downward compatible with LIN 1.3 and the TJA1020

2.3 Power management

I Smart operating modes and power management modes

I Cyclic wake-up capability in Standby and Sleep mode

I Local wake-up input with cyclic supply feature

I Remote wake-up capability via the LIN-bus

I External voltage regulators can easily be incorporated in the power supply system

(ﬂexible and fail-safe)

I 42 V battery related high-side switch for driving external loads such as relays and

wake-up switches

I Intelligent maskable interrupt output

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2.4 Fail-safe features

I Safe and predictable behavior under all conditions

I Programmable fail-safe coded window and time-out watchdog with on-chip oscillator,

guaranteeing autonomous fail-safe system supervision

I Fail-safe coded 16-bit SPI interface for the microcontroller

I Global enable pin for the control of safety-critical hardware

I Detection and detailed reporting of failures:

N On-chip oscillator failure and watchdog alerts

N Battery and voltage regulator undervoltages

N LIN-bus failures (short-circuits)

N TXD and RXD clamping situations and short-circuits

N Clamped or open reset line

N SPI message errors

N Overtemperature warning

I Rigorous error handling based on diagnostics

I Supply failure early warning allows critical data to be stored

I 23 bits of access-protected RAM is available e.g. for logging of cyclic problems

I Reporting in a single SPI message; no assembly of multiple SPI frames needed

I Limp-home output signal for activating application hardware in case system enters

Fail-safe mode (e.g. for switching on warning lights)

I Fail-safe coded activation of Software development mode and Flash mode

I Unique SPI readable device type identiﬁcation

I Software-initiated system reset

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

UJA1069TW^[1]

HTSSOP32

plastic thermal enhanced thin shrink small outline package; 32 leads; SOT549-1

body width 6.1 mm; lead pitch 0.65 mm; exposed die pad

UJA1069TW24^[2]HTSSOP24

plastic thermal enhanced thin shrink small outline package; 24 leads; SOT864-1

body width 4.4 mm; lead pitch 0.65 mm; exposed die pad

[1] UJA1069TW/5V0 is for the 5 V version; UJA1069TW/3V3 is for the 3.3 V version; UJA1069TW/3V0 is for the 3 V version.

[2] UJA1069TW24/5V0 is for the 5 V version; UJA1069TW24/3V3 is for the 3.3 V version; UJA1069TW/3V0 is for the 3 V version.

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LIN fail-safe system basis chip

4. Block diagram

31 (23)

SENSE

BAT

MONITOR

32 (24)

BAT42

27 (19)

BAT14

(3) 4

V1

UJA1069

29 (21)

SYSINH

30 (22)

V3

17 (13)

INH/LIMP

INH

V1 MONITOR

7 (6)

INTN

18 (14)

WAKE

TEST

(5) 6

(7) 8

WAKE

RESET/EN

WATCHDOG

OSCILLATOR

RSTN

EN

16 (12)

SBC

FAIL-SAFE

SYSTEM

CHIP

TEMPERATURE

11 (10)

9 (8)

SCK

SDI

SPI

10 (9)

12 (11)

SDO

SCS

26 (18)

25 (17)

3 (2)

RTLIN

LIN

TXDL

RXDL

5 (4)

23 (15)

GND

BAT42

001aad669

The pin numbers in parenthesis are for the UJA1069TW24 version.

Fig 1. Block diagram

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5. Pinning information

5.1 Pinning

1

2

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

n.c.

BAT42

SENSE

V3

3

TXDL

V1

4

SYSINH

n.c.

5

RXDL

RSTN

INTN

EN

6

BAT14

RTLIN

LIN

7

8

UJA1069TW

9

SDI

n.c.

10

11

12

13

14

15

16

SDO

SCK

SCS

n.c.

GND

n.c.

WAKE

INH/LIMP

TEST

001aad676

Fig 2. Pin conﬁguration (HTSSOP32)

1

2

24

23

22

21

20

19

n.c.

TXDL

V1

BAT42

SENSE

V3

3

4

RXDL

RSTN

INTN

EN

SYSINH

n.c.

5

6

BAT14

RTLIN

LIN

UJA1069TW24

7

18

17

16

15

14

13

8

SDI

9

SDO

SCK

SCS

TEST

n.c.

10

11

12

GND

WAKE

INH/LIMP

001aad677

Fig 3. Pin conﬁguration (HTSSOP24)

UJA1069_2

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5.2 Pin description

Table 2.

Symbol

Pin description

Description

HTSSOP32 HTSSOP24

n.c.

1

2

3

1

-

not connected

n.c.

TXDL

2

LIN transmit data input (LOW for dominant, HIGH for

recessive)

V1

4

5

6

7

3

4

5

6

voltage regulator output for the microcontroller (3 V, 3.3 V

or 5 V depending on the SBC version)

RXDL

RSTN

INTN

LIN receive data output (LOW when dominant, HIGH

when recessive)

reset output to microcontroller (active LOW; will detect

clamping situations)

interrupt output to microcontroller (active LOW;

open-drain, wire-AND this pin to other ECU interrupt

outputs)

EN

8

7

enable output (active HIGH; push-pull, LOW with every

reset / watchdog overﬂow)

SDI

9

8

SPI data input

SDO

SCK

SCS

n.c.

10

11

12

13

14

15

16

17

9

SPI data output (ﬂoating when pin SCS is HIGH)

SPI clock input

10

11

-

SPI chip select input (active LOW)

not connected

n.c.

-

not connected

n.c.

-

not connected

TEST

INH/LIMP

12

13

test pin (should be connected to ground in application)

inhibit / limp home output (BAT14 related, push-pull,

default ﬂoating)

WAKE

18

14

local wake-up input (BAT42 related, continuous or cyclic

sampling)

n.c.

19

20

21

22

23

24

25

26

27

28

29

-

not connected

n.c.

-

not connected

n.c.

-

not connected

n.c.

-

not connected

GND

n.c.

15

16

17

18

19

20

21

ground

not connected

LIN

LIN bus line (LOW in dominant state)

LIN-bus termination resistor connection

14 V battery supply input

not connected

RTLIN

BAT14

n.c.

SYSINH

system inhibit output (BAT42 related; e.g. for controlling

external DC-to-DC converter)

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Preliminary data sheet

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Table 2.

Pin description …continued

Symbol

Description

HTSSOP32 HTSSOP24

V3

30

22

unregulated 42 V output (BAT42 related; continuous

output, or cyclic mode synchronized with local wake-up

input)

SENSE

BAT42

31

32

23

24

fast battery interrupt / chatter detector input

42 V battery supply input (connect this pin to BAT14 in

14 V applications)

The exposed die pad at the bottom of the package allows better dissipation of heat from

the SBC via the printed-circuit board. The exposed die pad is not connected to any active

part of the IC and can be left ﬂoating, or can be connected to GND for the best EMC

performance.

6. Functional description

6.1 Introduction

The UJA1069 combines all peripheral functions around a microcontroller within typical

automotive networking applications into one dedicated chip. The functions are as follows:

• Power supply for the microcontroller

• Switched BAT42 output

• System reset

• Watchdog with Window mode and Time-out mode

• On-chip oscillator

• LIN transceiver for serial communication

• SPI control interface

• Local wake-up input

• Inhibit or limp-home output

• System inhibit output port

• Compatibility with 42 V power supply systems

• Fail-safe behavior

6.2 Fail-safe system controller

The fail-safe system controller is the core of the UJA1069 and is supervised by a

watchdog timer which is clocked directly by the dedicated on-chip oscillator. The system

controller manages the register conﬁguration and controls all internal functions of the

SBC. Detailed device status information is collected and presented to the microcontroller.

The system controller also provides the reset and interrupt signals.

The fail-safe system controller is a state machine. The different operating modes and the

transitions between these modes are illustrated in Figure 4. The following sections give

further details about the SBC operating modes.

UJA1069_2

Preliminary data sheet

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UJA1069

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mode change via SPI

watchdog

trigger

Standby mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

mode change via SPI

watchdog

trigger

wake-up detected with its wake-up interrupt disabled

OR mode change to Sleep with pending wake-up

mode change via SPI

OR watchdog time-out with watchdog timeout interrupt disabled

Sleep mode

Normal mode

OR watchdog OFF and I > I

V1

with reset option

thH(V1)

OR interrupt ignored > t

RSTN(INT)

V1: OFF

SYSINH: HIGH/float

LIN: off-line

V1: ON

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

SYSINH: HIGH

flash entry enabled (111/001/111 mode sequence)

OR mode change to Sleep with pending wake-up

OR watchdog not properly served

LIN: all modes available

watchdog: window

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

watchdog: time-out/OFF

INH/LIMP: LOW/float

RSTN: LOW

OR interrupt ignored > t

RSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

EN: LOW

wake-up detected

OR watchdog time-out

OR V3 overload detected

init Normal mode

via SPI successful

Start-up mode

V1: ON

SYSINH: HIGH

init Normal mode

via SPI successful

supply connected

for the first time

LIN: off-line

watchdog: start-up

INH/LIMP: HIGH/LOW/float

EN: LOW

init Flash mode via SPI

AND flash entry enabled

t > t

WD(init)

OR SPI clock count <> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

watchdog

trigger

leave Flash mode code

OR watchdog time-out

OR interrupt ignored > t

RSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

Restart mode

Flash mode

V1: ON

SYSINH: HIGH

LIN: off-line

V1: ON

wake-up detected

AND oscillator ok

SYSINH: HIGH

LIN: all modes available

watchdog: time-out

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

AND t > t

ret

watchdog: start-up

INH/LIMP: LOW/float

EN: LOW

t > t

WD(init)

OR SPI clock count <> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

Fail-safe mode

V1: OFF

SYSINH: HIGH/float

LIN: off-line

oscillator fail

OR RSTN externally clamped HIGH detected > t

OR RSTN externally clamped LOW detected > t

OR V1 undervoltage detected > t

V1(CLT)

RSTN(CHT)

RSTN(CLT)

from any

mode

watchdog: OFF

INH/LIMP: LOW

RSTN: LOW

EN: LOW

001aad670

Fig 4. Main state diagram

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6.2.1 Start-up mode

Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and

ground are connected for the ﬁrst time. Start-up mode is also entered after any event that

results in a system reset. The reset source information is provided by the SBC to support

different software initialization cycles that depend on the reset event.

It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode

or Fail-safe mode. Such a wake-up can originate either from the LIN-bus or from the local

WAKE pin.

On entering Start-up mode a lengthened reset time t_RSTNLis observed. This reset time is

either user-deﬁned (via the RLC bit in the System Conﬁguration register) or defaults to the

value as given in Section 6.12.12. During the reset lengthening time pin RSTN is held

LOW by the SBC.

When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog

timer will wait for initialization. If the watchdog initialization is successful, the selected

operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart

mode will be entered.

6.2.2 Restart mode

The purpose of the Restart mode is to give the application a second chance to start up,

should the ﬁrst attempt from Start-up mode fail. Entering Restart mode will always set the

reset lengthening time t_RSTNLto the higher value to guarantee the maximum reset length,

regardless of previous events.

If start-up from Restart mode is successful (the previous problems do not reoccur and

watchdog initialization is successful), then the selected operating mode will be entered.

From Restart mode this must be Normal mode. If problems persist or if V1 fails to start up,

then Fail-safe mode will be entered.

6.2.3 Fail-safe mode

Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also

entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible

system power consumption from the SBC and from the external components controlled by

the SBC.

A wake-up (via the LIN-bus or the WAKE pin) is needed to leave Fail-safe mode. This is

only possible if the on-chip oscillator is running correctly. The SBC restarts from Fail-safe

mode with a deﬁned delay t_ret, to guarantee a discharged V1 before entering Start-up

mode. Regulator V1 will restart and the reset lengthening time t_RSTNLis set to the higher

value; see Section 6.5.1.

6.2.4 Normal mode

Normal mode gives access to all SBC system resources, including LIN, INH/LIMP and

EN. Therefore in Normal mode the SBC watchdog runs in (programmable) Window mode,

for strictest software supervision. Whenever the watchdog is not properly served a system

reset is performed.

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Interrupts from SBC to the host microcontroller are also monitored. A system reset is

performed if the host microcontroller does not respond within t_RSTN(INT). Entering Normal

mode does not activate the LIN transceiver automatically. The LIN Mode Control (LMC) bit

must be used to activate the LIN medium if required, allowing local cyclic wake-up

scenarios to be implemented without affecting the LIN-bus.

6.2.5 Standby mode

In Standby mode the system is set into a state with reduced current consumption. The

watchdog will, however, continue to monitor the microcontroller (Time-out mode) since it is

powered via pin V1.

In the event that the host microcontroller can provide a low-power mode with reduced

current consumption in its Standby mode or Stop mode, the watchdog can be switched off

entirely in Standby mode of the SBC. The SBC monitors the microcontroller supply current

to ensure that there is no unobserved phase with disabled watchdog and running

microcontroller. The watchdog will remain active until the supply current drops below

I_thL(V1). Below this current limit the watchdog is disabled.

Should the current increase to I_thH(V1), e.g. as result of a microcontroller wake-up from

application speciﬁc hardware, the watchdog will start operating again with the previously

used time-out period. If needed, an interrupt can be issued when the watchdog restarts. If

the watchdog is not triggered correctly, a system reset will occur and the SBC will enter

Start-up mode.

If Standby mode is entered from Normal mode with the selected watchdog OFF option,

the watchdog will use the maximum time-out as deﬁned for Standby mode until the supply

current drops below the current detection threshold; the watchdog is now OFF. If the

current increases again, the watchdog is immediately activated, again using the maximum

watchdog time-out period. If the watchdog OFF option is selected during Standby mode,

the last used watchdog period will deﬁne the time for the supply current to fall below the

current detection threshold. This allows the user to align the current supervisor function to

the application needs.

Generally, the microcontroller can be activated from Standby mode via a system reset or

via an interrupt without reset. This allows implementation of differentiated start-up

behavior from Standby mode, depending on the application needs:

• If the watchdog is still running during Standby mode, the watchdog can be used for

cyclic wake-up behavior of the system. A dedicated Watchdog Time-out Interrupt

Enable (WTIE) bit enables the microcontroller to decide whether to receive an

interrupt or a hardware reset upon overﬂow. The interrupt option will be cleared in

hardware automatically with each watchdog overﬂow to ensure that a failing main

routine is detected while the interrupt service still operates. So the application

software must set the interrupt behavior each time before a standby cycle is entered.

• Any wake-up via the LIN-bus together with a local wake-up event will force a system

reset event or an interrupt to the microcontroller. So it is possible to exit Standby mode

without any system reset if required.

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When an interrupt event occurs the application software has to read the Interrupt register

within t_RSTN(INT). Otherwise a fail-safe system reset is forced and Start-up mode will be

entered. If the application has read out the Interrupt register within the speciﬁed time, it

can decide whether to switch into Normal mode via an SPI access or to stay in Standby

mode.

The following operations are possible from Standby mode:

• Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the

microcontroller is triggered periodically and checked for the correct response)

• Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;

the SBC provides information about the reset source to allow different start

sequences after reset)

• Wake-up by activity on the LIN-bus via an interrupt signal to the microcontroller

• Wake-up by bus activity on the LIN-bus via a reset signal

• Wake-up by increasing the microcontroller supply current without a reset signal

(where a stable supply is needed for the microcontroller RAM contents to remain valid

and wake-up from an external application not connected to the SBC)

• Wake-up by increasing the microcontroller supply current with a reset signal

• Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller

• Wake-up due to a falling edge at pin WAKE forcing a reset signal

6.2.6 Sleep mode

In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled

external supplies are switched off entirely, resulting in minimum system power

consumption. In this mode, the watchdog runs in Time-out mode or is completely off.

Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any

operation of the microcontroller. The INH/LIMP output is ﬂoating in parallel and pin V1 is

disabled. It is also possible for V3 to be ON, OFF or in Cyclic mode to supply external

wake-up switches.

If the watchdog is not disabled in software, it will continue to run and force a system reset

upon overﬂow of the programmed period time. The SBC enters Start-up mode and pin V1

becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode.

Depending on the application, the following operations can be selected from Sleep mode:

• Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed

periodically, the SBC provides information about the reset source to allow different

start sequences after reset

• Wake-up by activity on the LIN-bus or falling edge at pin WAKE

• An overload on V3, only if V3 is in a cyclic or in continuously ON mode

6.2.7 Flash mode

Flash mode can only be entered from Normal mode by entering a speciﬁc Flash mode

entry sequence. This fail-safe control sequence comprises three consecutive write

accesses to the Mode register, within the legal windows of the watchdog, using the

UJA1069_2

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operating mode codes 111, 001 and 111 respectively. As a result of this sequence, the

SBC will enter Start-up mode and perform a system reset with the related reset source

information (bits RSS[3:0] = 0110).

From Start-up mode the application software now has to enter Flash mode within t_WD(init)

by writing Operating Mode code 011 to the Mode register. This feeds back a successfully

received hardware reset (handshake between the SBC and the microcontroller). The

transition from Start-up mode to Flash mode is possible only once after completing the

Flash entry sequence.

The application can also decide not to enter Flash mode but to return to Normal mode by

using the Operating Mode code 101 for handshaking. This erases the Flash mode entry

sequence.

The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode,

but Operating Mode code 111 must be used for serving the watchdog. If this code is not

used or if the watchdog overﬂows, the SBC immediately forces a reset and enters Start-up

mode. Flash mode is properly exited using the Operating Mode code 110 (leave Flash

mode), which results in a system reset with the corresponding reset source information.

Other Mode register codes will cause a forced reset with reset source code ‘illegal Mode

register code’.

6.3 On-chip oscillator

The on-chip oscillator provides the clock signal for all digital functions and is the timing

reference for the on-chip watchdog and the internal timers.

If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is

an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the

oscillator has recovered to its normal frequency and the system receives a wake-up event.

6.4 Watchdog

The watchdog provides the following timing functions:

• Start-up mode; needed to give the software the opportunity to initialize the system

• Window mode; detects too early and too late accesses in Normal mode

• Time-out mode; detects a too late access, can also be used to restart or interrupt the

microcontroller from time to time (cyclic wake-up function)

• OFF mode; fail-safe shut-down during operation thus preventing any blind spots in the

system supervision

The watchdog is clocked directly by the on-chip oscillator.

To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are

coded with redundant bits. Therefore, only certain codes are allowed for a proper

watchdog service.

The following corrupted watchdog accesses result in an immediate system reset:

• Illegal watchdog period coding; only ten different codes are valid

• Illegal operating mode coding; only six different codes are valid

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Any microcontroller driven mode change is synchronized with a watchdog access by

reading the mode information and the watchdog period information from the same

register. This enables an easy software ﬂow control with deﬁned watchdog behavior when

switching between different software modules.

6.4.1 Watchdog start-up behavior

Following any reset event the watchdog is used to monitor the ECU start-up procedure. It

observes the behavior of the RSTN pin for any clamping condition or interrupted reset

wire. In case the watchdog is not properly served within t_WD(init), another reset is forced

and the monitoring procedure is restarted. In case the watchdog is again not properly

served, the system enters Fail-safe mode (see also Figure 4, Start-up mode and Restart

mode).

6.4.2 Watchdog window behavior

Whenever the SBC enters Normal mode, the Window mode of the watchdog is activated.

This ensures that the microcontroller operates within the required speed; a too fast as well

as a too slow operation will be detected. Watchdog triggering using the Window mode is

illustrated in Figure 5.

period

too early

trigger window

50 %

100 %

trigger

restarts

period

trigger

via SPI

last

trigger point

earliest possible

trigger point

latest possible

trigger point

trigger restarts period

(with different duration if

desired)

50 %

100 %

trigger

window

too early

new period

trigger

via SPI

earliest

possible

trigger

point

latest

possible

trigger

point

mce626

Fig 5. Watchdog triggering using Window mode

The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler.

The period can be changed within any valid trigger window. Whenever the watchdog is

triggered within the window time, the timer will be reset to start a new period.

The watchdog window is deﬁned to be between 50 % and 100 % of the nominal

programmed watchdog period. Any too early or too late watchdog access or wrong Mode

register code access will result in an immediate system reset, entering Start-up mode.

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6.4.3 Watchdog time-out behavior

Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the active

watchdog operates in Time-out mode. The watchdog has to be triggered within the actual

programmed period time; see Figure 6. The Time-out mode can be used to provide cyclic

wake-up events to the host microcontroller from Standby mode and Sleep mode.

period

trigger range

time-out

trigger

via SPI

earliest

possible

trigger

point

latest

possible

trigger

point

trigger restarts period

(with different duration if

desired)

trigger range

new period

time-out

mce627

Fig 6. Watchdog triggering using Time-out mode

In Standby and in Flash mode the nominal periods can be changed with any SPI access

to the Mode register.

Any illegal watchdog trigger code results in an immediate system reset, entering Start-up

mode.

6.4.4 Watchdog OFF behavior

In Standby mode and Sleep mode it is possible to switch off the watchdog entirely. For

fail-safe reasons this is only possible if the microcontroller has stopped program

execution. To ensure that there is no program execution, the V1 supply current is

monitored by the SBC while the watchdog is switched off.

When selecting the watchdog OFF code, the watchdog remains active until the

microcontroller supply current has dropped below the current monitoring threshold I_thL(V1)

.

After the supply current has dropped below the threshold, the watchdog stops at the end

of the watchdog period. In case the supply current does not drop below the monitoring

threshold, the watchdog stays active.

If the microcontroller supply current increases above I_thH(V1)while the watchdog is OFF,

the watchdog is restarted with the last used watchdog period time and a watchdog restart

interrupt is forced, if enabled.

In case of a direct mode change towards Standby mode with watchdog OFF selected, the

longest possible watchdog period is used. It should be noted that in Sleep mode V1

current monitoring is not active.

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6.5 System reset

The reset function of the UJA1069 offers two signals to deal with reset events:

• RSTN; the global ECU system reset

• EN; a fail-safe global enable signal

6.5.1 RSTN pin

The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW with

selectable pulse length upon the following events; see Figure 4:

• Power-on (ﬁrst battery connection) or V_BAT42below power-on reset threshold voltage

• Low V1 supply

• V1 current above threshold during Standby mode while watchdog OFF behavior is

selected

• V3 is down due to short-circuit condition during Sleep mode

• RSTN externally forced LOW, falling edge event

• Successful preparation for Flash mode completed

• Successful exit from Flash mode

• Wake-up from Standby mode via pins LIN or WAKE if programmed accordingly, or any

wake-up event from Sleep mode

• Wake-up event from Fail-safe mode

• Watchdog trigger failures (too early, overﬂow, wrong code)

• Illegal mode code via SPI applied

• Interrupt not served within t_RSTN(INT)

All of these reset events have a dedicated reset source in the System Status register to

allow distinction between the different events.

The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware

is properly reset. After the ﬁrst battery connection, a short power-on reset of 1 ms is

provided after voltage V1 is present. Once started, the microcontroller can set the Reset

Length Control (RLC) bit within the System Conﬁguration Register; this allows the reset

pulse to be adjusted for future reset events. With this bit set, all reset events are

lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms)

in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an

erroneously shortened reset pulse will restart any microcontroller, at least within the

second trial by using the long reset pulse.

The behavior of pin RSTN is illustrated in Figure 7. The duration of t_RSTNLdepends on the

setting of the RLC bit (deﬁnes the reset length). Once an external reset event is detected

the system controller enters the Start-up mode. The watchdog now starts to monitor pin

RSTN as illustrated in Figure 8. If the RSTN pin is not released in time then Fail-safe

mode is entered as shown in Figure 4.

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V1

V

rel(UV)(V1)

det(UV)(V1)

time

power-up

under-

voltage

missing

watchdog voltage

access spike

under-

power-

down

V

RSTN

time

t

RSTNL

coa054

Fig 7. Reset pin behavior

V

RSTN

time

t

RSTNL

t

WD(init)

RSTN

externally

forced LOW

V

RSTN

time

t

RSTNL

t

RSTN externally forced LOW

WD(init)

001aad181

Fig 8. Reset timing diagram

Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin

RSTN HIGH but pin RSTN level remains LOW for longer than t_RSTN(CLT), the SBC

immediately enters Fail-safe mode since this indicates an application failure.

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The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin

for longer than t_RSTN(CHT)while pin RSTN is driven internally to a LOW-level by the SBC,

the SBC falls back immediately to Fail-safe mode since the microcontroller cannot be

reset any more. By entering Fail-safe mode, the V1 voltage regulator shuts down and the

microcontroller stops.

Additionally, chattering reset signals are handled by the SBC in such a way that the

system safely falls back to Fail-safe mode with the lowest possible power consumption.

6.5.2 EN output

Pin EN can be used to control external hardware such as power components or as a

general purpose output if the system is running properly. During all reset events, when pin

RSTN is pulled LOW, the EN control bit will be cleared, pin EN will be pulled LOW and will

stay LOW after pin RSTN is released. In Normal mode and Flash mode of the SBC, the

microcontroller can set the EN control bit via the SPI. This results in releasing pin EN

which then returns to a HIGH-level.

6.6 Power supplies

6.6.1 BAT14, BAT42 and SYSINH

The SBC has two supply pins, pin BAT42 and pin BAT14. Pin BAT42 supplies most of the

SBC where pin BAT14 only supplies the linear voltage regulators and the INH/LIMP output

pin. This supply architecture allows different supply strategies including the use of

external DC-to-DC converters controlled by the pin SYSINH.

6.6.1.1 SYSINH output

The SYSINH output is a high-side switch from BAT42. It is activated whenever the SBC

requires supply voltage to pin BAT14, e.g. when V1 is on (see Figure 4 and Figure 8).

Otherwise pin SYSINH is ﬂoating. Pin SYSINH can be used to control e.g. an external

step-down voltage regulator to BAT14, to reduce power consumption in low-power modes.

6.6.2 SENSE input

The SBC has a dedicated SENSE pin for dynamic monitoring of the battery contact of an

electronic control unit. Connecting this pin in front of the polarity protection diode of the

ECU provides an early warning if the battery becomes disconnected.

6.6.3 Voltage regulator V1

The UJA1069 has an independent voltage regulator supplied out of the BAT14 pin.

Regulator V1 is intended to supply the microcontroller.

The V1 voltage is continuously monitored to provide the system reset signal when

undervoltage situations occur. Whenever the V1 voltage falls below one of the three

programmable thresholds, a hardware reset is forced.

A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events

lower than V_UV(VFI). This allows the application to receive a supply warning interrupt in

case one of the lower V1 undervoltage reset thresholds is selected.

The V1 regulator is overload protected. The maximum output current available from pin V1

depends on the voltage applied to pin BAT14 according to the characteristics section. For

thermal reasons, the total power dissipation should be taken into account.

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6.6.4 Switched battery output V3

V3 is a high-side switched BAT42-related output which is used to drive external loads

such as wake-up switches or relays. The features of V3 are as follows:

• Three application controlled modes of operation; ON, OFF or Cyclic mode.

• Two different cyclic modes allow the supply of external wake-up switches; these

switches are powered intermittently, thus reducing the system’s power consumption in

case a switch is continuously active; the wake-up input of the SBC is synchronized

with the V3 cycle time.

• The switch is protected against current overloads. If V3 is overloaded, pin V3 is

automatically disabled. The corresponding Diagnosis register bit is reset and an

interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the

corresponding reset source code becomes available in the RSS bits of the System

Status register. This signals that the wake-up source via V3 supplied wake-up

switches has been lost.

6.7 LIN transceiver

The integrated LIN transceiver of the UJA1069 is a LIN 2.0 compliant transceiver. The

transceiver has the following features:

• SAE J2602 compliant and compatible with LIN revision 1.3

• Fail-safe LIN termination to BAT42 via dedicated RTLIN pin

• Enhanced error handling and reporting of bus and TXD failures; these failures are

separately identiﬁed in the System Diagnosis register

6.7.1 Mode control

The controller of the LIN transceiver provides two modes of operation: Active mode and

Off-line mode; see Figure 9. In Off-line mode the transmitter and receiver do not consume

current, but wake-up events will be recognized by the separate wake-up receiver.

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Active mode

transmitter: ON/OFF (LTC)

receiver: ON

RXDL: bitstream

RTLIN: ON/75 µA

SBC enters

Normal or Flash mode

AND LMC = 1

Stand-by, Start-up,

Restart or Fail-safe mode

OR LMC = 0

Off-line mode

transmitter: OFF

receiver: wake-up

RXDL: wake-up status

RTLIN: 75 µA/OFF

SBC enters

Fail-safe mode

power-on

001aad184

Fig 9. States LIN transceiver

6.7.1.1 Active mode

In Active mode the LIN transceiver can transmit data to and receive data from the LIN bus.

To enter Active mode the LMC bit must be set in the Physical Layer register and the SBC

must be in Normal mode or Flash mode.

The LTC bit can be used to set the LIN transceiver to a Listen-only mode. The transmitter

output stage is disabled in this mode.

When leaving Active mode the LIN transmitter is disabled and the LIN receiver is

monitoring the LIN-bus for a valid wake-up.

6.7.1.2 Off-line mode

Off-line mode is the low-power mode of the LIN transceiver. The LIN transceiver is

disabled to save supply current. Pin RXDL reﬂects any wake-up event at the LIN-bus.

6.7.2 LIN wake-up

For a remote wake-up via LIN a LIN-bus signal is required as shown in Figure 10.

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LIN

wake-up

t

BUS(LIN)

001aad447

Fig 10. LIN wake-up timing diagram

6.7.3 Termination control

The RTLIN pin is in one of 3 different states: RTLIN = on, RTLIN = off or RTLIN = 75 µA;

see Figure 11.

Active mode and receiver dominant > t

LIN(dom)(det)

OR Off-line mode

RTLIN = 75 µA

RTLIN = ON

supplied directly

out of BAT42

supplied directly

out of BAT42

Active mode and receiver recessive > t

LIN(dom)(rec)

OR mode change to Active mode

Off-line mode

AND receiver recessive > t

LIN(dom)(rec)

Off-line mode

AND receiver dominant > t

mode change to Active mode

LIN(dom)(det)

power-on

RTLIN = OFF

001aad183

Fig 11. States of the RTLIN pin

During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN

provides an internal switch to BAT42. For master and slave operation an external resistor,

1 kΩ or 30 kΩ respectively, can be applied between pins RTLIN and LIN. An external

diode in series with the termination resistor is not required due to the incorporated internal

diode.

6.7.4 LIN slope control

The LSC bit in the Physical Layer Control register offers a choice between two LIN slope

times, allowing communication up to 20 kbit/s (normal) or up to 10.4 kbit/s (low slope).

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6.7.5 LIN driver capability

Setting the LDC bit in the Physical Layer Control register will increase the driver capability

of the LIN output stage. This feature is used in auto-addressing systems, where the

standard LIN 2.0 drive capability is insufﬁcient.

6.7.6 Bus and TXDL failure detection

The SBC handles and reports the following LIN-bus related failures:

• LIN-bus shorted to ground

• LIN-bus shorted to V_BAT14or V_BAT42; the transmitter is disabled

• TXDL clamped dominant; the transmitter is disabled

These failure events force an interrupt to the microcontroller whenever the status changes

and the corresponding interrupt is enabled.

6.7.6.1 TXDL dominant clamping

If the TXDL pin is clamped dominant for longer than t_{TXDL(dom)(dis)}the LIN transmitter is

disabled. After the TXDL pin becomes recessive the transmitter is reactivated

automatically when detecting bus activity or manually by setting and clearing the LTC bit.

6.7.6.2 LIN dominant clamping

When the LIN-bus is clamped dominant for longer than t_{LIN(dom)(det)}(which is longer than

t_{TXDL(dom)(dis)}), the state of the LIN termination is changed according to Figure 11.

6.7.6.3 LIN recessive clamping

If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter

is disabled. The transmitter is reactivated automatically when the LIN bus becomes

dominant or manually by setting and clearing the LTC bit.

6.8 Inhibit and limp-home output

The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for

an extra (external) voltage regulator, or as a ‘limp-home’ output. The pin is controlled via

the ILEN bit and ILC bit in the System Conﬁguration register; see Figure 12.

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state change via SPI

OR enter Fail-safe mode

INH/LIMP:

HIGH

INH/LIMP:

LOW

ILEN = 1

ILC = 1

ILEN = 1

ILC = 0

state change via SPI

OR (enter Start-up mode after

wake-up reset, external reset

or V1 undervoltage)

state change via SPI

OR enter Fail-safe mode

OR enter Restart mode

OR enter Sleep mode

state change via SPI

INH/LIMP:

floating

ILEN = 0

ILC = 1/0

power-on

001aad178

Fig 12. States of the INH/LIMP pin

When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a

default LOW level. The pin can be set to HIGH according to the state diagram.

When pin INH/LIMP is used as limp-home output, a pull-up resistor to V_BAT42ensures a

default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe

mode.

6.9 Wake-up input

The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has

an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are

selected via the WAKE Sample Control bit (WSC):

• Continuous sampling (with an internal clock) if the bit is set

• Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 13.

This is to save bias current within the external switches in low-power operation. Two

repetition times are possible, 16 ms and 32 ms.

If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the

level of bit WSC.

The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the

System Status register reﬂect the actual status of pin WAKE. The WAKE port can be

disabled by clearing the WEN bit in the System Conﬁguration register.

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t

w(CS)

t

on(CS)

V

3

approximately 70 %

t

su(CS)

sample

active

button pushed

button released

signal already HIGH

V

WAKE

due to biasing (history)

signal remains LOW

due to biasing (history)

flip flop

V

INTN

001aac307

Fig 13. Pin WAKE, cyclic sampling via V3

6.10 Interrupt output

Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in

the Interrupt register is set. By reading the Interrupt register all bits are cleared. The

Interrupt register will also be cleared during a system reset (RSTN LOW).

As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN

will be HIGH for at least t_INTNafter each read-out of the Interrupt register. Without further

interrupts within t_INTNpin INTN stays HIGH, otherwise it will revert to LOW again.

To prevent the microcontroller from being slowed down by repetitive interrupts, in Normal

mode some interrupts are only allowed to occur once per watchdog period; see

Section 6.12.7.

If an interrupt is not read out within t_RSTN(INT)a system reset is performed.

6.11 Temperature protection

The temperature of the SBC chip is monitored as long as the microcontroller voltage

regulator V1 is active. To avoid an unexpected shutdown of the application by the SBC,

the temperature protection will not switch off any part of the SBC or activate a deﬁned

system stop of its own accord. If the temperature is too high it generates an interrupt to

the microcontroller, if enabled, and the corresponding status bit will be set. The

microcontroller can then decide whether to switch off parts of the SBC to decrease the

chip temperature.

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6.12 SPI interface

The Serial Peripheral Interface (SPI) provides the communication link with the

microcontroller, supporting multi-slave and multi-master operation. The SPI is conﬁgured

for full duplex data transfer, so status information is returned when new control data is

shifted in. The interface also offers a read-only access option, allowing registers to be

read back by the application without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

• SCS - SPI chip select; active LOW

• SCK - SPI clock; default level is LOW due to low-power concept

• SDI - SPI data input

• SDO - SPI data output; ﬂoating when pin SCS is HIGH

Bit sampling is performed on the falling clock edge and data is shifted on the rising clock

edge; see Figure 14.

SCS

SCK

SDI

01

02

03

04

15

16

sampled

X

MSB

14

13

12

01

LSB

X

MSB

SDO

X

floating

mce634

Fig 14. SPI timing protocol

To protect against wrong or illegal SPI instructions, the SBC detects the following SPI

failures:

• SPI clock count failure (wrong number of clock cycles during one SPI access): only

16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock

cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.

In Start-up and Restart mode a reset is forced instead of an interrupt

• Forbidden mode changes according to Figure 4 result in an immediate system reset

• Illegal Mode register code. Undeﬁned operating mode or watchdog period coding

results in an immediate system reset; see Section 6.12.3

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6.12.1 SPI register mapping

Any control bit which can be set by software is readable by the application. This allows

software debugging as well as control algorithms to be implemented.

Watchdog serving and mode setting is performed within the same access cycle; this only

allows an SBC mode change whilst serving the watchdog.

Each register carries 12 data bits; the other 4 bits are used for register selection and

read/write deﬁnition.

6.12.2 Register overview

The SPI interface gives access to all SBC registers; see Table 3. The ﬁrst two bits (A1 and

A0) of the message header deﬁne the register address, the third bit is the read register

select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO)

allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can

be accessed also depends on the SBC operating mode.

Table 3.

Register overview

Operating

Register

Write access (RO = 0)

Read access (RO = 0 or RO = 1)

address bits mode

(A1, A0)

Read Register Select

(RRS) bit = 0

Read Register Select

(RRS) bit = 1

00

01

all modes

Mode register

System Status register

System Diagnosis register

Interrupt register

Normal mode;

Standby mode;

Flash mode

Interrupt Enable register

Interrupt Enable Feedback

register

Start-up mode; Special Mode register

Restart mode

Interrupt Enable Feedback

register

Special Mode Feedback

register

10

11

Normal mode;

Standby mode register

System Conﬁguration

Feedback register

General Purpose Feedback

register 0

Start-up mode; General Purpose register 0 System Conﬁguration

Restart mode;

Flash mode

General Purpose Feedback

register 0

Feedback register

Normal mode;

Standby mode register

Physical Layer Control

Feedback register

General Purpose Feedback

register 1

Start-up mode; General Purpose register 1 Physical Layer Control

General Purpose Feedback

register 1

Restart mode;

Flash mode

Feedback register

6.12.3 Mode register

In the Mode register the watchdog is deﬁned and re-triggered, and the SBC operating

mode is selected. The Mode register also contains the global enable output bit (EN) and

the Software Development Mode (SDM) control bit. During system operation cyclic access

to the Mode register is required to serve the watchdog. This register can be written to in all

modes.

At system start-up the Mode register must be written to within t_WD(init)from releasing

RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and

system mode coding. If an illegal code is detected, access is ignored by the SBC and a

system reset is forced in accordance with the state diagram of the system controller; see

Figure 4.

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Table 4.

Bit

Mode register bit description (bits 15 to 12 and 5 to 0)

Symbol

Description

Value

Function

15 and 14 A1, A0

register address 00

select Mode register

13

12

RRS

RO

Read Register

Select

1

0

1

0

read System Diagnosis register

read System Status register

Read Only

read selected register without writing to Mode register

read selected register and write to Mode register

11 to 6

5 to 3

NWP[5:0]

OM[2:0]

see Table 5

Operating Mode 001

Normal mode

010

011

100

101

110

111

Standby mode

initialize Flash mode^[1]

Sleep mode

initialize Normal mode

leave Flash mode

Flash mode ^[1]

2

SDM

Software

Development

Mode

1

0

Software development mode enabled^[2]

normal watchdog, interrupt, reset monitoring and fail-safe

behavior

1

0

EN

-

Enable

1

0

EN output pin HIGH

EN output pin LOW

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

[1] Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’,

while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up

mode to prepare the microcontroller for ﬂash memory download. The four RSS bits in the System Status register reﬂect the reset source

information, conﬁrming the Flash entry sequence. By using the Initializing Flash mode (within t_WD(init)after system reset) the SBC will

now successfully enter Flash mode.

[2] See Section 6.13.1.

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Table 5.

Bit

Mode register bit description (bits 11 to 6)^[1]

Symbol

Description

Value

Time

Normal

Standby

Flash mode Sleep mode

mode (ms)

(ms)

11 to 6

NWP[5:0]

Nominal

Watchdog Period

00 1001

00 1100

01 0010

01 0100

01 1011

10 0100

10 1101

11 0011

11 0101

11 0110

00 1001

00 1100

01 0010

01 0100

01 1011

10 0100

10 1101

11 0011

11 0101

11 0110

00 1001

00 1100

01 0010

01 0100

01 1011

10 0100

10 1101

11 0011

11 0101

11 0110

4

20

160

8

40

320

WDPRE = 00(as

set in the Special

Mode register)

16

32

40

48

56

64

72

80

6

80

640

160

1024

2048

3072

4096

6144

8192

OFF^[3]

240

320

640

1024

2048

4096

OFF^[2]

30

1024

2048

4096

8192

30

Nominal

Watchdog Period

12

24

48

60

72

84

96

108

120

10

20

40

80

100

120

140

160

180

200

60

480

WDPRE = 01(as

set in the Special

Mode register)

120

960

240

1536

3072

4608

6144

9216

12288

OFF^[3]

400

480

960

1536

3072

6144

OFF^[2]

50

1536

3072

6144

12288

50

Nominal

Watchdog Period

100

800

WDPRE = 10(as

set in the Special

Mode register)

200

1600

2560

5120

7680

10240

15360

20480

OFF^[3]

400

800

1600

1560

5120

10240

OFF^[2]

1600

1560

5120

10240

20480

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Table 5.

Bit

Mode register bit description (bits 11 to 6)^[1]…continued

Symbol

Description

Value

Time

Normal

Standby

Flash mode Sleep mode

mode (ms)

(ms)

11 to 6

NWP[5:0]

Nominal

Watchdog Period

00 1001

00 1100

01 0010

01 0100

01 1011

10 0100

10 1101

11 0011

11 0101

11 0110

14

70

560

28

140

1120

2240

3584

7168

10752

14336

21504

28672

OFF^[3]

WDPRE = 11(as

set in the Special

Mode register)

56

280

112

140

168

196

244

252

280

560

1120

2240

3584

7168

14336

OFF^[2]

1120

2240

3584

7168

14336

28672

[1] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f_osc= 512 kHz.

[2] See Section 6.4.4.

[3] The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is

immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry

without dips on V1. See Section 6.4.4.

6.12.4 System Status register

This register allows status information to be read back from the SBC. This register can be

read in all modes.

Table 6.

Bit

System Status register bit description

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

Read Only

00

0

read System Status register

13

12

RRS

RO

1

read System Status register without writing to Mode

register

0

read System Status register and write to Mode register

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LIN fail-safe system basis chip

Table 6.

Bit

System Status register bit description …continued

Symbol

Description

Value

Function

11 to 8

RSS[3:0]

Reset Source^[1]

0000

power-on reset; ﬁrst connection of BAT42 or BAT42 below

power-on voltage threshold or RSTN was forced LOW

externally

0001

0010

cyclic wake-up out of Sleep mode

low V1 supply; V1 has dropped below the selected reset

threshold

0011

0100

V1 current above threshold within Standby mode while

watchdog OFF behavior and reset option (V1CMC bit) are

selected

V3 voltage is down due to overload occurring during Sleep

mode

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

SBC successfully left Flash mode

SBC ready to enter Flash mode

reserved for SBCs with CAN transceiver

LIN wake-up event

local wake-up event (via pin WAKE)

wake-up out of Fail-safe mode

watchdog overﬂow

watchdog not initialized in time; t_WD(init)exceeded

watchdog triggered too early; window missed

illegal SPI access

interrupt not served within t_RSTN(INT)

reserved for SBCs with CAN transceiver

LIN wake-up detected; cleared upon read

no LIN wake-up

7

6

-

reserved

LWS

LIN Wake-up Status

1

0

5

4

3

2

1

0

EWS

Edge Wake-up Status

WAKE Level Status

1

pin WAKE negative edge detected; cleared upon read

pin WAKE no edge detected

0

WLS

1

pin WAKE above threshold

0

pin WAKE below threshold

TWS

Temperature Warning

Status

1

chip temperature exceeds the warning limit

chip temperature is below the warning limit

Software Development mode on

Software Development mode off

pin EN output activated (V1-related HIGH level)

pin EN output released (LOW level)

0

SDMS

ENS

Software Development

Mode Status

1

0

Enable Status

1

0

PWONS

Power-on reset Status

1

power-on reset; cleared after a successfully entered

Normal mode

0

no power-on reset

[1] The RSS bits are updated with each reset event and not cleared. The last reset event is captured.

6.12.5 System Diagnosis register

This register allows diagnosis information to be read back from the SBC. This register can

be read in all modes.

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LIN fail-safe system basis chip

Table 7.

Bit

System Diagnosis register bit description

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

Read Only

00

1

read System Diagnosis register

13

12

RRS

RO

1

read System Diagnosis register without writing to Mode

register

0

read System Diagnosis register and write to Mode register

reserved for SBCs with CAN transceiver

TXDL is clamped dominant

11 to 7

6 and 5

-

reserved

0 0000

LINFD[1:0] LIN failure diagnosis

11

10

01

00

1

LIN is shorted to GND (dominant clamped)

LIN is shorted to VBAT (recessive clamped)

no failure

4

V3D

V3 diagnosis

OK

0

fail; V3 is disabled due to an overload situation

reserved for SBCs with another voltage regulator

OK; V1 always above V_UV(VFI)since last read access

3

2

-

reserved

1

V1D

V1 diagnosis

1

0

fail; V1 was below V_UV(VFI)since last read access; bit is set

again with read access

1 and 0

-

reserved

00

reserved for SBCs with CAN transceiver

6.12.6 Interrupt Enable register and Interrupt Enable Feedback register

These registers allow setting, clearing and reading back the interrupt enable bits of the

SBC.

Table 8.

Bit

Interrupt Enable and Interrupt Enable Feedback register bit description

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

01

1

select the Interrupt Enable register

read the Interrupt register

13

12

RRS

RO

0

read the Interrupt Enable Feedback register

Read Only

1

read the register selected by RRS without writing to

Interrupt Enable register

0

1

read the register selected by RRS and write to Interrupt

Enable register

11

10

WTIE

OTIE

Watchdog Time-out

Interrupt Enable^[1]

a watchdog overﬂow during Standby causes an interrupt

instead of a reset event (interrupt based cyclic wake-up

feature)

0

1

no interrupt forced on watchdog overﬂow; a reset is forced

instead

Over-Temperature

Interrupt Enable

exceeding or dropping below the temperature warning limit

causes an interrupt

0

1

no interrupt forced

9

8

-

reserved

reserved for SBCs with CAN transceiver

SPIFIE

SPI clock count Failure

Interrupt Enable

wrong number of CLK cycles (more than, or less than 16)

forces an interrupt; from Start-up mode and Restart mode a

reset is performed instead of an interrupt

0

no interrupt forced; SPI access is ignored if the number of

cycles does not equal 16

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LIN fail-safe system basis chip

Table 8.

Interrupt Enable and Interrupt Enable Feedback register bit description …continued

Bit

Symbol

Description

Value

Function

7

BATFIE

BAT Failure Interrupt

Enable

1

0

1

0

1

0

1

falling edge at SENSE forces an interrupt

no interrupt forced

6

VFIE

Voltage Failure Interrupt

Enable

clearing of V1D or V3D forces an interrupt

no interrupt forced

5

4

-

reserved

reserved for SBCs with CAN transceiver

any change of the LIN Failure status bits forces an interrupt

no interrupt forced

LINFIE

LIN Failure Interrupt

Enable

3

WIE

WAKE Interrupt

Enable^[2]

a negative edge at pin WAKE generates an interrupt in

Normal mode, Flash mode or Standby mode

0

1

a negative edge at pin WAKE generates a reset in Standby

mode; no interrupt in any other mode

2

WDRIE

Watchdog Restart

Interrupt Enable

a watchdog restart during watchdog OFF generates an

interrupt

0

1

no interrupt forced

1

0

-

reserved

reserved for SBCs with CAN transceiver

LINIE

LIN Interrupt Enable

LIN-bus event results in a wake-up interrupt in Standby

mode and in Normal or Flash mode (unless LIN is in Active

mode already)

0

LIN-bus event results in a reset in Standby mode; no

interrupt in any other mode

[1] This bit is cleared automatically upon each overﬂow event. It has to be set in software each time the interrupt behavior is required

(fail-safe behavior).

[2] WEN (in the System Conﬁguration register) has to be set to activate the WAKE port function globally.

6.12.7 Interrupt register

The Interrupt register allows the cause of an interrupt event to be read. The register is

cleared upon a read access and upon any reset event. Hardware ensures that no interrupt

event is lost in case there is a new interrupt forced while reading the register. After reading

the Interrupt register pin INTN is released for t_INTNto guarantee an edge event at pin

INTN.

The interrupts can be classiﬁed into two groups:

• Timing critical interrupts which require immediate reaction (SPI clock count failure

which needs a new SPI command to be resent immediately, and a BAT failure which

needs critical data to be saved immediately into the nonvolatile memory)

• Interrupts which do not require an immediate reaction (overtemperature and LIN

failures, V1 and V3 failures and the wake-ups via LIN and WAKE. These interrupts will

be signalled in Normal mode to the microcontroller once per watchdog period

(maximum); this prevents overloading the microcontroller with unexpected interrupt

events (e.g. a chattering LIN failure). However, these interrupts are reﬂected in the

interrupt register

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LIN fail-safe system basis chip

Table 9.

Bit

Interrupt register bit description

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

Read Only

01

1

read Interrupt register

13

12

RRS

RO

1

read the Interrupt register without writing to the Interrupt

Enable register

0

1

read the Interrupt register and write to the Interrupt Enable

register

11

10

WTI

OTI

Watchdog Time-out

Interrupt

a watchdog overﬂow during Standby mode has caused an

interrupt (interrupt-based cyclic wake-up feature)

0

1

0

1

no interrupt

OverTemperature

Interrupt

the temperature warning status (TWS) has changed

no interrupt

9

8

-

reserved

reserved for SBCs with CAN transceiver

SPIFI

SPI clock count Failure

Interrupt

wrong number of CLK cycles (more than, or less than 16)

during SPI access

0

no interrupt; SPI access is ignored if the number of CLK

cycles does not equal 16

7

6

BATFI

VFI

BAT Failure Interrupt

1

0

1

0

1

0

1

0

1

falling edge at pin SENSE has forced an interrupt

no interrupt

Voltage Failure Interrupt

V1D or V3D has been cleared

no interrupt

5

4

-

reserved

reserved for SBCs with CAN transceiver

LIN failure status has changed

no interrupt

LINFI

LIN Failure Interrupt

3

2

WI

Wake-up Interrupt

a negative edge at pin WAKE has been detected

no interrupt

WDRI

Watchdog Restart

Interrupt

A watchdog restart during watchdog OFF has caused an

interrupt

0

1

0

no interrupt

1

0

-

reserved

reserved for SBCs with CAN transceiver

LIN wake-up event has caused an interrupt

no interrupt

LINI

LIN Wake-up Interrupt

6.12.8 System Conﬁguration register and System Conﬁguration Feedback register

These registers allow conﬁguration of the behavior of the SBC, and allow the settings to

be read back.

Table 10. System Conﬁguration and System Conﬁguration Feedback register bit description

Bit

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

10

1

select System Conﬁguration register

read the General Purpose Feedback register 0

read the System Conﬁguration Feedback register

13

RRS

0

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LIN fail-safe system basis chip

Table 10. System Conﬁguration and System Conﬁguration Feedback register bit description …continued

Bit

Symbol

Description

Value

Function

12

RO

Read Only

1

read register selected by RRS without writing to System

Conﬁguration register

0

read register selected by RRS and write to System

Conﬁguration register

11 and 10

-

reserved

00

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

9

8

-

reserved

0

1^[1]

reserved for SBCs with CAN transceiver

t_RSTNLlong reset lengthening time selected

t_RSTNLshort reset lengthening time selected

Cyclic mode 2; t_w(CS)long period; see Figure 13

Cyclic mode 1; t_w(CS)short period; see Figure 13

continuously ON

RLC

Reset Length Control

0

7 and 6

V3C[1:0]

V3 Control

11

10

01

00

0

OFF

5

4

-

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

V1CMC

V1 Current Monitor

Control

1

0

an increasing V1 current causes a reset if the watchdog

was disabled during Standby mode

an increasing V1 current just reactivates the watchdog

during Standby mode, and an interrupt is forced (if enabled)

3

2

1

0

WEN

WSC

ILEN

ILC

Wake Enable^[2]

1

0

1

0

1

0

1

0

WAKE pin enabled

WAKE pin disabled

Wake Sample Control

INH/LIMP Enable

INH/LIMP Control

Wake mode cyclic sample

Wake mode continuous sample

INH/LIMP pin active (See ILC bit)

INH/LIMP pin ﬂoating

INH/LIMP pin HIGH if ILEN bit is set

INH/LIMP pin LOW if ILEN bit is set

[1] RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure

situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached.

[2] If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status

register.

6.12.9 Physical Layer Control register and Physical Layer Control Feedback

register

These registers allow conﬁguration of the LIN transceiver of the SBC and allow the

settings to be read back.

Table 11. Physical Layer Control and Physical Layer Control Feedback register bit description

Bit

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

11

1

select Physical Layer Control register

read the General Purpose Feedback register 1

read the Physical Layer Control Feedback register

13

RRS

0

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LIN fail-safe system basis chip

Table 11. Physical Layer Control and Physical Layer Control Feedback register bit description …continued

Bit

Symbol

Description

Value

Function

12

RO

Read Only

1

read the register selected by RRS without writing to the

Physical Layer Control register

0

read the register selected by RRS and write to Physical

Layer Control register

11 to 5

4

-

reserved

000 0000 reserved for SBCs with CAN transceiver

LMC

LIN Mode Control

1

0

1

0

1

0

1

0

1

0

LIN Active mode (in Normal mode and Flash mode only)

LIN Active mode disabled

3

2

1

0

LSC

LDC

LWEN

LTC

LIN Slope Control

LIN Driver Control

LIN Wake-up Enable

up to 10.4 kbit/s (low slope)

up to 20 kbit/s (normal)

increased LIN driver current capability

LIN driver in conformance with the LIN 2.0 standard

wake-up via the LIN-bus enabled

wake-up via the LIN-bus disabled

LIN transmitter is disabled

LIN Transmitter

Control^[1]

LIN transmitter is enabled

[1] In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is

automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing

the LTC bit under software control.

6.12.10 Special Mode register and Special Mode Feedback register

These registers allow conﬁguration of global SBC parameters during start-up of a system

and allow the settings to be read back.

Table 12. Special Mode register and Special Mode Feedback register bit description

Bit

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

01

0

select Special Mode register

read the Interrupt Enable Feedback register

read the Special Mode Feedback register

13

12

RRS

RO

1

Read Only

1

read the register selected by RRS without writing to the

Special Mode register

0

read the register selected by RRS and write to the

Special Mode register

11 and 10

9

-

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

ISDM

Initialize Software

Development Mode^[1]

1

0

initialization of software development mode

normal watchdog interrupt, reset monitoring and fail-safe

behavior

8

7

-

reserved

0

reserved for SBCs with CAN transceiver

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

6 and 5

WDPRE [1:0] Watchdog Prescaler

00

01

10

11

watchdog prescale factor 1

watchdog prescale factor 1.5

watchdog prescale factor 2.5

watchdog prescale factor 3.5

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LIN fail-safe system basis chip

Table 12. Special Mode register and Special Mode Feedback register bit description …continued

Bit

Symbol

Description

Value

11

Function

4 and 3

V1RTHC [1:0] V1 Reset Threshold

Control

V1 reset threshold = 0.9 × V_V1(nom)

V1 reset threshold = 0.7 × V_V1(nom)

V1 reset threshold = 0.8 × V_V1(nom)

V1 reset threshold = 0.9 × V_V1(nom)

[2]

[3]

10

01

00

2 to 0

-

reserved

000

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

[1] See Section 6.13.1.

[2] Not supported for the UJA1069TW/3V0 and UJA1069TW/3V3 version.

[3] Not supported for the UJA1069TW/3V0 version.

6.12.11 General Purpose registers and General Purpose Feedback registers

The UJA1069 offers two 12-bit General Purpose registers (and accompanying General

Purpose Feedback registers) with no predeﬁned bit deﬁnition. These registers can be

used by the microcontroller for advanced system diagnosis or for storing critical system

status information outside the microcontroller. After Power-up General Purpose register 0

will contain a ‘Device Identiﬁcation Code’ consisting of the SBC type and SBC version.

This code is available until it is overwritten by the microcontroller (as indicated by the DIC

bit).

Table 13. General Purpose register 0 and General Purpose Feedback register 0 bit description

Bit

Symbol

A1, A0

RRS

Description

Value

Function

15, 14

13

register address

Read Register Select

10

1

read the General Purpose Feedback register 0

read the System Conﬁguration Feedback register

0

12

RO

Read Only

1

read the register selected by RRS without writing to the

General Purpose register 0

0

read the register selected by RRS and write to the General

Purpose register 0

11

DIC

Device Identiﬁcation

Control^[1]

1

0

General Purpose register 0 contains user-deﬁned bits

General Purpose register 0 contains the Device

Identiﬁcation Code

10 to 0

GP0[10:0]

General Purpose bits^[2]

1

0

user-deﬁned

[1] The Device Identiﬁcation Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the

Device Identiﬁcation Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC.

[2] During power-up the General Purpose register 0 is loaded with a ‘Device Identiﬁcation Code’ consisting of the SBC type and SBC

version, and the DIC bit is cleared.

Table 14. General Purpose register 1 and General Purpose Feedback register 1 bit description

Bit

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

11

1

select General Purpose register 1

read the General Purpose Feedback register 1

read the Physical Layer Control Feedback register

13

RRS

0

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LIN fail-safe system basis chip

Table 14. General Purpose register 1 and General Purpose Feedback register 1 bit description …continued

Bit

Symbol

Description

Value

Function

12

RO

Read Only

1

read the register selected by RRS without writing to the

General Purpose register 1

0

read the register selected by RRS and write to the General

Purpose register

11 to 0

GP1[11:0]

General Purpose bits

1

0

user-deﬁned

6.12.12 Register conﬁgurations at reset

At Power-on, Start-up and Restart mode the setting of the SBC registers is predeﬁned.

Table 15. System Status register: status at reset

Symbol

RSS

Name

Power-on

Start-up^[1]

Restart^[1]

Reset Source Status

LIN Wake-up Status

0000 (power-on reset)

0 (no LIN wake-up)

any value except 1100

0000 or 0010 or 1100 or 1110

LWS

1 if reset is caused by a no change

LIN wake-up, otherwise

no change

EWS

Edge Wake-up Status 0 (no edge detected)

1 if reset is caused by a no change

wake-up via pin WAKE,

otherwise no change

WLS

TWS

WAKE Level Status

actual status

Temperature Warning

Status

0 (no warning)

SDMS

Software Development actual status

Mode Status

actual status

ENS

Enable Status

0 (EN = LOW)

no change

0 (EN = LOW)

no change

PWONS

Power-on Status

1 (power-on reset)

[1] Depends on history.

Table 16. System Diagnosis register: status at reset

Symbol

LINFD

V3D

Name

Power-on

Start-up

Restart

LIN Failure Diagnosis 00 (no failure)

actual status

V3 Diagnosis

V1 Diagnosis

1 (OK)

0 (fail)

V1D

Table 17. Interrupt Enable register and Interrupt Enable Feedback register: status at reset

Symbol

Name

Power-on

Start-up

Restart

All

all bits

0 (interrupt disabled)

no change

Table 18. Interrupt register: status at reset

Symbol

Name

Power-on

Start-up

Restart

All

all bits

0 (no interrupt)

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Table 19. System Conﬁguration register and System Conﬁguration Feedback register: status at reset

Symbol

RLC

Name

Power-on

0 (short)

00 (off)

Start-up

Restart

Fail-Safe

1 (long)

Reset Length Control

V3 Control

no change

1 (long)

V3C

no change

V1CMC

V1 Current Monitor

Control

0 (watchdog

restart)

WEN

WSC

ILEN

Wake Enable

1 (enabled)

no change

Wake Sample Control 0 (control)

INH/LIMP Enable

0 (ﬂoating)

see Figure 12

if ILC = 1,

0 (ﬂoating) if ILC = 1, 1 (active)

otherwise no change

ILC

INH/LIMP Control

0 (LOW)

no change

0 (LOW)

Table 20. Physical Layer Control register and Physical Layer Control Feedback register: status at reset

Symbol

Name

Power-on

Start-up

Restart

Fail-Safe

LMC

LIN Mode Control

0 (Active mode

disabled)

no change

LSC

LDC

LWEN

LTC

LIN Slope Control

LIN Driver Control

LIN Wake-up Enable

0 (normal)

0 (LIN 2.0)

1 (enabled)

no change

LIN Transmitter Control 0 (on)

Table 21. Special Mode register: status at reset

Symbol

ISDM

Name

Power-on

Start-up

Restart

Initialize Software Development Mode

Error pin emulation mode

Watchdog Prescale Factor

V1 Reset Threshold Control

0 (no)

no change

00 (90 %)

ERREM

WDPRE

V1RTHC

0 (EN function)

00 (factor 1)

00 (90 %)

Table 22. General Purpose register 0 and General Purpose Feedback register 0: status at reset

Symbol

DIC

Name

Power-on

Start-up

Restart

Device Identiﬁcation Control

general purpose bits 10 to 7 (version)

0 (Device ID)

Mask version

no change

GP0[10:7]

GP0[6:0]

general purpose bits 6 to 0 (SBC type) 000 0101 (UJA1069) no change

Table 23. General Purpose register 1 and General Purpose Feedback register 1: status at reset

Symbol

Name

Power-on

Start-up

Restart

GP1[11:0]

general purpose bits 11 to 0

0000 0000 0000

no change

UJA1069_2

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LIN fail-safe system basis chip

6.13 Test modes

6.13.1 Software development mode

The Software development mode is intended to support software developers in writing

and pretesting application software without having to work around watchdog triggering

and without unwanted jumps to Fail-safe mode.

In Software development mode the following events do not force a system reset:

• Watchdog overﬂow in Normal mode

• Watchdog window miss

• Interrupt time-out

• Elapsed start-up time

However, in case of a watchdog trigger failure the reset source information is still provided

in the System Status register as if there was a real reset event.

The exclusion of watchdog related resets allows simpliﬁed software testing, because

possible problems in the watchdog triggering can be indicated by interrupts instead of

resets. The SDM bit does not affect the watchdog behavior in Standby and Sleep mode.

This allows the cyclic wake-up behavior to be evaluated during Standby and Sleep mode

of the SBC.

All transitions to Fail-safe mode are disabled. This allows working with an external

emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage of more

than t_V1(CLT)is the only exception that results in entering Fail-safe mode (to protect the

SBC). Transitions from Start-up mode to Restart mode are still possible.

There are two possibilities to enter Software development mode. One is by setting the

ISDM bit via the Special Mode register; possible only once after a ﬁrst battery connection

while the SBC is in Start-up mode. The second possibility to enter Software development

mode is by applying the correct V_th(TEST)input voltage at pin TEST before the battery is

applied to pin BAT42.

To stay in Software development mode the SDM bit in the Mode register has to be set with

each Mode register access (i.e. watchdog triggering) regardless of how Software

development mode was entered.

The Software development mode can be exited at any time by clearing the SDM bit in the

Mode register. Reentering the Software development mode is only possible by

reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset.

UJA1069_2

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LIN fail-safe system basis chip

6.13.2 Forced normal mode

For system evaluation purposes the UJA1069 offers the Forced normal mode. This mode

is strictly for evaluation purposes only. In this mode the characteristics as deﬁned in

Section 9 and Section 10 cannot be guaranteed.

In Forced normal mode the SBC behaves as follows:

• SPI access (writing and reading) is blocked

• Watchdog disabled

• Interrupt monitoring disabled

• Reset monitoring disabled

• Reset lengthening disabled

• All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than

t_V1(CLT)

• V1 is started with the long reset time t_RSTNL. In case of a V1 undervoltage, a reset is

performed until V1 is restored (normal behavior), and the SBC stays in Forced normal

mode; in case of an overload at V1 > t_V1(CLT)Fail-safe mode is entered

• V3 is on; overload protection active

• LIN is in Active mode and cannot switch to Off-line mode

• INH/LIMP pin is HIGH

• SYSINH is HIGH

• EN pin at same level as RSTN pin

Forced normal mode is activated by applying the correct V_th(TEST)input voltage at the

TEST pin during ﬁrst battery connection.

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

39 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

7. Limiting values

Table 24. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.

Symbol

Parameter

Conditions

Min

−0.3

-

Max

+60

Unit

V

V_BAT42

BAT42 supply voltage

load dump; t ≤ 500 ms

V

V_BAT14

BAT14 supply voltage

V_BAT42≥ V_BAT14− 1 V

continuous

−0.3

+33

+45

V

load dump; t ≤ 500 ms

-

V_DC(n)

DC voltage on pins

V1

−0.3

−1.5

−0.3

−1.5

−60

+5.5

V

V3 and SYSINH

INH/LIMP

V_BAT42+ 0.3

V_BAT42+ 1.2

+60

SENSE

WAKE

LIN and RTLIN

with respect to any other pin

+60

TXDL, RXDL, SDO, SDI, SCK, SCS,

RSTN, INTN and EN

−0.3

V_V1+ 0.3

TEST

−0.3

+15

V

V_trt

transient voltage at pin LIN

in accordance with

ISO 7637-3

−150

+100

[1]

I_WAKE

T_stg

DC current at pin WAKE

storage temperature

−15

−55

−40

-

mA

°C

+150

+125

+150

T_amb

T_vj

ambient temperature

[2]

[3]

[4]

virtual junction temperature

electrostatic discharge voltage

V_esd

HBM

at pins LIN, RTLIN,

WAKE, BAT42, V3,

SENSE; with respect to

GND

−8.0

+8.0

kV

at any other pin

MM; at any pin

−2.0

+2.0

kV

V

[5]

−200

+200

[1] Only relevant if V_WAKE< V_GND− 0.3 V; current will ﬂow into pin GND.

[2] In accordance with IEC 60747-1. An alternative deﬁnition of virtual junction temperature is: T_vj= T_amb+ P_d× R_th(vj-amb), where R_th(vj-amb)

is a ﬁxed value to be used for the calculation of T_vj. The rating for T_vjlimits the allowable combinations of power dissipation (P_d) and

ambient temperature (T_amb).

[3] Human Body Model (HBM): C = 100 pF; R = 1.5 kΩ.

[4] ESD performance according to IEC 61000-4-2 (C = 150 pF, R = 330 Ω) of pins LIN, RTLIN, WAKE, BAT42 and V3 with respect to GND

was veriﬁed by an external test house. Following results were obtained:

a) Equal or better than ±4 kV (unaided)

b) Equal or better than ±20 kV for pin LIN (using external ESD protection: NXP Semiconductors PESD1LIN diode)

[5] Machine Model (MM): C = 200 pF; L = 0.75 µH; R = 10 Ω.

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

40 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

8. Thermal characteristics

V1 dissipation

V3 dissipation

other dissipation

T

vj

6 K/W

23 K/W

6 K/W

T

(heat sink)

001aad671

case

R

th(c-a)

amb

Fig 15. Thermal model of the HTSSOP32 package

V1 dissipation

V3 dissipation

other dissipation

T

vj

6 K/W

17 K/W

6 K/W

T

(heat sink)

case

R

th(c-a)

amb

001aae136

Fig 16. Thermal model of the HTSSOP24 package

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

41 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

9. Static characteristics

Table 25. Static characteristics

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply; pin BAT42

I_BAT42

BAT42 supply

current

V1 and V3 off; LIN in Off-line

mode; OTIE = BATFIE = 0;

I

_SYSINH= I_WAKE= I_RTLIN

_LIN= 0 mA

=

V_BAT42= 8.1 V to 52 V

V_BAT42= 5.5 V to 8.1 V

-

50

70

53

0

70

93

76

1

µA

I_BAT42(add)

additional BAT42

supply current

V1 on; I_SYSINH= 0 mA

V3 in Cyclic mode; I_V3= 0 mA

V3 continuously on;

I_V3= 0 mA

30

50

T_vjwarning enabled; OTIE = 1

SENSE enabled; BATFIE = 1

LIN in Active mode;

-

20

2

40

µA

7

650

1300

LMC = 1; V_TXDL= V_V1

_RTLIN= I_LIN= 0 mA

;

I

LIN in Active mode; LMC = 1;

V_TXDL= 0 V (t < t_{LIN(dom)(det)});

I_RTLIN= I_LIN= 0 mA

V_BAT42= 12 V

-

1.5

3

5

mA

V_BAT42= 27 V

10

V_POR(BAT42)

BAT42 voltage level for setting PWONS

for power-on reset

PWONS = 0; V_BAT42falling

4.45

4.75

-

5

V

status bit change

for clearing PWONS

PWONS = 1; V_BAT42rising

-

5.5

5

V

Supply; pin BAT14

I_BAT14

BAT14 supply

current

V1 off; LIN in Off-line mode;

ILEN = 0; I_INH/LIMP= 0 mA

2

µA

I_BAT14(add)additional BAT14 supply current V1 on; I_V1= 0 mA

V1 on; I_V1= 0 mA;

-

200

150

300

200

µA

V_BAT14= 12 V

INH/LIMP enabled; ILEN = 1;

I_INH/LIMP= 0 mA

-

1

-

2

µA

V

V_BAT14

BAT14 voltage level for normal output current

capability at V1

9

6

27

8

for high output current

capability at V1

-

V

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

42 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

Table 25. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Battery supply monitor input; pin SENSE

V_th(SENSE)

input threshold low

battery voltage

detection

1

2.5

-

3

V

release

1.7

20

5

4

V

I_IH(SENSE)

HIGH-level input

current

Normal mode; BATFIE = 1

Standby mode; BATFIE = 1

50

10

0.2

100

20

2

µA

Normal mode or Standby

mode; BATFIE = 0

-

Voltage source; pin V1^[2]; see also Figure 17 to Figure 23

V_o(V1)

output voltage

V_BAT14= 5.5 V to 18 V;

_V1= −120 mA to −5 mA;

T_j= 25 °C

V_V1(nom)

0.1

−

V_V1(nom)

0.1

+

V

I

V_BAT14= 14 V; I_V1= −5 mA;

V_V1(nom)

0.025

V_V1(nom)

0.025

V

T_j= 25 °C

∆V_V1

supply voltage

regulation

V_BAT14= 9 V to 16 V;

-

1

5

25

mV

I

_V1= −5 mA; T_j= 25 °C

V_BAT14= 14 V;

_V1= −50 mA to −5 mA;

load regulation

-

25

I

T_j= 25 °C

[3]

voltage drift with

temperature

V_BAT14= 14 V; I_V1= −5 mA;

T_j= −40 °C to +150 °C

-

200

ppm/K

V_det(UV)(V1)

undervoltage

detection and reset V1RTHC[1:0] = 00 or 11

activation level

V

_BAT14= 14 V;

0.90 ×

V_V1(nom)

0.92 ×

V_V1(nom)

0.95 ×

V_V1(nom)

V

V_BAT14= 14 V;

V1RTHC[1:0] = 01

0.80 ×

V_V1(nom)

0.82 ×

V_V1(nom)

0.85 ×

V_V1(nom)

V_BAT14= 14 V;

V1RTHC[1:0] = 10

0.70 ×

V_V1(nom)

0.72 ×

V_V1(nom)

0.75 ×

V_V1(nom)

V_rel(UV)(V1)

undervoltage

detection release

level

V_BAT14= 14 V;

-

0.94 ×

V_V1(nom)

-

V1RTHC[1:0] = 00 or 11

V_BAT14= 14 V;

V1RTHC[1:0] = 01

0.84 ×

V_V1(nom)

V_BAT14= 14 V;

V1RTHC[1:0] = 10

0.74 ×

V_V1(nom)

V_UV(VFI)

I_thH(V1)

I_thL(V1)

undervoltage level

for generating a VFI

interrupt

V_BAT14= 14 V; VFIE = 1

0.90 ×

V_V1(nom)

0.93 ×

V_V1(nom)

0.97 ×

V_V1(nom)

undercurrent

threshold for

watchdog enable

−10

−6

−5

−3

−2

mA

undercurrent

−1.5

threshold for

watchdog disable

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

43 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

Table 25. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_V1

output current

capability

V_BAT14= 9 V to 27 V;

δV_V1= 0.05 × V_V1(nom)

−200

−135

−120

mA

V_BAT14= 9 V to 27 V;

V1 shorted to GND

−200

−110

-

mA

Ω

V_BAT14= 6 V to 8 V;

δV_V1= 0.05 × V_V1(nom)

-

−250

−150

−250

5

V_BAT14= 5.5 V;

δV_V1= 0.05 × V_V1(nom)

-

V_BAT14= 5.5 V;

δV_V1= 0.25 × V_V1(nom)

-

Z_ds(on)

regulator impedance V_BAT14= 4 V to 5 V

between pins BAT14

3

and V1

Voltage source; pin V3

V_{BAT42-V3(drop)}

I_det(OL)(V3)

I_L

V_BAT42to V_V3voltage V_BAT42= 9 V to 52 V;

-

1.0

−60

5

V

drop

I_V3= −20 mA

overload current

V_BAT42= 9 V to 52 V

−165

-

mA

µA

detection threshold

leakage current

V_V3= 0 V; V3C[1:0] = 00

-

0

System inhibit output; pin SYSINH

V_{BAT42-SYSINH(drop)}V_BAT42to V_SYSINH

voltage drop

I_SYSINH= −0.2 mA

-

1.0

-

2.0

5

V

I_L

leakage current

V_SYSINH= 0 V

µA

Inhibit/limp-home output; pin INH/LIMP

V_{BAT14-INH(drop)}

V_BAT14to V_INH

voltage drop

I_INH/LIMP= −10 µA;

ILEN = ILC = 1

-

0.7

1.2

-

1.0

2.0

4

V

I_INH/LIMP= −200 µA;

ILEN = ILC = 1

-

V

I_o(INH/LIMP)

I_L

output current

capability

V_INH/LIMP= 0.4 V;

ILEN = 1; ILC = 0

0.8

-

mA

µA

leakage current

V_INH/LIMP= 0 V to V_BAT14

ILEN = 0

;

-

5

Wake input; pin WAKE

V_th(WAKE)wake-up voltage

threshold

pull-up input current V_WAKE= 0 V

Serial peripheral interface inputs; pins SDI, SCK and SCS

2.0

3.3

-

5.2

V

I_WAKE(pu)

−25

−1.3

µA

V_IH(th)

HIGH-level input

threshold voltage

0.7 × V_V1

−0.3

-

V_V1+ 0.3

+0.3 × V_V1

400

V

V_IL(th)

LOW-level input

threshold voltage

-

V

R_pd(SCK)

pull-down resistor at V_SCK= 2 V; V_V1≥ 2 V

50

130

kΩ

pin SCK

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

44 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

Table 25. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R_pu(SCS)

pull-up resistor at

pin SCS

V_SCS= 1 V; V_V1≥ 2 V

50

130

400

kΩ

I_SDI

input leakage current V_SDI= 0 V to V_V1

at pin SDI

−5

-

+5

µA

Serial peripheral interface data output; pin SDO

I_OH

HIGH-level output

current

V_SCS= 0 V; V_O= V_V1− 0.4 V

−50

1.6

−5

-

−1.6

20

mA

µA

I_OL

LOW-level output

current

V_SCS= 0 V; V_O= 0.4 V

I_OL(off)

OFF-state output

leakage current

V_SCS= V_V1; V_O= 0 V to V_V1

+5

Reset output with clamping detection; pin RSTN

I_OH

HIGH-level output

current

V_RSTN= 0.7 × V_V1(nom)

−1000

-

−50

µA

mA

V

I_OL

LOW-level output

current

V_RSTN= 0.9 V

1

5

V_OL

LOW-level output

voltage

V_V1= 1.5 V to 5.5 V;

pull-up resistor to V1 ≥ 4 kΩ

0

0.2 × V_V1

V_V1+ 0.3

+0.3 × V_V1

V_IH(th)

V_IL(th)

HIGH-level input

threshold voltage

0.7 × V_V1

−0.3

V

LOW-level input

threshold voltage

V

Enable output; pin EN

I_OHHIGH-level output

V_OH= V_V1− 0.4 V

V_OL= 0.4 V

−20

1.6

0

-

−1.6

20

mA

V

current

I_OL

LOW-level output

current

V_OL

LOW-level output

voltage

I_OL= 20 µA; V_V1= 1.2 V

0.4

Interrupt output; pin INTN

I_OLLOW-level output

current

LIN transmit data input; pin TXDL

V_OL= 0.4 V

1.6

-

15

mA

V_IL

LOW level input

voltage

−0.3

-

+0.3 × V_V1

V_V1+ 0.3

25

V

V_IH

HIGH-level input

voltage

0.7 × V_V1

-

V

R_TXDL(pu)

TXDL pull-up

resistor

V_TXDL= 0 V

5

12

kΩ

LIN receive data output; pin RXDL

I_OH

HIGH-level output

current

V_RXDL= V_V1− 0.4 V

−50

-

−1.6

mA

I_OL

LOW-level output

current

V_RXDL= 0.4 V

1.6

20

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

45 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

Table 25. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.^[1]

Symbol

LIN-bus line; pin LIN

V_o(dom)LIN dominant output Active mode;

Parameter

Conditions

Min

Typ

Max

Unit

0

-

0.20 ×

V

voltage

V

_BAT42= 7 V to 18 V;

LDC = 0; t < t_{TXDL(dom)(dis)}

_TXDL= 0 V;

_BAT42-LIN= 500 Ω

V_BAT42

;

V

R

Active mode;

_BAT42= 7.6 V to 18 V;

LDC = 1; t < t_{TXDL(dom)(dis)}

_TXDL= 0 V; I_LIN= 40 mA

0.7

1.4

2.1

V

I_LIH

HIGH-level input

leakage current

V_LIN= V_BAT42; V_TXDL= V_V1

−10

0

+10

µA

V_BAT42= 8 V;

V

_LIN= 8 V to 18 V;

_TXDL= V_V1

I_LIL

LOW-level input

leakage current

V_BAT42= 12 V; V_LIN= 0 V;

_TXDL= V_V1

−100

-

µA

V

I_o(sc)

short-circuit output

current

Active mode;

27

40

60

mA

V_LIN= V_BAT42= 12 V;

V

_TXDL= 0 V; t < t_{TXDL(dom)(dis)}

;

LDC = 0

Active mode;

40

-

60

90

mA

V_LIN= V_BAT42= 18 V;

V_TXDL= 0 V; t < t_{TXDL(dom)(dis)}

LDC = 0

V_th(dom)

V_th(reces)

V_th(hyst)

V_th(cen)

receiver dominant

state

V_BAT42= 7 V to 27 V

-

0.4 ×

V_BAT42

V

receiver recessive

state

V_BAT42= 7 V to 27 V

0.6 ×

V_BAT42

-

V

receiver threshold

voltage hysteresis

0.05 ×

V_BAT42

0.175 ×

V_BAT42

V

receiver threshold

voltage center

0.475 ×

V_BAT42

0.500 ×

V_BAT42

0.525 ×

V_BAT42

V

[3]

C_i

I_L

input capacitance

leakage current

-

10

pF

V_LIN= 0 V to 18 V

V_BAT42= 0 V

−5

0

+5

µA

V_GND= V_BAT42= 12 V

−10

+10

LIN-bus termination resistor connection; pin RTLIN

V_RTLIN

RTLIN output

voltage

Active mode; I_RTLIN= −10 µA;

_BAT42= 7 V to 27 V

V_BAT42

1.0

−

V_BAT42

0.7

−

V_BAT42

0.2

−

V

Off-line mode;

_RTLIN= −10 µA;

_BAT42= 7 V to 27 V

V_BAT42

1.2

−

V_BAT42

1.0

−

-

I

V

∆V_RTLIN

RTLIN load

regulation

Active mode;

_RTLIN= −10 µA to −10 mA;

_BAT42= 7 V to 27 V

-

0.65

2

V

I

V

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

46 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

Table 25. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_RTLIN(pu)

RTLIN pull-up

current

Active mode;

−150

−60

−35

µA

V_RTLIN= V_LIN= 0 V;

t > t_{LIN(dom)(det)}

Off-line mode;

−150

−10

−60

−35

µA

V_RTLIN= V_LIN= 0 V;

t < t_{LIN(dom)(det)}

I_LL

LOW-level leakage

current

Off-line mode;

0

+10

V_RTLIN= V_LIN= 0 V;

t > t_{LIN(dom)(det)}

TEST input; pin TEST

V_th(TEST)input threshold

for entering Software

development mode;

T_j= 25 °C

1

5

8

V

voltage

for entering Forced normal

mode; T_j= 25 °C

2

10

4

13.5

8

V

R_(pd)TEST

pull-down resistor

between pin TEST and GND

kΩ

Temperature detection

T_j(warn)high junction

160

175

190

°C

temperature warning

level

[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient

temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (ﬁnal testing). Both pretesting

and ﬁnal testing use correlated test conditions to cover the speciﬁed temperature and power supply voltage range.

[2] V_V1(nom)is 3 V, 3.3 V or 5 V, depending on the SBC version.

[3] Not tested in production.

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

47 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

001aaf215

6

5

4

3

2

V

V1

(V)

type 5V0

I

=

V1

−100 µA

−50 mA

−120 mA

−250 mA

type 3V3

type 3V0

2

3

4

5

6

7

V

(V)

BAT14

a. T_j= 25 °C.

001aaf244

6

V

V1

(V)

type 5V0

5

4

3

2

I

=

V1

−100 µA

−50 mA

−120 mA

−250 mA

type 3V3

type 3V0

2

3

4

5

6

7

V

(V)

BAT14

b. T_j= 150 °C.

Fig 17. V1 output voltage (dropout) as a function of battery voltage

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

48 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

001aaf246

10

− I

T = +150 °C

j

I

BAT14

V1

(mA)

8

6

4

2

0

T = −40 °C

j

+25 °C

+150 °C

+25 °C

−40 °C

(1)

(2)

V

= 8 V

BAT14

5.5 V

0

−50

−100

−150

−200

−250

I

(mA)

V1

(1) Types 5V0, 3V3 and 3V0.

(2) Type 5V0 only.

a. At T_j= −40 °C, +25 °C and +150 °C.

001aaf247

5

I

− I

V1

BAT14

(mA)

4

3

2

1

0

(1)

(2)

V

= 9 V to 27 V

BAT14

5.5 V

0

−50

−100

−150

−200

−250

I

(mA)

V1

(1) Types 5V0, 3V3 and 3V0.

(2) Types 3V3 and 3V0.

b. At T_j= −40 °C to +150 °C.

Fig 18. V1 quiescent current as a function of output current

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001aaf245

6

4

2

0

type 5V0

V

V1

(V)

type 3V3

type 3V0

0

−40

−80

−120

−160

I

(mA)

V1

V_BAT14= 9 V to 27 V.

T_j= 25 °C to 125 °C.

Fig 19. V1 output voltage as a function of output current

001aaf248

160

PSRR

(dB)

V

= 14 V

14 V

BAT14

120

80

40

0

T = 25 °C

j

150 °C

5.5 V

25 °C to 150 °C

(1)

5.5 V

150 °C

2

3

1

10

f (Hz)

I_V1= −120 mA.

(1) Type 5V0 only.

Fig 20. V1 power supply ripple rejection as a function of frequency

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001aaf250

200

16

V

∆V

V1

(mV)

BAT14

(V)

V

BAT14

12

100

∆V

V1

8

0

4

−100

500

0

100

200

300

400

t (µs)

I_V1= −5 mA; C = 1 µF; ESR = 0.01 Ω; T_j= 25 °C.

a. Line transient response

001aaf251

−75

400

I

∆V

V1

(mA)

(mV)

−25

200

I

V1

∆V

V1

25

75

0

−200

500

0

100

200

300

400

t (µs)

V_BAT14= 14 V; C = 1 µF; ESR = 0.01 Ω; T_j= 25 °C.

b. Load transient response

Fig 21. V1 transient response as a function of time

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001aaf249

1

ESR

(Ω)

−1

−2

−3

10

stable operation area

unstable operation area

0

−40

−80

−120

I

(mA)

V1

Fig 22. V1 output stability related to ESR value of output capacitor

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I

= 30 mA

load

BAT42

BAT14

V1

SBC

100 µF/

0.1 Ω

100

nF

47 µF/

0.1 Ω

V

R

load

BAT

100

nF

GND

001aaf572

a. Test circuit

001aaf573

6

4

2

0

type 5V0

V

V1

(V)

V

= 8 V

BAT

type 3V3

type 3V0

V

= 5.5 V

BAT

V

= 12 V

BAT

0

0.4

0.8

1.2

1.6

2.0

t (µs)

b. Behavior at T_j= 25 °C

001aaf574

6

type 5V0

V

V1

(V)

V

= 8 V

BAT

4

2

0

type 3V3

type 3V0

V

= 5.5 V

BAT

V

= 12 V

BAT

0

0.4

0.8

1.2

1.6

2.0

t (µs)

c. Behavior at T_j= 85 °C

Fig 23. Switch-on behavior of V_V1

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10. Dynamic characteristics

Table 26. Dynamic characteristics

T_vj= −40 °C to +150 °C; V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure 24)^[2]

T_cyc

t_lead

clock cycle time

enable lead time

960

240

-

ns

clock is low when SPI select

falls

t_lag

enable lag time

clock is low when SPI select

rises

240

-

ns

t_SCKH

t_SCKL

t_su

clock HIGH time

480

80

-

ns

clock LOW time

-

input data setup time

input data hold time

output data valid time

SPI select HIGH time

-

t_h

400

-

t_DOV

pin SDO; C_L= 10 pF

400

-

t_SSH

480

LIN transceiver; pins LIN, TXDL and RXDL^[3]

[4]

[5]

[4]

[5]

δ1

δ2

δ3

δ4

duty cycle 1

duty cycle 2

duty cycle 3

duty cycle 4

V_{th(reces)(max)}= 0.744 × V_BAT42

_th(dom)(max)= 0.581 × V_BAT42

LSC = 0; t_bit= 50 µs;

;

0.396

-

V

;

V

_BAT42= 7 V to 18 V

_{th(reces)(min)}= 0.422 × V_BAT42

_th(dom)(min)= 0.284 × V_BAT42

V

;

-

0.581

;

LSC = 0; t_bit= 50 µs;

V

_BAT42= 7.6 V to 18 V

_{th(reces)(max)}= 0.778 × V_BAT42

_th(dom)(max)= 0.616 × V_BAT42

V

;

0.417

-

;

LSC = 1; t_bit= 96 µs;

V

_BAT42= 7 V to 18 V

_{th(reces)(min)}= 0.389 × V_BAT42

_th(dom)(min)= 0.251 × V_BAT42

V

;

-

0.590

;

LSC = 1; t_bit= 96 µs;

_BAT42= 7.6 V to 18 V

V

t_p(rx)

propagation delay of

receiver

C_RXDL= 20 pF

-

6

µs

t_p(rx)(sym)

t_BUS(LIN)

symmetry of receiver

propagation delay

rising edge with respect to

falling edge; C_RXDL= 20 pF

−2

30

+2

150

minimum dominant time for Off-line mode

wake-up of the

LIN-transceiver

t_{LIN(dom)(det)}

continuously dominant

clamped LIN-bus detection

time

Active mode; LIN = 0 V

40

-

160

2.2

ms

t_{LIN(dom)(rec)}

continuously dominant

clamped LIN-bus recovery

time

Active mode

0.8

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Table 26. Dynamic characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_{TXDL(dom)(dis)}TXDL permanent dominant Active mode; TXDL = 0 V

disable time

20

-

80

ms

Battery monitoring

t_BAT42(L)

BAT42 LOW time for

setting PWONS

5

-

20

µs

t_SENSE(L)

BAT42 LOW time for

setting BATFI

Power supply V1; pin V1

t_V1(CLT)V1 clamped LOW time

during ramp-up of V1

Power supply V3; pin V3

Start-up mode; V1 active

229

-

283

ms

t_w(CS)

cyclic sense period

V3C[1:0] = 10; see Figure 13

V3C[1:0] = 11; see Figure 13

V3C[1:0] = 10; see Figure 13

V3C[1:0] = 11; see Figure 13

14

-

18

ms

µs

28

36

t_on(CS)

cyclic sense on-time

345

423

µs

Wake-up input; pin WAKE

t_WU(ipf)input port ﬁlter time

V_BAT42= 5 V to 27 V

V_BAT42= 27 V to 52 V

5

-

120

250

390

µs

30

310

t_su(CS)

cyclic sense sample setup V3C[1:0] = 11 or 10;

time

see Figure 13

Watchdog

t_WD(ETP)

earliest watchdog trigger

point

programmed Nominal

Watchdog Period (NWP);

Normal mode

0.45 × NWP -

0.55 × NWP

1.1 × NWP

t_WD(LTP)

latest watchdog trigger

point

programmed nominal

watchdog period; Normal

mode, Standby mode and

Sleep mode

0.9 × NWP

-

t_WD(init)

watchdog initializing period watchdog time-out in Start-up

mode

229

1.3

-

283

1.7

ms

s

Fail-safe mode

t_ret

retention time

Fail-safe mode; wake-up

detected

1.5

Reset output; pin RSTN

t_RSTN(CHT)

clamped HIGH time,

pin RSTN

RSTN driven LOW internally

but RSTN pin remains HIGH

115

229

-

141

283

ms

t_RSTN(CLT)

clamped LOW time,

pin RSTN

RSTN driven HIGH internally

but RSTN pin remains LOW

t_RSTN(INT)

t_RSTNL

interrupt monitoring time

reset lengthening time

INTN = 0

229

0.9

-

283

1.1

ms

after internal or external reset

has been released; RLC = 0

after internal or external reset

has been released; RLC =1

18

-

22

ms

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Table 26. Dynamic characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Interrupt output; pin INTN

t_INTN

interrupt release

after SPI has read out the

Interrupt register

2

-

µs

Oscillator

f_osc

oscillator frequency

460.8

512

563.2

kHz

[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient

temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (ﬁnal testing). Both pretesting

and ﬁnal testing use correlated test conditions to cover the speciﬁed temperature and power supply voltage range.

[2] SPI timing is guaranteed for V_BAT42voltages down to 5 V. For V_BAT42voltages down to 4.5 V the guaranteed SPI timing values double, so

at these lower voltages a lower maximum SPI communication speed must be observed.

[3] t_bit= selected bit time, depends on LSC bit; 50 µs or 96 µs (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R₁/R₂/C₁):

1 kΩ/1 kΩ/10 nF; 1 kΩ/2 kΩ/6.8 nF; 1 kΩ/open/1 nF; see Figure 25 and Figure 26.

t_{bus(rec)(min)}

[4] δ1, δ3 =

[5] δ2, δ4 =

-------------------------------

2 × t_bit

t_{bus(rec)(max)}

--------------------------------

2 × t_bit

SCS

t

SSH

T

lead

lag

cyc

t

SCKL

SCKH

SCK

SDI

t

h

su

MSB

LSB

X

t

DOV

floating

SDO

X

MSB

LSB

001aaa405

Fig 24. SPI timing

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BAT42

SBC

GND

RXDL

TXDL

RTLIN

LIN

R1

R2

C1

20 pF

001aad179

Fig 25. Timing test circuit for LIN transceiver

t

bit

V

TXDL

t

bus(rec)(min)

bus(dom)(max)

V

BAT42

V

th(reces)(max)

th(dom)(max)

thresholds of

receiving node 1

LIN BUS

signal

V

th(reces)(min)

th(dom)(min)

thresholds of

receiving node 2

t

bus(rec)(max)

bus(dom)(min)

V

RXDL1

RXDL2

receiving

node 1

t

p(rx)r

p(rx)f

receiving

node 2

t

p(rx)f

p(rx)r

001aaa346

Fig 26. Timing diagram LIN transceiver

11. Test information

Immunity against automotive transients (malfunction and damage) in accordance with LIN

EMC Test Speciﬁcation / Version 1.0; August 1, 2004.

11.1 Quality information

This product has been qualiﬁed to the appropriate Automotive Electronics Council (AEC)

standard Q100 or Q101 and is suitable for use in automotive critical applications.

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12. Package outline

HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;

body width 6.1 mm; lead pitch 0.65 mm; exposed die pad

SOT549-1

E

A

D

X

c

H

v

M

A

y

exposed die pad side

E

D

h

Z

32

17

A

(A )

3

2

E

A

h

A

1

pin 1 index

θ

L

p

L

detail X

1

16

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

v

w

y

Z

θ

1

2

3

p

h

E

max.

8^o

0^o

0.15 0.95

0.05 0.85

0.30 0.20 11.1

0.19 0.09 10.9

5.1

4.9

6.2

6.0

3.6

3.4

8.3

7.9

0.75

0.50

0.78

0.48

mm

1.1

0.65

1

0.2

0.25

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-04-07

05-11-02

SOT549-1

MO-153

Fig 27. Package outline SOT549-1 (HTSSOP32)

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HTSSOP24: plastic thermal enhanced thin shrink small outline package; 24 leads;

body width 4.4 mm; lead pitch 0.65 mm; exposed die pad

SOT864-1

D

E

A

c

y

X

exposed die pad

M

H

E

v

A

D

H

Z

13

24

(A )

3

A

2

A

E

h

A

1

pin 1 index

θ

L

p

detail X

L

1

12

e

M

w

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

UNIT

A

1

A

2

A

3

b

c

D

E

e

H

E

L

p

v

w

y

Z

θ

p

h

max

°

0.15 0.95

0.05 0.80

0.30 0.2

0.19 0.1

7.9

7.7

4.3

4.1

4.5

4.3

3.3

3.1

6.6

6.2

0.75

0.50

0.5

0.2

8

0

mm

1.1

0.25

0.65

1

0.2 0.13 0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

04-09-23

05-12-06

SOT864-1

MO-153

Fig 28. Package outline SOT864-1 (HTSSOP24)

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13. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 29) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 27 and 28

Table 27. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 28. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 29.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 29. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

14. Revision history

Table 29. Revision history

Document ID

UJA1069_2

Release date

20070305

Data sheet status

Change notice

Supersedes

Preliminary data sheet

-

UJA1069_1

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 6: symbols corrected; replaced symbol t_RSTN(ext)with t_RSTN(CLT)and with t_RSTN(CHT)

;

replaced t_INTNHwith t_INTN

• Table 11: table note added

• Table 25: updated pin SDO conditions and pin LIN, parameter I_LILvalue

• Figure 24 and Figure 26 updated

• Soldering information updated

• Added Test information, see Section 11 “Test information”

• Added Figure 23

• Added a second condition row to I_LIHin Table 25

• Changed in Table note [2] of Table 26 “V_BAT14” to “V_BAT42

”

UJA1069_1

20051222 Objective data sheet

-

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

62 of 64

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15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of a NXP Semiconductors product can reasonably be expected to

15.2 Deﬁnitions

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

63 of 64

UJA1069

NXP Semiconductors

LIN fail-safe system basis chip

17. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

6.7.6.3

6.8

6.9

6.10

6.11

LIN recessive clamping . . . . . . . . . . . . . . . . . 21

Inhibit and limp-home output . . . . . . . . . . . . . 21

Wake-up input . . . . . . . . . . . . . . . . . . . . . . . . 22

Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 23

Temperature protection . . . . . . . . . . . . . . . . . 23

SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 24

SPI register mapping . . . . . . . . . . . . . . . . . . . 25

Register overview. . . . . . . . . . . . . . . . . . . . . . 25

Mode register . . . . . . . . . . . . . . . . . . . . . . . . . 25

System Status register. . . . . . . . . . . . . . . . . . 28

System Diagnosis register . . . . . . . . . . . . . . . 29

Interrupt Enable register and Interrupt

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2

Power management . . . . . . . . . . . . . . . . . . . . . 2

Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3

2.1

2.2

2.3

2.4

6.12

6.12.1

6.12.2

6.12.3

6.12.4

6.12.5

6.12.6

3

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

Enable Feedback register . . . . . . . . . . . . . . . 30

Interrupt register. . . . . . . . . . . . . . . . . . . . . . . 31

System Conﬁguration register and System

Conﬁguration Feedback register . . . . . . . . . . 32

Physical Layer Control register and Physical

Layer Control Feedback register . . . . . . . . . . 33

6

6.1

6.2

Functional description . . . . . . . . . . . . . . . . . . . 7

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Fail-safe system controller . . . . . . . . . . . . . . . . 7

Start-up mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9

Restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . 9

Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 12

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Watchdog start-up behavior . . . . . . . . . . . . . . 13

Watchdog window behavior . . . . . . . . . . . . . . 13

Watchdog time-out behavior. . . . . . . . . . . . . . 14

Watchdog OFF behavior. . . . . . . . . . . . . . . . . 14

System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 15

RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 17

BAT14, BAT42 and SYSINH . . . . . . . . . . . . . . 17

SYSINH output . . . . . . . . . . . . . . . . . . . . . . . . 17

SENSE input. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . 17

Switched battery output V3. . . . . . . . . . . . . . . 18

LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 18

Mode control. . . . . . . . . . . . . . . . . . . . . . . . . . 18

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Off-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 19

LIN wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Termination control . . . . . . . . . . . . . . . . . . . . . 20

LIN slope control. . . . . . . . . . . . . . . . . . . . . . . 20

LIN driver capability . . . . . . . . . . . . . . . . . . . . 21

Bus and TXDL failure detection . . . . . . . . . . . 21

TXDL dominant clamping . . . . . . . . . . . . . . . . 21

LIN dominant clamping. . . . . . . . . . . . . . . . . . 21

6.12.7

6.12.8

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.3

6.12.9

6.12.10 Special Mode register and Special Mode

Feedback register. . . . . . . . . . . . . . . . . . . . . . 34

6.12.11 General Purpose registers and General

Purpose Feedback registers . . . . . . . . . . . . . 35

6.12.12 Register conﬁgurations at reset . . . . . . . . . . . 36

6.13

6.13.1

6.13.2

Test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Software development mode . . . . . . . . . . . . . 38

Forced normal mode . . . . . . . . . . . . . . . . . . . 39

6.4

6.4.1

6.4.2

6.4.3

6.4.4

6.5

6.5.1

6.5.2

6.6

6.6.1

6.6.1.1

6.6.2

6.6.3

6.6.4

6.7

6.7.1

6.7.1.1

6.7.1.2

6.7.2

6.7.3

6.7.4

6.7.5

6.7.6

6.7.6.1

6.7.6.2

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 40

Thermal characteristics . . . . . . . . . . . . . . . . . 41

Static characteristics . . . . . . . . . . . . . . . . . . . 42

Dynamic characteristics. . . . . . . . . . . . . . . . . 54

Test information. . . . . . . . . . . . . . . . . . . . . . . . 57

Quality information . . . . . . . . . . . . . . . . . . . . . 57

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 58

8

9

10

11

11.1

12

13

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Introduction to soldering. . . . . . . . . . . . . . . . . 60

Wave and reﬂow soldering . . . . . . . . . . . . . . . 60

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 60

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 61

13.1

13.2

13.3

13.4

14

Revision history . . . . . . . . . . . . . . . . . . . . . . . 62

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 63

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 63

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 63

15.1

15.2

15.3

15.4

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 63

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 5 March 2007

Document identifier: UJA1069_2


型号：	UJA1069TW
厂家：	NXP
描述：	LIN fail-safe system basis chip LIN故障安全系统基础芯片
文件：	总64页 (文件大小：301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UJA1069TW [NXP]

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