UJA1169ATK/3_技术文档

UJA1169A

Mini high-speed CAN system basis chip

Rev. 1 — 12 May 2020

Product data sheet

1. General description

The UJA1169A is a mini high-speed CAN System Basis Chip (SBC) containing an

ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant HS-CAN transceiver

including CAN FD up to 5 Mbit/s and an integrated 5 V or 3.3 V 250 mA scalable supply

(V1) for a microcontroller and/or other loads. It also features a watchdog and a Serial

Peripheral Interface (SPI). The UJA1169A can be operated in very low-current Standby

and Sleep modes with bus and local wake-up capability. The microcontroller supply is

switched off in Sleep mode.

The UJA1169A comes in six variants. The UJA1169ATK, UJA1169ATK/F, UJA1169ATK/X

and UJA1169ATK/X/F contain a 5 V regulator (V1). V1 is a 3.3 V regulator in the

UJA1169ATK/3 and the UJA1169ATK/F/3.

The UJA1169ATK, UJA1169ATK/F, UJA1169ATK/3 and UJA1169ATK/F/3 variants

feature a second on-board 5 V regulator (V2) that supplies the internal CAN transceiver

and can also be used to supply additional on-board hardware.

The UJA1169ATK/X and UJA1169ATK/X/F are equipped with a 5 V supply (VEXT) for

off-board components. VEXT is short-circuit proof to the battery, ground and negative

voltages. The integrated CAN transceiver is supplied internally via V1, in parallel with the

microcontroller.

The UJA1169Axx/F variants support ISO 11898-2:2016 compliant CAN partial networking

with a selective wake-up function incorporating CAN FD-passive. CAN FD-passive is a

feature that allows CAN FD bus traffic to be ignored in Sleep/Standby mode. CAN

FD-passive partial networking is the perfect fit for networks that support both CAN FD and

classic CAN communications. It allows normal CAN controllers that do not need to

communicate CAN FD messages to remain in partial networking Sleep/Standby mode

during CAN FD communication without generating bus errors.

The UJA1169A implements the standard CAN physical layer as defined in

ISO 11898-2:2016. This implementation enables reliable communication in the CAN FD

fast phase at data rates up to 5 Mbit/s.

A dedicated LIMP output pin is provided to flag system failures.

A number of configuration settings are stored in non-volatile memory. This arrangement

makes it possible to configure the power-on and limp-home behavior of the UJA1169A to

meet the requirements of different applications.

UJA1169A

NXP Semiconductors

Mini high-speed CAN SBC with optional partial networking

2. Features and benefits

2.1 General

 ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant high-speed CAN

transceiver supporting CAN FD active communication up to 5 Mbit/s in the CAN FD

data field (all six variants)

 Autonomous bus biasing according to ISO 11898-2:2016

 Scalable 5 V or 3.3 V 250 mA low-drop voltage regulator for 5 V/3.3 V microcontroller

supply (V1) based on external PNP transistor concept for thermal scaling

 CAN-bus connections are truly floating when power to pin BAT is off

 No ‘false’ wake-ups due to CAN FD traffic (in variants supporting partial networking)

 Hardware and software compatible with the UJA1169 product family

2.2 Designed for automotive applications

 8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model

(HBM) on the CAN-bus pins

 6 kV ESD protection according to IEC TS 62228 on pins BAT, WAKE, VEXT and the

CAN-bus pins

 CAN-bus pins short-circuit proof to 58 V

 Battery and CAN-bus pins protected against automotive transients according to

ISO 7637-3

 Very low quiescent current in Standby and Sleep modes with full wake-up capability

 Leadless HVSON20 package (3.5 mm  5.5 mm) with improved Automated Optical

Inspection (AOI) capability and low thermal resistance

 Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)

compliant)

2.3 Low-drop voltage regulator for 5 V/3.3 V microcontroller supply (V1)

 5 V/3.3 V nominal output; 2 % accuracy

 250 mA output current capability

 Thermal management via optional external PNP

 Current limiting above 250 mA

 Support for microcontroller RAM retention down to a battery voltage of 2 V (5 V

variants only)

 Undervoltage reset with selectable detection thresholds of 60 %, 70 %, 80 % or 90 %

of output voltage, configurable in non-volatile memory (5 V variants only)

 Excellent transient response with a small ceramic output capacitor

 Output is short-circuit proof to GND

 Turned off in Sleep mode

2.4 On-board CAN supply (V2; UJA1169ATK, UJA1169ATK/F,

UJA1169ATK/3 and UJA1169ATK/F/3 only)

 5 V nominal output; 2 % accuracy

 100 mA output current capability

UJA1169A

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Product data sheet

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UJA1169A

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Mini high-speed CAN SBC with optional partial networking

 Current limiting above 100 mA

 Excellent transient response with a small ceramic output capacitor

 Output is short-circuit proof to GND

 User-defined on/off behavior via SPI

2.5 Off-board sensor supply (VEXT; UJA1169ATK/X and UJA1169ATK/X/F

only)

 5 V nominal output; 2 % accuracy

 100 mA output current capability

 Current limiting above 100 mA

 Excellent transient response with a small ceramic output load capacitor

 Output is short-circuit proof to BAT, GND and negative voltages down to 18 V

 User-defined on/off behavior via SPI

2.6 Power Management

 Standby mode featuring very low supply current; voltage V1 remains active to maintain

the supply to the microcontroller

 Sleep mode featuring very low supply current with voltage V1 switched off

 Remote wake-up capability via standard CAN wake-up pattern or ISO 11898-2:2016

compliant selective wake-up frame detection including CAN FD passive support (/F

versions only)

 Bit rates of 50 kbit/s, 100 kbit/s, 125 kbit/s, 250 kbit/s, 500 kbit/s and 1 Mbit/s

supported during selective wake-up

 Local wake-up via the WAKE pin

 Wake-up source recognition

2.7 System control and diagnostic features

 Mode control via the Serial Peripheral Interface (SPI)

 Overtemperature warning and shutdown

 Watchdog with Window, Timeout and Autonomous modes and microcontroller-

independent clock source

 Optional cyclic wake-up in watchdog Timeout mode

 Watchdog automatically re-enabled when wake-up event captured

 Watchdog period selectable between 8 ms and 4 s supporting remote flash

programming via the CAN bus

 LIMP output pin with configurable activation threshold

 Watchdog failure, RSTN clamping and overtemperature events trigger the dedicated

LIMP output signal

 16-, 24- and 32-bit SPI for configuration, control and diagnosis

 Bidirectional reset pin with variable power-on reset length; configurable in non-volatile

memory to support a number of different microcontrollers

 Customer configuration of selected functions via non-volatile memory

 Dedicated modes for software development and end-of-line flashing

UJA1169A

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Product data sheet

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UJA1169A

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Mini high-speed CAN SBC with optional partial networking

3. Product family overview

Table 1.

Feature overview of UJA1169A SBC family

Modes

Supplies

Host

Additional Features

Interface

Device

UJA1169ATK

●

UJA1169ATK/X

UJA1169ATK/F

UJA1169ATK/X/F

UJA1169ATK/3

UJA1169ATK/F/3

●

4. Ordering information

Table 2.

Ordering information

Type number^[1]

Package

Name

Description

Version

UJA1169ATK

HVSON20

plastic thermal enhanced extremely thin quad flat package; no SOT1360-1

leads; 20 terminals; body 3.5  5.5  0.85 mm

UJA1169ATK/X

UJA1169ATK/F^[2]

UJA1169ATK/X/F^[2]

UJA1169ATK/3

UJA1169ATK/F/3^[2]

[1] UJA1169ATK, UJA1169ATK/F, UJA1169ATK/3 and UJA1169ATK/F/3 with dedicated CAN supply (V2); UJA1169ATK/X and

UJA1169ATK/X/F with protected off-board sensor supply (VEXT).

[2] UJA1169ATK/F, UJA1169ATK/F/3 and UJA1169ATK/X/F with partial networking according to ISO 11898-2:2016 incorporating CAN FD

passive support.

UJA1169A

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Product data sheet

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5. Block diagram

VEXCTRL

15

VEXCC

6

UJA1169A

5

8

V1

14

5 V/3.3 V MICROCONTROLLER SUPPLY (V1)

AND PNP CONTROLLER

BAT

RSTN

11

13

WATCHDOG

LIMP

/X versions

only

5 V REGULATOR/

5 V SENSOR SUPPLY (/X versions)

V2/VEXT

non-/X versions

only

7

2

18

17

HS-CAN TRANSCEIVER

RXD

TXD

CANH

CANL

CAN FD active

PARTIAL NETWORKING

CAN FD passive

10

3

/F versions

only

SCK

SDI

SPI AND SYSTEM CONTROLLER

9

SDO

SCSN

20

12

WAKE

WAKE-UP

1, 4, 16, 19

GND

aaa-033689

The internal CAN transceiver is supplied from V1 in the UJA1169ATK/X and UJA1169ATK/X/F and

from V2 in the other variants.

Fig 1. Block diagram of UJA1169A

UJA1169A

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Product data sheet

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6. Pinning information

6.1 Pinning

GND

TXD

1

2

3

4

5

6

7

8

9

20 SCSN

19 GND

SDI

18 CANH

17 CANL

16 GND

GND

V1

UJA1169A

VEXCC

RXD

15 VEXCTRL

14 BAT

(1)

RSTN

SDO

13 V2/VEXT

12 WAKE

11 LIMP

SCK 10

aaa-033690

(1) V2 in the UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3; VEXT in the

UJA1169ATK/X and UJA1169ATK/X/F

Fig 2. Pin configuration diagram

6.2 Pin description

Table 3.

Symbol

Pin description

Pin Description

GND

TXD

SDI

1^[1]

ground

2

transmit data input

SPI data input

3

GND

V1

4^[1]

ground

5

5 V/3.3 V microcontroller supply voltage

VEXCC

6

current measurement for external PNP transistor; this pin is connected to

the collector of the external PNP transistor

RXD

RSTN

SDO

SCK

LIMP

WAKE

V2

7

receive data output; reflects data on bus lines and wake-up conditions

reset input/output; active-LOW

SPI data output

8

9

10

11

12

13

SPI clock input

limp home output, open-drain; active-LOW

local wake-up input

5 V CAN supply (UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and

UJA1169ATK/F/3 only)

VEXT

13

14

15

5 V sensor supply (UJA1169ATK/X and UJA1169ATK/X/F only)

battery supply voltage

BAT

VEXCTRL

control pin of the external PNP transistor; this pin is connected to the

base of the external PNP transistor

GND

16^[1]

17

ground

CANL

LOW-level CAN-bus line

UJA1169A

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Table 3.

Pin description …continued

Symbol

CANH

GND

18

19^[1]

Description

HIGH-level CAN-bus line

ground

SCSN

20

SPI chip select input; active-LOW

[1] The exposed die pad at the bottom of the package allows for better heat dissipation and grounding from the

SBC via the printed circuit board. For enhanced thermal and electrical performance, connect the exposed

die pad to GND.

7. Functional description

7.1 System controller

The system controller manages register configuration and controls the internal functions

of the UJA1169A. Detailed device status information is collected and made available to

the microcontroller.

7.1.1 Operating modes

The system controller contains a state machine that supports seven operating modes:

Normal, Standby, Sleep, Reset, Forced Normal, Overtemp and Off. The state transitions

are illustrated in Figure 3.

7.1.1.1 Normal mode

Normal mode is the active operating mode. In this mode, all the hardware on the device is

available and can be activated (see Table 4). Voltage regulator V1 is enabled to supply the

microcontroller.

The CAN interface can be configured to be active and thus to support normal CAN

communication. Depending on the SPI register settings, the watchdog may be running in

Window or Timeout mode and the V2/VEXT output may be active.

Normal mode can be requested from Standby mode via an SPI command (MC = 111).

7.1.1.2 Standby mode

Standby mode is the first-level power-saving mode of the UJA1169A, offering reduced

current consumption. The transceiver is unable to transmit or receive data in Standby

mode. The SPI remains enabled and V1 is still active; the watchdog is active (in Timeout

mode) if enabled. The behavior of V2/VEXT is determined by the SPI setting.

If remote CAN wake-up is enabled (CWE = 1; see Table 33), the receiver monitors bus

activity for a wake-up request. The bus pins are biased to GND (via R_i(cm)) when the bus is

inactive for t > t_to(silence)and at approximately 2.5 V when there is activity on the bus

(autonomous biasing). CAN wake-up can occur via a standard wake-up pattern or via a

selective wake-up frame (selective wake-up is enabled when CPNC = PNCOK = 1,

otherwise standard wake-up is enabled; see Table 16).

Pin RXD is forced LOW when any enabled wake-up event is detected. This event can be

either a regular wake-up (via the CAN bus or pin WAKE) or a diagnostic wake-up such as

an overtemperature event (see Section 7.11).

UJA1169A

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Product data sheet

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NORMAL

MC = Sleep &

no wake-up pending &

wake-up enabled &

SLPC = 0

MC = Normal

MC = Standby

SLEEP

STANDBY

MC = Sleep &

no wake-up pending &

wake-up enabled &

SLPC = 0

from Normal or Standby

MC = Sleep &

(wake-up pending OR

wake-up disabled OR

SLPC = 1)

any reset event

RSTN = HIGH &

FNMC = 0

V1 undervoltage

wake-up event

no overtemperature

RESET

RSTN = HIGH &

FNMC = 1

OVERTEMP

power-on

OFF

any reset event

FORCED

NORMAL

V

undervoltage

BAT

overtemperature event

from any mode

from any mode except Off & Sleep

MTP programming completed or

MTP factory presets restored

aaa-016003

Fig 3. UJA1169A system controller state diagram

The UJA1169A switches to Standby mode via Reset mode:

• from Off mode if the battery voltage rises above the power-on detection threshold

(V_th(det)pon

)

• from Overtemp mode if the chip temperature falls below the overtemperature

protection release threshold, T_th(rel)otp

UJA1169A

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• from Sleep mode on the occurrence of a regular or diagnostic wake-up event

Standby mode can also be selected from Normal mode via an SPI command (MC = 100).

7.1.1.3 Sleep mode

Sleep mode is the second-level power-saving mode of the UJA1169A. The difference

between Sleep and Standby modes is that V1 is off in Sleep mode and temperature

protection is inactive.

Any enabled regular wake-up via CAN or WAKE or any diagnostic wake-up event will

cause the UJA1169A to wake up from Sleep mode. The behavior of V2/VEXT is

determined by the SPI settings. The SPI is disabled. Autonomous bus biasing is active.

See Table 7 for watchdog behavior in Sleep mode.

Sleep mode can be requested from Normal or Standby mode via an SPI command

(MC = 001). The UJA1169A will switch to Sleep mode on receipt of this command,

provided there are no pending wake-up events and at least one regular wake-up source is

enabled. Any attempt to enter Sleep mode while one of these conditions has not been met

will cause the UJA1169A to switch to Reset mode and set the reset source status bits

(RSS) to 10100 (‘illegal Sleep mode command received’; see Table 6).

Since V1 is off in Sleep mode, the only way the SBC can exit Sleep mode is via a wake-up

event (see Section 7.11).

Sleep mode can be permanently disabled in applications where, for safety reasons, the

supply voltage to the host controller must never be cut off. Sleep mode is permanently

disabled by setting the Sleep control bit (SLPC) in the SBC configuration register (see

Table 9) to 1. This register is located in the non-volatile memory area of the device (see

Section 7.12). When SLPC = 1, a Sleep mode SPI command (MC = 001) triggers an SPI

failure event instead of a transition to Sleep mode.

7.1.1.4 Reset mode

Reset mode is the reset execution state of the SBC. This mode ensures that pin RSTN is

pulled down for a defined time to allow the microcontroller to start up in a controlled

manner.

The transceiver is unable to transmit or receive data in Reset mode. The behavior of

V2/VEXT is determined by the settings of bits V2C/VEXTC and V2SUC/VEXTSUC (see

Section 7.6.3). The SPI is inactive; the watchdog is disabled; V1 and overtemperature

detection are active.

The UJA1169A switches to Reset mode from any mode in response to a reset event (see

Table 6 for a list of reset sources).

The UJA1169A exits Reset mode:

• and switches to Standby mode if pin RSTN is released HIGH

• and switches to Forced Normal mode if bit FNMC = 1

• if the SBC is forced into Off or Overtemp mode

If a V1 undervoltage event forced the transition to Reset mode, the UJA1169A will remain

in Reset mode until the voltage on pin V1 has recovered.

UJA1169A

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7.1.1.5 Off mode

The UJA1169A switches to Off mode when the battery is first connected or from any mode

when V_BAT< V_th(det)poff. Only power-on detection is enabled; all other modules are

inactive. The UJA1169A starts to boot up when the battery voltage rises above the

power-on detection threshold V_th(det)pon(triggering an initialization process) and switches

to Reset mode after t_startup. In Off mode, the CAN pins disengage from the bus (zero load;

high-ohmic).

7.1.1.6 Overtemp mode

Overtemp mode is provided to prevent the UJA1169A being damaged by excessive

temperatures. The UJA1169A switches immediately to Overtemp mode from any mode

(other than Off mode or Sleep mode) when the global chip temperature rises above the

overtemperature protection activation threshold, T_th(act)otp

.

To help prevent the loss of data due to overheating, the UJA1169A issues a warning when

the IC temperature rises above the overtemperature warning threshold (T_th(warn)otp). When

this threshold is reached, status bit OTWS (see Table 6) is set and an overtemperature

warning event is captured (OTW = 1; see Table 27), if enabled (OTWE = 1; see Table 31).

In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are

in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still

be signaled by a LOW level on pin RXD, which will persist after the overtemperature event

has been cleared. V1 is off and pin RSTN is driven LOW. In the UJA1169ATK/X and

UJA1169ATK/X/F, VEXT is off. In the UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and

UJA1169ATK/F/3, V2 is turned off when the SBC enters Overtemp mode.

The UJA1169A exits Overtemp mode:

• and switches to Reset mode if the chip temperature falls below the overtemperature

protection release threshold, T_th(rel)otp

• if the device is forced to switch to Off mode (V_BAT< V_th(det)poff

7.1.1.7 Forced Normal mode

)

Forced Normal mode simplifies SBC testing and is useful for initial prototyping, as well as

first flashing of the microcontroller. The watchdog is disabled in Forced Normal mode. The

low-drop voltage regulator (V1) is active, VEXT/V2 is enabled and the CAN transceiver is

active.

Bit FNMC is factory preset to 1, so the UJA1169A initially boots up in Forced Normal

mode (see Table 9). This feature allows a newly installed device to be run in Normal mode

without a watchdog. So the microcontroller can, optionally, be flashed via the CAN bus

without having to consider the integrated watchdog.

The register containing bit FNMC (address 74h) is stored in non-volatile memory. So once

bit FNMC is programmed to 0, the SBC will no longer boot up in Forced Normal mode,

allowing the watchdog to be enabled.

Even in Forced Normal mode, a reset event (e.g. an external reset or a V1 undervoltage)

will trigger a transition to Reset mode with normal Reset mode behavior (except that the

CAN transmitter remains active if there is no V_CANundervoltage). When the UJA1169A

exits Reset mode, however, it returns to Forced Normal mode instead of switching to

Standby mode.

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In Forced Normal mode, only the Main status register, the Watchdog status register, the

Identification register, the MTPNV status register and registers stored in non-volatile

memory can be read. The non-volatile memory area is fully accessible for writing as long

as the UJA1169A is in the factory preset state (for details see Section 7.12).

7.1.1.8 Hardware characterization for the UJA1169A operating modes

Table 4.

Block

Hardware characterization by functional block

Operating mode

Off

off^[1]

Forced Normal Standby

Normal

Sleep

Reset

Overtemp

off

V1

on

off

on

[2]

VEXT/V2

RSTN

SPI

off

on

VEXT/V2 off

LOW

disabled active^[3]

HIGH

active

HIGH

active

LOW

disabled

off

Watchdog

off

determined by determined by bits

bits WMC (see WMC

Table 8)^[4]

determined by off

bits WMC^[4]

CAN

RXD

off

Active

Offline

Active/ Offline/

Listen-only

(determined by bits

CMC; see Table 16)

Offline

off

V1 level CAN bit stream V1 level/LOW CAN bit stream if

V1 level/LOW V1

V1

if wake-up

detected

CMC = 01/10/11;

otherwise same as

Standby/Sleep

if wake-up

detected

level/LOW level/LOW if

if wake-up wake-up

detected

[1] When the SBC switches from Reset, Standby or Normal mode to Off mode in the 5 V variants, V1 behaves as a current source during

power down while V_BATis falling from V_th(det)pofdown to 2 V (RAM retention feature; see Section 7.6.1).

[2] Determined by bits V2C/VEXTC and V2SUC/VEXTSUC (see Table 13)

[3] Limited register access: Main status register, Watchdog status register, Identification register and non-volatile memory only.

[4] Window mode is only active in Normal mode.

7.1.2 System control registers

7.1.2.1 Mode control register

The operating mode is selected via bits MC in the Mode control register. The Mode control

register is accessed via SPI address 01h (see Section 7.16).

Table 5.

Mode control register (address 01h)

Bit

7:3

2:0

Symbol Access Value Description

reserved

MC

R

-

R/W

mode control:

Sleep mode

001

100

111

Standby mode

Normal mode

7.1.2.2 Main status register

The Main status register can be accessed to monitor the status of the overtemperature

warning flag and to determine whether the UJA1169A has entered Normal mode after

initial power-up. It also indicates the source of the most recent reset event.

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Table 6.

Main status register (address 03h)

Bit

7

Symbol

reserved

OTWS

Access Value Description

R

-

6

overtemperature warning status:

0

1

IC temperature below overtemperature warning threshold

IC temperature above overtemperature warning threshold

Normal mode status:

5

NMS

RSS

R

0

1

UJA1169A has entered Normal mode (after power-up)

UJA1169A has powered up but has not yet switched to

Normal mode

4:0

reset source status:

00000

00001

00100

01100

01101

01110

01111

left Off mode (power-on)

CAN wake-up in Sleep mode

wake-up via WAKE pin in Sleep mode

watchdog overflow in Sleep mode (Timeout mode)

diagnostic wake-up in Sleep mode

watchdog triggered too early (Window mode)

watchdog overflow (Window mode or Timeout mode with

WDF = 1)

10000

10001

10010

10011

10100

10110

illegal watchdog mode control access

RSTN pulled down externally

left Overtemp mode

V1 undervoltage

illegal Sleep mode command received

wake-up from Sleep mode due to a frame detect error

7.2 Watchdog

7.2.1 Watchdog overview

The UJA1169A contains a watchdog that supports three operating modes: Window,

Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a

watchdog trigger event within a defined watchdog window triggers and resets the

watchdog timer. In Timeout mode, the watchdog runs continuously and can be triggered

and reset at any time within the watchdog period by a watchdog trigger. Watchdog

time-out mode can also be used for cyclic wake-up of the microcontroller. In Autonomous

mode, the watchdog can be off or in Timeout mode, depending on the selected SBC mode

(see Section 7.2.5).

The watchdog mode is selected via bits WMC in the Watchdog control register (Table 8).

The SBC must be in Standby mode when the watchdog mode and/or period is changed. If

Window mode is selected (WMC = 100), the watchdog remains in (or switches to)

Timeout mode until the SBC enters Normal mode. Any attempt to change the watchdog

operating mode (via WMC) or period (via NWP) while the SBC is in Normal mode causes

the UJA1169A to switch to Reset mode and the reset source status bits (RSS) to be set to

10000 (‘illegal watchdog mode control access’; see Table 6); an SPI failure (SPIF)

event is triggered, if enabled.

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Eight watchdog periods are supported, from 8 ms to 4096 ms. The watchdog period is

programmed via bits NWP. The selected period is valid for both Window and Timeout

modes. The default watchdog period is 128 ms.

A watchdog trigger event resets the watchdog timer. A watchdog trigger event is any valid

write access to the Watchdog control register. If the watchdog mode or the watchdog

period have changed as a result of the write access, the new values are valid immediately.

Table 7.

Watchdog configuration

Operating/watchdog mode

FNMC (Forced Normal mode control)

0

x

0

1

SDMC (Software Development mode control) x

x

WMC (watchdog mode control)

100 (Window) 010

(Timeout)

001

(Autonomous)

001

(Autonomous)

n.a.

Normal mode

Window

Timeout

off

Timeout

off

Timeout

off

Standby mode (RXD HIGH)^[1]

Standby mode (RXD LOW)^[1]

Sleep mode

Timeout

off

Other modes

off

[1] RXD LOW signals a pending wake-up.

7.2.1.1 Watchdog control register

Table 8. Watchdog control register (address 00h)

Bit

Symbol

Access Value

Description

7:5

WMC

R/W

watchdog mode control:

Autonomous mode

Timeout mode

001^[1]

010^[2]

100^[3]

Window mode

4

reserved

NWP

R

-

3:0

R/W

nominal watchdog period:

1000

0001

0010

1011

0100^[2]

1101

1110

0111

8 ms

16 ms

32 ms

64 ms

128 ms

256 ms

1024 ms

4096 ms

[1] Default value if SDMC = 1 (see Section 7.2.2)

[2] Default value.

[3] Selected in Standby mode but only activated when the SBC switches to Normal mode.

The watchdog is a valuable safety mechanism, so it is critical that it is configured correctly.

Two features are provided to prevent watchdog parameters being changed by mistake:

• redundant coding of configuration bits WMC and NWP

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• reconfiguration protection in Normal mode

Redundant codes associated with control bits WMC and NWP ensure that a single bit

error cannot cause the watchdog to be configured incorrectly (at least 2 bits must be

changed to reconfigure WMC or NWP). If an attempt is made to write an invalid code to

WMC or NWP (e.g. 011 or 1001 respectively), the SPI operation is abandoned and an SPI

failure event is captured, if enabled (see Section 7.11).

7.2.1.2 SBC configuration control register

Two operating modes have a major impact on the operation of the watchdog: Forced

Normal mode and Software Development mode (Software Development mode is provided

for test and development purposes only and is not a dedicated SBC operating mode; the

UJA1169A can be in any functional operating mode with Software Development mode

enabled; see Section 7.2.2). These modes are enabled and disabled via bits FNMC and

SDMC respectively in the SBC configuration control register (see Table 9). Note that this

register is located in the non-volatile memory area. The watchdog is disabled in Forced

Normal mode (FNM). In Software Development mode (SDM), the watchdog can be

disabled or activated for test and software debugging purposes.

Table 9.

SBC configuration control register (address 74h)

Bit Symbol

Access Value

Description

7:6 reserved

R

-

[1]

5:4 V1RTSUC R/W

V1 reset threshold (defined by bit V1RTC) at start-up:

00^[2]

01

V1 undervoltage detection at 90 % of nominal value at

start-up (V1RTC = 00)

V1 undervoltage detection at 80 % of nominal value at

start-up (V1RTC = 01)

10

V1 undervoltage detection at 70 % of nominal value at

start-up (V1RTC = 10)

11

V1 undervoltage detection at 60 % of nominal value at

start-up (V1RTC = 11)

[3]

3

2

FNMC

SDMC

R/W

Forced Normal mode control:

0

1^[2]

Forced Normal mode disabled

Forced Normal mode enabled

Software Development mode control:

Software Development mode disabled

Software Development mode enabled

0^[2]

1

0

reserved

SLPC

R

-

R/W

Sleep control:

0^[2]

1

Sleep mode commands accepted

Sleep mode commands ignored

[1] The V1 undervoltage threshold is fixed at 90 % in the UJA1169ATK/3 and UJA1169ATK/F/3, regardless of

the setting of bit V1RTSUC.

[2] Factory preset value.

[3] FNMC settings overrule SDMC.

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7.2.1.3 Watchdog status register

Information on the status of the watchdog is available from the Watchdog status register

(Table 10). This register also indicates whether Forced Normal and Software

Development modes are active.

Table 10. Watchdog status register (address 05h)

Bit

7:4

3

Symbol

reserved

FNMS

Access Value Description

R

-

Forced Normal mode status:

0

1

SBC is not in Forced Normal mode

SBC is in Forced Normal mode

Software Development mode status:

SBC is not in Software Development mode

SBC is in Software Development mode

watchdog status:

2

SDMS

WDS

R

0

1

1:0

00

01

10

11

watchdog is off

watchdog is in first half of the nominal period

watchdog is in second half of the nominal period

reserved

7.2.2 Software Development mode

Software Development mode is provided to simplify the software design process. When

Software Development mode is enabled, the watchdog starts up in Autonomous mode

(WMC = 001) and is inactive after a system reset, overriding the default value (see

Table 8). The watchdog is always off in Autonomous mode if Software Development mode

is enabled (SDMC = 1; see Table 7).

Software can be run without a watchdog in Software Development mode. However, it is

possible to activate and deactivate the watchdog for test purposes by selecting Window or

Timeout mode via bits WMC while the SBC is in Standby mode (note that Window mode

will only be activated when the SBC switches to Normal mode). Software Development

mode is activated via bit SDMC in non-volatile memory (see Table 9).

7.2.3 Watchdog behavior in Window mode

The watchdog runs continuously in Window mode. The watchdog will be in Window mode

if WMC = 100 and the UJA1169A is in Normal mode.

In Window mode, the watchdog can only be triggered during the second half of the

watchdog period. If the watchdog overflows, or is triggered in the first half of the watchdog

period (before t_trig(wd)1), a system reset is performed. After the system reset, the reset

source (either ‘watchdog triggered too early’ or ‘watchdog overflow’) can be read via the

reset source status bits (RSS) in the Main Status register (Table 6). If the watchdog is

triggered in the second half of the watchdog period (after t_trig(wd)1but before t_trig(wd)2), the

watchdog timer is restarted.

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7.2.4 Watchdog behavior in Timeout mode

The watchdog runs continuously in Timeout mode. The watchdog will be in Timeout mode

if WMC = 010 and the UJA1169A is in Normal, Standby or Sleep mode. The watchdog will

also be in Timeout mode if WMC = 100 and the UJA1169A is in Standby or Sleep mode. If

Autonomous mode is selected (WMC = 001), the watchdog will be in Timeout mode if one

of the conditions for Timeout mode listed in Table 11 has been satisfied.

In Timeout mode, the watchdog timer can be reset at any time by a watchdog trigger. If the

watchdog overflows, a watchdog failure event (WDF) is captured. If a WDF is already

pending when the watchdog overflows, a system reset is performed. In Timeout mode, the

watchdog can be used as a cyclic wake-up source for the microcontroller when the

UJA1169A is in Standby or Sleep mode. In Sleep mode, a watchdog overflow generates a

wake-up event while setting WDF.

When the SBC is in Sleep mode with watchdog Timeout mode selected, a wake-up event

is generated after the nominal watchdog period (NWP), setting WDF. RXD is forced LOW

and V1 is turned on. The application software can then clear the WDF bit and trigger the

watchdog before it overflows again.

7.2.5 Watchdog behavior in Autonomous mode

Autonomous mode is selected when WMC = 001. In Autonomous mode, the watchdog is

either off or in Timeout mode, according to the conditions detailed in Table 11.

Table 11. Watchdog status in Autonomous mode

UJA1169A operating mode

Watchdog status

SDMC = 0

SDMC = 1

Normal

Timeout mode

off

Standby; RXD HIGH

Sleep

off

any other mode

Standby; RXD LOW

off

Timeout mode

When Autonomous mode is selected, the watchdog will be in Timeout mode if the SBC is

in Normal mode or Standby mode with RXD LOW, provided Software Development mode

has been disabled (SDMC = 0). Otherwise the watchdog will be off.

In Autonomous mode, the watchdog will not be running when the SBC is in Standby (RXD

HIGH) or Sleep mode. If a wake-up event is captured, pin RXD is forced LOW to signal

the event and the watchdog is automatically restarted in Timeout mode. If the SBC was in

Sleep mode when the wake-up event was captured, it switches to Standby mode.

7.3 System reset

When a system reset occurs, the SBC switches to Reset mode and initiates process that

generates a low-level pulse on pin RSTN. The UJA1169A can distinguish up to 13

different reset sources, as detailed in Table 6.

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7.3.1 Characteristics of pin RSTN

Pin RSTN is a bidirectional open-drain low side driver with integrated pull-up resistance,

as shown in Figure 4. With this configuration, the SBC can detect the pin being pulled

down externally, e.g. by the microcontroller. The input reset pulse width must be at least

t_w(rst)to guarantee that external reset events are detected correctly.

V1

RSTN

015aaa276

Fig 4. RSTN internal pin configuration

7.3.2 Selecting the output reset pulse width

The duration of the output reset pulse is selected via bits RLC in the Start-up control

register (Table 12). The SBC distinguishes between a cold start and a warm start. A cold

start is performed if the reset event was combined with a V1 undervoltage event

(power-on reset, reset during Sleep mode, over-temperature reset, V1 undervoltage

before entering or while in Reset mode). The setting of bits RLC determines the output

reset pulse width for a cold start.

A warm start is performed if any other reset event occurs without a V1 undervoltage

(external reset, watchdog failure, watchdog change attempt in Normal mode, illegal Sleep

mode command). The SBC uses the shortest reset length (t_w(rst)as defined when

RLC = 11).

7.3.2.1 Start-up control register

Table 12. Start-up control register (address 73h)

Bit Symbol

7:6 reserved

5:4 RLC

Access

R

Value

Description

-

R/W

RSTN output reset pulse width:

t_w(rst)= 20 ms to 25 ms

00^[1]

01

t_w(rst)= 10 ms to 12.5 ms

10

t_w(rst)= 3.6 ms to 5 ms

11

t_w(rst)= 1 ms to 1.5 ms

3

V2SUC^[2]

R/W

R

V2/VEXT start-up control:

VEXTSUC^[3]

0^[1]

1

bits V2C/VEXTC set to 00 at power-up

bits V2C/VEXTC set to 11 at power-up

2:0 reserved

-

[1] Factory preset value.

[2] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3 only.

[3] UJA1169ATK/X and UJA1169ATK/X/F only.

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7.4 Reset sources

The following events will cause the UJA1169A to switch to Reset mode:

• V_V1drops below the selected V1 undervoltage threshold defined by bits V1RTC

(except in Sleep mode or Overtemp mode)

• via Off mode after an MTPNV programming cycle has been completed

• pin RSTN is pulled down externally

• the watchdog overflows in Window mode

• the watchdog is triggered too early in Window mode (before t_trig(wd)1

)

• the watchdog overflows in Timeout mode with WDF = 1 (watchdog failure pending)

• an attempt is made to reconfigure the Watchdog control register while the SBC is in

Normal mode

• the SBC leaves Off mode

• local or CAN-bus wake-up in Sleep mode

• diagnostic wake-up in Sleep mode

• the SBC leaves Overtemp mode

• illegal Sleep mode command received

• wake-up from Sleep mode due to a frame detect error

7.5 Global temperature protection

The temperature of the UJA1169A is monitored continuously, except in Sleep and Off

modes. The SBC switches to Overtemp mode if the temperature exceeds the

overtemperature protection activation threshold, T_th(act)otp. In addition, pin RSTN is driven

LOW and V1, V2/VEXT and the CAN transceiver are switched off (if the optional external

PNP transistor is connected, it will also be off; see Section 7.6.2). When the temperature

drops below the overtemperature protection release threshold, T_th(rel)otp, the SBC

switches to Standby mode via Reset mode.

In addition, the UJA1169A provides an overtemperature warning. When the IC

temperature rises above the overtemperature warning threshold (T_th(warn)otp), status bit

OTWS is set and an overtemperature warning event is captured (OTW = 1).

7.6 Power supplies

7.6.1 Battery supply voltage (V_BAT

)

The internal circuitry is supplied from the battery via pin BAT. The device must be

protected against negative supply voltages, e.g. by using an external series diode. If V_BAT

falls below the power-off detection threshold, V_th(det)poff, the SBC switches to Off mode.

However, in the 5 V variants, the microcontroller supply voltage (V1) remains active until

V

_BATfalls below 2 V, ensuring memory in the connected microcontroller remains active for

as long as possible (RAM retention feature; not available in the 3.3 V variants).

The SBC switches from Off mode to Reset mode t_startupafter the battery voltage rises

above the power-on detection threshold, V_th(det)pon. Power-on event status bit PO is set to

1 to indicate the UJA1169A has powered up and left Off mode (see Table 27).

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7.6.2 Voltage regulator V1

The UJA1169A provides a 5 V or 3.3 V supply (V1), depending on the variant. V1 can

deliver up to 250 mA load current. In the UJA1169ATK/X and UJA1169ATK/X/F variants,

the CAN transceiver is supplied internally via V1, reducing the output current available for

external components.

open

VEXCTRL

VEXCC

battery

UJA1169A

I

L

V1

BAT

V1

6.8 μF

22 μF

47 nF

aaa-033694

Fig 5. Typical application without external PNP (showing example component values)

To prevent the device overheating at high ambient temperatures or high average currents,

an external PNP transistor can be connected as illustrated in Figure 6. In this

configuration, the power dissipation is distributed between the SBC (I_V1) and the PNP

transistor (I_PNP).

The PNP transistor is activated when the load current reaches the PNP activation

threshold, I_th(act)PNP. Bit PDC in the Regulator control register (Table 13) is used to

regulate how power dissipation is distributed.

close to PNP

PHPT61003PY

I

PNP

10 nF

VEXCTRL

VEXCC

battery

1.6 Ω

I

L

UJA1169A

I

V1

BAT

V1

6.8 μF

22 μF

47 nF

aaa-033695

Fig 6. Typical application with external PNP (showing example component values)

For short-circuit protection, a resistor must be connected between pins V1 and VEXCC to

allow the current to be monitored. This resistor limits the current delivered by the external

transistor. If the voltage difference between pins VEXCC and V1 reaches V_th(act)Ilim, the

PNP current limiting activation threshold voltage, the transistor current will not increase

further. In general, any PNP transistor with a current amplification factor () of between 50

and 500 can be used.

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The output voltage on V1 is monitored. A system reset is generated if the voltage on V1

drops below the selected undervoltage threshold (60 %, 70 %, 80 % or 90 % of the

nominal V1 output voltage for the 5 V variants, selected via V1RTC in the Regulator

control register; fixed at 90 % for the 3.3 V variants; see Table 13).

The default value of the undervoltage threshold at power-up is determined by the value of

bits V1RTSUC in the SBC configuration control register (Table 9). The SBC configuration

control register is in non-volatile memory, allowing the user to define the default

undervoltage threshold (V1RTC) at any battery start-up.

In addition, an undervoltage warning (a V1U event; see Section 7.11) is generated if the

voltage on V1 falls below 90 % of the nominal value (and V1U event detection is enabled,

V1UE = 1; see Table 32). This information can be used as a warning, when the 60 %,

70 % or 80 % threshold is selected in the 5 V variants, to indicate that the level on V1 is

outside the nominal supply range. The status of V1, whether it is above or below the 90 %

undervoltage threshold, can be polled via bit V1S in the Supply voltage status register

(Table 14).

7.6.3 Voltage regulator V2

In the UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3, pin 13 is a

voltage regulator output (V2) delivering up to 100 mA.

The CAN transceiver is supplied internally from V2, consuming a portion of the available

current. V2 is not protected against shorts to the battery or to negative voltages and

should not be used to supply off-board components.

V2 is software controlled and must be turned on (via bit V2C in the Regulator control

register; see Table 13) to activate the supply voltage for the internal CAN transceiver. V2

is not required for wake-up detection via the CAN interface.

The default value of V2C at power-on is defined by bits V2SUC in non-volatile memory

(see Section 7.12). The status of V2 can be polled from the Supply voltage status register

(Table 14).

7.6.4 Voltage regulator VEXT

In the UJA1169ATK/X and UJA1169ATK/X/F, pin 13 is a voltage regulator output (VEXT)

that can be used to supply off-board components, delivering up to 100 mA. VEXT is

protected against short-circuits to the battery and negative voltages. Since the CAN

controller is supplied internally via V1, the full 100 mA supply current is available for

off-board loads connected to VEXT (provided the thermal limits of the PCB are not

exceeded).

VEXT is software controlled and must be turned on (via bit VEXTC in the Regulator

control register; see Table 13) to activate the supply voltage for off-board components.

The default value of VEXTC at power-on is defined by bits VEXTSUC in non-volatile

memory (see Section 7.12). The status of VEXT can be read from the Supply voltage

status register (Table 14).

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7.6.5 Regulator control register

Table 13. Regulator control register (address 10h)

Bit

7

Symbol

reserved

PDC

Access

R

Value Description

-

6

R/W

power distribution control:

V1 threshold current for activating the external PNP transistor, load current

rising; I_th(act)PNP(higher value; see Table 53)

0

V1 threshold current for deactivating the external PNP transistor, load

current falling; I_th(deact)PNP(higher value; see Table 53)

V1 threshold current for activating the external PNP transistor; load current

rising; I_th(act)PNP(lower value; see Table 53)

V1 threshold current for deactivating the external PNP transistor; load

current falling; I_th(deact)PNP(lower value; see Table 53)

1

-

5:4

3:2

reserved

V2C^[1]

VEXTC^[2]

R

R/W

V2/VEXT configuration:

00

01

10

11

V2/VEXT off in all modes

V2/VEXT on in Normal mode

V2/VEXT on in Normal, Standby and Reset modes

V2/VEXT on in Normal, Standby, Sleep and Reset modes

set V1 reset threshold:

1:0

V1RTC^[3]

R/W

00

01

10

11

reset threshold set to 90 % of V1 nominal output voltage

reset threshold set to 80 % of V1 nominal output voltage

reset threshold set to 70 % of V1 nominal output voltage

reset threshold set to 60 % of V1 nominal output voltage

[1] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3: default value at power-up defined by V2SUC bit setting (see

Table 12).

[2] UJA1169ATK/X and UJA1169ATK/X/F: default value at power-up defined by VEXTSUC bit setting (see Table 12).

[3] 5 V variants only; default value at power-up defined by setting of bits V1RTSUC (see Table 9). The threshold is fixed at 90 % in the 3.3 V

variants and V1RTC always reads 00 (regardless of the value written to V1RTC or the start-up threshold defined by V1RTSUC).

7.6.6 Supply voltage status register

Table 14. Supply voltage status register (address 1Bh)

Bit

7:3

2:1

Symbol

Access

Value Description

reserved

V2S^[1]

VEXTS^[2]

R

-

V2/VEXT status:

00^[3]

01

V2/VEXT voltage ok

V2/VEXT output voltage below undervoltage threshold

V2/VEXT output voltage above overvoltage threshold

V2/VEXT disabled

10

11

0

V1S

R

V1 status:

0^[3]

1

V1 output voltage above 90 % undervoltage threshold

V1 output voltage below 90 % undervoltage threshold

[1] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3 only.

[2] UJA1169ATK/X and UJA1169ATK/X/F only.

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[3] Default value at power-up.

7.7 LIMP output

The dedicated LIMP pin can be used to enable so called ‘limp home’ hardware in the

event of a serious ECU failure. Detectable failure conditions include SBC overtemperature

events, loss of watchdog service, short-circuits on pins RSTN or V1 and user-initiated or

external reset events (see Figure 7). The LIMP pin is a battery-robust, active-LOW,

open-drain output. The LIMP pin can also be forced LOW by setting bit LHC in the

Fail-safe control register (Table 15).

7.7.1 Reset counter

The UJA1169A uses a reset counter to detect serious failures. The reset counter is

incremented (bits RCC = RCC + 1; see Table 15) every time the SBC enters Reset mode.

When the system is running correctly, it is expected that the system software will reset this

counter (RCC = 00) periodically to ensure that routinely expected reset events do not

cause it to overflow.

If RCC is equal to 3 when the SBC enters Reset mode, the SBC assumes that a serious

failure has occurred and sets the limp-home control bit, LHC. This action forces the

external LIMP pin LOW with RCC overflowing to RCC = 0. Bit LHC can also be set via the

SPI interface.

The LIMP pin is set floating again if LHC is reset to 0 through software control or at

power-up when the SBC leaves Off mode.

The application software can preset the counter value to define how many reset events

are tolerated before the limp-home function is activated. If RCC is initialized to 3, for

example, the next reset event will immediately trigger the limp-home function. The default

counter setting at power-up is RCC = 00.

Besides a reset counter (RCC) overflow, the following events cause bit LHC to be set and

immediately trigger the limp-home function:

• overtemperature lasting longer than t_d(limp)

• SBC remaining in Reset mode for longer than t_d(limp)(e.g. because of a clamped

RSTN pin or a permanent V1 undervoltage).

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7.7.2 LIMP state diagram

OK

LHC = 0

(SBC mode = Reset or Overtemp)

and RCC ≠ 3 and FNMC = 0

Set LHC by SPI access

and FNMC = 0

→RCC++

SBC mode ≠ Reset and

SBC mode ≠ Overtemp

Clear LHC by SPI access

(SBC mode = Reset or Overtemp)

and RCC = 3 and FNMC = 0

LIMP

OK

Res/OT

LHC = 0

LHC = 1

→RCC++

(SBC mode = Reset or

Overtemp) and FNMC = 0

Power-on

→RCC++

→RCC = default

t > t

and FNMC = 0

d(limp)

SBC mode ≠ Reset and

SBC mode ≠ Overtemp

LIMP

Res/OT

LHC = 1

OFF

aaa-015318

SBC modes are derived from the SBC state diagram (see Figure 3). The reset counter overflows

from 3 to 0; t is the time the SBC remains continuously in Reset or Overtemp mode; time t is reset

at mode entry; time t is not reset on a transition between Reset and Overtemp modes

Fig 7. Limp function state diagram

Note that the SBC always switches to Reset mode after leaving Sleep mode, since the

SBC powers up V1 in response to a wake-up event. So RCC is incremented after each

Sleep mode cycle. The application software needs to monitor RCC and update the value

as necessary to ensure that multiple Sleep mode cycles do not cause the reset counter to

overflow.

The limp-home function and the reset counter are disabled in Forced Normal mode. The

LIMP pin is floating, RCC remains unchanged and bit LHC = 0.

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7.7.2.1 Fail-safe control register

The Fail-safe control register contains the reset counter along with limp home control

settings.

Table 15. Fail-safe control register (address 02h)

Bit

7:3

2

Symbol

reserved

LHC

Access Value Description

R/W

LIMP home control:

0

1

LIMP pin is floating

LIMP pin is driven LOW

reset counter control:

1:0

RCC

xx

incremented every time the SBC enters Reset mode

while FNMC = 0; RCC overflows from 11 to 00; default at

power-on is 00

RESET

LIMP

LOGIC

1 = on

0 = off

bit LHC

UJA1169A

aaa-033696

Fig 8. LIMP pin functional diagram

7.8 High-speed CAN transceiver

The integrated high-speed CAN transceiver is designed for active communication at bit

rates up to 1 Mbit/s, providing differential transmit and receive capability to a CAN protocol

controller. The transceiver is ISO 11898-2:2016 compliant. Depending on the derivative,

the CAN transmitter is supplied internally from V1 (in /X variants) or V2 (in variants with a

V2 regulator). Additional timing parameters defining loop delay symmetry are included to

ensure reliable communication in fast phase at data rates up to 5 Mbit/s, as used in CAN

FD networks.

The CAN transceiver supports autonomous CAN biasing as defined in ISO 11898-2:2016.

CANH and CANL are always biased to 2.5 V when the transceiver is in Active or

Listen-only modes (CMC = 01/10/11; see Table 16).

Autonomous biasing is active in CAN Offline mode, to 2.5 V if there is activity on the bus

(CAN Offline Bias mode) and to GND if there is no activity on the bus for t > t_to(silence)

(CAN Offline mode).

This is useful when the node is disabled due to a malfunction in the microcontroller or

when CAN partial networking is enabled. The SBC ensures that the CAN bus is correctly

biased to avoid disturbing ongoing communication between other nodes. The

autonomous CAN bias voltage is derived directly from V_BAT

.

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7.8.1 CAN operating modes

The integrated CAN transceiver supports four operating modes: Active, Listen-only,

Offline and Offline Bias (see Figure 9). The CAN transceiver operating mode depends on

the UJA1169A operating mode and on the setting of bits CMC in the CAN control register

(Table 16).

When the UJA1169A is in Normal mode, the CAN transceiver operating mode (Active,

Listen-only or Offline) can be selected via bits CMC. When the UJA1169A is in Standby or

Sleep mode, the transceiver is forced to Offline or Offline Bias mode (depending on bus

activity).

7.8.1.1 CAN Active mode

In CAN Active mode, the transceiver can transmit and receive data via CANH and CANL.

The differential receiver converts the analog data on the bus lines into digital data, which

is output on pin RXD. The transmitter converts digital data generated by the CAN

controller (input on pin TXD) into analog signals suitable for transmission over the CANH

and CANL bus lines.

CAN Active mode is selected when CMC = 01 or 10. When CMC = 01, undervoltage

detection is enabled and the transceiver will go to CAN Offline or CAN Offline Bias mode

when the voltage on V1 drops below V_uvd(CAN). When CMC = 10, undervoltage detection

is disabled. The transmitter will remain active until the voltage on V1 drops below the V1

reset threshold (selected via bits V1RTC). The SBC will then switch to Reset mode and

the transceiver will switch to CAN Offline or CAN Offline Bias mode.

The CAN transceiver is in Active mode when:

• the UJA1169A is in Normal mode (MC = 111) and the CAN transceiver has been

enabled by setting bits CMC in the CAN control register to 01 or 10 (see Table 16)

and:

– if CMC = 01, the voltage on pin V1 is aboveV_uvd(CAN)

– if CMC = 10, the voltage on pin V1 is above the V1 reset threshold

If pin TXD is held LOW (e.g. by a short-circuit to GND) when CAN Active mode is selected

via bits CMC, the transceiver will not enter CAN Active mode but will switch to or remain in

CAN Listen-only mode. It will remain in Listen-only mode until pin TXD goes HIGH in

order to prevent a hardware and/or software application failure from driving the bus lines

to an unwanted dominant state.

In CAN Active mode, the CAN bias voltage is the CAN supply voltage divided by two

(depending on the derivative, the bias voltage is either V1 divided by two or V2 divided by

two).

The application can determine whether the CAN transceiver is ready to transmit/receive

data or is disabled by reading the CAN Transceiver Status (CTS) bit in the Transceiver

Status Register (Table 17).

7.8.1.2 CAN Listen-only mode

CAN Listen-only mode allows the UJA1169A to monitor bus activity while the transceiver

is inactive, without influencing bus levels. This facility could be used by development tools

that need to listen to the bus but do not need to transmit or receive data or for

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software-driven selective wake-up. Dedicated microcontrollers could be used for selective

wake-up, providing an embedded low-power CAN engine designed to monitor the bus for

potential wake-up events.

In Listen-only mode the CAN transmitter is disabled, reducing current consumption. The

CAN receiver and CAN biasing remain active. This enables the host microcontroller to

switch to a low-power mode in which an embedded CAN protocol controller remains

active, waiting for a signal to wake up the microcontroller.

The CAN transceiver is in Listen-only mode when:

• the UJA1169A is in Normal mode and CMC = 11

The CAN transceiver will not leave Listen-only mode while TXD is LOW or CAN Active

mode is selected with CMC = 01 while the voltage on V1 is below the 90 % undervoltage

threshold.

7.8.1.3 CAN Offline and Offline Bias modes

In CAN Offline mode, the transceiver monitors the CAN bus for a wake-up event, provided

CAN wake-up detection is enabled (CWE = 1; see Table 33). CANH and CANL are biased

to GND.

CAN Offline Bias mode is the same as CAN Offline mode, with the exception that the CAN

bus is biased to 2.5 V. This mode is activated automatically when activity is detected on

the CAN bus while the transceiver is in CAN Offline mode. The transceiver will return to

CAN Offline mode if the CAN bus is silent (no CAN bus edges) for longer than t_to(silence)

.

The CAN transceiver switches to CAN Offline mode from CAN Active mode or CAN

Listen-only mode if:

• the SBC switches to Reset or Standby or Sleep mode OR

• the SBC is in Normal mode and CMC = 00

provided the CAN bus has been inactive for at least t_to(silence). If the CAN bus has been

inactive for less than t_to(silence), the CAN transceiver switches first to CAN Offline Bias

mode and then to CAN Offline mode once the bus has been silent for t_to(silence)

.

The CAN transceiver switches to CAN Offline/Offline Bias mode from CAN Active mode if

CMC = 01 and V_CANdrops below the 90 % undervoltage threshold or the voltage on V1

drops below the V1 reset threshold (CMC = 01 or 10).

The CAN transceiver switches to CAN Offline mode:

• from CAN Offline Bias mode if no activity is detected on the bus (no CAN edges) for

t > t_to(silence)OR

• when the SBC switches from Off or Overtemp mode to Reset mode

The CAN transceiver switches from CAN Offline mode to CAN Offline Bias mode if:

• a standard wake-up pattern is detected on the CAN bus OR

• the SBC is in Normal mode, CMC = 01 or 10 and V_CAN< 90 %

7.8.1.4 CAN Off mode

The CAN transceiver is switched off completely with the bus lines floating when:

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• the SBC switches to Off or Overtemp mode OR

• V_BATfalls below the CAN receiver undervoltage detection threshold, V_uvd(CAN)

It will be switched on again on entering CAN Offline mode when V_BATrises above the

undervoltage recovery threshold (V_uvr(CAN)) and the SBC is no longer in Off/Overtemp

mode. CAN Off mode prevents reverse currents flowing from the bus when the battery

supply to the SBC is lost.

CAN Active

transmitter: on

RXD: bitstream

CANH/CANL: terminated

[Reset OR Standby

to V

/2 (≈2.5 V)

CAN

OR Sleep OR

(Normal & CMC = 00) OR

(CMC = 01 & V

< 90 %)]

CAN

to(silence)

Normal & CMC = 11

& t > t

[Reset OR Standby

OR Sleep OR

(Normal & CMC = 00) OR

(CMC = 01 & V

< 90 %)]

CAN

t

to(silence)

Normal &

& t <

(CMC = 01 OR CMC = 10) &

(1)

V

> 90 %

CAN

(1)

V

> 90 %

CAN

Normal &

Normal & CMC = 11

(CMC = 01 OR

CAN Offline Bias

transmitter: off

RXD: wake-up/int

CAN Listen-only

CMC = 10) &

transmitter: off

RXD: bitstream

(1)

V

< 90 %

CAN

[Reset OR Standby OR Sleep OR

(Normal & CMC = 00)]

CANH/CANL: terminated

to 2.5 V (from V

)

Normal &

to 2.5 V (from V

)

BAT

& t < t

to(silence)

(CMC = 01 OR

CMC = 10) &

(1)

V

> 90 %

CAN

[Reset OR Standby OR Sleep OR

(Normal & CMC = 00)] &

from all modes

t > t

to(silence)

Normal & CMC = 11

CAN bus wake-up OR

[Normal &

(CMC = 01 OR CMC = 10) &

< 90 %]

[Reset OR Standby OR Sleep OR

(Normal & CMC = 00)]

Off OR

Overtemp OR

BAT

& t > t

V

< V

uvd(CAN)

to(silence)

V

CAN

CAN Offline

transmitter: off

CAN Off

RXD: wake-up/int

CANH/CANL: terminated

to GND

transmitter: off

RXD: wake-up/int

CANH/CANL: floating

leaving Off/Overtemp &

> V

V

BAT

uvr(CAN)

aaa-033788

(1) To prevent the bus lines being driven to a permanent dominant state, the transceiver will not switch to CAN Active mode or CAN

Listen-only mode if pin TXD is held LOW (e.g. by a short-circuit to GND)

Fig 9. CAN transceiver state machine (with FNMC = 0)

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7.8.2 CAN standard wake-up (partial networking not enabled)

If the CAN transceiver is in Offline mode and CAN wake-up is enabled (CWE = 1), but

CAN selective wake-up is disabled (CPNC = 0 or PNCOK = 0), the UJA1169A monitors

the bus for a wake-up pattern.

A filter at the receiver input prevents unwanted wake-up events occurring due to

automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be

transmitted on the CAN bus within the wake-up time-out time (t_to(wake)bus) to pass the

wake-up filter and trigger a wake-up event (see Figure 10; note that additional pulses may

occur between the recessive/dominant phases). The recessive and dominant phases

must last at least t_wake(busrec)and t_wake(busdom), respectively.

CANH

CANL

V

O(dif)

t

wake(busdom)

wake(busrec)

RXD

≤ t

to(wake)bus

aaa-021858

Fig 10. CAN wake-up timing

When a valid CAN wake-up pattern is detected on the bus, wake-up bit CW in the

Transceiver event status register is set (see Table 29) and pin RXD is driven LOW. If the

SBC was in Sleep mode when the wake-up pattern was detected, V1 is enabled to supply

the microcontroller and the SBC switches to Standby mode via Reset mode.

7.8.2.1 CAN control register

Table 16. CAN control register (address 20h)

Bit

7

Symbol

reserved

CFDC^[1]

Access

R

Value

Description

-

6

R/W

CAN FD control:

0

1

CAN FD tolerance disabled

CAN FD tolerance enabled

CAN partial networking configuration OK:

5

PNCOK^[1]

R/W

0

1

partial networking register configuration invalid (wake-up via standard

wake-up pattern only)

partial networking registers configured successfully

CAN partial networking control:

4

CPNC^[1]

reserved

R/W

R

0

1

-

disable CAN selective wake-up

enable CAN selective wake-up

3:2

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Table 16. CAN control register (address 20h) …continued

Bit

Symbol

Access

Value

Description

1:0

CMC

R/W

CAN transceiver operating mode selection (available when UJA1169A is in

Normal mode; MC = 111):

00

01

10

11

Offline mode

Active mode; see Section 7.8.1.1

Listen-only mode

[1] UJA1169ATK/F and UJA1169ATK/X/F only; otherwise reserved.

7.8.2.2 Transceiver status register

Table 17. Transceiver status register (address 22h)

Bit

Symbol

Access

Value

Description

7

CTS

R

CAN transceiver status:

0

1

CAN transceiver not in Active mode

CAN transceiver in Active mode

CAN partial networking error:

6

CPNERR^[1]

R

0

1

no CAN partial networking error detected (PNFDE = 0 AND

PNCOK = 1)

CAN partial networking error detected (PNFDE = 1 OR PNCOK = 0;

wake-up via standard wake-up pattern only)

5

4

3

CPNS^[1]

COSCS^[1]

CBSS

R

CAN partial networking status:

0

1

CAN partial networking configuration error detected (PNCOK = 0)

CAN partial networking configuration ok (PNCOK = 1)

CAN oscillator status:

0

1

CAN partial networking oscillator not running at target frequency

CAN partial networking oscillator running at target frequency

CAN bus silence status:

0

1

-

CAN bus active (communication detected on bus)

CAN bus inactive (for longer than t_to(silence)

)

2

1

reserved

VCS^[2]

R

V_CANstatus:

0

1

CAN supply voltage is above the undervoltage threshold, V_uvd(CAN)

CAN supply voltage is below the undervoltage threshold, V_uvd(CAN)

CAN failure status:

0

CFS

R

0

1

no TXD dominant time-out event detected

CAN transmitter disabled due to a TXD dominant time-out event

[1] UJA1169ATK/F and UJA1169ATK/X/F only; otherwise reserved reading 0.

[2] Only active when CMC = 01.

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7.9 CAN partial networking (UJA1169A /F variants only)

Partial networking allows nodes in a CAN network to be selectively activated in response

to dedicated wake-up frames (WUF). Only nodes that are functionally required are active

on the bus while the other nodes remain in a low-power mode until needed.

If both CAN wake-up (CWE = 1) and CAN selective wake-up (CPNC = 1) are enabled,

and the partial networking registers are configured correctly (PNCOK = 1), the transceiver

monitors the bus for dedicated CAN wake-up frames.

7.9.1 Wake-up frame (WUF)

A wake-up frame is a CAN frame according to ISO11898-1:2003, consisting of an

identifier field (ID), a Data Length Code (DLC), a data field and a Cyclic Redundancy

Check (CRC) code including the CRC delimiter.

The wake-up frame format, standard (11-bit) or extended (29-bit) identifier, is selected via

bit IDE in the Frame control register (Table 21).

A valid WUF identifier is defined and stored in the ID registers (Table 19). An ID mask can

be defined to allow a group of identifiers to be recognized as valid by an individual node.

The identifier mask is defined in the ID mask registers (Table 20), where a 1 means ‘don’t

care’.

In the example illustrated in Figure 11, based on the standard frame format, the 11-bit

identifier is defined as 1A0h. The identifier is stored in ID registers 2 (29h) and 3 (2Ah).

The three least significant bits of the ID mask, bits 2 to 4 of Mask register 2 (2Dh), are

‘don’t care’. This means that any of eight different identifiers will be recognized as valid in

the received WUF (from 1A0h to 1A7h).

UJA1169A (FD variants) SPI Settings

11-bit Identifier field:

0

1

0

1

0

1

0

1

0

1

0

1

0x1A0 stored in ID

registers 2 and 3

ID mask:

0x007 stored in Mask

registers 2 and 3

Valid Wake-Up Identifiers: 0x1A0 to 0x1A7

0

1

0

1

0

x

aaa-033697

Fig 11. Evaluating the ID field in a selective wake-up frame

The data field indicates the nodes to be woken up. Within the data field, groups of nodes

can be predefined and associated with bits in a data mask. By comparing the incoming

data field with the data mask, multiple groups of nodes can be woken up simultaneously

with a single wake-up message.

The data length code (bits DLC in the Frame control register; Table 21) determines the

number of data bytes (between 0 and 8) expected in the data field of a CAN wake-up

frame. If one or more data bytes are expected (DLC  0000), at least one bit in the data

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field of the received wake-up frame must be set to 1 and at least one equivalent bit in the

associated data mask register in the transceiver (see Table 22) must also be set to 1 for a

successful wake-up. Each matching pair of 1s indicates a group of nodes to be activated

(since the data field is up to 8 bytes long, up to 64 groups of nodes can be defined). If

DLC = 0, a data field is not expected.

In the example illustrated in Figure 12, the data field consists of a single byte (DLC = 1).

This means that the data field in the incoming wake-up frame is evaluated against data

mask 7 (stored at address 6Fh; see Table 22 and Figure 13). Data mask 7 is defined as

10101000 in the example, indicating that the node is assigned to three groups (Group1,

Group 3 and Group 5).

The received message shown in Figure 12 could, potentially, wake up four groups of

nodes: groups 2, 3, 4 and 5. Two matches are found (groups 3 and 5) when the message

data bits are compared with the configured data mask (DM7).

DLC

Data mask 7

stored

values

0

1

0

2

1

3

1

0

4

1

5

1

0

6

0

7

0

8

Groups:

received

message

1

0

015aaa365

Fig 12. Evaluating the Data field in a selective wake-up frame

Optionally, the data length code and the data field can be excluded from the evaluation of

the wake-up frame. If bit PNDM = 0, only the identifier field is evaluated to determine if the

frame contains a valid wake-up message. If PNDM = 1 (the default value), the data field is

included for wake-up filtering.

When PNDM = 0, a valid wake-up message is detected and a wake-up event is captured

(and CW is set to 1) when:

• the identifier field in the received wake-up frame matches the pattern in the ID

registers after filtering AND

• the CRC field in the received frame (including a recessive CRC delimiter) was

received without error

When PNDM = 1, a valid wake-up message is detected when:

• the identifier field in the received wake-up frame matches the pattern in the ID

registers after filtering AND

• the frame is not a Remote frame AND

• the data length code in the received message matches the configured data length

code (bits DLC) AND

• if the data length code is greater than 0, at least one bit in the data field of the

received frame is set and the corresponding bit in the associated data mask register is

also set AND

• the CRC field in the received frame (including a recessive CRC delimiter) was

received without error

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If the UJA1169A receives a CAN message containing errors (e.g. a ‘stuffing’ error) that are

transmitted in advance of the ACK field, an internal error counter is incremented. If a CAN

message is received without any errors appearing in front of the ACK field, the counter is

decremented. Data received after the CRC delimiter and before the next Start of Frame

(SOF) is ignored by the partial networking module. If the counter overflows (counter > 31),

a frame detect error is captured (PNFDE = 1) and the device wakes up; the counter is

reset to zero when the bias is switched off and partial networking is re-enabled.

Partial networking is assumed to be configured correctly when PNCOK is set to 1 by the

application software. The UJA1169A clears PNCOK after a write access to any of the

CAN partial networking configuration registers (see Section 7.9.3).

If selective wake-up is disabled (CPNC = 0) or partial networking is not configured

correctly (PNCOK = 0), and the CAN transceiver is in Offline mode with wake-up enabled

(CWE = 1), then any valid wake-up pattern according to ISO 11898-2:2016 will trigger a

wake-up event.

If the CAN transceiver is not in Offline mode (CMC  00) or CAN wake-up is disabled

(CWE = 0), all wake-up patterns on the bus are ignored.

CAN bit rates of 50 kbit/s, 100 kbit/s, 125 kbit/s, 250 kbit/s, 500 kbit/s and 1Mbit/s are

supported during selective wake-up. The bit rate is selected via bits CDR (see Table 18).

7.9.2 CAN FD frames

CAN FD stands for ‘CAN with Flexible Data-Rate’. It is based on the CAN protocol as

defined in ISO 11898-1:2015.

CAN FD is being gradually introduced into automotive market. In time, all CAN controllers

will be required to comply with the new standard (enabling ‘FD-active’ nodes) or at least to

tolerate CAN FD communication (enabling ‘FD-passive’ nodes). The UJA1169ATK/F,

UJA1169ATK/F/3 and UJA1169ATK/X/F support FD-passive features by means of a

dedicated implementation of the partial networking protocol.

The /F variants can be configured to recognize CAN FD frames as valid CAN frames.

When CFDC = 1, the error counter is decremented every time the control field of a CAN

FD frame is received. The UJA1169Axx/F remains in low-power mode (CAN FD-passive)

with partial networking enabled. CAN FD frames are never recognized as valid wake-up

frames, even if PNDM = 0 and the frame contains a valid ID. After receiving the control

field of a CAN FD frame, the UJA1169Axx/F ignores further bus signals until idle is again

detected.

CAN FD passive is supported up to a ratio of one-to-eight between arbitration and data bit

rates, without unwanted wake-ups. The CAN FD filter parameter defined in ISO

11898-2:2016 and SAE J2284 is supported up to a ratio of one-to-four, with a maximum

supported bit data bit rate of 2 Mbit/s and a maximum arbitration speed of 500 kbit/s.

CAN FD frames are interpreted as frames with errors by the partial networking module

when CFDC = 0. So the error counter is incremented when a CAN FD frame is received. If

the ratio of CAN FD frames to valid CAN frames exceeds the threshold that triggers error

counter overflow, bit PNFDE is set to 1 and the device wakes up.

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7.9.3 CAN partial networking configuration registers

Dedicated registers are provided for configuring CAN partial networking.

7.9.3.1 Data rate register

Table 18. Data rate register (address 26h)

Bit

7:3

2:0

Symbol

reserved

CDR

Access

R

Value

Description

-

R/W

CAN data rate selection:

50 kbit/s

000

001

010

011

100

100 kbit/s

125 kbit/s

250 kbit/s

reserved (intended for future use; currently

selects 500 kbit/s)

101

110

500 kbit/s

reserved (intended for future use; currently

selects 500 kbit/s)

111

1000 kbit/s

7.9.3.2 ID registers

Table 19. ID registers 0 to 3 (addresses 27h to 2Ah)

Addr. Bit Symbol Access Value Description

27h

28h

29h

7:0 ID07:ID00

7:0 ID15:ID08

7:2 ID23:ID18

R/W

-

bits ID07 to ID00 of the extended frame format

bits ID15 to ID08 of the extended frame format

bits ID23 to ID18 of the extended frame format

bits ID05 to ID00 of the standard frame format

1:0 ID17:ID16

7:5 reserved

4:0 ID28:ID24

R/W

R

-

bits ID17 to ID16 of the extended frame format

2Ah

R/W

bits ID28 to ID24 of the extended frame format

bits ID10 to ID06 of the standard frame format

7.9.3.3 ID mask registers

Table 20. ID mask registers 0 to 3 (addresses 2Bh to 2Eh)

Addr. Bit Symbol

2Bh 7:0 M07:M00

2Ch 7:0 M15:M08

2Dh 7:2 M23:M18

Access Value Description

R/W

-

mask bits ID07 to ID00 of the extended frame format

mask bits ID15 to ID08 of the extended frame format

mask bits ID23 to ID18 of the extended frame format

mask bits ID05 to ID00 of the standard frame format

1:0 M17:M16

2Eh 7:5 reserved

4:0 M28:M24

R/W

R

-

mask bits ID17 to ID16 of the extended frame format

R/W

mask bits ID28 to ID24 of the extended frame format

mask. bits ID10 to ID06 of the standard frame format

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7.9.3.4 Frame control register

Table 21. Frame control register (address 2Fh)

Bit

Symbol

Access

Value

Description

7

IDE

R/W

-

identifier format:

0

1

-

standard frame format (11-bit)

extended frame format (29-bit)

partial networking data mask:

6

PNDM

R/W

0

data length code and data field are ‘don’t care’ for

wake-up

1

-

data length code and data field are evaluated at

wake-up

5:4

3:0

reserved

DLC

R

R/W

number of data bytes expected in a CAN frame:

0000

0001

0010

0011

0100

0101

0110

0111

1000

0

1

2

3

4

5

6

7

8

1001 to

1111

tolerated, 8 bytes expected

7.9.3.5 Data mask registers

Table 22. Data mask registers (addresses 68h to 6Fh)

Addr.

68h

Bit

7:0

Symbol

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

Access Value

Description

R/W

-

data mask 0 configuration

data mask 1 configuration

data mask 2 configuration

data mask 3 configuration

data mask 4 configuration

data mask 5 configuration

data mask 6 configuration

data mask 7 configuration

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

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DLC > 8

DLC = 8

DLC = 7

DLC = 6

DLC = 5

DLC = 4

DLC = 3

DLC = 2

DLC = 1

DM0 DM1

DM2

DM3

DM4

DM5

DM6 DM7

DM0

DM1

DM6

DM7

DM6 DM7

DM7

aaa-015874

Fig 13. Data mask register usage for different values of DLC

7.10 CAN fail-safe features

7.10.1 TXD dominant time-out

A TXD dominant time-out timer is started when pin TXD is forced LOW while the

transceiver is in CAN Active Mode. The transmitter is disabled if the LOW state on pin

TXD persists for longer than the TXD dominant time-out time (t_to(dom)TXD), releasing the

bus lines to recessive state. This function prevents a hardware and/or software application

failure from driving the bus lines to a permanent dominant state (blocking all network

communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.

The TXD dominant time-out time also defines the minimum possible bit rate of 4.4 kbit/s.

When the TXD dominant time-out time is exceeded, a CAN failure event is captured

(CF = 1; see Table 29), if enabled (CFE = 1; see Table 33). In addition, the status of the

TXD dominant time-out can be read via the CFS bit in the Transceiver status register

(Table 17) and bit CTS is cleared.

7.10.2 Pull-up on TXD pin

Pin TXD has an internal pull-up towards V1 to ensure a safe defined recessive driver state

in case the pin is left floating.

7.10.3 V_CANundervoltage event

When CMC = 01, a CAN failure event is captured (CF = 1), if enabled, when the supply to

the CAN transceiver falls below the undervoltage detection threshold, V_uvd(CAN). In

addition, status bit VCS is set to 1.

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7.10.4 Loss of power at pin BAT

When power is lost at pin BAT, the SBC behaves passively towards the CAN-bus pins,

disabling the bias circuitry. This ensures that a loss of power at BAT does not affect

ongoing communication between nodes on the network.

7.11 Wake-up and interrupt event handling

7.11.1 WAKE pin

Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture

enable register (see Table 34). A wake-up event is triggered by a LOW-to-HIGH (if

WPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This

arrangement allows for maximum flexibility when designing a local wake-up circuit. In

applications that do not use the local wake-up facility, local wake-up should be disabled

and the WAKE pin connected to GND.

7.11.1.1 WAKE pin status register

Table 23. WAKE pin status register (address 4Bh)

Bit

7:2

1

Symbol

reserved

WPVS

Access Value Description

R

-

WAKE pin status:

0

1

-

voltage on WAKE pin below switching threshold (V_th(sw))

voltage on WAKE pin above switching threshold (V_th(sw)

)

0

reserved

R

While the SBC is in Normal mode, the status of the voltage on pin WAKE can always be

read via bit WPVS. Otherwise, WPVS is only valid if local wake-up is enabled (WPRE = 1

and/or WPFE = 1).

7.11.2 Wake-up diagnosis

Wake-up and interrupt event diagnosis in the UJA1169A is intended to provide the

microcontroller with information on the status of a range of features and functions. This

information is stored in the event status registers (Table 27 to Table 29) and is signaled on

pin RXD, if enabled.

A distinction is made between regular wake-up events and interrupt events.

Table 24. Regular events

Symbol Event

Power-on Description

CW

CAN wake-up

disabled

rising edge on WAKE pin disabled

falling edge on WAKE pin disabled

see Transceiver event status register (Table 29)

WPR

WPF

see WAKE pin event capture status register

(Table 30)

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Table 25. Diagnostic events

Symbol Event

Power-on

always enabled

disabled

Description

PO

power-on

see System event status register

(Table 27)

OTW

SPIF

WDF

V2O^[1]

overtemperature warning

SPI failure

disabled

watchdog failure

V2 overvoltage

always enabled

disabled

see Supply event status register

(Table 28)

VEXTO^[2]VEXT overvoltage

V2U^[1]

V2 undervoltage

VEXTU^[2]VEXT undervoltage

V1U V1 undervoltage

PNFDE^[3]PN frame detection error

disabled

always enabled

disabled

see Transceiver event status register

(Table 29)

CBS

CF

CAN -bus silence

CAN failure

disabled

[1] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3 only.

[2] UJA1169ATK/X and UJA1169ATK/X/F only.

[3] UJA1169ATK/F, UJA1169ATK/F/3 and UJA1169ATK/X/F only; otherwise reserved.

PO, WDF and PNFDE interrupts are always enabled and thus captured. Wake-up and

interrupt detection can be enabled/disabled for the remaining events individually via the

event capture enable registers (Table 31 to Table 33).

If an event occurs while the associated event capture function is enabled, the relevant

event status bit is set. If the transceiver is in CAN Offline mode with V1 active (SBC

Normal or Standby mode), pin RXD is forced LOW to indicate that a wake-up or interrupt

event has been detected. If the UJA1169A is in sleep mode when the event occurs, the

microcontroller supply, V1, is activated and the SBC switches to Standby mode (via Reset

mode).

The microcontroller can monitor events via the event status registers. An extra status

register, the Global event status register (Table 26), is provided to help speed up software

polling routines. By polling the Global event status register, the microcontroller can quickly

determine the type of event captured (system, supply, transceiver or WAKE pin) and then

query the relevant event status register (Table 27, Table 28, Table 29 or Table 30

respectively).

After the event source has been identified, the status flag should be cleared (set to 0) by

writing 1 to the relevant bit (writing 0 will have no effect). A number of status bits can be

cleared in a single write operation by writing 1 to all relevant bits.

It is strongly recommended to clear only the status bits that were set to 1 when the status

registers were last read. This precaution ensures that events triggered just before the

write access are not lost.

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7.11.3 Interrupt/wake-up delay

If interrupt or wake-up events occur very frequently while the transceiver is in CAN Offline

mode, they can have a significant impact on the software processing time (because pin

RXD is repeatedly driven LOW, requiring a response from the microcontroller each time

an interrupt/wake-up is generated). The UJA1169A incorporates an event delay timer to

limit the disturbance to the software.

When one of the event capture status bits is cleared, pin RXD is released (HIGH) and a

timer is started. If further events occur while the timer is running, the relevant status bits

are set. If one or more events are pending when the timer expires after t_d(event), pin RXD

goes LOW again to alert the microcontroller. In this way, the microcontroller is interrupted

once to process a number of events rather than several times to process individual

events.

If all events are cleared while the timer is running, RXD remains HIGH after the timer

expires, since there are no pending events. The event capture registers can be read at

any time.

The event capture delay timer is stopped immediately when pin RSTN goes low (triggered

by a HIGH-to-LOW transition on the pin). RSTN is driven LOW when the SBC enters

Reset, Sleep, Overtemp and Off modes. A pending event is signaled on pin RXD when

the SBC enters Sleep mode.

7.11.4 Sleep mode protection

The wake-up event capture function is critical when the UJA1169A is in Sleep mode,

because the SBC only leaves Sleep mode in response to a captured wake-up event. To

avoid potential system deadlocks, the SBC distinguishes between regular and diagnostic

events (see Section 7.11). Wake-up events (via the CAN bus or the WAKE pin) are

classified as regular events; diagnostic events signal failure/error conditions or state

changes. At least one regular wake-up event must be enabled before the UJA1169A can

switch to Sleep mode. Any attempt to enter Sleep mode while all regular wake-up events

are disabled triggers a system reset.

Another condition that must be satisfied before the UJA1169A can switch to Sleep mode

is that all event status bits must be cleared. If an event is pending when the SBC receives

a Sleep mode command (MC = 001), it immediately switches to Reset mode. This

condition applies to both regular and diagnostic events.

Sleep mode can be permanently disabled in applications where, for safety reasons, the

supply voltage to the host controller must never be cut off. Sleep mode is permanently

disabled by setting the Sleep control bit (SLPC) in the SBC configuration register (see

Table 9) to 1. This register is located in the non-volatile memory area of the device. When

SLPC = 1, a Sleep mode SPI command (MC = 001) triggers an SPI failure event instead

of a transition to Sleep mode.

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7.11.5 Event status and event capture registers

After an event source has been identified, the status flag should be cleared (set to 0) by

writing 1 to the relevant status bit (writing 0 will have no effect).

7.11.5.1 Event status registers

Table 26. Global event status register (address 60h)

Bit

7:4

3

Symbol

reserved

WPE

Access

Value

Description

R

-

WAKE pin event:

0

1

no pending WAKE pin event

WAKE pin event pending at address 64h

transceiver event:

2

1

0

TRXE

SUPE

SYSE

R

0

1

no pending transceiver event

transceiver event pending at address 63h

supply event:

0

1

no pending supply event

supply event pending at address 62h

system event:

0

1

no pending system event

system event pending at address 61h

Table 27. System event status register (address 61h)

Bit

7:5

4

Symbol

reserved

PO

Access Value

Description

R

-

R/W

power-on:

0

1

no recent battery power-on

the UJA1169A has left Off mode after battery

power-on

3

2

reserved

OTW

R

-

R/W

overtemperature warning:

0

1

overtemperature not detected

the global chip temperature has exceeded the

overtemperature warning threshold, T_th(warn)otp(not in

Sleep mode)

1

SPIF

R/W

SPI failure:

0

1

no SPI failure detected

SPI clock count error (only 16-, 24- and 32-bit

commands are valid), illegal WMC, NWP or MC code

or attempted write access to locked register (not in

Sleep mode)

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Table 27. System event status register (address 61h) …continued

Bit

Symbol

Access Value

Description

0

WDF

R/W

watchdog failure:

0

no watchdog failure event captured

1

watchdog overflow in Window or Timeout mode or

watchdog triggered too early in Window mode; a

system reset is triggered immediately in response to

a watchdog failure in Window mode; when the

watchdog overflows in Timeout mode, a system reset

is only performed if a WDF is already pending

(WDF = 1)

Table 28. Supply event status register (address 62h)

Bit

7:3

2

Symbol

Access

R

Value

Description

reserved

V2O^[1]/

VEXTO^[2]

-

R/W

V2/VEXT overvoltage:

0

1

no V2/VEXT overvoltage event captured

V2/VEXT overvoltage event captured

V2/VEXT undervoltage:

1

0

V2U^[1]

/

R/W

VEXTU^[2]

0

1

no V2/VEXT undervoltage event captured

V2/VEXT undervoltage event captured

V1 undervoltage:

V1U

0

1

no V1 undervoltage event captured

voltage on V1 has dropped below the 90 %

undervoltage threshold while V1 is active (event is

not captured in Sleep mode because V1 is off);

V1U event capture is independent of the setting of

bits V1RTC

[1] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3 only.

[2] UJA1169ATK/X and UJA1169ATK/X/F only.

Table 29. Transceiver event status register (address 63h)

Bit

7:6

5

Symbol

reserved

PNFDE

Access

R

Value

Description

-

R/W

partial networking frame detection error:

0

1

no partial networking frame detection error

detected

partial networking frame detection error detected

CAN bus status:

4

CBS

R/W

R

0

1

CAN bus active

no activity on CAN bus for t_to(silence)(detected only

when CBSE = 1 while bus active)

3:2

reserved

-

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Table 29. Transceiver event status register (address 63h) …continued

Bit

Symbol

Access

Value

Description

1

CF

R/W

CAN failure:

0

1

no CAN failure detected

(CMC = 01 & CAN transceiver deactivated due to

V_CANundervoltage) OR dominant clamped TXD

(not in Sleep mode)

0

CW

R/W

CAN wake-up:

0

1

no CAN wake-up event detected

CAN wake-up event detected while the transceiver

is in CAN Offline Mode

Table 30. WAKE pin event status register (address 64h)

Bit

7:2

1

Symbol

reserved

WPR

Access

R

Value

Description

-

R/W

WAKE pin rising edge:

0

1

no rising edge detected on WAKE pin

rising edge detected on WAKE pin

WAKE pin falling edge:

0

WPF

R/W

0

1

no falling edge detected on WAKE pin

falling edge detected on WAKE pin

7.11.5.2 Event capture enable registers

Table 31. System event capture enable register (address 04h)

Bit

7:3

2

Symbol

reserved

OTWE

Access

R

Value

Description

-

R/W

overtemperature warning enable:

overtemperature warning disabled

overtemperature warning enabled

SPI failure enable:

0

1

0

SPIFE

R/W

R

0

1

-

SPI failure detection disabled

SPI failure detection enabled

reserved

Table 32. Supply event capture enable register (address 1Ch)

Bit

7:3

2

Symbol

Access

R

Value

Description

reserved

V2OE^[1]/

VEXTOE^[2]

-

R/W

V2/VEXT overvoltage enable:

0

1

V2/VEXT overvoltage detection disabled

V2/VEXT overvoltage detection enabled

V2/VEXT undervoltage enable:

1

V2UE^[1]/

VEXTUE^[2]

R/W

0

1

V2/VEXT undervoltage detection disabled

V2/VEXT undervoltage detection enabled

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Table 32. Supply event capture enable register (address 1Ch) …continued

Bit

Symbol

Access

Value

Description

0

V1UE

R/W

V1 undervoltage enable:

V1 undervoltage detection disabled

V1 undervoltage detection enabled

0

1

[1] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3 only.

[2] UJA1169ATK/X and UJA1169ATK/X/F only.

Table 33. Transceiver event capture enable register (address 23h)

Bit

7:5

4

Symbol

reserved

CBSE

Access

R

Value

Description

-

R/W

CAN bus silence enable:

0

1

-

CAN bus silence detection disabled

CAN bus silence detection enabled

3:2

1

reserved

CFE

R

R/W

CAN failure enable:

0

1

CAN failure detection disabled

CAN failure detection enabled

CAN wake-up enable:

0

CWE

R/W

0

1

CAN wake-up detection disabled

CAN wake-up detection enabled

Table 34. WAKE pin event capture enable register (address 4Ch)

Bit

7:2

1

Symbol

reserved

WPRE

Access

R

Value

Description

-

R/W

WAKE pin rising-edge enable:

0

1

rising-edge detection on WAKE pin disabled

rising-edge detection on WAKE pin enabled

WAKE pin falling-edge enable:

0

WPFE

R/W

0

1

falling-edge detection on WAKE pin disabled

falling-edge detection on WAKE pin enabled

7.12 Non-volatile SBC configuration

The UJA1169A contains Multiple Time Programmable Non-Volatile (MTPNV) memory

cells that allow some of the default device settings to be reconfigured. The MTPNV

memory address range is from 73h to 74h. For details, see Table 9 and Table 12.

7.12.1 Programming MTPNV cells

NXP delivers the UJA1169A in so-called ‘Forced Normal’ mode, also referred to as the

‘factory preset’ configuration. In order to change the default settings, the device must be in

Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the

watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode.

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If the device has been programmed previously, the factory presets may need to be

restored before reprogramming can begin (see Section 7.12.2). When the factory presets

have been restored successfully, a system reset is generated automatically and

UJA1169A switches back to Forced Normal mode.

Programming of the non-volatile memory (NVM) registers is performed in two steps. First,

the required values are written to addresses 73h and 74h. In the second step,

reprogramming is confirmed by writing the correct CRC value to the MTPNV CRC control

register (see Section 7.12.1.2). The SBC starts reprogramming the MTPNV cells as soon

as the CRC value has been validated. If the CRC value is not correct, reprogramming is

aborted. On completion, a system reset is generated to indicate that the MTPNV cells

have been reprogrammed successfully. Note that the MTPNV cells cannot be read while

they are being reprogrammed.

After an MTPNV programming cycle has been completed, the NVM is protected from

being overwritten.

The MTPNV cells can be reprogrammed a maximum of 200 times (N_cy(W)MTP; see

Table 53). Bit NVMPS in the MTPNV status register (Table 35) indicates whether the

non-volatile cells can be reprogrammed. This register also contains a write counter,

WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a

maximum value of 111111; there is no overflow; performing a factory reset also increments

the counter). This counter is provided for information purposes only; reprogramming will

not be rejected when it reaches its maximum value.

An error correction code status bit, ECCS, is set to indicate the CRC check mechanism in

the SBC has detected and corrected a single bit failure in non-volatile memory. If more

than one bit failure is detected, the SBC will not restart after MTPNV reprogramming.

Check the ECCS flag at the end of the production cycle to verify the content of non-volatile

memory. When this flag is set, it indicates a device or ECU failure.

7.12.1.1 MTPNV status register

Table 35. MTPNV status register (address 70h)

Bit

Symbol

Access

Value Description

write counter status:

7:2

WRCNTS

R

xxxxxx

contains the number of times the MTPNV cells were

reprogrammed

1

0

ECCS

R

error correction code status:

0

1

no bit failure detected in non-volatile memory

bit failure detected and corrected in non-volatile

memory

NVMPS

non-volatile memory programming status:

MTPNV memory cannot be overwritten

MTPNV memory is ready to be reprogrammed

0

1^[1]

[1] Factory preset value.

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7.12.1.2 MTPNV CRC control register

The cyclic redundancy check value stored in bits CRCC in the MTPNV CRC control

register is calculated using the data written to registers 73h and 74h.

Table 36. MTPNV CRC control register (address 75h)

Bit

Symbol

Access

Value

Description

7:0

CRCC

R/W

cyclic redundancy check control:

CRC control data

-

The CRC value is calculated using the data representation shown in Figure 14 and the

modulo-2 division with the generator polynomial: X⁸+ X⁵+ X³+ X²+ X + 1. The result of

this operation must be bitwise inverted.

7

6

1

0

7

6

1

0

register 0x73

register 0x74

015aaa382

Fig 14. Data representation for CRC calculation

The following parameters can be used to calculate the CRC value (e.g. via the AUTOSAR

method):

Table 37. Parameters for CRC coding

Parameter

Value

8 bits

2Fh

FFh

no

CRC result width

Polynomial

Initial value

Input data reflected

Result data reflected

XOR value

no

FFh

Alternatively, the following algorithm can be used:

data

crc

for

=

0

FFh

// unsigned byte

=

i

=

0

to

1

data

for

=

content_of_address(73h + i) EXOR crc

j

=

0

to

7

if data



128

data

=

data

data EXOR 2Fh

*

2

// shift left by 1

else

data

=

data * 2 // shift left by 1

j

=

data

i

=

crc EXOR FFh

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7.12.2 Restoring factory preset values

Factory preset values are restored if the following conditions apply continuously for at

least t_d(MTPNV)during battery power-up:

• pin RSTN is held LOW

• CANH is pulled up to V_BAT

• CANL is pulled down to GND

After the factory preset values have been restored, the SBC performs a system reset and

enters Forced Normal mode. Since the CAN bus is clamped dominant, pin RXD is forced

LOW during the factory preset restore process. A rising edge on pin RXD indicates the

end of the factory preset restore process (i.e. after t_d(MTPNV)). Due to bit PO being set after

power-on, pin RXD goes LOW again during the system reset.

Note that the write counter, WRCNTS, in the MTPNV status register is incremented every

time the factory presets are restored.

7.13 Device identification

7.13.1 Device identification register

A byte is reserved at address 7Eh for a product identification code used to distinguish the

different UJA1169A derivatives.

Table 38. Identification register (address 7Eh)

Bit

Symbol

Access

Value

Description

7:0

IDS[7:0]

R

identification status:

UJA1169ATK

CFh

C9h

EFh

E9h

CEh

EEh

UJA1169ATK/3

UJA1169ATK/F

UJA1169ATK/F/3

UJA1169ATK/X

UJA1169ATK/X/F

7.14 Register locking

Sections of the register address area can be write-protected to protect against unintended

modifications. This facility only protects locked bits from being modified via the SPI and

will not prevent the UJA1169A updating status registers etc.

7.14.1 Lock control register

Table 39. Lock control register (address 0Ah)

Bit Symbol Access Value Description

7

6

reserved

LK6C

R

-

R/W

lock control 6: address area 68h to 6Fh - data mask (/F

versions only)

0

1

SPI write access enabled

SPI write access disabled

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Table 39. Lock control register (address 0Ah) …continued

Bit Symbol Access Value Description

5

LK5C

R/W

lock control 5: address area 50h to 5Fh - unused register

range

0

1

SPI write access enabled

SPI write access disabled

4

3

LK4C

LK3C

R/W

lock control 4: address area 40h to 4Fh - WAKE pin control

SPI write access enabled

0

1

SPI write access disabled

lock control 3: address area 30h to 3Fh - unused register

range

0

1

SPI write access enabled

SPI write access disabled

2

1

0

LK2C

LK1C

LK0C

R/W

lock control 2: address area 20h to 2Fh - transceiver control

SPI write access enabled

0

1

SPI write access disabled

lock control 1: address area 10h to 1Fh - regulator control

SPI write access enabled

0

1

SPI write access disabled

lock control 0: address area 06h to 09h - general-purpose

memory

0

1

SPI write access enabled

SPI write access disabled

7.15 General-purpose memory

UJA1169A allocates 4 bytes of memory as general-purpose registers for storing user

information. The general-purpose registers can be accessed via the SPI at address 06h to

09h without read or write cycle limitations (see Table 40).

7.16 SPI

7.16.1 Introduction

The Serial Peripheral Interface (SPI) provides the communication link with the

microcontroller, supporting multi-slave operations. The SPI is configured for full duplex

data transfer, so status information is returned when new control data is shifted in. The

interface also offers a read-only access option, allowing the application to read back

registers without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

• SCSN: SPI chip select; active LOW

• SCK: SPI clock; default level is LOW due to low-power concept (pull-down)

• SDI: SPI data input

• SDO: SPI data output; floating when pin SCSN is HIGH

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Bit sampling is performed on the falling edge of the clock and data is shifted in/out on the

rising edge, as illustrated in Figure 15.

SCSN

SCK

SDI

01

02

03

04

N-1

N

sampled

X

MSB

MSB-1

MSB-2

MSB-3

LSB+1

LSB

X

MSB

MSB-1

MSB-2

MSB-3

LSB+1

SDO

X

floating

015aaa255

Fig 15. SPI timing overview (see Figure 20 for detailed SPI timing)

The SPI data in the UJA1169A is stored in a number of dedicated 8-bit registers. Each

register is assigned a unique 7-bit address. Two bytes (16 bits) must be transmitted to the

SBC for a single register read or write operation. The first byte contains the 7-bit address

along with a ‘read-only’ bit (the LSB). The read-only bit must be 0 to indicate a write

operation (if this bit is 1, a read operation is assumed and any data on the SDI pin is

ignored). The second byte contains the data to be written to the register.

24- and 32-bit read and write operations are also supported. The register address is

automatically incremented, once for a 24-bit operation and twice for a 32-bit operation, as

illustrated in Figure 16.

Register Address Range

0x00

0x01

0x02

0x03

0x04

0x05

0x06

data

0x07

0x7D 0x7E 0x7F

ID=0x05

data

addr 0000101

data byte 1

data byte 2

data byte 3

A6 A5 A4 A3 A2 A1 A0 RO

x

Address Bits

Read-only Bit

Data Bits

x

015aaa289

Data Bits

Fig 16. SPI data structure for a write operation (16-, 24- or 32-bit)

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The contents of the addressed registers are returned via pin SDO during an SPI data read

or write operation,

The UJA1169A tolerates attempts to write to registers that do not exist. If the available

address space is exceeded during a write operation, the data above the valid address

range is ignored (without generating an SPI failure event).

A reserved bit can be read and (over)written without affecting device functionality; the

read value should be ignored.

During a write operation, the UJA1169A monitors the number of SPI bits transmitted. If the

number recorded is not 16, 24 or 32, then the write operation is aborted and an SPI failure

event is captured (SPIF = 1).

If more than 32 bits are clocked in on pin SDI during a read operation, the data stream on

SDI is reflected on SDO from bit 33 onwards.

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7.16.2 Register map

The addressable register space contains 128 registers with addresses from 00h to 7Fh.

An overview of the register mapping is provided in Table 40 to Table 49. The functionality

of individual bits is discussed in more detail in relevant sections of the data sheet.

Table 40. Overview of primary control registers

Address Register Name

Bit:

7

6

5

4

3

2

1

0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

Watchdog control

Mode control

Fail-safe control

Main status

WMC

reserved

reserved NWP

MC

LHC

RCC

reserved OTWS

reserved

NMS

RSS

System event enable

Watchdog status

Memory 0

OTWE

SDMS

SPIFE

WDS

reserved

FNMS

GPM[7:0]

Memory 1

GPM[15:8]

Memory 2

GPM[23:16]

GPM[31:24]

reserved LK6C

Memory 3

Lock control

LK5C

LK4C

LK3C

LK2C

LK1C

LK0C

Table 41. Overview of regulator control registers

Address Register Name

Bit:

7

6

5

4

3

2

1

0

10h

Regulator control

reserved^[1]PDC reserved

V2C^[2]/

VEXTC^[3]

V1RTC^[4]

1Bh

1Ch

Supply status

reserved

V2S^[2]/VEXTS^[3]

V2OE^[2]V2UE^[2]/

VEXTOE^[3]VEXTUE^[3]

V1S

Supply event enable

/

V1UE

[1] Reserved bits can be read and overwritten without affecting device functionality; default value at power-up is 00 (other reserved bits

always return 0).

[2] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3 only.

[3] UJA1169ATK/X and UJA1169ATK/X/F only.

[4] Fixed at 00 in UJA1169ATK/3 and UJA1169ATK/F/3.

Table 42. Overview of transceiver control and partial networking registers

Address Register Name

Bit:

7

6

5

4

3

2

1

0

20h

22h

23h

26h

27h

28h

29h

CAN control

reserved CFDC^[1]

PNCOK^[1]CPNC^[1]reserved

CMC

Transceiver status

CTS

CPNERR^[1]CPNS^[1]

COSCS^[1]CBSS reserved VCS

CFS

Transceiver event enable reserved

CBSE reserved CFE

CWE

Data rate

reserved

ID[7:0]^[1]

ID[15:8]^[1]

ID[23:16]^[1]

CDR^[1]

Identifier 0

Identifier 1

Identifier 2

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Table 42. Overview of transceiver control and partial networking registers …continued

Address Register Name

Bit:

7

6

5

4

3

2

1

0

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

Identifier 3

Mask 0

reserved

M[7:0]^[1]

M[15:8]^[1]

M[23:16]^[1]

reserved

IDE^[1]

DM0[7:0]^[1]

DM1[7:0]^[1]

DM2[7:0]^[1]

DM3[7:0]^[1]

DM4[7:0]^[1]

DM5[7:0]^[1]

DM6[7:0]^[1]

DM7[7:0]^[1]

ID[28:24]^[1]

Mask 1

Mask 2

Mask 3

M[28:24]^[1]

Frame control

Data mask 0

Data mask 1

Data mask 2

Data mask 3

Data mask 4

Data mask 5

Data mask 6

Data mask 7

PNDM^[1]

reserved

DLC^[1]

[1] UJA1169ATK/F, UJA1169ATK/F/3 and UJA1169ATK/X/F only; otherwise reserved.

Table 43. Overview of WAKE pin control and status registers

Address

Register Name

Bit:

7

6

5

4

3

2

1

0

4Bh

4Ch

WAKE pin status

WAKE pin enable

reserved

WPVS

WPRE

reserved

WPFE

Table 44. Overview of event capture registers

Address Register Name

Bit:

7

6

5

4

3

1

0

60h

61h

62h

Global event status

System event status

Supply event status

reserved

WPE

TRXE

SUPE

SYSE

WDF

V1U

PO

reserved OTW

V2O^[1]/

SPIF

V2U^[1]

/

VEXTO^[2]VEXTU^[2]

63h

64h

Transceiver event status reserved

WAKE pin event status reserved

PNFDE^[3]CBS

reserved

CF

CW

WPR

WPF

[1] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3 only.

[2] UJA1169ATK/X and UJA1169ATK/X/F only.

[3] UJA1169ATK/F, UJA1169ATK/F/3 and UJA1169ATK/X/F only; otherwise reserved.

Table 45. Overview of MTPNV status register

Address

Register Name

Bit:

7

6

5

4

3

2

1

0

70h

MTPNV status

WRCNTS

ECCS

NVMPS

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Table 46. Overview of Start-up control register

Address

Register Name

Bit:

7

6

5

4

3

2

1

0

73h

Start-up control

reserved

RLC

V2SUC^[1]/

VEXTSUC^[2]

reserved

[1] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3 only.

[2] UJA1169ATK/X and UJA1169ATK/X/F only.

Table 47. Overview of SBC configuration control register

Address Register Name

Bit:

7

6

5

4

3

2

1

0

74h

SBC configuration control reserved

V1RTSUC

FNMC

SDMC

reserved SLPC

Table 48. Overview of CRC control register

Address

Register Name

Bit:

7

6

5

4

3

2

1

0

75h

MTPNV CRC control

CRCC[7:0]

Table 49. Overview of Identification register

Address

Register Name

Bit:

7

6

4

7Eh

Identification

IDS[7:0]

7.16.3 Register configuration in UJA1169A operating modes

A number of register bits may change state automatically when the UJA1169A switches

from one operating mode to another. This feature is particularly evident when the

UJA1169A switches to Off mode. These changes are summarized in Table 50. If an SPI

transmission is in progress when the UJA1169A changes state, the transmission is

ignored (automatic state changes have priority).

Table 50. Register bit settings in UJA1169A operating modes

Symbol

Off (power-on

default)

Standby

Normal^[1]

Sleep

Overtemp

Reset

CBS

0

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

CBSE

CBSS

CDR^[2]

CF

0

1

101

0

CFDC^[2]

0

CFE

0

CFS

0

CMC

01

0

COSCS^[2]

CPNC^[2]

CPNERR^[2]

0

1

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Table 50. Register bit settings in UJA1169A operating modes …continued

Symbol

Off (power-on

default)

Standby

Normal^[1]

Sleep

Overtemp

Reset

CPNS^[2]

CRCC

CTS

0

actual state

no change

0

actual state

no change

actual state

no change

actual state

MTPNV

actual state

no change

0

actual state

no change

0

actual state

no change

0

00000000

0

CW

0

no change

actual state

MTPNV

no change

actual state

MTPNV

no change

actual state

MTPNV

no change

actual state

MTPNV

CWE

DMn^[2]

DLC^[2]

ECCS

FNMC

FNMS

GPMn

IDn

0

11111111

0000

actual state

MTPNV

0

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

1 if RCC = 3 or

00000000

0

IDE

IDS

see Table 38

0

LHC

1 if t > t_d(limp)

otherwise no

change

;

t > t_d(limp)

;

otherwise no

change

LKnC

MC

0

no change

100

no change

111

no change

001

no change

don’t care

no change

actual state

0100

no change

100

NMS

1

no change

actual state

no change

actual state

no change

MTPNV

0

no change

actual state

no change

actual state

no change

MTPNV

no change

actual state

0100

NVMPS

NWP

actual state

no change

actual state

no change

MTPNV

0100

OTW

0

no change

actual state

no change

MTPNV

no change

actual state

no change

RCC++

OTWE

OTWS

PDC

PNCOK^[2]

PNDM^[2]

PNFDE^[2]

PO

0

1

0

1

RCC

00

RLC

MTPNV

RSS

00000

no change

MTPNV

no change

MTPNV

no change

MTPNV

10010

reset source

MTPNV

SDMC

SDMS

SLPC

SPIF

MTPNV

0

actual state

MTPNV

actual state

MTPNV

actual state

MTPNV

actual state

MTPNV

actual state

MTPNV

0

1

no change

SPIFE

SUPE

SYSE

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Table 50. Register bit settings in UJA1169A operating modes …continued

Symbol

Off (power-on

default)

Standby

Normal^[1]

Sleep

Overtemp

Reset

TRXE

0

no change

V1RTC

defined by V1RTSUC no change

in 5 V variants^[3]

V1RTSUC

V1S

MTPNV

0

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

V1UE

V1U

VCS

V2C^[4]/

VEXTC^[5]

defined by

V2SUC^[4]/VEXTSUC^[5]

V2O^[4]/

0

no change

actual state

MTPNV

no change

actual state

MTPNV

no change

actual state

MTPNV

no change

actual state

MTPNV

no change

actual state

MTPNV

VEXTO^[5]

V2OE^[4]/

VEXTOE^[5]

V2S^[4]/

VEXTS^[5]

V2SUC^[4]/

VEXTSUC^[5]

0

00

MTPNV

V2U^[4]/

0

no change

VEXTU^[5]

V2UE^[4]/

VEXTUE^[5]

WDF

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

no change

actual state

WDS

0

actual state

[6]

WMC

WPE

0

no change

actual state

WPF

0

WPR

0

WPFE

WPRE

WPVS

WRCNTS

0

actual state

[1] Exceptions apply for Forced Normal mode (FNMC = 1); see Section 7.1.1.7).

[2] UJA1169ATK/F, UJA1169ATK/F/3, and UJA1169ATK/X/F only; otherwise reserved.

[3] Fixed at 00 in UJA1169ATK/3 and UJA1169ATK/F/3.

[4] UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F and UJA1169ATK/F/3 only.

[5] UJA1169ATK/X and UJA1169ATK/X/F only.

[6] 001 if SDMC = 1; otherwise 010.

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8. Limiting values

Table 51. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

[2]

V_x

voltage on pin x^[1]

pin V1, V2 (UJA1169ATK, UJA1169ATK/3,

UJA1169ATK/F and UJA1169ATK/F/3)

0.3 +6

V

[3]

pins TXD, RXD, SDI, SDO, SCK, SCSN, RSTN

pin VEXT (UJA1169ATK/X, UJA1169ATK/X/F)

pin VEXCC

0.3 V_V1+ 0.3

V

18

+40

V

0.3 +6

V

pin WAKE

18

+40

V

pins LIMP, BAT, VEXCTRL

0.3 +40

V

pins CANH and CANL with respect to any other pin

58

-

+58

+20

+40

V

I_I(LIMP)

input current on pin LIMP LHC = 1

mA

V

V_(CANH-CANL)voltage between pin

CANH and pin CANL

40

[4]

V_trt

transient voltage

on pins CANL, CANH, WAKE, VEXT, BAT

pulse 1

100

-

V

pulse 2a

-

75

-

pulse 3a

150

pulse 3b

-

100

[5]

V_ESD

electrostatic discharge

voltage

IEC 61000-4-2 (150 pF, 330 ) discharge circuit

on pins CANH and CANL; pin BAT with capacitor;

pin WAKE with 10 nF capacitor and 10 k resistor;

pin VEXT with 2.2 F capacitor

6

+6

kV

Human Body Model (HBM)

on any pin

[6]

[7]

[8]

[9]

2

4

8

+2

+4

+8

kV

on pins BAT, LIMP, WAKE, VEXT

on pins CANH, CANL

Machine Model (MM)

on any pin

100 +100

500 +500

V

[10]

[11]

Charged Device Model (CDM)

on any pin

V

T_vj

virtual junction

temperature

40

0

+150

+125

+150

C

when programming the MTPNV cells

T_stg

storage temperature

55

[1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients)

never exceed these values.

[2] When the device is not powered up, I_V1(max) = 25 mA.

[3] Maximum voltage should never exceed 6 V.

[4] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637 part 2.

[5] Verified by an external test house according to IEC TS 62228, Section 4.3.

[6] According to AEC-Q100-002.

[7] Pins stressed to reference group containing all grounds, emulating the application circuit (Figure 21). HBM pulse as specified in

AEC-Q100-002 used.

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[8] Pins stressed to reference group containing all ground and supply pins, emulating the application circuit (Figure 21). HBM pulse as

specified in AEC-Q100-002 used.

[9] According to AEC-Q100-003.

[10] According to AEC-Q100-011.

[11] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T_vj= T_amb+ P  R_th(j-a), where R_th(j-a)is a

fixed value used in the calculation of T_vj. The rating for T_vjlimits the allowable combinations of power dissipation (P) and ambient

temperature (T_amb).

9. Thermal characteristics

Table 52. Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

[1]

R_th(vj-a)

thermal resistance from virtual junction to ambient HVSON20

33.5

K/W

[1] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers

(thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 m).

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10. Static characteristics

Table 53. Static characteristics

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

V_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply; pin BAT

I_BAT

battery supply current

Normal mode; MC = 111;CAN

Active mode

CAN recessive; V_TXD= V_V1

CAN dominant; V_TXD= 0 V

-

4

7.5

67

65

mA

A

46

[2]

Sleep mode; MC = 001;

CAN Offline mode; V2/VEXT off;

V_BAT= 7 V to 18 V;

40 C < T_vj< 85 C;

[2]

Standby mode; MC = 100;

CAN Offline mode; V2/VEXT off;

I_V1= 0 A; V_BAT= 7 V to 18 V;

40 C < T_vj< 85 C

-

91

32

81

A

additional current with V2 on

(V2C = 01/10/11);

I_V2= 0 A; V_BAT= 7 V to 18 V;

40 C < T_vj< 85 C

8

additional current with VEXT on

(VEXTC = 01/10/11);

72

I_VEXT= 0 A; V_BAT= 7 V to 18 V;

40 C < T_vj< 85 C

additional current in CAN Offline

Bias mode;

40 C < T_vj< 85 C

-

38

55

A

[3]

additional current in CAN Offline

Bias mode with partial networking

active; Standby or Sleep mode;

40 C < T_vj< 85 C

0.4

0.65

mA

additional current from WAKE

input; WPRE = WPFE = 1; 40 C

< T_vj< 85 C

-

2

3

A

V_th(det)pon

V_th(det)poff

power-on detection threshold

voltage

V_BATrising

4.2

2.8

-

4.55

3

V

power-off detection threshold

voltage

V_BATfalling

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Table 53. Static characteristics …continued

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

V

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Voltage source: pin V1

[3]

V_O

output voltage

V_O(V1)nom= 5 V;

4.9

5

5.1

V

V_BAT= 5.5 V to 28 V;

I_V1= 200 mA to 0 mA

V

_O(V1)nom= 5 V;

4.9

5

5.1

V

V_BAT= 5.65 V to 28 V;

I_V1= 250 mA to 0 mA

V_O(V1)nom= 5 V;

-

5.5

V_BATbelow V_th(det)poffand rising;

t  t_startup; T_vj 125 C

V_O(V1)nom= 3.3 V;

V_BAT= 3.834 V to 28 V;

I_V1= 200 mA to 0 mA

3.234

3.3

3.366

V_O(V1)nom= 3.3 V;

V_BAT= 3.984 V to 28 V;

I_V1= 250 mA to 0 mA

V_ret(RAM)

RAM retention voltage

difference

between V_BATand V_V1; 5 V variants

only

V_BAT= 2 V to 3 V; I_V1= 2 mA

V_BAT= 2 V to 3 V; I_V1= 200 A

-

100

10

3

mV



[3]

R_ON(BAT-V1)

ON resistance between pin

BAT and pin V1

V_BAT= 3.25 V to 5.65 V;

I_V1= 250 mA

-

V_BAT= 2.8 V to 3.25 V;

3.2



I_V1= 250 mA

V_uvd

undervoltage detection voltage 5 V variants

V_uvd(nom)= 90 %

4.5

4

-

4.75

4.25

3.75

3.25

V

V_uvd(nom)= 80 %

V_uvd(nom)= 70 %

3.5

3

V_uvd(nom)= 60 %

-

3.3 V variants

V_uvd(nom)= 90 %

2.97

4.5

-

3.135

4.75

3.135

-

V

V_uvr

undervoltage recovery voltage 5 V variants (90 %)

3.3 V variants (90 %)

V

2.97

214

500

-

V

I_sink

sink current

V_BAT= 5.65 V to 18 V

mA

I_O(sc)

short-circuit output current

250

59

I_DD(CAN)intV1internal CAN supply current

from V1

Normal mode; MC = 111; CAN

Active mode; CAN dominant;

V_TXD= 0 V; short-circuit on bus

lines;

3V < (V_CANH= V_CANL) < +18 V

PNP base; pin VEXCTRL

I_O(sc)

short-circuit output current

V_VEXCTRL 4.5 V;

4.2

5.8

7.5

mA

V_BAT= 6 V to 28 V

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Table 53. Static characteristics …continued

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

V

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_th(act)PNP

PNP activation threshold

current

load current increasing; external

PNP transistor connected - see

Section 7.6.2

PDC 0

-

130

100

80

mA

[3]

PDC 0; T_vj= 150 C

PDC 1

60

-

83

-

PDC 1; T_vj= 150 C

36

50

59

I_th(deact)PNP

PNP deactivation threshold

current

load current falling; external PNP

transistor connected - see

Section 7.6.2

PDC 0

-

70

59

18

17

7.5

mA

V

[3]

PDC 0; T_vj= 150 C

PDC 1

26

-

44

-

PDC 1; T_vj= 150 C

6

11

-

V_th(Ictrl)PNP

PNP current control threshold rising edge on pin BAT

voltage

5.9

PNP collector; pin VEXCC

V_th(act)Ilimcurrent limiting activation

threshold voltage

measured across resistor

connected between pins VEXCC

and V1 (see Section 7.6.2);

2 V  V_V1 5.5 V;

240

-

330

mV

6 V < V_BAT< 28 V

Voltage source: V2 (UJA1169ATK, UJA1169ATK/F, UJA1169ATK/3 and UJA1169ATK/F/3 only)

V_O

output voltage

V_BAT= 5.8 V to 28 V;

I_V2= 100 mA to 0 mA

4.9

4.5

5.2

-

5

5.1

4.75

5.5

V



V_th(uvp)

V_th(ovp)

R_ON(BAT-V2)

I_O(sc)

undervoltage protection

threshold voltage

detection and recovery thresholds

-

overvoltage protection

threshold voltage

detection and recovery thresholds

-

ON resistance between pin

BAT and pin V2

V_BAT= 4.5 V to 5.8 V;

I_V2= 100 mA to 5 mA

-

8.7

short-circuit output current

250

-

100

mA

I_DD(CAN)intV2internal CAN supply current

from V2

Normal mode; MC = 111; CAN

Active mode; CAN dominant; V_TXD

= 0 V; short-circuit on bus lines;

3V < (V_CANH= V_CANL) < +18 V

-

59

Voltage source: VEXT (UJA1169ATK/X and UJA1169ATK/X/F only)

V_O

output voltage

V_BAT= 6 V to 28 V;

I_VEXT= 100 mA to 0 mA

4.9

4.5

5.2

5

-

5.1

V

V_th(uvp)

V_th(ovp)

undervoltage protection

threshold voltage

detection and recovery thresholds

4.75

5.5

overvoltage protection

threshold voltage

-

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NXP Semiconductors

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Table 53. Static characteristics …continued

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

V

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R_ON(BAT-VEXT)ON resistance between pin

BAT and pin VEXT

V_BAT= 4.5 V to 6 V;

I_VEXT= 100 mA to 5 mA

-

11



I_O(sc)

short-circuit output current

250

-

100

mA

Limp-home output (LIMP)

V_O

I_LO

output voltage

I_LIMP= 0.8 mA; LHC = 1;

T_vj= 40 C to T_{th(act)otp(max)}

-

0.4

+5

V

output leakage current

V_LIMP= 0 V to 28 V; LHC = 0

5

A

Serial peripheral interface inputs; pins SDI, SCK and SCSN

V_th(sw)

switching threshold voltage

0.25V_V1

0.05V_V1

-

0.75V_V1

-

V

V_th(sw)hys

switching threshold voltage

hysteresis

R_pd(SCK)

pull-down resistance on pin

SCK

40

60

80

k

R_pu(SCSN)

R_pd(SDI)

pull-up resistance on pin SCSN

40

60

80

k

pull-down resistance on pin

SDI

V_SDI< V_th(sw)

R_pu(SDI)

C_i

pull-up resistance on pin SDI

input capacitance

V_SDI> V_th(sw)

V_i= V_V1

40

-

60

3

80

6

k

[3]

pF

Serial peripheral interface data output; pin SDO

V_OH

HIGH-level output voltage

I_OH= 4 mA

V_V1

-

V

 0.4

V_OL

I_LO(off)

C_o

LOW-level output voltage

I_OL= 4 mA

-

0.4

+5

6

V

off-state output leakage current V_SCSN= V_V1; V_SDO= 0 V or V_V1

5

-

A

pF

[3]

output capacitance

SCSN = V_V1

3

CAN transmit data input; pin TXD

V_th(sw)

switching threshold voltage

0.25V_V1

0.05V_V1

-

0.75V_V1

-

V

V_th(sw)hys

switching threshold voltage

hysteresis

R_pu

pull-up resistance

40

60

-

80

-

k

CAN receive data output; pin RXD

V_OH

HIGH-level output voltage

I_OH= 4 mA

V_V1

V

 0.4

V_OL

R_pu

LOW-level output voltage

pull-up resistance

I_OL= 4 mA

-

0.4

80

V

CAN Offline mode

40

60

k

Local wake input; pin WAKE

V_th(sw)rrising switching threshold

2.8

2.4

-

4.1

V

voltage

V_th(sw)f

falling switching threshold

voltage

3.75

V_hys(i)

I_i

input hysteresis voltage

input current

250

-

800

1.5

mV

T_vj= 40 C to +85 C

A

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Table 53. Static characteristics …continued

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

V

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

High-speed CAN-bus lines; pins CANH and CANL

V_O(dom)

dominant output voltage

CAN Active mode; V_TXD= 0 V

pin CANH; R_L= 50  to 65 

pin CANL; R_L= 50  to 65 

2.75

0.5

3.5

1.5

-

4.5

V

2.25

+400

V

V_dom(TX)sym

V_TXsym

transmitter dominant voltage

symmetry

V_dom(TX)sym

V_CAN V_CANH V_CANL; V_CAN= 5 V

=

400

mV

[3]

[4]

transmitter voltage symmetry

V_TXsym= V_CANH+ V_CANL

f_TXD= 250 kHz, 1 MHz or 2.5 MHz;

C_SPLIT= 4.7 nF;

;

0.9V_CAN

-

1.1V_CAN

V

V_CAN= 4.75 V to 5.25 V

V_O(dif)

differential output voltage

CAN Active mode (dominant);

V_TXD= 0 V; V_CAN= 4.75 V to 5.5 V

R_L= 50  to 65 

R_L= 45  to 70 

R_L= 2240 

1.5

1.4

1.5

-

3.0

3.3

5.0

V

recessive; R_L= no load

CAN Active/Listen-only/Offline

Bias mode; V_TXD= V_V1

50

-

+50

mV

CAN Offline mode

0.2

-

+0.2

3

V

V_O(rec)

recessive output voltage

CAN Active mode; V_TXD= V_V1

R_L= no load

2

0.5V_CAN

CAN Offline mode;

R_L= no load

0.1

0

+0.1

3

V

CAN Offline Bias/Listen-only

modes; R_L= no load

2

2.5

I_O(sc)dom

dominant short-circuit output

current

CAN Active mode;

V_TXD= 0 V; V_CAN= 5 V

pin CANH;

3 V  V_CANH +27 V

55

-

mA

pin CANL;

15 V  V_CANL +18 V

+55

+3

I_O(sc)rec

recessive short-circuit output

current

V_CANL= V_CANH= 27 V to +32 V;

3

V_TXD= V_V1

V_th(RX)dif

differential receiver threshold

voltage

12 V  V_CANL +12 V;

12 V  V_CANH +12 V

CAN Active/Listen-only modes

CAN Offline mode

0.5

0.4

0.7

0.9

V

1.15

V_rec(RX)

receiver recessive voltage

12 V  V_CANL +12 V;

12 V  V_CANH +12 V

CAN Active/Listen-only modes

CAN Offline/Offline Bias modes

4^[3]

-

+0.5

+0.4

V

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Table 53. Static characteristics …continued

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

V

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_dom(RX)

receiver dominant voltage

12 V  V_CANL +12 V;

12 V  V_CANH +12 V

CAN Active/Listen-only modes

CAN Offline/Offline Bias modes

0.9

1.15

1

-

9.0^[3]

60

V

-

V

V_{th(RX)dif(hys)}differential receiver threshold

voltage hysteresis

CAN Active/Listen-only modes;

12 V  V_CANL +12 V;

30

mV

12 V  V_CANH +12 V

R_i

input resistance

2 V  V_CANL +7 V;

2 V  V_CANH +7 V

9

15

-

28

+1

52

20

k

%

R_i

input resistance deviation

differential input resistance

0 V  V_CANL +5 V;

0 V  V_CANH +5 V

1

19

-

R_i(dif)

C_i(cm)

2 V  V_CANL +7 V;

2 V  V_CANH +7 V

30

-

k

pF

[3]

common-mode input

capacitance

C_i(dif)

I_L

differential input capacitance

leakage current

-

10

+5

pF

V_BAT= V_CAN= 0 V or V_BAT= V_CAN

=

5

A

shorted to ground via 47 k; V_CANH

= V_CANL= 5 V

V_uvd(CAN)

V_uvr(CAN)

I_DD(CAN)

CAN undervoltage detection

voltage

on pin BAT; V_BATfalling

at V_CAN; see Section 7.10.3

V_BATrising

4.2

4.5

1

-

4.55

4.75

5

V

-

V

CAN undervoltage recovery

voltage

-

V

on V_CAN; see Section 7.10.3

-

4.75

6

V

[5]

CAN supply current

CAN Active mode; CAN recessive;

V_TXD= V_V1

3

mA

CAN Active mode; CAN dominant;

3

7.5

15

mA

V_TXD= 0 V;

R_L= no load

Temperature protection

T_th(act)otp

overtemperature protection

167

177

187

C

activation threshold

temperature

T_th(rel)otp

overtemperature protection

release threshold temperature

127

137

147

C

T_th(warn)otp

overtemperature protection

warning threshold temperature

Reset output; pin RSTN

V_OL

LOW-level output voltage

V_V1= 1.0 V to 5.5 V; pull-up resistor

0

-

0.2V_V1

V

to V_V1 900 

R_pu

pull-up resistance

40

60

-

80

k

V_th(sw)

switching threshold voltage

0.25V_V1

0.75V_V1

V

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Table 53. Static characteristics …continued

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

V

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_th(sw)hys

switching threshold voltage

hysteresis

0.05V_V1

-

V

MTP non-volatile memory

N_cy(W)MTPnumber of MTP write cycles

V_BAT= 6 V to 28 V;

-

200

-

T_vj= 0 C to +125 C

[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to

cover the specified temperature and power supply voltage range.

[2] See Figure 17.

[3] Not tested in production; guaranteed by design.

[4] The test circuit used to measure the bus output voltage symmetry (which includes C_SPLIT) is shown in Figure 23.

[5] From V1 in VEXT versions (UJA1169ATK/X and UJA1169ATK/X/F) and from V2 in other variants.

aaa-034449

100

I

BAT

(μA)

80

60

40

20

0

(1))

(2))

-50

-25

0

25

50

75

100

T

vj

(°C)

(1) Standby Mode: MC = 100, CWE = 1, CAN Offline mode, V_BAT= 12 V, I_V1= 0 A.

(2) Sleep mode: MC = 001, CAN Offline mode, V_BAT= 12 V.

Fig 17. UJA1169A typical Standby and Sleep mode quiescent current (A)

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11. Dynamic characteristics

Table 54. Dynamic characteristics

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

V_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Voltage source; pin V1

t_startup

start-up time

from V_BATexceeding the power-on

detection threshold until V_V1exceeds

the 90 % undervoltage threshold;

C_V1= 4.7 F

-

2.8

4.7

ms

t_d(uvd)

undervoltage detection delay

time

V_V1falling

6

-

54

63

s

t_d(uvd-RSTNL)

delay time from undervoltage undervoltage on V1

detection to RSTN LOW

Voltage source; pin V2 (UJA1169ATK, UJA1169ATK/F, UJA1169ATK/3 and UJA1169ATK/F/3)/VEXT(UJA1169ATK/X,

UJA1169ATK/X/F)

t_d(uvd)

undervoltage detection delay

time

V_V2/V_VEXTfalling

6

-

32

2.8

32

s

ms

s

at start-up of V_V2/V_VEXT

V_V2/V_VEXTfalling

2.2

6

2.5

-

t_d(ovd)

overvoltage detection delay

time

Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO; see Figure 20

t_cy(clk)

t_SPILEAD

t_SPILAG

t_clk(H)

clock cycle time

250

50

100

50

-

ns

SPI enable lead time

SPI enable lag time

clock HIGH time

-

t_clk(L)

clock LOW time

-

t_su(D)

data input set-up time

data input hold time

data output valid time

SDI to SDO delay time

-

t_h(D)

-

t_v(Q)

pin SDO; C_L= 20 pF

50

t_d(SDI-SDO)

SPI address bits and read-only bit;

C_L= 20 pF

-

t_WH(S)

chip select pulse width HIGH

pin SCSN

250

50

-

ns

t_{d(SCKL-SCSNL)}

delay time from SCK LOW to

SCSN LOW

CAN transceiver timing; pins CANH, CANL, TXD and RXD

[2]

[3]

t_{d(TXD-busdom)}

t_{d(TXD-busrec)}

t_{d(busdom-RXD)}

t_{d(busrec-RXD)}

t_d(TXDL-RXDL)

delay time from TXD to bus

dominant

-

80

105

120

-

ns

delay time from TXD to bus

recessive

-

delay time from bus dominant

to RXD

-

delay time from bus recessive

to RXD

-

delay time from TXD LOW to

RXD LOW

T_bit(TXD)= 200 ns

255

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Table 54. Dynamic characteristics …continued

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

V

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ Max

Unit

[3]

t_d(TXDH-RXDH)

delay time from TXD HIGH to T_bit(TXD)= 200 ns

RXD HIGH

-

255

ns

[3]

t_bit(bus)

transmitted recessive bit width t_bit(TXD)= 500 ns

t_bit(TXD)= 200 ns

435

155

400

120

65

45

0.5

-

530

210

550

220

+40

+15

1.8

ns

s

t_bit(RXD)

bit time on pin RXD

t_bit(TXD)= 500 ns

t_bit(TXD)= 200 ns

t_bit(TXD)= 500 ns

t_bit(TXD)= 200 ns

t_rec

receiver timing symmetry

bus dominant wake-up time

t_wake(busdom)

first pulse (after first recessive) for

wake-up on pins CANH and CANL;

CAN Offline mode

second pulse for wake-up on pins

CANH and CANL

0.5

-

1.8

s

t_wake(busrec)

bus recessive wake-up time

first pulse for wake-up on pins CANH

and CANL;

CAN Offline mode

second pulse (after first dominant) for

wake-up on pins CANH and CANL

0.5

0.8

2.7

0.95

-

1.8

10

s

ms

s

t_to(wake)bus

t_to(dom)TXD

t_to(silence)

bus wake-up time-out time

TXD dominant time-out time

bus silence time-out time

between first and second dominant

pulses; CAN Offline mode

CAN Active mode;

V_TXD= 0 V

3.3

recessive time measurement started

in all CAN modes

1.17

200

220

t_{d(busact-bias)}

t_startup(CAN)

delay time from bus active to

bias

s

CAN start-up time

to CTS = 1; when switching to Active

mode

-

CAN partial networking

[4]

N_bit(idle)

number of idle bits

before a new SOF is accepted;

CFDC = 1

6

5

-

10

-

[4]

[5]

t_fltr(bit)dom

dominant bit filter time

arbitration data rate  500 kbit/s;

CFDC = 1

17.5

%

Pin RXD: event capture timing (valid in CAN Offline mode only)

t_d(event)

t_blank

event capture delay time

blanking time

CAN Offline mode

0.9

-

1.1

25

ms

when switching from Offline to

Active/Listen-only mode

s

Watchdog

[6]

[8]

t_trig(wd)1

watchdog trigger time 1

watchdog trigger time 2

Normal mode; watchdog Window

mode only

0.45 

-

0.55  ms

NWP^[7]

t_trig(wd)2

Normal/Standby mode

0.9 

1.11  ms

NWP^[7]

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Table 54. Dynamic characteristics …continued

T_vj= 40 C to +150 C; V_BAT= 2.8 V to 28 V; V_CAN= V_V1(UJA1169ATK/X, UJA1169ATK/X/F);

_CAN= V_V2(UJA1169ATK, UJA1169ATK/3, UJA1169ATK/F, UJA1169ATK/F/3); R_L= R_(CANH-CANL)= 60 ; all voltages are

V

defined with respect to ground; positive currents flow into the IC; typical values are given at V_BAT= 13 V; unless otherwise

specified.^[1]

Symbol

Parameter

Conditions

Min

Typ Max

Unit

[4]

t_{d(SCSNH-RSTNL)}delay time from SCSN HIGH to rising edge to falling edge; watchdog

-

0.2

ms

RSTN LOW

in window mode, triggered in the

first half of the watchdog period

(before t_trig(wd)1

)

Pin RSTN: reset pulse width

t_w(rst)

reset pulse width

output pulse width

RLC = 00

20

10

3.6

1

-

25

12.5

5

ms

s

RLC = 01

RLC = 10

RLC = 11

1.5

-

input pulse width

18

Pin LIMP

t_d(limp)

limp delay time

wake-up time

117

50

-

145

-

ms

s

s

Pin WAKE

t_wake

MTP non-volatile memory

t_d(MTPNV)

MTPNV delay time

before factory presets are restored;

V_BAT= 6 V to 28 V

0.9

1.1

t_ret(data)

data retention time

T_vj= 85 C

20

10

-

year

ms

t_prog(MTPNV)

MTPNV programming time

correct CRC code received at

12

14

address 075h; V_BAT= 6 V to 28 V

Mode transition

t_d(act)norm

normal mode activation delay MC = 111; delay before CAN is

-

320

s

time

activated after the SBC switches to

Normal mode

[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to

cover the specified temperature and power supply voltage range.

[2] See Figure 18 and Figure 22.

[3] See Figure 19 and Figure 22.

[4] Not tested in production; guaranteed by design.

[5] Up to 2 Mbit/s data speed.

[6] A system reset will be performed if the watchdog is in Window mode and is triggered earlier than t_trig(wd)1after the start of the watchdog

period (thus in the first half of the watchdog period).

[7] The nominal watchdog period is programmed via the NWP control bits.

[8] The watchdog will be reset if it is in window mode and is triggered after t_trig(wd)1, but not later than t_trig(wd)2, after the start of the watchdog

period (thus, in the second half of the watchdog period). If the watchdog is triggered later than t_trig(wd)2after the start of the watchdog

period (watchdog overflow), a system reset will be performed.

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HIGH

70 %

TXD

30 %

LOW

CANH

CANL

dominant

0.9 V

V

O(dif)

0.5 V

recessive

HIGH

70 %

RXD

30 %

LOW

t

d(TXD-busrec)

d(TXD-busdom)

t

d(busdom-RXD)

d(busrec-RXD)

aaa-029311

Fig 18. CAN transceiver timing diagram

70 %

TXD

30 %

t

5 x t

d(TXDL-RXDL)

bit(TXD)

t

bit(TXD)

0.9 V

V

O(dif)

0.5 V

t

bit(bus)

70 %

RXD

30 %

t

d(TXDH-RXDH)

t

bit(RXD)

aaa-029312

Fig 19. CAN FD timing definitions according to ISO 11898-2:2016

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SCSN

t

SPILEAD

SPILAG

t

cy(clk)

WH(S)

t

clk(H) clk(L)

t

d(SCKL-SCSNL)

SCK

X

t

h(D)

t

h(D)

(1)

(2)

v(Q)

t

su(D)

SDI

X

MSB

LSB

X

t

d(SDI-SDO)

SDO

X

MSB

LSB

X

time

aaa-027898

(1) The SDI-to-SDO delay time is valid for SPI address bits and the read-only bit.

(2) The data output valid time is valid for the SPI data bits.

Fig 20. SPI timing diagram

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12. Application information

12.1 Application diagram

close to PNP

PHPT61003PY

1.6 Ω

10 nF

VEXCTRL

15

VEXCC

(depending on PNP

battery

and current balancing)

6

V1

5

6.8 μF

BAT

14

V

CC

RSTN

SCSN

SDO

SCK

SDI

8

20

9

RSTN

22 μF

47 nF

10 kΩ

MICRO-

CONTROLLER

LIMP

WAKE

CANH

to application

11

12

18

standard

μC ports

application

2 kΩ

off-board switch

(example application)

10

3

10 kΩ

UJA1169A

RXD

TXD

10 nF

7

RXD

TXD

2

V

SS

60 Ω

other on-board loads

4.7 nF

in variants with V2 supply

V2/VEXT

13

CANL

off-board loads up to 100 mA

in variants with VEXT supply

17

6.8 μF

1, 4, 16, 19

GND

aaa-033698

The application diagram contains example components and component values. A PHPT60603PY transistor could be used in

place of the PHPT61003PY.

Fig 21. Typical application using the UJA1169A

12.2 Application hints

Further information on the application of the UJA1169A can be found in the NXP

application hints document AH1902 Application Hints - Mini high speed CAN system basis

chips UJA116xA.

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13. Test information

TXD

RXD

CANH

CANL

R

C

L

60 Ω

100 pF

15 pF

aaa-030850

Fig 22. Timing test circuit for CAN transceiver

TXD

CANH

CANL

30 Ω

f

TXD

C

SPLIT

4.7 nF

RXD

aaa-030851

Fig 23. Test circuit for measuring transceiver driver symmetry

13.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for

integrated circuits, and is suitable for use in automotive applications.

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14. Package outline

HVSON20: plastic thermal enhanced extremely thin quad flat package; no leads;

20 terminals; body 3.5 x 5.5 x 0.85 mm

SOT1360-1

X

D

B

A

E

A

1

C

detail X

terminal 1

index area

terminal 1

index area

e

C

1

v

w

C A

C

B

e

b

y

1

y

C

1

10

L

K

E

h

20

11

D

h

0

3

6 mm

w

scale

Dimensions

Unit

(1)

A

b

C

D

h

E

e

1

K

L

v

y

1

h

max 1.00 0.05 0.30

nom 0.85 0.03 0.25 0.2

min 0.80 0.00 0.20

5.6 4.85 3.6 1.85

5.5 4.80 3.5 1.80 0.5 4.5

5.4 4.75 3.4 1.75

0.40 0.55

0.35

0.50

mm

0.1 0.05 0.05 0.1

0.30 0.45

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot1360-1_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

15-05-13

15-07-06

SOT1360-1

MO-240

Fig 24. Package outline SOT1360-1 (HVSON20)

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15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

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• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 25) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 55 and 56

Table 55. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 56. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 25.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 25. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17. Soldering of HVSON packages

Section 16 contains a brief introduction to the techniques most commonly used to solder

Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON

leadless package ICs can be found in the following application notes:

• AN10365 ‘Surface mount reflow soldering description”

• AN10366 “HVQFN application information”

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18. Appendix: ISO 11898-2:2016 parameter cross-reference list

Table 57. ISO 11898-2:2016 to NXP data sheet parameter conversion

ISO 11898-2:2016

NXP data sheet

Notation Symbol Parameter

Parameter

HS-PMA dominant output characteristics

Single ended voltage on CAN_H

Single ended voltage on CAN_L

Differential voltage on normal bus load

Differential voltage on effective resistance during arbitration

Optional: Differential voltage on extended bus load range

HS-PMA driver symmetry

V_{CAN_H}

V_{CAN_L}

V_Diff

V_O(dom)

dominant output voltage

differential output voltage

V_O(dif)

Driver symmetry

V_SYM

V_TXsym

transmitter voltage symmetry

Maximum HS-PMA driver output current

Absolute current on CAN_H

I_{CAN_H}

I_{CAN_L}

I_O(sc)dom

dominant short-circuit output

current

Absolute current on CAN_L

HS-PMA recessive output characteristics, bus biasing active/inactive

Single ended output voltage on CAN_H

Single ended output voltage on CAN_L

Differential output voltage

V_{CAN_H}

V_{CAN_L}

V_Diff

V_O(rec)

recessive output voltage

differential output voltage

TXD dominant time-out time

V_O(dif)

Optional HS-PMA transmit dominant timeout

Transmit dominant timeout, long

t_dom

t_to(dom)TXD

Transmit dominant timeout, short

HS-PMA static receiver input characteristics, bus biasing active/inactive

Recessive state differential input voltage range

Dominant state differential input voltage range

V_Diff

V_th(RX)dif

differential receiver threshold

voltage

V_rec(RX)

receiver recessive voltage

receiver dominant voltage

V_dom(RX)

HS-PMA receiver input resistance (matching)

Differential internal resistance

R_Diff

R_i(dif)

R_i

differential input resistance

input resistance

Single ended internal resistance

R_{CAN_H}

R_{CAN_L}

Matching of internal resistance

HS-PMA implementation loop delay requirement

Loop delay

MR

R_i

input resistance deviation

t_Loop

t_d(TXDH-RXDH)delay time from TXD HIGH to

RXD HIGH

t_d(TXDL-RXDL)

delay time from TXD LOW to RXD

LOW

Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to

2 Mbit/s and above 2 Mbit/s up to 5 Mbit/s

Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,

intended

t_Bit(Bus)

t_bit(bus)

transmitted recessive bit width

Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s

Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s

t_Bit(RXD)

t_bit(RXD)

bit time on pin RXD

t_Rec

t_rec

receiver timing symmetry

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Table 57. ISO 11898-2:2016 to NXP data sheet parameter conversion

ISO 11898-2:2016

NXP data sheet

Notation Symbol Parameter

Parameter

HS-PMA maximum ratings of V_{CAN_H}, V_{CAN_L}and V_Diff

Maximum rating V_Diff

V_Diff

V_(CANH-CANL)voltage between pin CANH and

pin CANL

General maximum rating V_{CAN_H}and V_{CAN_L}

V_{CAN_H}

V_{CAN_L}

V_x

voltage on pin x

Optional: Extended maximum rating VCAN_H and VCAN_L

HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered

Leakage current on CAN_H, CAN_L

I_{CAN_H}

I_{CAN_L}

I_L

leakage current

Number of recessive bits before next SOF

Number of recessive bits before a new SOF shall be

n_{Bits_idle}

N_bit(idle)

number of idle bits

dominant bit filter time

accepted

Bitfiter in CAN FD data phase

CAN FD data phase bitfilter (option 1)

pBitfilter_opt_fltr(bit)dom

tion1

HS-PMA bus biasing control timings

CAN activity filter time, long

CAN activity filter time, short

Wake-up timeout, short

[1]

t_Filter

t_wake(busdom)

bus dominant wake-up time

bus recessive wake-up time

bus wake-up time-out time

[1]

t_wake(busrec)

t_to(wake)bus

t_Wake

Wake-up timeout, long

Timeout for bus inactivity

Bus Bias reaction time

t_Silence

t_Bias

t_to(silence)

bus silence time-out time

t_{d(busact-bias)}

delay time from bus active to bias

[1] t_{fltr(wake)bus}- bus wake-up filter time, in devices with basic wake-up functionality

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19. Revision history

Table 58. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

UJA1169A v.1

20200512

Product data sheet

-

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20. Legal information

20.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

20.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

20.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

UJA1169A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 12 May 2020

78 of 80

UJA1169A

NXP Semiconductors

Mini high-speed CAN SBC with optional partial networking

22. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.4

7.5

7.6

Reset sources . . . . . . . . . . . . . . . . . . . . . . . . 18

Global temperature protection . . . . . . . . . . . . 18

Power supplies. . . . . . . . . . . . . . . . . . . . . . . . 18

Battery supply voltage (V_BAT). . . . . . . . . . . . . 18

Voltage regulator V1 . . . . . . . . . . . . . . . . . . . 19

Voltage regulator V2 . . . . . . . . . . . . . . . . . . . 20

Voltage regulator VEXT . . . . . . . . . . . . . . . . . 20

Regulator control register. . . . . . . . . . . . . . . . 21

Supply voltage status register . . . . . . . . . . . . 21

LIMP output . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reset counter. . . . . . . . . . . . . . . . . . . . . . . . . 22

LIMP state diagram . . . . . . . . . . . . . . . . . . . . 23

Fail-safe control register . . . . . . . . . . . . . . . . 24

High-speed CAN transceiver . . . . . . . . . . . . . 24

CAN operating modes . . . . . . . . . . . . . . . . . . 25

CAN Active mode. . . . . . . . . . . . . . . . . . . . . . 25

CAN Listen-only mode. . . . . . . . . . . . . . . . . . 25

CAN Offline and Offline Bias modes . . . . . . . 26

CAN Off mode . . . . . . . . . . . . . . . . . . . . . . . . 26

CAN standard wake-up (partial networking

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Designed for automotive applications. . . . . . . . 2

Low-drop voltage regulator for 5 V/3.3 V

microcontroller supply (V1). . . . . . . . . . . . . . . . 2

On-board CAN supply (V2; UJA1169ATK,

UJA1169ATK/F, UJA1169ATK/3 and

UJA1169ATK/F/3 only) . . . . . . . . . . . . . . . . . . . 2

Off-board sensor supply (VEXT;

UJA1169ATK/X and UJA1169ATK/X/F only) . . 3

Power Management . . . . . . . . . . . . . . . . . . . . . 3

System control and diagnostic features . . . . . . 3

2.1

2.2

2.3

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.6

7.7

7.7.1

7.7.2

7.7.2.1

7.8

7.8.1

7.8.1.1

7.8.1.2

7.8.1.3

7.8.1.4

7.8.2

2.4

2.5

2.6

2.7

3

4

5

Product family overview . . . . . . . . . . . . . . . . . . 4

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

not enabled). . . . . . . . . . . . . . . . . . . . . . . . . . 28

CAN control register. . . . . . . . . . . . . . . . . . . . 28

Transceiver status register. . . . . . . . . . . . . . . 29

CAN partial networking (UJA1169A /F variants

only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Wake-up frame (WUF). . . . . . . . . . . . . . . . . . 30

CAN FD frames . . . . . . . . . . . . . . . . . . . . . . . 32

CAN partial networking configuration

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Data rate register . . . . . . . . . . . . . . . . . . . . . . 33

ID registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

ID mask registers. . . . . . . . . . . . . . . . . . . . . . 33

Frame control register . . . . . . . . . . . . . . . . . . 34

Data mask registers. . . . . . . . . . . . . . . . . . . . 34

CAN fail-safe features . . . . . . . . . . . . . . . . . . 35

TXD dominant time-out . . . . . . . . . . . . . . . . . 35

Pull-up on TXD pin. . . . . . . . . . . . . . . . . . . . . 35

V_CANundervoltage event . . . . . . . . . . . . . . . . 35

Loss of power at pin BAT. . . . . . . . . . . . . . . . 36

Wake-up and interrupt event handling . . . . . . 36

WAKE pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7

7.1

7.1.1

Functional description . . . . . . . . . . . . . . . . . . . 7

System controller . . . . . . . . . . . . . . . . . . . . . . . 7

Operating modes . . . . . . . . . . . . . . . . . . . . . . . 7

Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 7

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Off mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . 10

Forced Normal mode . . . . . . . . . . . . . . . . . . . 10

Hardware characterization for the UJA1169A

operating modes. . . . . . . . . . . . . . . . . . . . . . . 11

System control registers. . . . . . . . . . . . . . . . . 11

Mode control register . . . . . . . . . . . . . . . . . . . 11

Main status register . . . . . . . . . . . . . . . . . . . . 12

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Watchdog overview . . . . . . . . . . . . . . . . . . . . 12

Watchdog control register. . . . . . . . . . . . . . . . 13

SBC configuration control register . . . . . . . . . 14

Watchdog status register . . . . . . . . . . . . . . . . 15

Software Development mode . . . . . . . . . . . . . 15

Watchdog behavior in Window mode . . . . . . . 15

Watchdog behavior in Timeout mode . . . . . . . 16

Watchdog behavior in Autonomous mode . . . 16

System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Characteristics of pin RSTN . . . . . . . . . . . . . . 17

Selecting the output reset pulse width . . . . . . 17

Start-up control register . . . . . . . . . . . . . . . . . 17

7.8.2.1

7.8.2.2

7.9

7.1.1.1

7.1.1.2

7.1.1.3

7.1.1.4

7.1.1.5

7.1.1.6

7.1.1.7

7.1.1.8

7.9.1

7.9.2

7.9.3

7.9.3.1

7.9.3.2

7.9.3.3

7.9.3.4

7.9.3.5

7.10

7.10.1

7.10.2

7.10.3

7.10.4

7.11

7.1.2

7.1.2.1

7.1.2.2

7.2

7.2.1

7.2.1.1

7.2.1.2

7.2.1.3

7.2.2

7.2.3

7.2.4

7.2.5

7.3

7.11.1

7.11.1.1 WAKE pin status register . . . . . . . . . . . . . . . . 36

7.11.2

7.11.3

7.11.4

7.11.5

Wake-up diagnosis. . . . . . . . . . . . . . . . . . . . . 36

Interrupt/wake-up delay . . . . . . . . . . . . . . . . . 38

Sleep mode protection. . . . . . . . . . . . . . . . . . 38

Event status and event capture registers. . . . 39

7.3.1

7.3.2

7.3.2.1

7.11.5.1 Event status registers . . . . . . . . . . . . . . . . . . 39

7.11.5.2 Event capture enable registers . . . . . . . . . . . 41

continued >>

UJA1169A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 12 May 2020

79 of 80

UJA1169A

NXP Semiconductors

Mini high-speed CAN SBC with optional partial networking

7.12

7.12.1

Non-volatile SBC configuration. . . . . . . . . . . . 42

Programming MTPNV cells . . . . . . . . . . . . . . 42

7.12.1.1 MTPNV status register . . . . . . . . . . . . . . . . . . 43

7.12.1.2 MTPNV CRC control register . . . . . . . . . . . . . 44

7.12.2

7.13

7.13.1

7.14

7.14.1

7.15

7.16

7.16.1

7.16.2

7.16.3

Restoring factory preset values . . . . . . . . . . . 45

Device identification . . . . . . . . . . . . . . . . . . . . 45

Device identification register. . . . . . . . . . . . . . 45

Register locking . . . . . . . . . . . . . . . . . . . . . . . 45

Lock control register . . . . . . . . . . . . . . . . . . . . 45

General-purpose memory. . . . . . . . . . . . . . . . 46

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Register map . . . . . . . . . . . . . . . . . . . . . . . . . 49

Register configuration in UJA1169A

operating modes. . . . . . . . . . . . . . . . . . . . . . . 51

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 54

Thermal characteristics . . . . . . . . . . . . . . . . . 55

Static characteristics. . . . . . . . . . . . . . . . . . . . 56

Dynamic characteristics . . . . . . . . . . . . . . . . . 63

9

10

11

12

12.1

12.2

Application information. . . . . . . . . . . . . . . . . . 68

Application diagram . . . . . . . . . . . . . . . . . . . . 68

Application hints . . . . . . . . . . . . . . . . . . . . . . . 68

13

13.1

14

Test information. . . . . . . . . . . . . . . . . . . . . . . . 69

Quality information . . . . . . . . . . . . . . . . . . . . . 69

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 70

Handling information. . . . . . . . . . . . . . . . . . . . 71

15

16

Soldering of SMD packages . . . . . . . . . . . . . . 71

Introduction to soldering . . . . . . . . . . . . . . . . . 71

Wave and reflow soldering . . . . . . . . . . . . . . . 71

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 71

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 72

16.1

16.2

16.3

16.4

17

18

Soldering of HVSON packages. . . . . . . . . . . . 73

Appendix: ISO 11898-2:2016 parameter

cross-reference list . . . . . . . . . . . . . . . . . . . . . 74

19

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 76

20

Legal information. . . . . . . . . . . . . . . . . . . . . . . 77

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 77

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 78

20.1

20.2

20.3

20.4

21

22

Contact information. . . . . . . . . . . . . . . . . . . . . 78

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 May 2020

Document identifier: UJA1169A


型号：	UJA1169ATK/3
厂家：	NXP
描述：	Mini high-speed CAN system basis chip
文件：	总80页 (文件大小：935K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UJA1169ATK/3 [NXP]

相关型号：

UJA1169ATK/F

UJA1169ATK/F/3

UJA1169ATK/X

UJA1169ATK/X/F

UJA1169L

UJA1169LTK

UJA1169LTK/F

UJA1169LTK/X

UJA1169LTK/X/F

UJA1169TK

UJA1169TK/3

UJA1169TK/F