XA-H3 [NXP]
CMOS 16-bit highly integrated microcontroller; CMOS 16位高度集成的微控制器
| 型号： | XA-H3 |
| 厂家： | 
NXP |
| 描述： | CMOS 16-bit highly integrated microcontroller |
| 文件： | 总36页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
XA-H3
CMOS 16-bit highly integrated
microcontroller
Preliminary specification
IC28 Data Handbook
1999 Sep 24
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
DESCRIPTION
The powerful 16-bit XA CPU core and rich feature set make the
XA-H3 and XA-H4 devices ideal for high-performance real-time
applications such as industrial control and networking. By supporting
of up to 32 MB of external memory, these devices provide a low-cost
solution to embedded applications of any complexity. Features like
DMA, memory controller and four advanced UARTs help solve I/O
intensive tasks with a minimum of CPU load.
The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The
XA-H3/H4 devices are members of the Philips XA (eXtended
Architecture) family of high performance 16-bit microcontrollers.
The XA-H3 and XA-H4 are designed to significantly minimize the
need for external components.
FEATURES
• Large Memory Support (up to 6 MB external)
• Dynamic Bus Timing – each of 6 chip selects has individual
programmable bus timing.
• De-multiplexed Address/Data Bus
• Six Programmable Chip Selects
– Support for Unified Memory – allows easy user modification of
all code
• 32 Programmable General Purpose I/O Pins
• Four UARTs with 230.4 kbps capability
• Eight DMA Channels
– External ISP Flash support for easy code download
• Dynamic Bus Sizing – each of 6 Chip Selects can be programmed
for 8-bit or 16-bit bus.
Table 1. XA-H3 and XA-H4 features comparison
Feature
XA-H3
XA-H4
Maximum External Memory
(Harvard Memory Mode)
6 MB
32 MB
(16 MB Code, 16 MB Data)
Maximum External Memory (Unified Memory Mode)
Memory Controller supports both Harvard and Unified architectures
De-multiplexed Address/Data Bus
DRAM Controller
6 MB
16 MB
Yes
Yes
Yes
Yes
No
Yes
DMA Channels
8
8
Dynamic Bus Sizing
Yes
Yes
Dynamic Bus Timing
Yes
Yes
Programmable Chip Selects
General Purpose IO Pins
6
6
33
33
Potential Interrupt Pins
16
16
Interrupts (programmable priority)
7 Standard SW
4 High Priority SW
13 Hardware Event
7 Standard SW
4 High Priority SW
13 Hardware Event
Counter/Timers
2 plus Watchdog
2 plus Watchdog
1
Baud Rate Generators
4
4
Serial Ports
4 UARTS
4 USARTS
Maximum Serial Data Rates
asynch to 230.4 kbps (no sync)
asynch to 230.4 kbps
sync to 1 Mbps
Match Characters
Hardware Autobaud
SCP/SPI Bus
No
No
No
4 async chars per USART
up to 230.4 kbps
NOTE:
1. Can be used as additional counters if not needed as BRGs.
2
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
ORDERING INFORMATION
ROMless Only
H3 = PXAH30KFBE
NOTE
Temperature range °C and Package
Freq (MHz)
Package Drawing Number
30
SOT407-1
–40 to +85°C, 100-Pin Low Profile Quad Flat Package (LQFP)
K=30 MHz, F = (–40 to +85), BE = LQFP
PIN CONFIGURATION
VSS
VDD
A0
1
2
3
4
5
6
7
8
9
75 P1.7_BRG2
74 P1.6_RTS2
73 P1.5_CTS2
72 P1.4_CD2
71 P1.3_TRClk2
70 P1.2_RTClk2
69 P1.1_TxD2
68 P1.0_RxD2
67 P3.7_Int1_TRClk1
66 P3.6_TxD1
65 P3.5_RxD1
64 P3.4_CTS1
63 P3.3_Timer1_BRG1
62 VDD
A1
MOLD MARK
A2
A3
A4
A5
A6
A7 10
A8 11
XA-H3
A9 12
Top View 100 Pin LQFP
Part Number: PXAH30KFBE
A10 13
A11 14
A12 15
A13 16
A14 17
A15 18
VSS 19
VDD 20
A16 21
A17 22
A18 23
A19 24
D0 25
K = 30 MHz, F = –40 to +85°C, BE = LQFP pkg
LQFP Package = SOT407-1
61 XTALOUT
60 XTALIN
59 VSS
58 P3.2_Timer0_ResetOut
57 P3.1_CS5_RTS1
56 P3.0_CS4_RTClk1
55 Reset_In
MOLD MARK
54 BLE
53 BHE
52 WAIT_Size16
51 OE
SU01234
3
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
LOGIC SYMBOL XA-H3
V
DD
V
SS
Int0
XTAL1
XTAL2
MISC.
Int2
UART1
PORT3
CD1
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
CS4
CS5
RTClk1
RTS1
ResetOut, Timer0
Timer1
BRG1
CTS1
RxD1
TxD1
TRClk1
CS3
CS2
CS1
CS0
Int1
UART3
PORT2
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
RxD3
TxD3
RTClk3
ComClk, TRClk3
CD3
A19 – A0
D15 – D0
CTS3
RTS3
BRG3
UART2
PORT1
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
RxD2
TxD2
RTClk2
TRClk2
CD2
CTS2
RTS2
BRG2
ClkOut
BHE
BLE
OE
WE
UART0
PORT0
TxD0
RxD0
Wait, Size16
ResetIn
0.0
0.1
0.2
0.3
0.4
0.5
BRG0
RTS0
CTS0
CD0
TRClk0
RTClk0
0.6
0.7
GPOut
SU01235
4
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
XA-H3 BLOCK DIAGRAM
XA-H3 CPU Core
Data
256 Bytes Data
SRAM
MMR Bus
SFR Bus
DMA R0
DMA T0
UART 0
UART 1
UART 2
UART 3
Port 0
Port 1
Port 2
DMA R1
DMA T1
DMA R2
DMA T2
Port 3
Timer 0
DMA R3
DMA T3
Timer 1
Watchdog
Timer
Memory Bus Controller
6 Chip Selects
Dynamic Bus Sizing
Dynamic Bus Timing
External
System Bus
SU01247
5
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
XA-H3 MEMORY MAPS
FFFFFFh
6 MB *
Common Code
and Data Space
000000h
Unified Memory
(von Neuman architecture)
*In either memory architecture, the XA-H3 can support a maximum of
6 MB because each of six Chip Selects is capable of 1 MB each. In
Unified architecture, Code and Data can share the same physical
Memory Chip and address space.
Code Space + Data Space = 6 MB Maximum Total with 1 MB per Chip Select. Each CS
(and thus, 1 MB space) can support either Code or Data in Harvard architecture.
FFFFFFh
FFFFFFh
Dedicated
Code Space
Dedicated
Data Space
000000h
000000h
Harvard Architecture
SU01248
6
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
PIN DESCRIPTIONS
Lqfp
Pin No.
See
Note
Mnemonic
Type
Name and Function
V
SS
1, 19, 28,
44, 59,
76, 88
Ground: 0 V reference.
I
V
DD
2, 20, 29,
43, 62,
77, 89
Power Supply: This is the power supply voltage for normal, idle, and power down operation.
I
Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on
their default states, and the processor to begin execution at the address contained in the reset
vector.
ResetIn
55
52
I
I
WAIT/
Size16
Wait/Size16: During Reset, this input determines bus size for boot device (“1” = 16-bit boot device;
“0” = 8-bit.) During normal operation this is the Wait input (“1” = Wait; “0” = Proceed.)
Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock
generator circuits.
XTALIn
60
61
I
I
XTALOut
Crystal 2: Output from the oscillator amplifier.
Chip Select 0: This output provides the active low chip select to the boot device (usually ROM or
Flash.) From reset, it is enabled and mapped to an address range based at 000000h. It can be
remapped by software to a higher base in the address map (see the “Memory Interface” chapter in
the XA-H3 User Manual.)
CS0
CS1
49
48
O
O
Chip Select 1*: Chip Selects 1 through 5 come out of reset disabled. They function as normal chip
selects on the H3. CS1 can be “swapped” with CS0 (see the SWAP operation in the “Memory
Controller” chapter of the XA-H3 User Manual.) CS1 is usually mapped to be based at 000000h
after the swap, but is capable of being based anywhere in the 16 MB address space.
CS2
CS3
47
46
O
O
Chip Select 2 *: Active low Chip Selects CS1 through CS5 come out of reset disabled. They can
be programmed to function as normal chip selects. CS2 through CS5 are not used with the
“SWAP” operation (only /CS0 and CS1 can be swapped; see “Memory Controller” chapter in the
XA-H3 User Manual.) They are mappable to any region of the 16 MB address space.
Chip Select 3 *: See Chip Select 2 for description.
See Pins 56, 57 for 2 additional Chip Selects
WE
OE
50
51
54
O
O
O
Write Enable: Goes active low during all bus write cycles only.
Output Enable: Goes active low during all bus read cycles only.
BLE
Byte Low Enable: Goes active low during all bus cycles that access data bus lines D7 – D0, read
or write.
BHE
53
O
Byte High Enable: Goes active low during all bus cycles that access data bus lines D15 – D8,
read or write. Never goes active on an 8-bit bus; always goes active on Reads or Fetches on a
16-bit bus, even if the processor does not need these bits. In other words, all Reads (byte or word)
on a 16-bit bus, assert BHE.
ClkOut
45
O
Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may
be used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock
output may be disabled by software. WARNING: The capacitive loading on this output must not
exceed 40 pf.
A19 – A0
D15 – D0
24 – 21,
18 – 3
O
Address[19:0]: These address lines output A19 – A0 during all external bus cycles.
42 – 30,
27 – 25
I/O
Data[15:0]: Bi-directional data bus, D15 – D0; for those bus cycles that are programmed to occur
on an “8-bit bus”, D15 – D8 are unused.
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
TxD0
90
91
92
93
94
95
99
100
96
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
P0.0_BRG0*: Port 0 Bit 0, or UART0 BRG output, or UART0 TxClk output
P0.1_RTS0: Port 0 Bit 1 , or UART0 RTS (Request To Send) output.
P0.2_CTS0: Port 0 Bit 2, or UART0 CTS (Clear To Send) input.
P0.3_CD0: Port 0 Bit 3, or UART0 Carrier Detect input.
P0.4_TRClk0: Port 0 Bit 4, or UART0 TR clock input.
P0.5_RTClk0: Port 0 Bit 5, or UART0 RT clock input.
P0.6: Port 0 Bit 6
1
1
1
1
1, 2
1, 2
1
P0.7: Port 0 Bit 7
1
TxD0: Transmit data for UART0.
7
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Lqfp
Pin No.
See
Note
Mnemonic
Type
Name and Function
RxD0
97
I
RxD0: Receive data for UART0
GPOut
98
O
GPOut – General Purpose Output Bar: Similar to GPIO, but Push/Pull and inverted output only.
WARNING: This output is inverted. The polarity of the pin is the opposite of the bit that drives it
(GPOut[7])
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
68
69
70
71
72
73
74
75
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1.0_RxD2: Port 1 Bit 0, or UART2 RxD input
P1.1_TxD2: Port 1 Bit 1, or UART2 TxD output
P1.2_RTClk2: Port 1 Bit 2, or UART2 RT Clock input
P1.3_TRClk2: Port 1 Bit 3, or UART2 TR Clock input
P1.4_CD2: Port 1 Bit 4, or UART2 Carrier Detect input
P1.5_CTS2: Port 1 Bit 5, or UART2 Clear To Send input
P1.6_RTS2: Port 1 Bit 6, or UART2 Request To Send output
2
2
P1.7_BRG2: Port 1 Bit 7, or BRG output, or TxClk output (see UART clk diagrams in the XA-H3
User Manual.)
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
80
81
82
83
84
85
86
87
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P2.0_RxD3: Port 2 Bit 0, or UART3 Rx Data input
P2.1_TxD3: Port 2 Bit 1, or UART3 Tx Data output
P2.2_RTClk3: Port 2 Bit 2, or UART3 RT Clock input
P2.3_ComClk_TRClk3: Port 2 Bit 3, or UART3 TR Clock input
P2.4_CD3: Port 2 Bit 4, or UART3 Carrier Detect input
P2.5_CTS3: Port 2 Bit 5, or UART3 Clear To Send input
P2.6_RTS3: Port 2 Bit 6, or UART3 Request To Send output
2
2
P2.7_BRG3: Port 2 Bit 7, or BRG output, or TxClk output (see UART clock diagrams in the XA-H3
User Manual.)
P3.0
56
I/O
P3.0_CS4_RTClk1: Port 3 Bit 0, or CS4 output, or UART1 RT Clock input
2
Active low chip selects CS1 through CS5 come out of reset disabled. CS2 through CS5 are not
used with the “SWAP” operation (see “Memory Controller” chapter in the XA-H3 User Manual.)
They are mappable to any region of the 16 MB address space.
P3.1_CS5_RTS1: Port 3 Bit 1, or CS5 output, or UART1 Request To Send output
Active low chip selects CS1 through CS5 come out of reset disabled. CS2 through CS5 are not
used with the “SWAP” operation (see “Memory Controller” chapter in the XA-H3 User Manual.)
They are mappable to any region of the 16 MB address space.
P3.1
57
I/O
P3.2_Timer0_ResetOut: Port 3 Bit 2, or Timer0 input or output, or ResetOut output.
ResetOut: If the ResetOut function is selected, this pin outputs a low whenever the XA-H3
processor is reset by an internal source (Watchdog Reset or the RESET instruction.)
WARNING: Unlike the other 31 GPIO pins, during power up reset, this pin can output a strongly
driven low pulse. The duration of this low pulse ranges from 0 ns to 258 system clocks, starting at
the time that VCC is valid. The state of the ResetIn pin does not affect this pulse; in other words
ResetIn is not passed to ResetOut.
P3.2
58
I/O
When used as GPIO, this pin can also be driven low by software without resetting the XA-H3.
P3.3_Timer1_BRG1: Port 3 Bit 3, or Timer1 input or output, or UART1 BRG output.
P3.4_CTS1: Port 3 Bit 4, or UART1 Clear To Send input
P3.3
P3.4
63
64
65
66
67
78
79
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P3.5
P3.5_RxD1: Port 3 Bit 5, or UART1 Receive Data input
P3.6
P3.6_TxD1: Port 3 Bit 6, or UART1 Transmit Data output
P3.7
P3.7_Int1_TRClk1: Port 3 Bit 7, or External Interrupt 1 input, or UART1 TR Clock input
CD1_Int2: UART1 Carrier Detect, or External Interrupt 2
2
CD1_Int2
Int0
External Interrupt 0
NOTES:
1. See XA-H3 User Guide, “Pins Chapter,” for how to program selection of pin functions.
2. RTClk input is usually used for Rx Clock if an external clock is needed, but can be used for either Rx or Tx or both. TRClk is usually used for
Tx Clock, but can be used for Rx or Tx or both.
8
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
CONTROL REGISTER OVERVIEW
There are two types of control registers in the XA-H3, these are SFRs
(Special Function Registers), and MMRs (Memory Mapped Registers.)
The SFR registers, with the exception of MRBL, MRBH, MICFG, BCR,
BRTH, BRTL, and RSTSRC are the standard XA core registers. See
WARNINGs about BCR, BRTH, and BRTL in Table 2.
on-chip peripherals, and can be accessed by any addressing mode
that can be used for off-chip data accesses. The MMRs are
implemented in a relocatable block. See the “Memory Controller”
chapter in the XA-H3 User Manual for details on how to relocate the
MMRs by writing a new base address into the MRBL and MRBH
(MMR Base Low and High) registers.
SFRs are accessed by “direct addressing” only (see IC25 XA User
Manual for direct addressing.) The MMRs are specific to the XA-H3
Table 2. Special Function Registers (SFR)
Bit Functions and Addresses
Reset
SFR
Address
Name
BCR
Description
Value
MSB
LSB
Bus Configuration Reg
46Ah
WARNING – Never write to the BCR register in the XA-H3 – it is initialized to 07h,
07h
the only legal value. This is not the same as for some other XA derivatives.
RESERVED – see
Warning
BTRH
BTRL
Bus Timing Reg High
Bus Timing Reg Low
469h
468h
FFh
EFh
WARNING – Immediately after reset, always write BTRH = 51h, followed by
writing BTRL = 40h in that order. Follow these two writes with five NOPS. This is
not the same as for some other XA derivatives.
MRBL#
MRBH#
MMR Base Address Low
496h
MA15
MA23
–
MA14
MA22
–
MA13
MA21
–
MA12
MA20
–
–
MA19
–
–
MA18
–
–
MA17
–
MRBE
MA16
x0h
xx
MMR Base Address High 497h
MICFG# ClkOut Tri-St Enable
1 = Enabled
499h
CLKOE
01h
CS
DS
ES
Code Segment
Data Segment
Extra Segment
443h
441h
442h
00h
00h
00h
33F
33E
33D
33C
33B
–
33A
339
338
EHSWR3 EHSWR2 EHSWR1 EHSWR0
EAuto
ESC23
ESC01
IEH*
Interrupt Enable High
427h
00h
337
EA
–
336
335
334
333
ET1
–
332
331
ET0
330
IEL*
IPA0
IPA1
IPA2
IPA3
IPA4
IPA5
IPA6
IPA7
Interrupt Enable Low
Interrupt Priority A0
Interrupt Priority A1
Interrupt Priority A2
Interrupt Priority A3
Interrupt Priority A4
Interrupt Priority A5
Interrupt Priority A6
Interrupt Priority A7
426h
4A0h
4A1h
4A2h
4A3h
4A4h
4A5h
4A6h
4A7h
EDMAH EDMAL
PT0
EX2
EX1
EX0
00h
00h
00h
00h
00h
00h
00h
00h
00h
PX0
–
PT1
–
PX1
–
PDMAL
Reserved
PSC23
–
PX2
–
PDMAH
PSC01
PAutoB
PHSWR0
PHSWR2
–
–
–
–
–
–
–
PHSWR1
PHSWR3
–
–
387
38F
397
39F
386
38E
396
39E
385
38D
395
39D
384
38C
394
39C
383
38B
393
39B
382
38A
392
39A
381
389
391
399
380
388
390
398
P0*
P1*
P2*
P3*
Port 0
Port 1
Port 2
Port 3
430h
431h
432h
433h
FFh
FFh
FFh
FFh
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1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Bit Functions and Addresses
SFR
Address
Reset
Value
Name
Description
MSB
LSB
P0CFGA Port 0 Configuration A
P1CFGA Port 1 Configuration A
P2CFGA Port 2 Configuration A
P3CFGA Port 3 Configuration A
P0CFGB Port 0 Configuration B
P1CFGB Port 1 Configuration B
P2CFGB Port 2 Configuration B
P3CFGB Port 3 Configuration B
470h
471h
472h
473h
4F0h
4F1h
4F2h
4F3h
5
5
5
5
5
5
5
5
227
–
226
–
225
–
224
–
223
–
222
–
221
PD
220
IDL
PCON*
Power Control Reg
404h
00h
20F
SM
207
C
20E
TM
206
AC
20D
RS1
205
–
20C
RS0
204
–
20B
IM3
203
–
20A
IM2
202
V
209
IM1
201
N
208
IM0
200
Z
PSWH*
PSWL*
Program Status Word High 401h
Program Status Word Low 400h
2
2
3
7
217
C
216
AC
215
F0
214
RS1
213
RS0
212
V
211
F1
210
P
PSW51* 80C51 Compatible PSW
RSTSRC Reset Source Reg
402h
463h
ROEN
–
–
–
–
R_WD
R_CMD R_EXT
RTH0
RTH1
RTL0
RTL1
Timer 0 Reload High
Timer 1 Reload High
Timer 0 Reload Low
Timer 1 Reload Low
455h
457h
454h
456h
00h
00h
00h
00h
SCR
System Configuration Reg
Segment Selection Reg
440h
403h
–
–
–
–
PT1
21B
PT0
21A
CM
219
PZ
00h
21F
21E
21D
21C
218
SSEL*
SWE
ESWEN R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG
00h
00h
Software Interrupt Enable 47Ah
–
SWE7
SWE6
SWE5
SWE4
SWE3
SWE2
SWE1
357
–
356
355
354
353
352
351
350
SWR*
42Ah
SWR7
SWR6
SWR5
SWR4
SWR3
SWR2
SWR1
00h
287
TF1
286
285
TF0
284
283
IE1
282
IT1
281
IE0
280
IT0
TCON*
TH0
Timer 0/1 Control
Timer 0 High
Timer 1 High
Timer 0 Low
410h
451h
453h
450h
452h
45Ch
TR1
TR0
00h
00h
00h
00h
00h
00h
TH1
TL0
TL1
Timer 1 Low
TMOD
Timer 0/1 Mode
GATE
C/T
M1
M0
GATE
C/T
M1
M0
10
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Bit Functions and Addresses
SFR
Address
Reset
Value
Name
Description
MSB
LSB
28F
–
28E
–
28D
–
28C
–
28B
–
28A
289
–
288
TSTAT*
Timer 0/1 Extended Status 411h
T1OE
T0OE
00h
2FF
2FE
2FD
2FC
–
2FB
–
2FA
2F9
2F8
–
WDCON* Watchdog Control
41Fh
45Fh
45Dh
45Eh
PRE2
PRE1
PRE0
WDRUN WDTOF
6
00h
x
WDL
Watchdog Timer Reload
WFEED1 Watchdog Feed 1
WFEED2 Watchdog Feed 2
NOTES:
x
*
#
SFRs marked with an asterisk (*) are bit addressable.
SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-H3 and XA-H4.
1. The XA-H3 implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be
8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. 16-bit SFR reads will return undefined data in the
upper byte.
2. SFR is loaded from the reset vector.
3. F1, F0, and P reset to “0”. All other bits are loaded from the reset vector.
4. Unimplemented bits in SFRs are “X” (unknown) at all times. “1”s should not be written to these bits since they may be used for other
purposes in future XA derivatives. The reset value shown for these bits is “0”.
5. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh and
PnCFGB register will contain 00h. See warning in XA-H3 User Manual about P3.2_Timer0_ResetOut pin during first 258 clocks after power
up. Basically, during this period, this pin may output a strongly-driven low pulse. If the pulse does occur, it will terminate in a transition to high
at a time no later than the 259th system clock after valid V power up.
CC
6. The WDCON reset value is E6 for a Watchdog reset; E4 for all other reset causes.
7. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to “1”, the others will be “0”. RSTSRC[7] enables the ResetOut
function; “1” = Enabled, “0” = Disabled. See XA-H3 User Manual for details; RSTSRC[7] differs in function from most other XA derivatives.
8. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt or
other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a read-modify-write
operation. XA-H3 SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in WDCON).
11
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Table 3. Memory Mapped Registers (MMR)
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
UART0 Registers
UART0 Write Register 0
UART0 Write Register 1
UART0 Write Register 2
UART0 Write Register 3
UART0 Write Register 4
UART0 Write Register 5
Reserved – do not write
Reserved – do not write
UART0 Write Register 8
UART0 Write Register 9
UART0 Write Register 10
UART0 Write Register 11
UART0 Write Register 12
UART0 Write Register 13
UART0 Write Register 14
UART0 Write Register 15
Reserved – do not write
Reserved – do not write
UART0 Read Register 0
UART0 Read Register 1
Reserved – do not write
UART0 Read Register 3
Reserved – do not write
Reserved – do not write
UART0 Read Register 8
Reserved – do not write
UART0 Read Register 10
Reserved – do not write
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
800h
802h
804h
806h
808h
80Ah
80Ch
80Eh
810h
812h
814h
816h
818h
81Ah
81Ch
81Eh
828h
82Ah
820h
822h
824h
826h
82Ch
82Eh
830h
832h
834h
836-83Eh
Command register
00h
xx
Tx/Rx Interrupt & data transfer mode
Extended Features Control
xx
Receive Parameter and Control
00h
Tx/Rx miscellaneous parameters & mode
Tx parameter and control
00h
00h
00h
xx
Reserved – do not write
Reserved – do not write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Transmit Data Buffer
xx
Master Interrupt control
xx
Miscellaneous Tx/Rx control register
Clock Mode Control
00h
xx
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Miscellaneous Control bits
External / Status interrupt control
Reserved – do not write
00h
00h
xx
f8h
00h
00h
Reserved – do not write
RO
RO
Tx/Rx buffer and external status
Receive condition status
–
RO
8
8
8
8
Interrupt Pending Bits
Reserved – do not write
Reserved – do not write
Receive Buffer
RO
RO
8
Clock status
–
UART1 Registers
UART1 Write Register 0
UART1 Write Register 1
UART1 Write Register 2
UART1 Write Register 3
UART1 Write Register 4
UART1 Write Register 5
Reserved – do not write
Reserved – do not write
UART1 Write Register 8
UART1 Write Register 9
UART1 Write Register 10
UART1 Write Register 11
UART1 Write Register 12
UART1 Write Register 13
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
8
8
8
8
840h
842h
844h
846h
848h
84Ah
84Ch
84Eh
850h
852h
854h
856h
858h
85Ah
Command register
00h
xx
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx miscellaneous parameters & mode
Tx. parameter and control
xx
00h
00h
00h
00h
xx
Reserved – do not write
Reserved – do not write
R/W
R/W
R/W
R/W
R/W
R/W
Transmit Data Buffer
xx
Master Interrupt control
xx
Miscellaneous Tx/Rx control register
Clock Mode Control
00h
xx
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
00h
00h
12
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
Miscellaneous Control bits
UART1 Write Register 14
UART1 Write Register 15
Reserved – do not write
Reserved – do not write
UART1 Read Register 0
UART1 Read Register 1
Reserved – do not write
UART1 Read Register 3
Reserved – do not write
Reserved – do not write
UART1 Read Register 8
Reserved – do not write
UART1 Read Register 10
Reserved – do not write
R/W
R/W
8
8
8
8
8
8
85Ch
85Eh
868h
xx
External / Status interrupt control
Reserved – do not write
f8h
00h
00h
86Ah
860h
Reserved – do not write
RO
RO
Tx/Rx buffer and external status
Receive condition status
862h
864h
RO
8
8
8
8
866
Interrupt Pending Bits
Reserved – do not write
Reserved – do not write
Receive Buffer
86Ch
86Eh
870h
RO
RO
872h
8
874h
Clock status
876-87Eh
UART2 Registers
UART2 Write Register 0
UART2 Write Register 1
UART2 Write Register 2
UART2 Write Register 3
UART2 Write Register 4
UART2 Write Register 5
Reserved – do not write
Reserved – do not write
UART2 Write Register 8
UART2 Write Register 9
UART2 Write Register 10
UART2 Write Register 11
UART2 Write Register 12
UART2 Write Register 13
UART2 Write Register 14
UART2 Write Register 15
Reserved – do not write
Reserved – do not write
UART2 Read Register 0
UART2 Read Register 1
Reserved – do not write
UART2 Read Register 3
Reserved – do not write
Reserved – do not write
UART2 Read Register 8
Reserved – do not write
UART2 Read Register 10
Reserved – do not write
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
880h
882h
884h
886h
888h
88Ah
88Ch
88Eh
890h
892h
894h
896h
898h
89Ah
89Ch
89Eh
8A8h
8AAh
8A0h
8A2h
8A4h
8A6h
8ACh
8AEh
8B0h
8B2h
8B4h
8B6-8BEh
Command register
00h
xx
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
xx
00h
Tx/Rx miscellaneous parameters & mode
Tx. parameter and control
00h
00h
00h
xx
Reserved – do not write
Reserved – do not write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Transmit Data Buffer
xx
Master Interrupt control
xx
Miscellaneous Tx/Rx control register
Clock Mode Control
00h
xx
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Miscellaneous Control bits
External / Status interrupt control
Reserved – do not write
00h
00h
xx
f8h
00h
00h
Reserved – do not write
RO
RO
Tx/Rx buffer and external status
Receive condition status
RO
8
8
8
8
Interrupt Pending Bits
Reserved – do not write
Reserved – do not write
Receive Buffer
RO
RO
8
Clock status
13
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
UART3 Registers
UART3 Write Register 0
UART3 Write Register 1
UART3 Write Register 2
UART3 Write Register 3
UART3 Write Register 4
UART3 Write Register 5
Reserved – do not write
Reserved – do not write
UART3 Write Register 8
UART3 Write Register 9
UART3 Write Register 10
UART3 Write Register 11
UART3 Write Register 12
UART3 Write Register 13
UART3 Write Register 14
UART3 Write Register 15
Reserved – do not write
Reserved – do not write
UART3 Read Register 0
UART3 Read Register 1
Reserved – do not write
UART3 Read Register 3
Reserved – do not write
Reserved – do not write
UART3 Read Register 8
Reserved – do not write
UART3 Read Register 10
Reserved – do not write
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8C0h
8C2h
8C4h
8C6h
8C8h
8CAh
8CCh
8CEh
8D0h
8D2h
8D4h
8D6h
8D8h
8DAh
8DCh
8DEh
8E8h
8EAh
8E0h
8E2h
8E4h
8E6h
8ECh
8EEh
8F0h
Command register
00h
xx
Tx/Rx Interrupt & data transfer mode
Extended Features Control
xx
Receive Parameter and Control
00h
Tx/Rx miscellaneous parameters & mode
Tx. parameter and control
00h
00h
00h
xx
Reserved – do not write
Reserved – do not write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Transmit Data Buffer
xx
Master Interrupt control
xx
Miscellaneous Tx/Rx control register
Clock Mode Control
00h
xx
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Miscellaneous Control bits
External / Status interrupt control
Reserved – do not write
00h
00h
xx
f8h
00h
00h
Reserved – do not write
RO
RO
Tx/Rx buffer and external status
Receive condition status
RO
8
8
8
8
Interrupt Pending Bits
Reserved – do not write
Reserved – do not write
Receive Buffer
RO
RO
8F2h
–
8
8F4h
Clock status
8F6-8FEh
Rx DMA Registers
DMA Control Register Ch.0 Rx
FIFO Control & Status Reg Ch.0 Rx
Segment Register Ch.0 Rx
R/W
R/W
R/W
R/W
8
8
8
8
100h
101h
102h
104h
Control Register
00h
00h
00h
00h
Control & Status Register
Points to 64 k data segment
Buffer Base Register Ch.0 Rx
Wrap Reload Value for A15 – A8, A7 – A0
reloaded to zero by hardware
Buffer Bound Register Ch.0 Rx
Address Pointer Reg Ch.0 Rx
Byte Count Register Ch.0 Rx
R/W
R/W
R/W
16
16
16
106h
108h
10Ah
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
0000h
0000h
Corresponds to A15 – A0 Byte Count, generates 0000h
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.0 Lo Rx
Data FIFO Register Ch.0 Hi Rx
R/W
R/W
16
16
10Ch
10Eh
10Ch = Byte 0 = older,
10Dh = Byte 1 = younger
10Eh = Byte 2 = older,
10Fh = Byte 3 = younger
Control Register
00h
00h
00h
00h
00h
00h
00h
DMA Control Register Ch.1 Rx
FIFO Control & Status Register Ch.1 Rx
Segment Register Ch. 1 Rx
R/W
R/W
R/W
8
8
8
110h
111h
112h
Control & Status Register
Points to 64 k data segment
14
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
Buffer Base Register Ch. 1 Rx
R/W
8
114h
Wrap Reload Value for A15 – A8, A7 – A0
reloaded to zero by hardware
00h
Buffer Bound Register Ch.1 Rx
Address Pointer Reg Ch.1 Rx
Byte Count Register Ch.1 Rx
R/W
R/W
R/W
16
16
16
116h
118h
11Ah
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
0000h
0000h
Corresponds to A15 – A0 Byte Count, generates 0000h
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.1 Lo Rx
Data FIFO Register Ch.1 Hi Rx
R/W
R/W
16
16
11Ch
11Eh
11Ch = Byte 0 = older,
11Dh = Byte 1 = younger
11Eh = Byte 2 = older,
11Fh = Byte 3 = younger
Control Register
00h
00h
00h
00h
00h
00h
00h
DMA Control Register Ch.2 Rx
FIFO Control & Status Register Ch.2 Rx
Segment Register Ch. 2 Rx
R/W
R/W
R/W
R/W
8
8
8
8
120h
121h
122h
124h
Control & Status Register
Points to 64 k data segment
Buffer Base Register Ch. 2 Rx
Wrap Reload Value for A15 – A8, A7 – A0 00h
reloaded to zero by hardware
Buffer Bound Register Ch.2 Rx
Address Pointer Reg Ch.2 Rx
Byte Count Register Ch.2 Rx
R/W
R/W
R/W
16
16
16
126h
128h
12Ah
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
0000h
0000h
Corresponds to A15 – A0 Byte Count, generates 0000h
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.2 Lo Rx
Data FIFO Register Ch.2 Hi Rx
R/W
R/W
16
16
12Ch
12Eh
12Ch = Byte 0 = older,
12Dh = Byte 1 = younger
12Eh = Byte 2 = older,
12Fh = Byte 3 = younger
Control Register
00h
00h
00h
00h
00h
00h
00h
DMA Control Register Ch.3 Rx
FIFO Control & Status Register Ch.3 Rx
Segment Register Ch. 3 Rx
R/W
R/W
R/W
R/W
8
8
8
8
130h
131h
132h
134h
Control & Status Register
Points to 64 k data segment
Buffer Base Register Ch. 3 Rx
Wrap Reload Value for A15 – A8, A7 – A0 00h
reloaded to zero by hardware
Buffer Bound Register Ch.3 Rx
Address Pointer Reg Ch.3 Rx
Byte Count Register Ch.3 Rx
R/W
R/W
R/W
16
16
16
136h
138h
13Ah
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
0000h
0000h
Corresponds to A15 – A0 Byte Count, generates 0000h
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.3 Lo Rx
Data FIFO Register Ch.3 Hi Rx
R/W
R/W
16
16
13Ch
13Eh
13Ch = Byte 0 = older,
13Dh = Byte 1 = younger
13Eh = Byte 2 = older,
13Fh = Byte 3 = younger
00h
00h
00h
00h
Tx DMA Registers
DMA Control Register Ch.0 Tx
FIFO Control & Status Register Ch.0 Tx
Segment Register Ch. 0 Tx
R/W
R/W
R/W
R/W
8
8
8
8
140h
141h
142h
144h
Control Register
00h
00h
00h
00h
Control & Status Register
Points to 64 k data segment
Buffer Base Register Ch. 0 Tx
Wrap Reload Value for A15 – A8, A7 – A0
reloaded to zero by hardware
Buffer Bound Register Ch.0 Tx
Address Pointer Reg Ch.0 Tx
Byte Count Register Ch.0 Tx
R/W
R/W
R/W
16
16
16
146h
148h
14Ah
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
0000h
0000h
Corresponds to A15 – A0 Byte Count, generates 0000h
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.0 Tx
R/W
16
14Ch
14C = Byte0 = older
0000h
14D = Byte 1 = younger
15
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
14E = Byte2 = older
Data FIFO Register Ch.0 Tx
R/W
16
14Eh
0000h
14F = Byte3 = younger
Control Register
DMA Control Register Ch.1 Tx
FIFO Control & Status Register Ch.1 Tx
Segment Register Ch.1 Tx
R/W
R/W
R/W
R/W
8
8
8
8
150h
151h
152h
154h
00h
00h
00h
Control & Status Register
Points to 64 k data segment
Buffer Base Register Ch.1 Tx
Wrap Reload Value for A15 – A8, A7 – A0
reloaded to zero by hardware
00h
Buffer Bound Register Ch.1 Tx
Address Pointer Reg Ch.1 Tx
Byte Count Register Ch.1 Tx
R/W
R/W
R/W
16
16
16
156h
158h
15Ah
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
0000h
0000h
Corresponds to A15 – A0 Byte Count, generates 0000h
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.1 Lo Tx
Data FIFO Register Ch.1 Hi Tx
DMA Control Register Ch.2 Tx
FIFO Control & Status Register Ch.2 Tx
Segment Register Ch.2 Tx
R/W
R/W
R/W
R/W
R/W
R/W
16
16
8
15Ch
15Eh
160h
161h
162h
164h
Byte0 & 1
0000h
0000h
00h
Byte2 & 3
Control Register
Control & Status Register
Points to 64 k data segment
8
00h
8
00h
Buffer Base Register Ch.2 Tx
8
Wrap Reload Value for A15 – A8, A7 – A0
reloaded to zero by hardware
00h
Buffer Bound Register Ch.2 Tx
Address Pointer Reg Ch.2 Tx
Byte Count Register Ch.2 Tx
R/W
R/W
R/W
16
16
16
166h
168h
16Ah
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
0000h
0000h
Corresponds to A15 – A0 Byte Count, generates 0000h
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.2 Lo Tx
Data FIFO Register Ch.2 Hi Tx
DMA Control Register Ch.3 Tx
FIFO Control & Status Register Ch.3 Tx
Segment Register Ch. 3 Tx
R/W
R/W
R/W
R/W
R/W
R/W
16
16
8
16Ch
16Eh
170h
171h
172h
174h
Byte0 & 1
0000h
0000h
00h
Byte2 & 3
Control Register
8
Control & Status Register
Points to 64 k data segment
Wrap Reload Value for A15 – A8,
A7 – A0 reloaded to zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
00h
8
00h
Buffer Base Register Ch. 3 Tx
8
00h
Buffer Bound Register Ch.3 Tx
Address Pointer Reg Ch.3 Tx
Byte Count Register Ch.3 Tx
R/W
R/W
R/W
16
16
16
176h
178h
17Ah
0000h
0000h
Corresponds to A15 – A0 Byte Count, generates 0000h
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.3Lo Tx
Data FIFO Register Ch.3 Hi Tx
R/W
R/W
R/W
16
16
17Ch
17Eh
Byte0 & 1
Byte2 & 3
0000h
0000h
–
180-1FEh RESERVED for future DMA
Miscellaneous DMA Registers
Rx Character Time Out Register Ch.0
Rx Character Time Out Register Ch.1
Rx Character Time Out Register Ch.2
Rx Character Time Out Register Ch.3
Global DMA Interrupt Register
GPOut
R/W
R/W
R/W
R/W
R/W
R/W
8
8
200h
202h
204h
206h
210h
260h
0 value disables counter interrupt.
Same as above, for Rx1
Same as above, for Rx2
Same as above, for Rx3
DMA Interrupt Flags
00h
00h
8
00h
8
00h
16
8
0000h
8xh
GPOut[7] drives pin 98 (GPOut) through an
inverter.
GPOut[6-0] are unused, and must be written
with zeroes.
16
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
Memory Interface (MIF) Registers
MIF Bank 0 Config
B0CFG
B0AM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
280h
281h
282h
284h
285h
286h
288h
289h
28Ah
28Ch
28Dh
28Eh
290h
291h
292h
294h
295h
296h
2BEh
2BFh
0Fh
00h
MIF Bank 0 Base Address
MIF Bank 0 Timing Params
MIF Bank 1 Config
B0TMG
B1CFG
B1AM
MIF Bank 1 Base Address
MIF Bank 1 Timing Params
MIF Bank 2 Config
B1TMG
B2CFG
B2AM
MIF Bank 2 Base Address
MIF Bank 2 Timing Params
MIF Bank 3 Config
B2TMG
B3CFG
B3AM
MIF Bank 3 Base Address
MIF Bank 3 Timing Params
MIF Bank 4 Config
B3TMG
B4CFG
B4AM
MIF Bank 4 Base Address
MIF Bank 4 Timing Params
MIF Bank 5 Config
B4TMG
B5CFG
B5AM
MIF Bank 5 Base Address
MIF Bank 5 Timing Params
B5TMG
MBCL
MIF Memory Bank Configuration Lock Register
Reserved – do not write
Reserved – do not write
Miscellaneous Registers
Hi-Pri Soft Ints & Pin Mux Control Reg.
XInt2
R/W
R/W
16
8
2D0h
2D2h
Control bits for Hi-Priority Soft Ints, and Pin Mux 0000h
External Interrupt 2 Control
00h
FUNCTIONAL DESCRIPTION
The XA-H3 functions are described in the following sections.
Because all blocks are thoroughly documented in either the IC25 XA
Data Handbook, or the XA-H3 User Manual, only brief descriptions
are given in this datasheet, in conjunction with references to the
appropriate document.
XA CPU
BIU
XA CPU
The CPU is a 30 MHz implementation of the standard XA CPU core.
See the XA Data Handbook (IC25) for details. The CPU core is
identical to the G3 core. See caveat in next paragraph about the Bus
Interface Unit.
Internal Cpu Bus
Bus Interface Unit (BIU)
This is the internal Bus, not the bus at the pins. This internal bus
connects the CPU to Memory Controller.
External
Memory
and I/O Bus
DMA
Channels
x8
Memory
Controller
WARNING: Immediately after reset, always write BTRH = 51h,
followed by BTRL = 40h, in that order. Once written, do not change
the values in these registers. Follow these two writes with five
NOPS. Never write to the BCR register, it comes out of reset
initialized to 07h, which is the only value that will work.
SU01236
Figure 1. XA CPU Core BIU (Bus Interface Unit)
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Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Timers 0 and 1
ResetOut
Timers 0 and 1 are the standard XA-G3 timer 0 and 1. Each has an
associated I/O pin and interrupt. See the XA-G3 data sheet in the
IC25 XA Data Handbook for details. Many XA derivatives include a
standard XA Timer 2. The Timer 2 block has been removed in order
to provide other functions on the XA-H3.
The P3.2_Timer0_ResetOut pin provides an external indication (if the
ResetOut function is enabled in the RSRSRC register) via an active
low output when an internal reset occurs (internal reset is Reset
instruction or Watchdog time out.) If the ResetOut function is enabled,
the ResetOut pin will be driven low when a Watchdog reset occurs or
the Reset instruction is executed. This signal may be used to inform
other devices in the system that the XA-H3 has been internally reset.
The ResetIn signal does NOT get passed on to ResetOut. When
activated, the duration of the ResetOut pulse is 256 system clocks.
Watchdog Timer
This timer is a standard XA-G3 Watchdog Timer. See the G3
datasheet in IC25. Also, if you intend to use the Watchdog Timer to
assert the ResetOut pin, see “ResetOut” in the XA-H3 User Manual.
The Watchdog Timer is enabled at reset, and must be periodically
fed to prevent timeout. If the watchdog times out, it will generate an
internal reset; and if ResetOut is enabled the internal reset will
generate a ResetOut pulse (active low pulse on ResetOut pin.)
WARNING: At power on time, from the time that power coming up is
valid, the P3.2_Timer0_ResetOut pin may be driven low for any
period from zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
Reset Source Register
Reset
The reset source identification register (RSTSRC) indicates the cause
of the most recent XA reset. The cause may have been an externally
applied reset signal, execution of the RESET instruction, or a
Watchdog reset. Figure 2 shows the fields in the RSTSRC register. If
the ResetOut function is tied back into the ResetIn pin, then all resets
will be external resets, and will thus appear as external resets in the
reset source register. RSTSRC[7] enables the ResetOut function; 1 =
Enabled, 0 = Disabled. See XA-H3 User Manual for details;
RSTSRC[7] differs in function from most other XA derivatives.
On the XA-H3 there are two pins associated with reset. The ResetIn
pin provides an external reset into the XA-H3. The port pin
P3.2_Timer0_ResetOut output can be configured as ResetOut.
Because ResetOut does not reflect ResetIn, the ResetOut pin can
be tied directly back into the ResetIn pin without other PC board
logic. This configuration will make all resets (internal or external)
appear to the XA as external resets. See the XA-H3 User Manual for
a full discussion of the reset functions.
ResetIn
The ResetIn function is the standard XA-G3 ResetIn function. The
ResetIn signal does NOT get passed on to ResetOut. See the
XA-H3 User Manual for details on reset.
RSTSRC
Reg Type and Address = SFR 463h
Not Bit Addressable
Reset Value = see below
MSB
LSB
ROEN
—
—
—
—
R_WD
R_CMD
R_EXT
BIT
SYMBOL
FUNCTION
RSTSRC.7 ROEN
ResetOut function enable bit – see XA-H3 User Manual for details
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
RSTSRC.6
RSTSRC.5
RSTSRC.4
RSTSRC.3
–
–
–
–
RSTSRC.2 R_WD
Indicates that the last reset was caused by a watchdog timer overflow (see WARNING.)
Indicates that the last reset was caused by execution of the RESET instruction (see WARNING.)
Indicates that the last reset was caused by the external ResetIn input.
RSTSRC.1 R_CMD
RSTSRC.0 R_EXT
WARNING:
If ResetOut function is tied back into ResetIn pin, RSTSRC will always show external reset ONLY, because external reset always takes
precedence over internal reset.
SU01237
Figure 2. RSTSRC Reset Source Register
MEMORY CONTROLLER AND I/O BUS INTERFACE
The Memory Controller and bus interface generate bus cycles that are
designed to service SRAMs, Flash, EEPROM, peripheral chips, etc.
interface with no external decode logic or interface chips. The bus
interface provides 6 mappable chip select outputs. The bus timing for
each individual memory bank or peripheral can be programmed to
accommodate slow or fast devices, with various bus protocols.
The XA-H3 has a highly programmable memory bus interface. Most
SRAMs, Flash, ROMs, and peripheral chips can be connected to this
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Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Each memory bank and associated chip select is capable of
supporting a 1 MB address space (six chip selects can thus support
6 MB of SRAM and other generic devices.)
The Memory Interface can be programmed to support both Intel
style and 68000 bus style SRAMs and peripherals.
XA-H3
CS5 (or P3.1, RTS1)
Memory Controller
CS4 (or P3.0, RTClk1)
CS3
CS2
CS1
CS0
A19–A0
D15–D0
SRAM Controller
Dynamic Bus Sizing
Dynamic Bus Timing
ClkOut
BHE
BLE
OE
WE
WAIT, SIZE16
SU01238
Figure 3. Memory Bus Interface Signal Pins
Bus Interface Pins
For the following discussion, see Figure 3.
Chip Select Pins
There are six chip select pins (CS5 – CS0)mapped to six sets of
bank control registers. The following attributes are individually
programmable for each bank and associated chip select : bank
on/off, address range, external device access time, detailed bus
strobe sequence, and bus width.
WARNING:Ontheexternalbus, ALLXA-H3readsare16-bitReads.IftheCPUinstructiononlyspecifies8-bits,thentheCPUusestheappropriate
byte, and discards the extra byte. Thus “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus. On an 8-bit bus, this will appear
as two consecutive 8-bit reads even though the CPU instruction specified a byte read.
Some 8-bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and least
expensive) solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries.
An added benefit of this technique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of
2 consecutive bytes.
Clock Output
The CLKOUT pin allows easier external bus interfacing in some
situations. This output reflects the XTALIn clock input to the XA
(referred to internally as CClk or System Clock), but is delayed to
match the external bus outputs and strobes. The default is for
CLKOUT to be output enabled at reset, but it may be turned off
(tri-state disabled) by software via the MICFG MMR.
WARNING: The capacitive loading on this output must not
exceed 40 pf.
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Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
CS5
CS4
I/O Chip or Memory
I/O Chip or Memory
I/O Chip or Memory
I/O Chip or Memory
CS3
CS2
XA-H3
CS0
CS
WE
ROM or Flash
128 k x 8
OE
OE
A16–A0
D7–D0
A16–A0
D7–D0
A19–A0
D15–D0
CS1
CS
BLE
BLE
BHE
BHE
A15–A1
D15–D0
A15–A1
32 k x 16 SRAM
D15–D0
OE
WE
WE
NOTE:
The 16-bit wide RAM does not need the A0 pin from the processor. During byte writes to the RAM, the A0 value will cause
either BLE or BHE pin to go active from the XA-H3, but not to both. For all Word Writes, Word Reads, Code Fetches, and
Byte Reads, both BLE and BHE will go active.
SU01239
Figure 4. Typical System Bus Configuration
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1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Table 4. Memory interface control registers
Reg
Register Name
Description
Type
MRBH
MRBL
“MMR Base Address” High
SFR
This SFR is used to relocate the MMRs. It contains address bits a23 – a16 of the
8 bits base address for the 4 kB Memory Mapped Register space. See the User Manual for
using this SFR to relocate the MMRs.
“MMR Base Address” Low
SFR
Contains address bits a15 – a12 of the base address for the 4 kB Memory Mapped
8 bits Register space.
MICFG MIF Configuration
MMR Contains the CLKOUT Enable bit.
8 bits
MBCL
Memory Bank Configuration Lock
MMR
8 bits
Contains the bits for locking and unlocking the BiCFG Registers.
BiCFG Bank i Configuration
MMR Contains the size, type, bus width, and enable bits for Memory Bank i.
8 bits
BiAM
Bank i Base Address
MMR Contains the base address bits for Memory Bank i.
8 bits
BiTMG Bank i Timing
MMR Contains the timing control bits for Memory Bank i.
8 bits
EIGHT CHANNEL DMA CONTROLLER
The XA-H3/H4 has eight DMA channels; one Rx DMA channel
dedicated to each UART Receive (Rx) channel, and one Tx DMA
channel dedicated to each UART Transmit (Tx) channel. All DMA
channels are optimized to support memory efficient circular data
buffers in external memory. All DMA channels can also support
traditional linear data buffers.
Transmit DMA Channel Modes
The four Tx channels have three DMA modes specifically designed
for various applications of the attached UARTs. These modes are
summarized in the following table. Full details for all DMA functions
can be found in the DMA chapter of the XA-H3 User Manual.
Table 5. Tx DMA modes summary
Mode
Byte Count Source
Header in memory
Maskable Interrupt
Description
Tx
Chaining
On stop
DMA channel picks up header from memory at end of
transmission. If byte count in header is greater than zero,
then DMA transmits the number of bytes specified in the
byte count. If byte count equals 0, then a maskable
interrupt is generated. This process repeats until byte count
in data header is zero. See XA-H3 User Manual for details.
Stop on TC Processor loads Byte Count Register
Byte count completed
(Tx DMA stops)
Processor loads byte count into DMA. DMA sends that
number of bytes, generates maskable interrupt, and stops.
Periodic
Interrupt
Loaded by processor into DMA, used by
DMA only to determine the number of
bytes between interrupts. Processor can
calculate the byte count from the DMA
address pointer.
When Byte Counter
reaches zero and is
reloaded by DMA
hardware from the byte rolls over, a new maskable interrupt is generated.
count register.
DMA runs until commanded to stop by processor. CPU
loaded value in Byte Count Register is used to generate
an interrupt for every n bytes. Every time byte counter
Receive DMA Channel Modes
The Rx DMA channels have two DMA modes specifically designed
for various applications of the attached UARTs. These modes are
summarized in the following table. For full details on implementation
and use, see the XA-H3 User Manual.
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Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Table 6. Rx DMA modes summary
Mode
Byte Count Source
Maskable Interrupt
Description
The DMA channel runs until commanded to
Periodic Interrupt Loaded by processor into DMA, used by
DMA only to determine the number of
bytes between interrupts. Processor can
calculate the byte count from the DMA
address pointer.
When Byte Counter reaches
zero and is reloaded by DMA stop by the processor. It generates a
hardware from the byte count maskable interrupt once per n bytes, where n
register.
is the number written once into the byte count
register by the processor, thus an interrupt is
generated once every n received bytes.
Asynchronous
with Character
Time Out
Byte Count can be calculated by software If no character is received
Processor specifies time out period between
incoming characters. If no character is
received within that time, a maskable
interrupt is generated.
from the DMA address pointer.
within a specified time out
period, then interrupt.
Asynchronous
without interrupt
Byte Count can be calculated by software No interrupt generated
from the DMA address pointer.
Whenever a new character is received, it is
moved into the memory buffer – no interrupt
is generated.
Data FIFO 3
Data FIFO 1
Data FIFO 2
Data FIFO 0
DMA Control
Segment
Buffer Base
Rx Channel
Buffer Bound
Address Pointer
Byte Count
FIFO Control
Rx Time Out
Data FIFO 2
Data FIFO 0
Data FIFO 3
Data FIFO 1
DMA Control
Segment
Tx Channel
Buffer Base
Buffer Bound
Address Pointer
Byte Count
FIFO Control
SU01240
Figure 5. Rx and Tx DMA Registers
DMA Registers
In addition to the 16-bit Global DMA Interrupt Register (which is shared
by all eight DMA channels), each DMA channel has seven control
registers and a four-byte Data FIFO. The four Rx DMA channels have
one additional register, the Rx Character Time Out Register. All DMA
registers can be read and written in Memory Mapped Register (MMR)
space. These registers are summarized below.
• Global DMA Interrupt Register (not shown in figure): All DMA
interrupt flags are in this register .
• DMA Control Register: Contains the master mode select and
interrupt enable bits for the channel.
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Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Hi-Z, and allows the pin to be used as an input. WARNING: At
• Segment Register: Holds A23–A16 (the current segment) of the
power on time, from the time that power coming up is valid, the
P3.2_Timer0_ResetOut pin may be driven low for any period from
zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
24-bit data buffer address.
• Buffer Base Register: Holds a pointer (A15–A8) to the lowest byte
in the memory buffer.
• Buffer Bound Register: Points to the first out-of-bounds address
Power Reduction Modes
above a circular buffer.
The XA-H3 supports Idle and Power Down modes of power
reduction. The idle mode leaves most peripherals running in order to
allow them to activate the processor when an interrupt is generated.
The power down mode stops the oscillator in order to absolutely
minimize power. The processor can be made to exit power down
mode via a reset or one of the external interrupt inputs (INT0 or
INT1). This will occur if the interrupt is enabled and its priority is
higher than that defined by IM3 through IM0. In power down mode,
the power supply voltage may be reduced to the RAM keep-alive
voltage VRAM. This retains the RAM, register, and SFR contents at
• Address Pointer Register: Points to a single byte or word in the
data buffer in memory. The 24-bit DMA address is formed by
concatenating the contents of the Segment Register [A23–A16]
with the contents of the Address Pointer Register [A15–A0].
• Byte Count Register: Holds the initial number of bytes to be
transferred. In Tx Chaining mode, this register is not used
because the byte count is brought into the byte counter from
buffer headers in memory.
the point where power down mode was entered. WARNING: V
must be raised to within the operating range before power down
mode is exited.
DD
• FIFO Control & Status Register: Holds the queuing order and
full/empty status for the Data FIFO Registers.
• Data FIFO Registers: A four-byte data FIFO buffer internal to the
Interrupts
DMA channel.
In the XA architecture, all exceptions, including Reset, are handled in
the same general exception structure. The highest priority exception is
of course Reset, and it is non-maskable. All exceptions are vectored
through the Exception Vector Table in low memory. Coming out of
Reset, these vectors must be stored in non-volatile memory based at
location 000000. Later in the boot sequence, SRAM or other memory
can be mapped into this address space if desired. There is a feature
in the XA-H3 Memory Controller called “Bank Swap” that supports
replacing the ROM vector table and other low memory with RAM. See
the XA-H3 User Manual for details.
• Rx Char Time Out Register (RxCTOR, Rx DMA channels only):
Holds the initial value for an 8-bit character timeout countdown
timer which can generate an interrupt.
Four UARTS
• Asynchronous transfers up to 230.4 kbps
• 5, 6, 7, or 8 data bits per character
• 1, 1.5, or 2 Stop bits per character
• Even or Odd parity generate and check
• Parity, Rx Overrun, and Framing Error detection
• Break detection
The XA-H3 has a standard XA CPU Interrupt Controller,
implemented with 15 Maskable Event Interrupts. Event Interrupts
are defined as maskable interrupts usually generated by hardware
events. However, in the XA-H3, 4 of the 15 Event Interrupts are
generated by software writing directly to the interrupt flag bit. These
4 interrupts are referred to as High Priority Software Interrupts.
• Programmable Baud Rate Generator
• Auto Echo and Loopback Modes
See the IC25 XA Data Handbook for a full explanation of the
exception structure, including event interrupts, of the XA CPU.
Because the High Priority Software Interrupts are specific to the
XA-H3, they are explained in the XA-H3 User Manual.
I/O Port Output Configuration
Port input/output configurations are the same as standard XA ports:
open drain, quasi-bidirectional, push-pull, and off (off means tri-state
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Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
XA Core
Interrupt Controller
DMAH
DMA
Interrupts
DMAL
RxD0
CTS0
CD0
UART0/
RxD1
CTS1
UART1
CD1_INT2
INT2
RxD2
CTS2
CD2
Interrupt
Enable/
Disable Bits
Master
Enable
“EA”
Interrupt
To XA CPU
UART2/
UART3
RxD3
CTS3
CD3
INT0
INT1
Timer 0
Timer 1
High Priority
4
Software Ints
HSWR 3–0
SU01241
Figure 6. XA-H3 Interrupt Structure Overview
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Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Table 7. UART0 Interrupts (Interrupt structure is the same except for bit locations for all 4 UARTs)
Potential
UART0
Interrupt
Individual Enable Bit
MMR Hex Offset
Source Bit
Group Enable Bit(S)
MMR Hex Offset
Group Flag Bit
Master Enable Bit
MMR Hex Offset
MMR Hex Offset
MMR Hex Offset
Rx Character Available
–
RR0[0]
820[0]
WR1[4:3]
802[4:3]
Even Channel Rx IP UART0/1 Master
Interrupt Enable
RR3[5]
WR9[3]
826[5]
812[3]
CRC/Framing Error
Rx Overrun
–
–
RR1[6]
822[6]
RR1[5]
822[5]
RR1[4]
822[4]
RR0[2]
820[2]
Parity Error
WR1[2]
802[2]
Tx Buffer Empty
See WR1[1]
Tx Interrupt Enable
WR1[1]
Even Channel Tx IP
RR3[4]
802[1]
826[4]
Break/Abort
Break/
RR0[7]
820[7]
Master External/Status
Interrupt Enable
Even Channel
External/Status IP
Abort IE
WR1[0]
802[0]
RR3[3]
826[3]
WR15[7]
81E[7]
Tx Underrun/EOM
CTS
Tx Underrun/EOM IE
WR15[6]
81E[6]
RR0[6]
820[6]
CTS IE
WR15[5]
81E[5]
RR0[5]
820[5]
DCD
DCD IE
RR0[3]
820[3]
WR15[3]
81E[3]
Zero Count
Zero Count IE
WR15[1]
81E[1]
RR0[1]
820[1]
EXCEPTION/TRAPS PRECEDENCE
Description
Reset (h/w, watchdog, s/w)
Break Point
Vector Address
Arbitration Ranking
0000–0003
0004–0007
0008–000B
000C–000F
0010–0013
0014–0017
0040–007F
0 (High)
1
1
1
1
1
1
Trace
Stack Overflow
Divide by 0
User RETI
TRAP 0–15 (software)
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Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
EVENT INTERRUPTS
Description Event
Interrupt Source
Interrupt Vector
Address
Priority Register Bit
Field (SFR)
Flag Bit
Enable Bit (SFR)
Arb. Rank
High Priority
Software Interrupt 3
HSWR3
MMR 2D0[15]
00BF–00BC
00BB–00B8
00B7–00B4
00B3–00B0
00A7–00A4
00A3–00A0
009B–0098
0097–0094
0093–0090
008F–008C
008B–0088
0087–0084
0083–0080
EHSWR3
427[7]
33F
PHSWR3
4A7[6:4]
17
High Priority
Software Interrupt 2
HSWR2
MMR 2D0[14]
EHSWR2
427[6]
33E
PHSWR2
4A7[2:0]
16
15
14
11
10
8
High Priority
Software Interrupt 1
HSWR1
MMR 2D0[13]
EHSWR1
427[5]
33D
PHSWR1
4A6[6:4]
High Priority
Software Interrupt 0
HSWR0
MMR 2D0[12]
EHSWR0
427[4]
33C
PHSWR0
4A6[2:0]
UART “UART2/3”
Interrupt
multiple OR from
UART2 & UART3
ESC23
427[1]
339
PSC23
4A4[6:4]
UART “UART0/1”
Interrupt
multiple OR from
UART0 & UART1
ESC01
427[0]
338
PSC01
4A4[2:0]
DMA “DMAH”
Interrupt
multiple OR from
DMA
EDMAH
426[6]
336
PDMAH
4A3[2:0]
DMA “DMAL”
Interrupt
multiple OR from
DMA
EDMAL
426[5]
335
PDMAL
4A2[6:4]
7
External Interrupt 2
(INT2)
IE2
MMR 2D2[0]
EX2
426[4]
334
PX2
4A2[2:0]
6
Timer 1
TF1
SFR 410[7]
287
ET1
426[3]
333
PT1
4A1[6:4]
5
External Interrupt 1
(INT1)
IE1
SFR 410[3]
283
EX1
426[2]
332
PX1
4A1[2:0]
4
Timer 0
TF0
SFR 410[5]
285
ET0
426[1]
331
PT0
4A0[6:4]
3
External Interrupt 0
(INT0)
IE0 SFR 410[1]
EX0 426[0] 330
PX0 4A0[2:0]
2
SOFTWARE INTERRUPTS
Description
Software Interrupt 1
Software Interrupt 2
Software Interrupt 3
Software Interrupt 4
Software Interrupt 5
Software Interrupt 6
Software Interrupt 7
Flag Bit
SWR1
SWR2
SWR3
SWR4
SWR5
SWR6
SWR7
Vector Address
Enable Bit
SWE1
SWE2
SWE3
SWE4
SWE5
SWE6
SWE7
Interrupt Priority
(fixed at 1)
(fixed at 2)
(fixed at 3)
(fixed at 4)
(fixed at 5)
(fixed at 6)
(fixed at 7)
0100–0103
0104–0107
0108–010B
010C–010F
0110–0113
0114–0117
0118–011B
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Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Rating
Unit
°C
°C
v
–55 to +125
–65 to +150
Storage temperature range
Voltage on any other pin to V
–0.5 to V +0.5 V
SS
DD
Maximum I per I/O pin
15
mA
W
OL
Power dissipation (based on package heat transfer, not device power consumption)
1.5
PRELIMINARY DC ELECTRICAL CHARACTERISTICS
V
= 5.0 V +/– 10% or 3.3 V +/– 10% unless otherwise specified; T
= –40°C to +85°C for industrial, unless otherwise specified.
DD
amb
Limits
Symbol
Parameter
Test Conditions
Unit
Min
Typ
64
Max
80
I
Power supply current, operating
5.0 V, 30 MHz
3.3 V, 30 MHz
5.0 V, 30 MHz
3.3 V, 30 MHz
5.0 V, 3.0 V
mA
mA
mA
mA
µA
V
DD
55
70
I
ID
Power supply current, Idle mode
50
70
44
60
1
I
Power supply current, Power Down mode
RAM keep-alive voltage
500
PDI
V
RAM
1.5
–0.5
2.2
V
IL
Input low voltage
0.22 V
V
DD
V
IH
Input high voltage, except Xtal1, RST
Input high voltage to Xtal1, RST
V
V
IH1
For both 3.0 & 5.0 V
0.7 V
V
DD
8
V
OL
Output low voltage all ports
I
I
= 3.2 mA, V = 4.5 V
0.5
0.4
V
OL
DD
= 1.0 mA, V = 3.0 V
V
OL
DD
V
Output high voltage, all ports
Output high voltage, all ports
Input/Output pin capacitance
I
= –100 µA, V = 4.5 V
2.4
2.0
2.4
2.2
V
OH1
OH2
OH
DD
I
= –30 µA, V = 3.0 V
V
OH
DD
V
I
I
= 3.2 mA, V = 4.5 V
V
OH
DD
= 1.0 mA, V = 3.0 V
V
OH
DD
C
15
pF
µA
µA
µA
µA
IO
7
I
I
Logical 0 input current, all ports
V
IN
= 0.45 V
–50
±10
IL
6
Input leakage current, all ports
V
IN
= V or V
IL IH
LI
5
I
Logical 1 to 0 transition current, all ports
At V = 5.5 V
–650
–250
TL
DD
At V = 3.6 V
DD
NOTE:
1. V must be raised to within the operating range before power down mode is exited.
DD
2. Ports in quasi-bidirectional mode with weak pullup.
3. Ports in PUSH-PULL mode, both pullup and pulldown assumed to be the same strength.
4. In all output modes.
5. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when
is approximately 2 V.
V
IN
6. Measured with port in high impedance mode.
7. Measured with port in quasi-bidirectional mode.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum I per port pin:
15 mA (NOTE: This is +85°C specification for V = 5 V)
OL
DD
Maximum I per 8-bit port:
26 mA
71 mA
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
27
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
PRELIMINARY AC ELECTRICAL CHARACTERISTICS (5.0 V +/–10%)
Limits
Symbol
Figure
Parameter
All Cycles
Unit
Min
Max
F
System Clock Frequency
System Clock Period = 1/FC
XTALIN High Time
0
30
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
t
C
13
13
13
13
13
All
All
All
All
All
14
33.33
t
t * 0.5
–
CHCX
C
t
XTALIN Low Time
t * 0.4
–
CLCX
CLCH
CHCL
C
t
t
XTALIN Rise Time
–
–
5
XTALIN Fall Time
5
t
Address Valid to Strobe low
t
– 21
–
AVSL
C
7
t
Address hold after CLKOUT rising edge
1
–
1
1
–
CHAH
t
Delay from CLKOUT rising edge to address valid
25
21
19
CHAV
CHSH
7
t
Delay from CLKOUT rising edge to Strobe High
7
t
Delay from CLKOUT rising edge to Strobe Low
CHSL
t
ClkOut Duty Cycle High (into 40 pF max.)
t
–7
t
+3
CODH
CHCX
CHCX
Data Read Only
t
10
Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at end
of Data Read Cycle (not code fetch)
t
C
– 12
–
ns
AHDR
Data Read and Instruction Fetch Cycles
t
7, 8, 10, 11
7, 8, 10, 11
10
Data In Valid setup to ClkOut rising edge
25
0
–
–
–
ns
ns
ns
DIS
2
t
Data In Valid hold after ClkOut rising edge
DIH
t
OE high to XA Data Bus Driver Enable
Write Cycles
t
C
– 14
OHDE
t
t
9
Clock High to Data Valid
–
25
–
ns
ns
ns
ns
CHDV
t
12
Data Valid prior to Strobe Low
t
C
t
C
t
C
– 23
– 25
– 25
DVSL
SHAH
SHDH
9, 12
9, 12
Minimum Address Hold Time after strobe goes inactive
Data hold after strobes (CS and BHE/BLE) high
Wait Input
–
t
–
t
15
15
WAIT setup (stable high or low) to CLKOUT rising edge
WAIT hold (stable high or low) after CLKOUT rising edge
20
0
–
–
ns
ns
WS
t
WH
NOTE:
1. On a 16-bit bus, if only one byte is being written, then only one of BLE or BHE will go active. On an 8-bit bus, BLE goes active for all (odd or
even address) accesses. BHE will not go active during any accesses on an 8 bit bus.
2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all reads and fetches, in order to meet hold
time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address changes.
3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active
4. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance
for all outputs (except ClkOut) = 80 pF.
5. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H3 User Manual for details.
6. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus,
A3 – A1 are incremented for each new word of the burst. On an 8-bit bus, A3 – A0 are incremented for each new byte of the burst code fetch.
7. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a
maximum value is specified in the table for this parameter, it is tested.
28
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
AC ELECTRICAL CHARACTERISTICS (3.3 V +/–10%)
Vdd = 3.3 V +/– 10%; T
= –40°C to +85°C ( industrial )
amb
Limits
Symbol
Figure
Parameter
All Cycles
Unit
Min
Max
F
System Clock (internally called CClk) Frequency
System Clock Period = 1/FC
XTALIN High Time
0
30
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
t
C
13
13
13
13
13
All
All
All
All
All
14
33.33
t
t * 0.5
–
CHCX
C
t
XTALIN Low Time
t * 0.4
–
CLCX
CLCH
CHCL
C
t
t
XTALIN Rise Time
–
–
5
XTALIN Fall Time
5
t
Address Valid to Strobe low
t
– 21
–
AVSL
C
7
t
Address hold after CLKOUT rising edge
1
–
1
1
–
CHAH
t
Delay from CLKOUT rising edge to address valid
30
28
25
CHAV
CHSH
7
t
Delay from CLKOUT rising edge to Strobe High
Delay from CLKOUT rising edge to Strobe Low
ClkOut Duty Cycle High (into 40 pF max.)
Data Read Only
7
t
CHSL
t
t
–7
t
+3
CODH
CHCX
CHCX
t
10
Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at end
of Data Read Cycle (not code fetch)
t
C
– 12
–
ns
AHDR
Data Read and Instruction Fetch Cycles
t
7, 8, 10, 11
7, 8, 10, 11
10
Data In Valid setup to ClkOut rising edge
32
0
–
–
–
ns
ns
ns
DIS
2
t
Data In Valid hold after ClkOut rising edge
DIH
t
OE high to XA Data Bus Driver Enable
Write Cycles
t
C
– 19
OHDE
t
t
9
Clock High to Data Valid
–
30
–
ns
ns
ns
ns
CHDV
t
12
Data Valid prior to Strobe Low
t
– 23
DVSL
SHAH
SHDH
C
9, 12
9, 12
Minimum Address Hold Time after strobe goes inactive
Data hold after strobes (CS and BHE/BLE) high
Wait Input
–
tC – 25
t
t
C
– 25
–
t
15
15
WAIT setup (stable high or low)prior to CLKOUT rising edge
WAIT hold (stable high or low) after CLKOUT rising edge
25
0
–
–
ns
ns
WS
t
WH
NOTE:
1. On a 16-bit bus, if only one byte is being written, then only one of BLE or BHE will go active. On an 8-bit bus, BLE goes active for all (odd or
even address) accesses. BHE will not go active during any accesses on an 8-bit bus.
2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all reads and fetches, in order to meet hold
time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address changes.
3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active
4. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance
for all outputs (except ClkOut) = 80 pF.
5. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H3 User Manual for details.
6. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus,
A3 – A1 are incremented for each new word of the burst. On an 8-bit bus, A3 – A0 are incremented for each new byte of the burst code fetch.
7. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a
maximum value is specified in the table for this parameter, it is tested.
29
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
TIMING DIAGRAMS
All references to numbered Notes are to the notes following the AC Electrical Characteristics tables
ClkOut
A0
t
t
CHAV
CHAH
A19–A1
t
t
(Does Not Include A0)
CHSL
AHDR
t
AVSL
CS
BHE/BLE
OE
t
CHSH
Note 3
t
(Note 2)
DIH
t
DIS
D15–D0
Note:
On Generic Data Reads, A0 can terminate a full clock period before A19–A1, and therefore
should not be used on some peripheral devices.
SU01277
Figure 7. Read on 16-Bit Bus
ClkOut
A[19:0]
t
t
CHAV
CHAV
t
CHAV
Address
Address + 2
Address + 4
t
CHSL
t
CHSH
t
AVSL
CS
BHE/BLE
t
OHDE
Note 3
OE
t
t
t
DIH
(Note 2)
DIH
DIH
Note 2
Note 2
t
t
DIS
t
DIS
DIS
Driven
by XA
D[15:0]
Driven by XA
Note:
The processor can prefetch from one to eight words.
SU01131
Figure 8. Burst Code Fetch on 16-Bit Bus
30
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
ClkOut
t
t
CHSH
CHAV
A
t
CHSL
t
CS
AVSL
t
SHAH
Note 1
BHE/BLE
WE
t
SHDH
t
CHDV
D
SU01278
Figure 9. Write ( byte write on 8-bit bus, or all writes on 16-bit bus )
ClkOut
A19 – A1
A0
t
t
AHDR
CHAV
t
CHSL
t
CHSH
CS
t
AVSL
BLE
OE
Note 3
t
OHDE
t
DIH
t
Note 2
t
DIS
DIS
Driven by XA
Note 2
Driven by XA
D7 – D0
On all cycles on 8-bit bus, BHE remains high (inactive)
Note:
On the external bus, ALL XA-H4 reads are 16-bit reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the
extra byte. Thus, “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus. On an 8-bit bus, this will appear as two consecutive 8-bit reads even
though the CPU will only use one of the two bytes.
WARNING: Some 8-bit I/O devices (especially FIFOS) cannot operate correctly with 2 bytes being read for a one byte read. The most common (and least expensive)
solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this tech-
nique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
SU01283
Figure 10. Read (16-Bit or 8-Bit) on 8 Bit Bus
31
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Clkout
t
CHAV
t
t
t
CHAV
CHAV
CHAV
Even Address
Address + 1
Address + 2
Address + 3
t
CHAV
t
Note 3
CHSH
OE, BLE, CS
D[7:0]
t
t
t
t
t
t
t
t
DIH
DIS
DIH
DIS
DIH
DIS
DIH
DIS
Note 2
Note 2
Note 2
Note 2
LS Byte
MS Byte
LS Byte
MS Byte
Note:
BHE remains high (inactive) for all accesses on an 8-bit bus. A burst code fetch can be
from 1 to 8 words (1 word = 2 bytes), a 2 word fetch is shown here.
SU01245
Figure 11. Burst Code Fetch on 8-bit bus
Clkout
t
t
t
CHSH
CHAV
CHSL
A19 – A1
t
t
SHAH
A0
SHAH
t
CHSL
CS
t
AVSL
t
t
AVSL
BLE, WE
t
SHDH
DVSL
D7 – D0
Note. OE is inactive during all writes.
SU01246
Figure 12. 16-Bit Write on 8-Bit Bus
32
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
V
– 0.5
DD
0.7 V
DD
XTALIN
0.2 V – 0.1
DD
0.45 V
t
CHCX
t
t
t
CLCH
CHCL
CLCX
t
C
SU01146
Figure 13. External Clock Input Drive
t
CODH
ClkOut
WARNING: ClkOut is specified into 40 pF max, do not overload.
SU01147
Figure 14. ClkOut Duty Cycle
ClkOut
t
t
WH
WS
WAIT
t
t
– Setup time of WAIT to rising edge of ClkOut.
– Hold time of WAIT after ClkOut High.
WS
WH
SU01148
Figure 15. External WAIT Pin Timing
33
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
34
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
NOTES
35
1999 Sep 24
Philips Semiconductors
Preliminary specification
CMOS 16-bit highly integrated microcontroller
XA-H3
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 09-99
Document order number:
9397 750 06431
Philips
Semiconductors
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