KGL4195KD [OKI]
Telecom Circuit, 1-Func,;
| 型号： | KGL4195KD |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Telecom Circuit, 1-Func, 电信 电信集成电路 |
| 文件： | 总13页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1, 2008
ODHKGL4195KD-09
KGL4195KD
11.3 Gbps Modulator Driver IC
FEATURES
•
•
•
•
•
•
•
Wide Temperature Range
Maximum Input Data Rate
Output Amplitude
Maximum Output Offset
Crossing Point Controllability
Small Package
:
:
:
:
:
:
from -40°C to 95°C
up to 11.3Gbps
up to 3.0Vpp
1.2V at 50 Load
35% - 80%
4 x 4 mm QFN
Low Power Consumption
APPLICATIONS
•
•
•
•
•
•
Sonet OC-192 / STM64 Transmission System up to 11.3Gbps
WDM System
10GBE System
Optical Transponder/Transceiver/Transmitter
300Pin / XENPAK / Xpak / X2 /XFP
Sonet/SDH Test Equipment
GENERAL DESCRIPTIONS
KGL4195KD is a high performance electroabsorption modulator and direct modulated LASER diode driver IC
for sonet/SDH and 10GBE applications up to 11.3Gbps.
The device provids typically 3.0Vpp output , output amplitude control, output offset control and output crossing
point ( X-Point )control.
KGL4195KD data input accepts single-ended or differential AC coupled signal. KGL4195KD suports differential
DC coupled or AC coupled ( using external bias tee ) output.
The output amplitude is able to be controled from 1.0Vpp up to 3.0Vpp by bias voltage of VC1. The output offset
can be tuned over 1.2V by bias voltage VC2. The output crossing point ( X-Point ) is capable of adjusting from
35% to 80% of the output eye diagram via the differential voltage between VB1 and VB2.
KGL4195KD is very low power device, typical power consumption is 0.8W at output DC coupled and 2.5Vpp
output amplitude / 1.0V output offset condition or 0.65W at output AC coupled using bias tee and 2.5Vpp output
/ no offset condition.
The packege of KGL4195KD is 4 x 4mm QFN pacakge.
VD1
VD2
FUNCTION DIAGRAM
50
OUT
IN
Crossing
Point
Control
OUTB
INB
50
VB1 VB2
VC1 VC2
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ODHKGL4195KD-09
KGL4195KD
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VD1
Min
-0.3
-0.3
Max
4.0
Unit
V
Note
Supply Voltage
6.0
V
Output DC coupled 1)
Supply Voltage of Output Stage
VD2
Output AC coupled
using bias tee 2)
-0.3
4.0
V
X-Point Control and Reference Voltage
Output Amplitude Control Voltage
Output Bias Control Voltage
Input Amplitude
VB1/VB2
VC1
VC2
Vin
-1.0
-1.0
-1.0
-
2.4
1.6
2.6
1.5
100
125
V
V
V
Vpp
°C
°C
AC coupled
Operating Temperature at Package Base
Storage Temperature
Ts
-40
-45
Tst
1) Refer to TYPICAL APPLICATION ( Output DC coupled ) of page 6.
2) Refer to TYPICAL APPLICATION ( Output AC coupled ) of page 7.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
3.13
4.75
Typ
3.3
5.0
Max
Unit
V
Note
Supply Voltage
VD1
3.47
5.25
V
Output DC coupled 2)
Supply Voltage of Output Stage
VD2
Output AC coupled
using bias tee 3)
3.13
3.3
3.47
V
X-Point Control Voltage
VB1
VB2 1)
VC1
0.6
1.0
0
1.2
1.8
1.4
1.2
2.4
1.2
1.2
95
V
V
X-Point Reference Voltage
Output Amplitude Control Voltage
Output Bias Control Voltage
Single-ended Input Amplitude
Differential Input Amplitude
Operating Temperature at Package Base
Input Interface
1.2
-
-
-
-
-
V
VC2
0
V
0.4
0.2
-40
Vpp
Vpp
°C
AC coupled
AC coupled
Vin
Ts
AC coupled (External blocking capacitor is required)
DC coupled ( Need 50 termination to VD2 )2) or
AC coupled using bias tee 3)
Output Interface
1) VB2 can be open or biased by the external circuit. For VB2 opened, VB2 is biased at about 0.364 x VD1.
2) Refer to TYPICAL APPLICATION ( Output DC coupled ) of page 6.
3) Refer to TYPICAL APPLICATION ( Output AC coupled ) of page 7.
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KGL4195KD
ELECTRICAL CHARACTERISTICS
♦ TEMPERATURE RANGE -5°C ~ 85°C
This table is electrical characteristics at “OUT” port.
Parameter
Maximum Input Data Rate
Supply Current
Symbol
Condition
NRZ
Min
11.3
-
Typ
-
Max
-
Unit
Gbps
mA
Id1
90
135
Condition2, No Offset,
Maximum Amplitude
Conditon1,
Maximum Offset ,
Maximum Amplitude
-
-
-
120
160
0.65
160
mA
mA
W
Supply Current
Id2
-
-
Condition2, Amplitude
2.5Vpp,No offset
Power Consumption
Pw
Condition1, Amplitude
2.5Vpp, No Offset
-
-
0.8
1.0
3.0
-
1.2
-
W
50 load
Minimum Output Amplitude
Vo(min)
Vpp
Condition2, No Offset,
Maximum Amplitude
Conditon1, No Offset ,
Maximum Amplitude
2.6
Maximum Output Amplitude
Vo(max)
Vpp
2.7
-
3.0
2.0
-
-
-
Ta = R.T.
Amplitude Monitor Resistance
Output High Voltage
Rmod
DC coupled,
50 load, no offset
V(HI) 1)
VD2-0.5
VD2
V
Vo(ofs) 1)
V(LO)
Rbias
XPH
1.0
1.2
1.4
2.0
80
35
-
-
1.6
-
V
V
DC coupled, 50 load
DC coupled, 50 load
Ta = R.T.
Output High Voltage Offset
Minimum Output Low Voltage
Bias Monitor Resistance
-
-
%
%
%
ps
dB
High
Low
75
-
50 load, NRZ
X-Point Control Range
XPL
40
10
40
-
50 load, -5–85°C
50 load, 20%–80%
100kHz–10GHz
X-Point Stability
Del (Xp)
Tr/Tf
-10
-
Output Rise/Fall Time
Input Return Loss
27
12
S11
-
Note) Condition1 : VD2=5.0V, 50 load, output DC coupled
Condition2 : VD2=3.3V, 50 load, output AC coupled
3/13
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KGL4195KD
♦ Temperature range -40°C ~ 95°C
This table is electrical characteristics at “OUT” port.
Parameter
Maximum Input Data Rate
Supply Current
Symbol
Condition
NRZ
Min
11.3
-
Typ
-
Max
-
Unit
Gbps
mA
Id1
90
140
Condition2, No Offset,
Maximum Amplitude
Conditon1,
Maximum Offset ,
Maximum Amplitude
-
-
-
120
160
0.65
166
mA
mA
W
Supply Current
Id2
-
-
Condition2, Amplitude
2.5Vpp,No offset
Power Consumption
Pw
Condition1, Amplitude
2.5Vpp, No Offset
-
-
0.8
1.0
3.0
-
1.22
-
W
50 load
Minimum Output Amplitude
Vo(min)
Vpp
Condition2, No Offset,
Maximum Amplitude
Conditon1, No Offset ,
Maximum Amplitude
2.4
Maximum Output Amplitude
Vo(max)
Vpp
2.5
3.0
2.0
-
-
-
Ta = R.T.
Amplitude Monitor Resistance
Output High Voltage
Rmod
-
DC coupled,
50 load, no offset
V(HI) 1)
VD2-0.55
VD2
V
Vo(ofs) 1)
V(LO)
Rbias
XPH
0.9
1.2
1.4
2.0
80
35
-
-
1.6
-
V
V
DC coupled, 50 load
DC coupled, 50 load
Ta = R.T.
Output High Voltage Offset
Minimum Output Low Voltage
Bias Monitor Resistance
-
-
%
%
%
ps
dB
High
Low
73
-
50 load, NRZ
X-Point Control Range
XPL
42
12
43
-
50 load, -40–95°C
50 load, 20%–80%
100kHz–10GHz
X-Point Stability
Del (Xp)
Tr/Tf
-12
-
Output Rise/Fall Time
Input Return Loss
27
12
S11
-
Note) Condition1 : VD2=5.0V, 50 load, output DC coupled
Condition2 : VD2=3.3V, 50 load, output AC coupled
1) Output high voltage with offset control is defined by “V(HI)-Vo(ofs)
V(HI)
VD2
Vo(ofs)
Vo(min)
Vo(max)
V(LO)
GND
No Offset Condition
Maximum Offset Condition
4/13
ODHKGL4195KD-09
KGL4195KD
PACKAGE DIMENSIONS
( Top View )
PIN CONNECTION
No.
1
Symbol
GND
GND
GND
GND
Rmod
Rbias
GND
OUT
GND
OUTB
GND
GND
VC2
Note
4.0 ±0.2
Ground
Ground
Ground
Ground
#18
#13
2
3
4
5
Amplitude Monitor Output Port
Bias Monitor Output Port
Ground
6
7
8
Output Port
4195
D XXX
9
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Inverted Output Port
Ground
Ground
Output Bias Control Port
Output Amplitude Control Port
Supply Voltage Port
Supply Voltage Port
X-Point Reference Port
X-Point Control Port
Ground
VC1
#1
#6
VD2
VD1
( Side View )
VB2
VB1
GND
GND
INB
Ground
Inverted Input Port
Ground
GND
IN
Signal Input Port
Ground
GND
( Bottom View )
2 - 3.2
0.5Px5 = 2.5
Index-pattern (C0.2)
#14 #15
#18
#13
#16
#17
4 - R0.1
#5
#4
#1
#6
#3
#2
10 - 0.3
4 - 0.45
0.8
4 - (0.65)
4 - (0.85)
1.5
2.5
( Unit : mm )
Note : This package is non-hermetic.
5/13
ODHKGL4195KD-09
KGL4195KD
TYPICAL APPLICATION (DC coupled)
Chip
Capacitor
0.1F
Chip
Capacitor
0.1F
LD Anode
KGL4195KD
VD1
VD2
LD
AC Ground
50
OUTB
OUT
INB
Data-bar Input
50
EA
IN
Data Input
EML
Blocking
Capacitor
Ex. 0.1F
VB1
VB2
GND VC1 VC2
Chip
Capacitor
0.1F
6/13
ODHKGL4195KD-09
KGL4195KD
TYPICAL APPLICATION (AC coupled)
Chip
Capacitor
0.1F
Chip
Capacitor
0.1F
LD Anode
KGL4195KD
OUTB
VD1
VD2
LD
EA
50
AC Ground
INB
Data-bar Input
50
IN
Data Input
OUT
EML
Blocking
Capacitor
Ex. 0.1F
GND
VC1 VC2
VB1
VB2
Chip
Capacitor
0.1F
7/13
ODHKGL4195KD-09
KGL4195KD
TYPICAL CHARACTERISTICS ( OUTPUT DC COUPLED CONDITION )
Input Signal : 11.3Gbps, NRZ PN31, Differential 0.2Vp-p (each port)
VD1=3.3V, VD2=5.0V
Display Factor V:600mV/div, H:20ps/div
Test circuit diagram of these measurements is shown in page 9.
Maximum Amplitude
Minimum Amplitude
ID1 : 87.0mA
ID2 : 114.6mA
Power : 0.863W
Amplitude : 3.10Vpp
Tr/Tf : 27.6/26.2ps
JitterPP : 11.1ps
Xp : 49.7%
ID1 : 83.6mA
ID2 : 23.6mA
Power : 0.394W
Amplitude : 0.649Vpp
Tr/Tf : 25.8/20.0ps
JitterPP : 11.7ps
Xp : 50.5%
Crossing Point 80%
Amplitude Dependence
5
4
3
2
1
0
Sample 1 : Vhigh
Sample 1 : Vlow
Sample 2 : Vhigh
Sample 2 : VLow
ID1 : 88.1mA
ID2 : 114.6mA
Power : 0.863W
Amplitude : 3.08Vpp
Tr/Tf : 27.6/26.7ps
JitterPP : 12.8ps
Xp : 80.0%
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VC1 (V)
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KGL4195KD
TEST CIRCUIT EXAMPLE COMPATIBLE WITH OUTPUT DC COUPLED CONDITION
Power
Supply
VB1
Power
Supply
VD1
Power
Supply
VD2
Power
Supply
VC1
Power
Supply
VC2
Digital
Multi-
Meter
Vout
Digital
Multi-
Meter
Voutb
5.0V
3.3V
50
50
VB1
VB2
VD1
VD2
VC1
VC2
Vtop
0V
INB
OUTB
Vbase
PPG
Data-bar
11.3Gbps, PN31
Data
CH2
CH1
DCA
KGL4195KD
IN
OUT
Test Fixture
Bias Tee
At DC coupled,
Output Amplitude = Vtop – Vbase
Output High Voltage = Vout + Vtop
Output Low Voltage = Vout + Vbase
9/13
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KGL4195KD
TYPICAL CHARACTERISTICS ( OUTPUT AC COUPLED CONDITION )
Input Signal : 11.3Gbps, NRZ PN31, Differential 0.2Vp-p (each port)
VD1=3.3V, VD2=3.3V
Display Factor V:600mV/div, H:20ps/div
Test circuit diagram of these measurements is shown in page 11
Maximum Amplitude
Minimum Amplitude
ID1 : 84.3mA
ID2 : 112.7mA
ID1 : 79.8mA
ID2 : 20.8mA
Power : 0.331W
Amplitude : 0.58Vpp
Tr/Tf : 20.4/18.7ps
JitterPP : 10.9ps
Xp : 49.2%
Power : 0.650W
Amplitude : 3.01Vpp
Tr/Tf : 27.1/25.8ps
JitterPP : 10.8ps
Xp : 50.1%
Crossing Point 80%
PowerVSAmplitude
1.0
0.5
0.0
ID1 : 84.4mA
ID2 : 112.6mA
Power : 0.650W
Amplitude : 2.86Vpp
Tr/Tf : 27.1/25.3.ps
JitterPP : 14.4ps
Xp : 80.0%
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Output Amplitude (Vpp)
10/13
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KGL4195KD
TEST CIRCUIT EXAMPLE COMPATIBLE WITH OUTPUT AC COUPLED CONDITION
Power
Supply
VB1
Power
Supply
VD1
Power
Supply
VD2
Power
Supply
VC1
Power
Supply
VC2
3.3V
3.3V
VB1
VB2
VD1
VD2
VC1
VC2
Vtop
0V
INB
OUTB
Vbase
PPG
Data-bar
11.3Gbps, PN31
Data
CH2
CH1
KGL4195KD
DCA
IN
OUT
Test Fixture
Bias Tee
11/13
ODHKGL4195KD-09
KGL4195KD
APPLICATION NOTE
1. For stable operation;
To prevent a dependence of “X-Point” on the supply voltage VD1,
Case 1 : VB2 is open
VB2 is biased at about 0.364 x VD1 (1.2V@VD1=3.3V) by the internal circuit.
Control VB1, so that the voltage difference “VB1–VB2” is constant.
Case 2 : VB2 is biased
Bias VB2 at about 1.2V by using the external voltage source independent of VD1.
Control VB1 by using the external voltage source independent of VD1.
2. Power-up/shut-down sequence;
For power-up, supply voltage (VD2) at first, next supply voltage (VD1), then control voltages ( VB1, (VB2),
VC1, VC2 ).
For shut-down, control voltages ( VB1, (VB2), VC1, VC2 ). at first, next VD1, then VD2.
Customer does not need to care about the sequence for the control voltages (VB1,(VB2),VC1,VC2).
TYPICAL PCB LAYOUT AND ASSEMBLING INFORMATION
Please request us the application note named GTD18791 and GTD18806.
ESD CONSIDERATIONS
This device can be damaged by ESD; therefore appropriate precautions must be taken to avoid exposure to
ESD and EOS during handling, assembly, and testing of these devices. Failure to adhere to proper
ESD/EOS precautions during handling and assembly of these devices can damage or adversely affect
device reliability.
SAFETY AND HANDLING INFORMATION ON GaAs DEVICES
Arsenic Compound (GaAs Devices)
The product contains arsenic (As) as a compound.
This material is stable for normal use, however, its dust or vapor may be potentially hazardous to the human
body.
Avoid ingestion, fracture, burning or chemical treatment to the product.
• Do not put the product in your mouth.
• Do not burn or destroy the product.
• Do not perform chemical treatment for the product.
Keep laws and ordinances related to the disposal of the products.
12/13
ODHKGL4195KD-09
KGL4195KD
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. OKI SEMICONDUCTOR assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident,
improper handling, or unusual physical or electrical stress including, but not limited to, exposure to
parameters beyond the specified maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2008 OKI SEMICONDUCTOR CO., LTD.
13/13
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