ML2250_技术文档

FEDL2250DIGEST-09

Issue Date: Sep. 15, 2005

OKI Semiconductor

ML2251/52/53/54/56-XXX,

ML22Q54/Q58

2-Channel Mixing Oki ADPCM Algorithm-Based Speech Synthesis LSI

This document contains minimum specifications. For full specifications, please contact your nearest Oki office or

representative.

GENERAL DESCRIPTION

The ML2250 family is a 2-channel mixing speech synthesis device with an on-chip voice data (i.e., phrases)

storing mask ROM and a flash memory. Besides playing the built-in voice data, this device can output voice data

that is input from outside the device. This ML2250 family allows selecting the playback method from the 8-bit

PCM, non-linear 8-bit PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithms. And the sound volume

is adjustable as well.

The ML2250 family incorporates a 14-bit D/A converter and low-pass filter.

It is easy to configure a speech synthesizer by externally connecting a power amplifier and a CPU to the ML2250

family.

The ML2250 family line-up includes 2 types of products: with on-chip mask ROM, and with on-chip flash

memory.

ML2251/52/53/54/56-XXX

This is a CMOS single chip speech synthesis device with an on-chip mask ROM. Products with 5 types of mask

ROMs are available in the ML2250 family depending upon the total playback time length.

ML22Q54/Q58

The ML22Q54/Q58 is a speech synthesis device with a 4-Mbit flash memory built in. The voice data can be

easily written to the flash memory using a special tool. The on-chip flash memory product is suitable for the

diversified low volume production or short delivery time applications that the on-chip mask ROM product

cannot support. The ML22Q54/Q58 is most suitable for evaluation because the circuit configuration is the same

as the on-chip mask ROM product. As it is easy to write to build in-flash memory, it is able to combine fixed

message and variable message.

1/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

Table below summarizes the points of difference between the ML2250 family and currently manufactured

products with a ROM built in.

ML2250 family

MSM6650 family

MSM9800 family

ML2210 family

Serial

Parallel, serial or Parallel or

stand-alone

Interface

Parallel or serial

stand-alone

2-bit ADPCM2

4-bit ADPCM2

8-bit PCM

8-bit non-linear PCM

16-bit PCM

4-bit ADPCM

8-bit PCM

8-bit non-linear PCM

4-bit ADPCM

8-bit PCM

8-bit non-linear PCM

Playback method

Max. number of

phrases

256

127

63

247

4.0/5.3/6.0/6.4/8.0/10.7

Sampling frequency /12.0/12.8/16.0/21.3/

4.0/5.3/6.4/8.0/

10.7/12.8/16.0/

32.0

4.0/5.3/6.4/8.0/10.7/ 4.0/5.3/6.4/8.0/10.7/

(kHz)

24.0/25.6/32.0/42.7/

48.0

12.8/16.0

256 kHz (CR

oscillation)

4.096 MHz (XT)

Voltage type: 12

bits

256 kHz (CR

oscillation)

4.096 MHz (XT)

Clock frequency

4.096 MHz

D/A converter

Low-pass filter

Voltage type: 14 bits

Current type: 10 bits Current type: 12 bits

FIR type interpolation

filter

Secondary comb

filter

Secondary comb

Primary comb filter

filter

Number of channels 2 channels

2 channels

1 channel

None

Both 2 channels without Can edit 8

Phrase control table user definable phrase

restrictions

phrases (1

channel only)

4 steps

(–6 dB steps)

4 types

Can edit 8 phrases

29 steps

Volume adjustment

Set at VREF.

None

Set at VREF.

None

(–2 dB/–5 dB steps)

Repeat function

STOP

No limit

Each channel

independent

Simultaneous

channels 1 and 2

Available

Seam silence

interval in

0 (Note)

4 sampling cycles 3 sampling cycles

4 sampling cycles

continuous playback

External data input

possible

Others

—

Note: Continuous playback shown in the figure below is possible.

1 phrase

Conventional

ML2250 family

Silence interval

No silence interval

2/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

FEATURES

Maximum playback time length (sec) (In 4-bit ADPCM2)

F_SAM= 4.0 kHz F_SAM= 6.4 kHz F_SAM= 8.0 kHz F_SAM= 16 kHz F_SAM= 32 kHz

Type

ROM capacity

ML2251

ML2252

ML2253

ML2254

ML22Q54

ML2256

ML22Q58

512 Kbit

1 Mbit

3 Mbit

4 Mbit

6 Mbit

8 Mbit

31.7

64.5

19.8

40.3

15.8

32.2

7.9

16.1

48.8

65.2

98.0

130.4

3.9

8.0

195.5

261.1

392.1

522.2

122.2

163.2

245.1

326.4

97.7

24.4

32.6

49.0

65.2

130.5

196.0

261.0

Non-linear 8-bit PCM, 8-bit PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithms

Serial input/parallel input selectable

Phrase control table function i.e., user definable phrase control table function

2 channels mixing function

Master clock frequency:

Sampling frequency:

4.096 MHz

4.0 kHz, 5.3 kHz, 6.0kHz, 6.4 kHz, 8.0 kHz, 10.7 kHz, 12.0kHz,

12.8 kHz, 16.0 kHz, 21.3 kHz, 24.0kHz, 25.6 kHz, 32.0 kHz,

42.7 kHz, 48 kHz

Maximum number of phrases:

256 phrases

Sound volume adjustment function built in (2 sounds independently adjustable in 29 steps)

External voice data can be input

14-bit D/A converter built in

Built-in low-pass filter:

Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K)

(ML2251-XXXGA/ ML2252-XXXGA/ ML2253-XXXGA/

Digital filter

ML2254-XXXGA /ML2256-XXXGA / ML22Q54GA/ML22Q58GA)

(P-VFLGA33-5.03X5.78-0.80-W)

33-pin W-CSP

(ML2253-XXXHB/ ML2254-XXXHB)

(ML2256-XXXHB)

3/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

BLOCK DIAGRAM

ML2251/52/53/54-/56XXX

4/36

FEDL2250DIGEST-09

OKI Semiconductor

ML22Q54

ML2250 family

5/36

FEDL2250DIGEST-09

OKI Semiconductor

ML22Q58

ML2250 family

6/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

PIN CONFIGURATION (TOP VIEW)

ML2251/52/53/54/56-XXXGA

44-pin plastic QFP

NC

DW

BUSY1

1

2

3

4

5

6

7

8

9

33 NC

32 SERIAL

31 DGND

30 AV_DD

29 AOUT

28 DAO

27 AGND

26 D7/DI

25 NC

DL

NCR2/

NCR1/NDR

RD

TESTO1

TESTO2

RESET

TEST 10

NC 11

24 D6/SCK

23 D5/DO

NC: No Connection

7/36

FEDL2250DIGEST-09

OKI Semiconductor

ML22Q54GA

ML2250 family

44-pin plastic QFP

NC

DW

BUSY1

1

2

3

4

5

6

7

8

9

33 NC

32 SERIAL

31 DGND

30 AV_DD

29 AOUT

28 DAO

27 AGND

26 D7/DI

25 NC

DL

NCR2/

NCR1/NDR

RD

TESTO

BY

RD/

RESET

TEST 10

NC 11

24 D6/SCK

23 D5/DO

NC: No Connection

8/36

FEDL2250DIGEST-09

OKI Semiconductor

ML22Q58GA

ML2250 family

44-pin plastic QFP

NC

DW

BUSY1

1

2

3

4

5

6

7

8

9

33 NC

32 SERIAL

31 DGND

30 AV_DD

29 AOUT

28 DAO

27 AGND

26 D7/DI

25 NC

DL

NCR2/

NCR1/NDR

RD

TESTO

BY

RD/

RESET

TEST 10

NC 11

24 D6/SCK

23 D5/DO

NC: No Connection

9/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2253/54-XXXHB

ML2250 family

33pin W-CSP(Bottom View)

D5/DO

D6/SCK

AGND

DAO

D3

D4

D1

D2

DGND

XT

TEST

6

5

4

3

2

1

D0

DVDD

RESET

TESTO1

BUSY1

D7/DI

TESTO2

AOUT

DGND

NCR1/NDR

RD

AVDD

CS

WR

NCR2/DL

SERIAL

F

OPTANA

E

DGND

D

DVDD

C

DW

BUSY2/ERR

B

A

10/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2256-XXXHB

ML2250 family

33pin W-CSP

(Bottom View)

XT

D0

D5

D6

D3

D4

D7

GND

D1

XT

7

6

VDD

AGND

DAO

D2

TEST

TESTO1

NCR2/DL

WR

RESET

RD

5

4

3

2

1

TESTO2

DW

AOUT

AVDD

NCR1/NDR

BUSY1

SERIAL

OPTANA

GND

E

CS

D

GND

C

VDD

B

BUSY2/ERR

A

11/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

PIN DESCRIPTIONS-1

ML2251/52/53/54/56-XXXGA and ML2253/54/56-XXXHB Common Pins

QFP

WCSP

ML2256

WCSP pin

Symbol

Type

Description

When using the built-in ROM for voice output, this pin

outputs “L” level while channel 2 side processes a

command and while plays back voice.

BUSY2/ER

Works as ERRpin when using the EXT command for voice

output. If an abnormality occurred in the transfer of data,

the pin will output “L” level and the voice output may

become noisy.

43

A1

O

R

“H” level at power on.

Outputs “L” level while the channel 1 side processes a

command and plays back voice.

“H” level at power on.

3

4

B2

A2

B3

BUSY1

O

The command input of channel 2 side is valid at “H” level

when using the built-in ROM for voice output.

Works as DLpin when using EXT command for the voice

output. This pin outputs the signal that captures voice

data to inside. The data is captured inside on the rising

edge of DL.

NCR2/DL

“H” level at power on.

The command input of channel 1 side is valid at “H” level

when using the built-in ROM for voice output.

Works as NDR pin when using EXT command for the

voice output. The voice data input is valid at “H” level.

“H” level at power on.

NCR1/ND

R

5

C3

A3

O

At “L” level input, the device enters the initial state; the

oscillation stops, and AOUT output and DAQ output are

GND level at this time.

9

B4

A5

B5

RESET

I

Test pin for the device.

Input “L” level to this pin. This pin has a pull-down resistor

built in.

10

TEST

Wired to a crystal or ceramic oscillator.

A feedback resistor of around 1 M is built in between this

XT pin and XTpin (pin 15).

When using an external clock, input the clock from this

pin.

14

15

A6

B6

A7

B7

XT

I

Wired to a ceramic or crystal oscillator.

When using an external clock, keep this pin open.

XT

O

16

18

19

20

E6

D5

D6

C5

D7

C5

C6

B6

D3

D2

D1

D0

CPU interface data bus pins in the parallel input interface.

I/O Channel status output pins at RDpin = “L” level.

In the serial input interface, keep these pins at “L” level.

CPU interface data bus pin in the parallel input interface.

When RDpin is at “L” level, this pin D4 usually outputs “L”

level.

21

E5

D6

D4

I/O

In the serial input interface, keep this pin at “L” level.

CPU interface data bus pin in the parallel input interface.

When RDpin is at “L” level, this D5/DO pin usually outputs

“L” level.

23

F6

E7

D5/DO

I/O Works as channel status output pin in the serial interface.

When CS and RD pins are “L” level, the status of each

channel is output serially from this D5/DO pin in

synchronization with SCK clock.

12/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

QFP

ML2256

WCSP pin

Symbol

D6/SCK

Type

I/O

Description

CPU interface data bus pin in the parallel input interface.

Usually outputs “L” level when RD= “L” level.

Works as serial clock input pin in the serial input interface.

When the SCK input is at “L” level on the falling edge of WR,

RD, DW, the DI input is captured in the device on the rising

edge of SCK clock. And when the SCK input is at “H” level

on the falling edge of WR, RD, DW, the DI input is captured

on the falling edge of SCK clock.

24

F5

E6

CPU interface data bus pin in the parallel input interface.

26

C4

D5

D7/DI

I/O Usually output “L” level when RDis at “L” level.

Works as serial data input pin in the serial input interface.

28

29

F3

E3

E4

E3

DAO

O

DAO pin outputs analog signal of 14-bit DAC.

AOUT pin usually outputs the analog signal of 14-bit DAC

via voltage follower.

AOUT

CPU interface switching pin.

32

36

37

42

F1

D2

E1

C2

D2

D1

C2

B2

SERIAL

CS

I

Serial input interface at “H” level. And parallel input interface

at “L” level.

CPU interface chip select pin.

When CS pin is at “H” level, the WR, DW, and RD signals

cannot be input to the device.

Keep this pin “L” level. The analog signal of 14-bit DAC is

output from DAO pin and from AOUT pin via voltage

follower.

OPTANA

WR

CPU interface write signal.

When CSpin is at “H” level, the WRsignal cannot be input to

the device.

Data write signal when using EXT command for the voice

output.

Set the pin to “H” level when not using EXT command.

When CSpin is at “H” level, the DWsignal cannot be input to

the device.

This pin has a pull-up resistor built in.

CPU interface read signal.

2

6

B1

A3

C3

DW

I

When CSpin is at “H” level, the RDsignal cannot be input to

the device.

A4

RD

This pin has a pull-up resistor built in.

Output pin for testing.

Keep this pin open.

B4

C4

TESTO1

TESTO2

7, 8

30

B3, A4

F2

O

Analog power supply pin.

Insert a 0.1 F or larger bypass capacitor between this pin

and AGND pin.

E2

AV_DD

DV_DD

—

Digital power supply pin.

Insert a 0.1 F or larger bypass capacitor between this pin

and DGND pin.

13, 40

B5, C1

A6,B1

—

27

17, 31,

39

F4

C6, D1,

E2

E5

AGND

DGND

—

Analog ground pin.

C1,C7,E1

Digital ground pin.

13/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

PIN DESCRIPTIONS-2

ML22Q54/Q58GA Common Pins

44-pin plastic QFP

Symbol

Type

O

Description

When using the built-in ROM for voice output, this pin outputs “L” level

while channel 2 side processes a command and while plays back voice.

Works as ERRpin when using EXT command for the voice output. If an

abnormality occurred in the transfer of data, the ERR pin outputs “L”

level and the voice output may become noisy.

“H” level at power on.

43

BUSY2/ERR

Outputs “L” level while the channel 1 side processes a command and

while plays back voice.

“H” level at power on.

The input command of channel 2 is valid at “H” level when using the

built-in ROM for voice output.

DL pin when using EXT command for the voice output. It outputs the

voice data capture signal. The data is captured on the rising edge of DL.

“H” level at power on.

3

4

BUSY1

O

NCR2/DL

The command input of channel 1 side is valid at “H” level when using

the built-in ROM for voice output.

NDR pin when using EXT command for the voice output. The voice data

input is effective at “H” level.

5

NCR1/NDR

O

“H” level at power on.

When “L” level is input to this pin, the device is reset, the oscillation

stops, and AOUT and DAQ outputs go into GND level.

Test pin for the device.

9

RESET

I

10

TEST

Input “L” level to this pin. This pin has a pull-down resistor built in.

Wired to a crystal or ceramic oscillator.

A feedback resistor of around 1 M is built in between this XT pin and

XTpin (pin 15).

14

XT

I

When using an external clock, input the clock from this pin.

Wired to a ceramic or crystal oscillator.

When using an external clock, keep this pin open.

CPU interface data bus pins in the parallel input interface.

Channel status output pins when RDis at “L” level.

The pins output the flash memory data when reading the built-in flash

memory data.

In the serial input interface, keep these pins at “L” level.

CPU interface data bus pin in the parallel input interface.

The pin outputs flash memory data when reading the built-in flash

memory data.

When RDis at “L” level other than when reading the flash memory data,

this pin usually outputs “L” level.

15

XT

O

16

18

19

20

D3

D2

D1

D0

I/O

21

D4

In the serial input interface, keep this pin at “L” level.

CPU interface data bus pin in the parallel input interface.

The pin outputs flash memory data when reading the built-in flash

memory data.

When RDis at “L” level other than when reading the flash memory data,

this pin usually outputs “L” level.

23

D5/DO

I/O

Channel status output pin in the serial input interface.

When CS and RD are at “L” level, this D5/DO pin serially outputs the

status of each channel in synchronization with SCK clock. When

reading data of the built-in flash memory, the pin will output serially the

flash memory data.

14/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

Symbol

D6/SCK

Type

I/O

Description

Works as CPU interface data bus pin in parallel input interface.

Works as flash memory data output pin when reading the built-in flash

memory data.

When RDis at “L” level other than when reading the flash memory data,

this D6/SCK pin usually outputs “L” level.

Works as serial clock input pin in the serial input interface.

When the SCK input is at “L” level on the falling edge of WR, RD, DW,

the DI input is captured in device on the rising edge of SCK clock. And

when the SCK input is at “H” level on the falling edge of CS, the DI input

is captured on the falling edge of SCK clock.

24

Works as CPU interface data bus pin in the parallel input interface.

Works as flash data output pin when reading the built-in flash memory

data.

When RD is at “L” level at times other than reading the flash memory

data, this D7/DI pin usually outputs “L” level.

26

D7/DI

I/O

Works as serial data input pin in the serial input interface.

DAO pin outputs the 14-bit DAC analog signal.

AOUT pin outputs the 14-bit DAC analog signal via voltage follower.

CPU interface switching pin.

At “H” level: Serial input interface. At “L” level: Parallel input interface.

CPU interface chip select pin.

28

29

DAO

O

AOUT

32

SERIAL

I

36

CS

I

When CSpin is at “H” level, the WR, DW, and RDsignals cannot be input

to the device.

Keep this pin “L” level. 14-bit DAC analog signal is output from DAO pin

and 14-bit DAC analog signal is output from AOUT pin via the voltage

follower.

37

42

OPTANA

I

CPU interface write signal.

WR

When CSpin is at “H” level, the WRsignal cannot be input to the device.

Data write signal at EXT command and Flash I/F command.

When the EXT and Flash I/F commands are not used, keep this pin at

“H” level.

2

DW

I

When CSpin is at “H” level, the DWsignal cannot be input to the device.

This pin has a pull-up resistor built in.

CPU interface read signal.

This pin is used when reading the status signal of each channel or when

reading data of the built-in flash memory.

When not in use, keep this pin to “H” level.

6

7

8

RD

I

This pin has a pull-up resistor built in.

Output pin for testing.

Keep this pin open.

TESTO

RD/BY

O

Output pin to indicate the automatic erase/write status of the built-in

flash memory.

Outputs “L” level during erase or programming cycle to indicate the

busy state. Goes to “H” level at the end of the erase or programming

cycle and enters into the ready state.

15/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

30

Symbol

AV_DD

Type

Description

Analog power supply pin.

—

Insert a 0.1 F or larger bypass capacitor between this pin and AGND

pin.

Digital power supply pin.

13, 40

DV_DD

—

Insert a 0.1 F or larger bypass capacitor between this pin and DGND

pin.

27

AGND

DGND

—

Analog ground pin.

Digital ground pin.

17, 31, 39

Applicable to ML22Q58 Pins

38

Symbol

Type

O

Description

3V regulator output pin for the built-in flash power supplies. Connect a

10 F or larger condenser between REGOUT pin and DGND pin.

Reference voltage output pin for regulator. Recommends connecting a

150pF condenser between REGOUT pin and DGND pin.

REGOUT

41

VBG

O

16/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V)

Unit

Parameter

Power supply voltage

Input voltage

Symbol

V_DD

Condition

Ta = 25°C

ML2251/52/53/54/56-XXX

ML22Q58

Rating

–0.3 to +7.0

–0.3 to +4.6

V

Ta = 25°C, ML22Q54

V_IN

Ta = 25°C

–0.3 to V_DD+0.3

V

Ta=25°C

Without ML2253/54-XXXHB

Ta=25°C

900

Power Dissipation

P_D

mW

660

1060

6

ML2253/54-XXXHB

Ta=25°C

ML2256-XXXHB

Ta = 25 C, Applies to output pins

excluding REGOUT pin

Ta = 25 C, Applies to REGOUT pin

—

mA

Output short current

Storage temperature

I_SC

45

mA

T_STG

–55 to +150

°C

RECOMMENDED OPERATING CONDITIONS (3 V)

ML225152/53/54/56-XXX, ML22Q54/Q58

(GND = 0 V)

Unit

Parameter

Symbol

V_DD

Condition

ML2251/52/53/54/56-XXX,

ML22Q54

Range

2.7 to 3.6

V

Power supply voltage

ML22Q58

2.7 to 3.3

–40 to +85

0 to +70

ML2251/52/53/54/56-XXX

ML22Q54/Q58

Operating temperature

Master clock frequency

T_OP

f_OSC

°C

Min.

3.5

Typ.

Max.

4.5

—

MHz

4.096

RECOMMENDED OPERATING CONDITIONS (5 V)

ML2251/52/53/54/56-XXX, ML22Q58

(GND = 0 V)

Parameter

Symbol

V_DD

Condition

—

Range

4.5 to 5.5

–40 to +85

0 to +70

0 to +50

Typ.

Unit

V

°C

Power supply voltage

ML2251/52/53/54/56-XXX

ML22Q58

Operating temperature

Master clock frequency

T_OP

ML22Q58 (Writing Flash)

Min.

3.5

Max.

4.5

f_OSC

—

MHz

4.096

17/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

ELECTRICAL CHARACTERISTICS

DC Characteristics (3 V)

ML2251/52/53/54/56-XXX, ML22Q54/Q58

ML2251/52/53/54/56-XXX: DV_DD= AV_DD= 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = –40 to +85°C

ML22Q54: DV_DD= AV_DD= 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = 0 to +70°C

ML22Q58 : DV_DD= AV_DD= 2.7 to 3.3 V, DGND = AGND = 0 V, Ta = 0 to +70°C

Parameter

“H” input voltage

“L” input voltage

“H” output voltage

“L” output voltage

“H” input current 1

“H” input current 2

(Note 1)

Symbol

V_IH

Condition

—

Min.

0.86 V_DD

—

Typ.

—

Max.

Unit

V

—

0.14 V_DD

—

V_IL

—

V

V_OH

V_OL

I_IH1

I_OH= –1 mA

I_OL= 2 mA

V_IH= V_DD

V_DD–0.4

—

0.4

V

—

10

A

I_IH2

V_IH= V_DD

0.3

2.0

15

A

“H” input current 3

(Note 2)

V_IH= V_DD

Pull-down resistor built in pin

V_IL= GND

I_IH3

I_IL1

I_IL2

8

40

—

130

—

A

“L” input current 1

“L” input current 2

(Note 3)

–10

–120

V_IL= GND

Pull-up resistor built in pin

–40

–10

“L” input current 3

(Note 1)

I_IL3

I_DD1

I_DD2

V_IL= GND

–15

—

–2.0

6

–0.3

35

A

mA

f_OSC= 4.096 MHz at no load

(ML2251/52/53/54/56-XXX)

f_OSC= 4.096 MHz at no load

(ML22Q54/Q58)

Playback

Operating current

consumption

—

9

35

Built-in Flash

f_OSC= 4.096 MHz at no load

Read Operation

memory access

Operating current

consumption 1

Built-in Flash

memory access

Operating current

consumption 2

I_DD3

I_DD4

I_DDS

—

10

20

35

60

mA

(ML22Q54/Q58)

f_OSC= 4.096 MHz at no load

Write and Erase Operation

(ML22Q54/Q58)

Ta = –40 to +70°C

Ta = –40 to +85°C

Ta = 0 to +70°C

(ML22Q54/Q58)

—

15

50

A

Standby current

consumption

—

55

A

Notes: 1. Applies to XT pin.

2. Applies to TEST pin.

3. Applies to RDand DWpins.

18/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

DC Characteristics (5 V)

ML2251/52/53/54/56-XXX, ML22Q58

ML2251/52/53/54/56-XXX : DV_DD= AV_DD= 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = –40 to +85°C

ML22Q58 : DV_DD= AV_DD= 2.7 to 3.3 V, DGND = AGND = 0 V, Ta = 0 to +70°C

Parameter

“H” input voltage

“L” input voltage

“H” output voltage

“L” output voltage

“H” input current 1

“H” input current 2

(Note 1)

Symbol

V_IH

Condition

—

Min.

0.8 V_DD

—

Typ.

—

Max.

—

Unit

V

V_IL

V_OH

V_OL

—

0.2 V_DD

—

V

I_OH= –1 mA

I_OL= 2 mA

V_IH= V_DD

V

_DD–0.4

—

0.4

V

I_IH1

—

10

A

I_IH2

V_IH= V_DD

0.8

5.0

20

A

“H” input current 3

(Note 2)

V_IH= V_DD

Pull-down resistor built in pin

V_IL= GND

I_IH3

I_IL1

I_IL2

30

–10

—

350

—

A

“L” input current 1

“L” input current 2

(Note 3)

V_IL= GND

Pull-up resistor built in pin

–230

–60

“L” input current 3

(Note 1)

I_IL3

I_DD1

I_DD2

V_IL= GND

–20

—

–5.0

19

–0.8

40

A

mA

f_OSC= 4.096 MHz at no load

(ML2251/52/53/54/56-XXX)

f_OSC= 4.096 MHz at no load

(ML22Q58)

Operating current

consumption

—

22

40

Built-in Flash

f_OSC= 4.096 MHz at no load

Read Operation

memory access

Operating current

consumption 1

Built-in Flash

memory access

Operating current

consumption 2

I_DD3

I_DD4

I_DDS

—

23

33

40

60

mA

(ML22Q58)

f_OSC= 4.096 MHz at no load

Write and Erase Operation

(ML22Q58)

Ta = –40 to +70°C

Ta = –40 to +85°C

Ta = 0 to +70°C

(ML22Q58)

—

15

A

Standby current

consumption

100

—

100

A

Notes: 1. Applies to XT pin.

2. Applies to TEST pin.

3. Applies to RDand DWpins.

19/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

Analog Section Characteristics (3 V)

ML2251/52/53/54/56-XXX, ML22Q54/Q58

ML2251/52/53/54/56-XXX: DV_DD= AV_DD= 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = –40 to +85°C

ML22Q54: DV_DD= AV_DD= 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = 0 to +70°C

ML22Q58 : DV_DD= AV_DD= 2.7 to 3.3 V, DGND = AGND = 0 V, Ta = 0 to +70°C

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

AOUT output load

resistance

R_LAO

—

50

—

k

AOUT output voltage range

DAO output impedance

V_AOUT

R_DAO

No output load

0.5

30

—

AV_DD–0.5

V

k

—

50

70

Analog Section Characteristics (5 V)

ML2251/52/53/54/56-XXX, ML22Q58

ML2251/52/53/54/56-XXX : DV_DD= AV_DD= 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = –40 to +85°C

ML22Q58 : DV_DD= AV_DD= 2.7 to 3.3 V, DGND = AGND = 0 V, Ta = 0 to +70°C

Parameter

output

resistance

Symbol

Condition

Min.

Typ.

Max.

Unit

AOUT

load

R_LAO

—

50

—

k

AOUT output voltage range

DAO output impedance

REGOUT output voltage

VBG output voltage

V_AOUT

R_DAO

V_REGO

V_BG

No output load

—

0.5

30

2.7

1.0

—

50

3

AV_DD–0.5

V

k

V

70

3.3

1.5

ML22Q58

1.3

20/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

FUNCTIONAL DESCRIPTION

Micro-computer Interface

The micro-computer interface in the ML2250 family has 2 types of interface circuits built in: Parallel interface and

serial interface. The interface setting can be changed with the SERIAL pin.

SERIAL pin = "H" level: Serial interface

SERIAL pin = "L" level: Parallel interface

Table below shows the SERIAL pin status in the serial and parallel interfaces.

SERIAL = “L”

SERIAL = “H”

Parallel interface

Serial interface

D7 (I/O)

D6 (I/O)

D5 (I/O)

D4 (I/O)

D3 (I/O)

D2 (I/O)

D1 (I/O)

D0 (I/O)

D (I)

SCK (I)

DO (O)

D4 (I)

D3 (I)

D2 (I)

D1 (I)

D0 (I)

Serial data input pin

Serial clock input pin

Serial data output pin

Not used. (Input “L” level.)

Data input/output pins

1. Parallel Interface

When selecting the parallel interface, the I/O pins ÝÍ, ÉÎô ÜÉ, D7 to D0, and ÎÜ are used as input pins to input

various commands and data, and as output pins to read out the status of the commands and data input.

The micro-computer interface becomes effective when the ÝÍ pin is set to “L” level.

When a command or data is input, the input data to D7 through D0 pins is captured inside the device on the

rising edge of the ÉÎ pin.

The ÜÉ pin is used to input data after having input the EXT or Flash I/F command. The method to input data to

the ÜÉ pin is the same as the method to input command from the ÉÎ pin.

To read the channels status, pins ÝÍ and ÎÜ are made “L” level. By doing so, the status signals (NCR1, NCR2,

ÞËÍÇï, ÞËÍÇî) of each channel are output to D3 through D0 pins. D7 to D4 pins usually output “L” level.

Command and Data Input Timing

CS (I)

WR, DW (I)

Data Stable

D7 to D0 (I/O)

21/36

FEDL2250DIGEST-09

OKI Semiconductor

Status Read Timing

ML2250 family

CS (I)

RD (I)

D7 to D0 (I/O)

Data Stable

Table below shows the contents of each data output when reading the status of the channels.

D7

D6

D5

D4

D3

D2

D1

D0

Output status signal

“L” level

Channel 2 busy output (BUSY2)

Channel 1 busy output (BUSY1)

Channel 2 NCR output (NCR2)

Channel 1 NCR output (NCR1)

The ÞËÍÇ signal outputs “L” level when either a command is being processed or the playback of a pertinent

channel is going on. In other states, the ÞËÍÇ signal outputs “H” level.

The NCR signal outputs “L” level when either a command is being processed or a pertinent channel is in standby

for playback. In other states, the NCR signal outputs “H” level.

To read out a status after inputting Flash I/F command for ML22Q54/Q58, D7-D0 pins output “L” level during

command processing. After the command processing is completed, D7-D0 pins output ”H” level.

22/36

FEDL2250DIGEST-09

OKI Semiconductor

2. Serial Interface

ML2250 family

When selecting the serial interface, the I/O pins ÝÍ, ÉÎ, ÜÉ, DI, SCK, ÎÜ, and DO are used as input pins to

input various commands and data, and as output pins to read out the status of the commands and data.

The micro-computer interface becomes effective when ÝÍ pin is set to “L” level.

To input the commands and data, “L” level is input to ÝÍ and ÉÎ pins followed by, from MSB, to DI pin in

synchronization with the input clock signal at SCK pin. Data at DI pin is captured inside the device on the

rising or falling edge of the clock at SCK pin. And the command is executed on the rising edge of the ÉÎ pin.

The selection of rising/falling edge of SCK clock is determined by the input level of the SCK pin on the falling

edge of the ÝÍ pin. If the SCK pin on the falling edge of the ÝÍ pin is at “L” level, the DI pin data is captured

inside the device on the rising edge of SCK clock. Conversely, if the SCK pin on the falling edge of the ÝÍ pin

is at “H” level, then the DI pin data is captured on the falling edge of SCK clock.

Use the ÜÉ pin to input various data after having input the EXT or Flash I/F command. The data input method

is the same as to input data from the ÉÎ pin.

The selection of rising/falling edge of SCK clock is determined by the input level of the SCK pin on the falling

edge of the ÉÎ pin. If the SCK pin on the falling edge of the ÉÎ pin is at “L” level, the DI pin data is captured

inside the device on the rising edge of SCK clock. Conversely, if the SCK pin on the falling edge of the ÉÎ pin

is at “H” level, then the DI pin data is captured on the falling edge of SCK clock.

Use the ÜÉ pin to input various data after having input the EXT or Flash I/F command. The data input method

is the same as to input data from the ÉÎ pin.

Command and Data Input Timings

SCK Rising Edge Operation

CS(I)

WR, DW(I)

DI(I)

D7 D6 D5 D4 D3 D2 D1 D0

SCK(I)

SCK falling Edge Operation

CS(I)

WR, DW(I)

DI(I)

D7 D6 D5 D4 D3 D2 D1 D0

SCK(I)

23/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

To read the channel status, input “L” level to ÝÍ and ÎÜ pins. DQ pin will output the channel status in

synchronization with SCK clock.

The selection of rising/falling edge of SCK clock, similar to when inputting the commands and data, is determined

by the level at SCK pin at the falling edge of ÎÜ pin.

The status signals in the parallel interface are output to D7 to D0 pins sequentially from D7.

Status Read Timing

SCK Rising Edge Operation

CS(I)

RD(I)

SCK(I)

Hi-Z

DO(O)

D7 D6 D5 D4 D3 D2 D1 D0

SCK Falling Edge Operation

CS(I)

RD(I)

SCK(I)

Hi-Z

DO(O)

D7 D6 D5 D4 D3 D2 D1 D0

24/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

Commands List

Each command is 1-byte (8 bits) input. PLAY, MUON, and FLASH I/F only are 2 bytes input.

Command

PUP1

D7 D6 D5 D4 D3 D2 D1 D0

Description

Instantly shifts the power down device to the

command standby state.

0

1

0

1

0

Suppresses pop noise and shifts the power

down device to the command standby state.

Instantly shifts the device from the command

standby state to the power down state.

Suppresses pop noise and shifts the device

from the command standby state to power down

state.

PUP2

PDWN1

PDWN2

PLAY

0

1

0

Inputs the phrase after the playback channel is

specified, and then starts the playback.

0

1

0

C1 C0

F1 F0

F7

F6

F5

F4

F3

F2

Playback start command with phrase

specification.

Inputs the phrase after the

playback channel is specified, and then starts

the playback.

START

0

1

0

1

0

C1 C0

Playback start command without phrase

specification. Inputs the phrase with the FADR

command and starts the playback on multiple

channels at the same time.

Phrase

specification

command.

With this command, specifies the playback

phrase for each channel.

FADR

M7 M6 M5 M4 M3 M2 M1 M0

Specifies the finish channel and ends the voice.

STOP

0

1

0

1

0

1

0

C1 C0

Inserts silence time after specifying the channel

to insert silence, and then inserts silence.

MUON

M7 M6 M5 M4 M3 M2 M1 M0

Repeats the playback mode setting command.

Effective only for the channel being used for

playback.

Repeat playback mode releasing command.

Inputting the STOP command releases repeat

playback mode automatically.

SLOOP

CLOOP

1

0

1

0

C1 C0

C1 C2

Specifies the channel whose sound volume is to

be set, and then sets the volume of that channel.

1

0

1

0

VOL

EXT

V7

V6

V5

V4

V3

V2

V1

0

V0

0

Inputs voice data from the CPU I/F to play it

back.

Performs data read/write/erase of the built-in

flash memory. This command cannot be used

while the playback is going on. (Applicable to the

ML22Q54/Q58.)

1

0

1

0

Flash I/F

BE SE WR RD

C1, C0:

Channel specification (C0 = “1”: Channel 1; CH = “1”: Channel 2; C0, C1 = “1”: Channel 1,

Channel 2)

F7 to F0:

M7 to M0:

X0:

Phrase address

Silence time length

Releases the repeated playback

Sound volume

V4 to V0:

RD, WR, SE, BE: Mode (RD = “1”: Read data; WR = “1”: Write data; SE = “1”: Erase sector; BE = “1”:

Erase block)

25/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

Power Down Function

In power down state, the power down function in the device stops the internal operation and oscillation, sets

AOUT to GND, and minimizes the static Idd.

When an external clock is in use, input “L” level to the XT pin, so that current does not flow into the oscillation

circuit.

Figure below shows the equivalent circuit of ÈÌ and XT pins.

To master clock inside the device

1 M approx.

RESET

XT

Initial state at the reset input

At the reset input, status of each output pins is described in the table below.

Output pin

NCR1

NCR2

Status

“H” level

Output pin

XT

AOUT

DAO

Status

“L” level

Hi-z level

BUSY1

BUSY2

VBG

REGOUT

Channel Status

Channel status is of 2 types: NCRn and ÞËÍÇ².

Channel

CH1

Channel status

NCR1

NCR2

BUSY1

BUSY2

CH2

NCRn = “H” indicates that it is possible to input the PLAY, START and MUON commands for the phrase to be

played back next for channel n.

ÞËÍÇ² = “H” indicates a state in which channel n has not performed voice processing. ÞËÍÇ² = “L” indicates a

state in which channel n is performing voice processing.

Meanwhile, after a command is input, the NCR and ÞËÍÇ signals of all channels are at “L” level during the

processing of the command.

26/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

Voice Synthesis Algorithm

The ML2250 family contains 5 algorithm types to match the characteristic of playback voice: 2-bit ADPCM 2

algorithm, 4-bit ADPCM 2 algorithm, 8-bit PCM algorithm, 8-bit non-linear PCM algorithm, and 16-bit PCM

algorithm.

Key feature of each algorithm is described in the table below.

Voice synthesis algorithm

Applied waveform

Feature

Oki’s specific speech synthesis algorithm of low

bit rate with improved 2-bit ADPCM.

Oki’s specific speech synthesis algorithm of

improved waveform follow-up with improved

4-bit ADPCM.

Oki 2-bit ADPCM2

Normal voice waveform

Oki 4-bit ADPCM2

Normal voice waveform

High-frequency

inclusive sound effect etc.

components Algorithm which plays back mid-range of

Oki 8-bit Nonlinear PCM

8-bit PCM

waveform as 10-bit equivalent voice quality.

High-frequency

inclusive sound effect etc.

components

Normal 8-bit PCM algorithm

High-frequency

inclusive sound effect etc.

components

16-bit PCM

Normal 16-bit PCM algorithm

Memory Allocation and Creating Voice Data

The ROM is partitioned into 4 data areas: voice (i.e., phrase) control area, test area, voice area, and phrase control

table area.

The voice control area manages the ROM’s voice data. It controls the start/end addresses of voice data, usage/not

usage of the phrase control table function and so on. The voice control area stores voice control data for 256

phrases.

The test area stores the data for testing.

The voice area stores the actual waveform data.

The phrase control table area stores data for effective use of voice data. As for the details, please refer to the Phrase

Control Table Function.

There is no phrase control table area if the phrase control table is not used.

The ROM data is created using a development tool.

ROM Addresses (ML2252)

0x00000

Voice control area

(16 Kbit Fixed)

0x007FF

0x00800

Test area

0x00807

0x00808

Voice area

max: 0x1FFFF

Phrase Control Table area

Depends on creation of ROM

data.

max: 0x1FFFF

27/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

Built-in ROM Usage Prohibited Area

(Applies to ML2251/52/53/54/56-XXX, ML22Q54/Q58)

The 8 bytes between the voice control area and the voice area in the ROM is the prohibited area for use.

The voice data are stored automatically behind 00808(HEX) address by using the development tool (AR207) when

creating the ROM data.

Table below lists the addresses prohibited for use in every ROM model.

Model

ML2251

Voice data area

00808 to FFFF

00808 to 1FFFF

00808 to 5FFFF

00808 to 7FFFF

00808 to BFFFF

00808 to FFFFF

Usage prohibited area

00800 to 00807

ML2252

ML2253

ML2254, 22Q54

ML2256

ML22Q58

Note: The addresses are indicated in hexadecimal notation.

Playback Time and Memory Capacity

The playback time depends upon the memory capacity, sampling frequency, and playback method.

The equation showing the relationship is given below.

1.024 (Memory capacity – 16) (Kbit)

Sampling frequency (kHz) Bit length

Playback time [sec] =

(Bit length is ADPCM, ADPCM 2 = 4 bits; PCM = 8 bits.)

Example: Let the sampling frequency is 16 kHz and 4-bit ADPCM algorithm. If one 8 Mbits ROM is used, then the

playback time is obtained as follows:

1.024 (8192 – 16) (Kbit)

Playback time =

131 (sec)

16 (kHz) 4 (bit)

The above equation gives the playback time when the phrase control table function is not used.

28/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

Mixing Function

The ML2250 family can perform simultaneous mixing of 2 channels. It is possible to specify PLAY and STOP for

each channel separately.

Precautions for Waveform Clamp at the Time of Channels Mixing

When mixing of channels is done, the clamp occurrence possibility increases from the mixing calculation point

of view. If it is known beforehand that the clamp will occur, then adjust the sound volume by VOL command.

Mixing of Different Sampling Frequency

It is not possible to perform analog mixing by a different sampling frequency.

When performing analog mixing, the sampling frequency group of the first playback channel is selected.

Therefore, please note that if analog mixing is performed by a sampling frequency group other than the selected

sampling frequency group, then the playback will not be of constant speed: some times faster and at other times

slower.

The available sampling groups for analog mixing by a different sampling frequency are listed below.

4.0 kHz, 8.0 kHz, 16.0 kHz, 32.0 kHz

··· (Group 1)

5.3 kHz, 10.6 kHz, 21.3 kHz, 42.7 kHz ··· (Group 2)

6.0kHz, 12.0kHz, 24.0kHz, 48.0kHz

6.4 kHz, 12.8 kHz, 25.6 kHz

··· (Group 3)

··· (Group 4)

Figures below show a case when a sampling frequency group played back a different sampling frequency group.

fs = 16.0 kHz

Channel 1

fs = 25.6 kHz (Invalid. Played back as fs = 32.0 kHz.)

Channel 2

Figure 1 In Case a Different Sampling Frequency Played Back

during Playback of the Other Channel Playback

Normal playback if not played back by

other channel.

fs = 16.0 kHz

Channel 1

Channel 2

fs = 25.6 kHz (Valid)

End of channel 1

Figure 2 In Case a Different Sampling Frequency Played Back

after the End of the Other Channel

29/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

Phrase Control Table Function

The phrase control table function makes it possible to play back multiple phrases in succession. The following

functions are set using the phrase control table function:

Continuous playback:

There is no limit to the number of times a continuous playback can be specified. It

depends on the memory capacity only.

Silence insertion function: 4 to 1024 ms

Using the phrase control table function enables to effectively use the memory capacity of voice ROM.

Below is an example of the ROM configuration in the case of using the phrase control table function.

Example 1: Phrases Using the Phrase Control Table Function

Phrase 1

Phrase 2

Phrase 3

Phrase 4

Phrase 5

A

E

A

B

C

D

B

C

D

B

D

Silence

E

C

D

Example 2: Example of ROM Data in case Example 1 Converted to ROM

Address control area

A

B

C

D

E

F

Editing area

30/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

APPLICATION CIRCUIT EXAMPLE (ML2251/52/53/54/56-XXX, ML22Q54)

Parallel Interface

MCU

Serial Interface

MCU

RESET

CS

WR

RD

D7-0

SCK

DI

8

NCR1

NCR2

BUSY1

BUSY2

DO

NCR1

NCR2

BUSY1

BUSY2

AOUT

SERIAL

amplifier

SERIAL

OPTANA

30pF

XT

4.096MHz

XT

30pF

31/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

APPLICATION CIRCUIT EXAMPLE (ML22Q58)

Parallel Interface (at 5V)

Parallel Interface(at 3V)

MCU

RESET

CS

RESET

CS

WR

RD

D7-0

8

NCR1

NCR2

BUSY1

BUSY2

NCR1

NCR2

BUSY1

BUSY2

AOUT

150pF

30pF

amplifier

VBG

NC

SERIAL

OPTANA

SERIAL

OPTANA

REGOUT

10 F

DVDD

AVDD

DVDD

AVDD

30pF

XT

5V

XT

3V

DGND

AGND

DGND

AGND

4.096MHz

30pF

4.096MHz

30pF

XT

Serial Interface (at 5V)

Serial Interface (at 3V)

RESET

CS

WR

RD

SCK

DI

MCU

RESET

CS

WR

RD

SCK

DI

MCU

DO

NCR1

NCR2

BUSY1

BUSY2

NCR1

NCR2

BUSY1

BUSY2

AOUT

150pF

amplifier

VBG

amplifier

VBG

NC

SERIAL

OPTANA

SERIAL

OPTANA

REGOUT

DVDD

REGOUT

DVDD

10 F

AVDD

30pF

5V

30pF

3V

XT

DGND

AGND

XT

DGND

AGND

4.096MHz

30pF

XT

30pF

32/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

PACKAGE DIMENSIONS

44pin plastic QFP

(Unit: mm)

QFP44-P-910-0.80-2K

Ó·®®±® º·²·•¸

Package material

Lead frame material

Pin treatment

Package weight (g)

Rev. No./Last Revised

Epoxy resin

42 alloy

Solder plating ( 5µm)

0.41 TYP.

4/Nov. 28, 1996

ë

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in

storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,

package name, pin number, package code and desired mounting conditions (reflow method, temperature and

times).

33/36

FEDL2250DIGEST-09

OKI Semiconductor

33-pin W-CSP

ML2250 family

ÐóÊÚÔÙßííóëòðíÈëòéèóðòèðóÉ

Ð¿½µ¿¹» ³¿¬»®·¿´

Þ¿´´ ³¿¬»®·¿´

Û°±¨§ ®»•·²

Í²ñÐ¾

Î»ªò Ò±òñÔ¿•¬ Î»ª·•»¼

ðòðí ÌÇÐò

ïñÒ±ªò íðô îððì

ë

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in

storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,

package name, pin number, package code and desired mounting conditions (reflow method, temperature and

times).

34/36

FEDL2250DIGEST-09

OKI Semiconductor

ML2250 family

REVISION HISTORY

Page

Previous Current

Document

No.

Date

Description

Edition

PEDL2250DIGSET-01 Jun. 25, 2002

FEDL2250DIGSET-01 Oct. 15, 2002

FEDL2250DIGSET-02 May 12, 2003

–

Preliminary edition 1

–

Final edition 1

Final edition 2

Added ML2251 and ML2253

Eliminated mentioned items about PWM

Added ML2256

FEDL2250DIGSET-03 Oct. 17, 2003

FEDL2250DIGSET-04 Apr. 20, 2004

Added mentioned items about initial state at

reset input

–

22

–

Added ML22Q58

10-12,

33

Added ML2253/54-XXXHB(W-CSP Package)

Added the pin equivalent circuits

16-18

FEDL2250DIGSET-06 Dec. 27, 2004

Corrected the airticle and charts about serial

Interface

19,20

22,23

30,31

1

27

–

Changed the application circuit example

Modified the description of ML22Q54/Q58 in

the “GENERAL DESCRIPTION” Section.

Added “(ML2256-XXXHB)” to the 33-pin

W-CSP package.

–

3

Added

the

33-pin

W-CSP

package

–

11

configuration of ML2256-XXXHB

Added the “ML2256 WCSP pin “ Column” in the

table.

–

12,13

FEDL2250DIGSET-08 Jun.13, 2005

–

12

13

Added ML2256 to the heading above the table.

Modified the description of QFP Pin 24.

Changed the contents in the “Condition” and

“Rating” Columns of Parameter “Power

Dissipation” in the table in the “ABSOLUTE

MAXIMUM RATINGS” Section.

–

17

The “DIGEST” version is not changed.

FEDL2250DIGSET-09 Sep.15, 2005

–

35/36

FEDL2250DIGEST-09

OKI Semiconductor

NOTICE

ML2250 family

1. The information contained herein can change without notice owing to product and/or technical improvements.

Before using the product, please make sure that the information being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an explanation

for the standard action and performance of the product. When planning to use the product, please ensure that the

external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the

specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating

temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation

resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or

unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified

maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted

by us in connection with the use of the product and/or the information and drawings contained herein. No

responsibility is assumed by us for any infringement of a third party’s right which may result from the use

thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial

applications (e.g., office automation, communication equipment, measurement equipment, consumer

electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any

system or application that requires special or enhanced quality and reliability characteristics nor in any system

or application where the failure of such system or application may result in the loss or damage of property, or

death or injury to humans.

Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace

equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular

countries. The purchaser assumes the responsibility of determining the legality of export of these products and

will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

36/36


型号：	ML2250
厂家：	OKI ELECTRONIC COMPONETS
描述：	2-Channel Mixing Oki ADPCM Algorithm-Based Speech Synthesis LSI 双通道混合的算法冲ADPCM语音合成LSI 语音合成 PC
文件：	总36页 (文件大小：267K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML2250 [OKI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E