MSC23Q836D-60DS18 [OKI]
8,388,608-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE; 8,388,608字×36位的动态RAM模块：快速页面模式类型
| 型号： | MSC23Q836D-60DS18 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 8,388,608-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE |
| 文件： | 总9页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
This version: Mar. 6. 2000
Semiconductor
MSC23Q836D-xxBS18/DS18
8,388,608-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE
DESCRIPTION
The MSC23Q836D-xxBS18/DS18 is an 8,388,608-word x 36-bit CMOS dynamic random access memory module
which is composed of sixteen 16Mb DRAMs (4Mx4) in SOJ packages and two 16Mb DRAMs (4/CAS 4Mx4) in SOJ
packages mounted with eighteen decoupling capacitors. This is a 72-pin single in-line memory module. This module
supports any application where high density and large capacity of storage memory are required.
FEATURES
• 8,388,608-word x 36-bit organization
• 72-pin Single In-Line Memory Module
MSC23Q836D-xxBS18 : Gold tab
MSC23Q836D-xxDS18 : Solder tab
• Single 5V power supply, ±10% tolerance
• Input
: TTL compatible
• Output : TTL compatible, 3-state
• Refresh : 2048cycles/32ms
• Fast page mode capability
• /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
• Multi-bit test mode capability
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation (Max.)
Operating Standby
Cycle Time
Family
(Min.)
tRAC
60ns
70ns
tAA
tCAC
15ns
20ns
MSC23Q836D-60BS18/DS18
MSC23Q836D-70BS18/DS18
30ns
35ns
110ns
130ns
4703mW
4455mW
99mW
1/9
Semiconductor
MSC23Q836D
MODULE OUTLINE
MSC23Q836D-xxBS18/DS18
(Unit : mm)
9.30Max.
107.95±0.2*1
3.38Typ.
101.19Typ.
φ3.18
1
72
R1.57
2.03Typ.
6.35Typ.
6.35
1.04Typ.
1.27±0.1
+0.1
1.27
−0.08
95.25
Note:
1. Tolerance over 12.5mm from board edge is 0.5.
±
2/9
Semiconductor
MSC23Q836D
PIN CONFIGURATION
Pin No.
1
Pin Name
Pin No.
19
Pin Name
A10
Pin No.
37
Pin Name
DQ17
Pin No.
55
Pin Name
DQ12
V
SS
2
DQ0
DQ18
DQ1
20
DQ4
38
DQ35
56
DQ30
3
21
DQ22
DQ5
39
V
SS
57
DQ13
4
22
40
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
/RAS1
NC
58
DQ31
5
DQ19
DQ2
23
DQ23
DQ6
41
59
V
CC
6
24
42
60
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
7
DQ20
DQ3
25
DQ24
DQ7
43
61
8
26
44
62
9
DQ21
27
DQ25
A7
45
63
10
11
12
13
14
15
16
17
18
V
CC
28
46
64
NC
A0
A1
A2
A3
A4
A5
A6
29
NC
47
/WE
65
30
V
CC
48
NC
66
31
A8
49
DQ9
67
PD1
32
A9
50
DQ27
DQ10
DQ28
DQ11
DQ29
68
PD2
33
/RAS3
/RAS2
DQ26
DQ8
51
69
PD3
34
52
70
PD4
35
53
71
NC
36
54
72
V
SS
Presence Detect Pins
Pin No.
67
Pin Name
-60
-70
PD1
PD2
PD3
PD4
NC
NC
68
V
SS
V
SS
69
NC
NC
V
SS
70
NC
3/9
Semiconductor
MSC23Q836D
BLOCK DIAGRAM
/RAS0
/CAS0
/RAS1
/RAS
/CAS
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ
DQ
DQ
DQ
/RAS
/CAS
D0
D1
D9
/RAS
/CAS
DQ
DQ
DQ
DQ
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
/RAS
/CAS
D10
/CAS1
/RAS
/CAS
DQ
DQ9
DQ
/RAS
/CAS
DQ DQ10 DQ
DQ DQ11 DQ
DQ DQ12 DQ
D2
D3
D11
D12
/RAS
/CAS
DQ DQ13 DQ
DQ DQ14 DQ
DQ DQ15 DQ
DQ DQ16 DQ
/RAS
/CAS
/RAS
/RAS
/CAS0
/CAS1
/CAS2
/CAS3
/CAS0
/CAS1
/CAS2
/CAS3
DQ0
DQ8
DQ0
DQ1 DQ17 DQ1
DQ2 DQ26 DQ2
DQ3 DQ35 DQ3
D8
D4
D17
D13
/RAS
/CAS
DQ DQ18 DQ
DQ DQ19 DQ
DQ DQ20 DQ
DQ DQ21 DQ
/RAS
/CAS
/RAS
/CAS
DQ DQ22 DQ
DQ DQ23 DQ
DQ DQ24 DQ
DQ DQ25 DQ
/RAS
/CAS
D5
D14
/CAS2
/RAS
/CAS
DQ DQ27 DQ
DQ DQ28 DQ
DQ DQ29 DQ
DQ DQ30 DQ
/RAS
/CAS
D6
D7
D15
D16
/RAS
/CAS
DQ DQ31 DQ
DQ DQ32 DQ
DQ DQ33 DQ
DQ DQ34 DQ
/RAS
/CAS
/CAS3
/RAS2
/RAS3
A0-A10
/WE
A0-A10 : D0-D17
/WE : D0-D17
V
CC
VCC : D0-D17
C0-C17
V
SS
VSS & /OE : D0-D17
4/9
Semiconductor
MSC23Q836D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
0.5 to 7.0
50
Unit
V
Voltage on Any Pin Relative to V
V
T
−
SS
Short Circuit Output Current
Power Dissipation
IOS
mA
W
PD *
TOPR
18
Operating Temperature
Storage Temperature
0 to 70
40 to 125
°C
°C
T
STG
−
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Symbol
Min.
4.5
0
Typ.
5.0
0
Max.
Unit
V
V
CC
5.5
0
Power Supply Voltage
V
SS
V
Input High Voltage
Input Low Voltage
V
2.4
V
CC
0.5
V
V
+
IH
V
IL
0.5
−
0.8
Capacitance
(V = 5V ±10%, Ta = 25°C, f = 1 MHz)
CC
Parameter
Input Capacitance (A0 - A10)
Symbol
Typ.
Max.
125
140
43
Unit
pF
pF
pF
pF
pF
CIN1
Input Capacitance (/WE)
C
IN2
Input Capacitance (/RAS0 - /RAS3)
Input Capacitance (/CAS0 - /CAS3)
I/O Capacitance (DQ0 - DQ35)
C
IN3
C
IN4
50
C
I/O
26
5/9
Semiconductor
MSC23Q836D
DC Characteristics
(V = 5V ±10%, Ta = 0°C to 70°C)
CC
-60
-70
Parameter
Symbol
Condition
Unit
Note
Min.
2.4
0
Max.
Min.
2.4
0
Max.
Output High Voltage
Output Low Voltage
V
OH
V
CC
V
CC
V
V
IOH = 5.0mA
−
V
OL
IOL = 4.2mA
0.4
0.4
0V V 6.5V;
≤
≤
IN
Input Leakage Current
Output Leakage Current
ILI
All other pins not
under test = 0V
180
180
180
180
A
A
−
−
µ
DQ disable
ILO
20
−
20
20
−
20
µ
0V V
V
≤
≤
OUT
CC
Average Power
Supply Current
(Operating)
/RAS, /CAS cycling,
RC = Min.
ICC1
855
810
mA 1, 2
t
/RAS, /CAS = V
36
18
36
18
IH
Power supply current
(Standby)
ICC2
mA
1
/RAS, /CAS
0.2V
V
CC
≥
−
Average Power
Supply Current
(/RAS only refresh)
/RAS cycling,
ICC3
ICC6
ICC7
/CAS = V ,
855
855
675
810
810
630
mA 1, 2
mA 1, 2
mA 1, 3
IH
tRC = Min.
Average Power
Supply Current
(/CAS before /RAS refresh)
/RAS cycling,
/CAS before /RAS
Average Power
Supply Current
(Fast Page Mode)
/RAS = V ,
IL
/CAS cycling,
tPC = Min.
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while /RAS = VIL.
3. The address can be changed once or less while /CAS = VIH.
6/9
Semiconductor
MSC23Q836D
AC Characteristics (1/2)
(V = 5V ±10%, Ta = 0°C to 70°C) Note: 1, 2, 3, 9, 10
CC
-60
-70
Parameter
Symbol
Unit
Note
Min.
110
40
Max.
Min.
130
45
Max.
Random Read or Write Cycle Time
Fast Page Mode Cycle Time
Access Time from /RAS
tRC
tPC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAC
tCAC
tAA
60
15
30
35
70
20
35
40
4, 5, 6
Access Time from /CAS
4, 5
4, 6
4
Access Time from Column Address
Access Time from /CAS Precharge
Output Low Impedance Time from /CAS
/CAS to Data Output Buffer Turn-off Delay Time
Transition Time
tCPA
tCLZ
tOFF
tT
0
0
3
0
0
3
4
15
50
32
20
50
32
7
3
Refresh Period
tREF
tRP
/RAS Precharge Time
40
60
60
15
10
15
60
5
50
70
70
20
10
20
70
5
/RAS Pulse Width
tRAS
tRASP
tRSH
tCP
10K
10K
/RAS Pulse Width (Fast Page Mode)
/RAS Hold Time
100K
100K
/CAS Precharge Time (Fast Page Mode)
/CAS Pulse Width
tCAS
tCSH
tCRP
tRHCP
tRCD
tRAD
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
10K
10K
/CAS Hold Time
/CAS to /RAS Precharge Time
/RAS Hold Time from /CAS Precharge
/RAS to /CAS Delay Time
35
20
15
0
40
20
15
0
45
30
50
35
5
6
/RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
10
0
10
0
Column Address Set-up Time
Column Address Hold Time
Column Address to /RAS Lead Time
Read Command Set-up Time
Read Command Hold Time
Read Command Hold Time referenced to /RAS
10
30
0
15
35
0
0
0
8
8
0
0
7/9
Semiconductor
MSC23Q836D
AC Characteristics (2/2)
(V = 5V ±10%, Ta = 0°C to 70°C) Note: 1, 2, 3, 9, 10
CC
-60
-70
Parameter
Symbol
Unit
Note
Min.
0
Max.
Min.
0
Max.
Write Command Set-up Time
tWCS
tWCH
tWP
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Command Hold Time
10
10
15
15
0
15
10
20
20
0
Write Command Pulse Width
Write Command to /RAS Lead Time
Write Command to /CAS Lead Time
Data-in Set-up Time
tRWL
tCWL
tDS
Data-in Hold Time
tDH
10
5
15
5
/CAS Active Delay Time from /RAS Precharge
/RAS to /CAS Set-up Time (/CAS before /RAS)
/RAS to /CAS Hold Time (/CAS before /RAS)
/WE to /RAS Precharge Time (/CAS before /RAS)
/WE Hold Time from /RAS (/CAS before /RAS)
/RAS to /WE Set-up Time (Test Mode)
/RAS to /WE Hold Time (Test Mode)
tRPC
tCSR
tCHR
tWRP
tWRH
tWTS
tWTH
10
10
10
10
10
10
10
10
10
10
10
10
8/9
Semiconductor
MSC23Q836D
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles
(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.
2. The AC characteristics assumes tT = 5ns.
3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are
measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100pF.
5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met.
tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then
the access time is controlled by tCAC
.
6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met.
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then
the access time is controlled by tAA.
7. tOFF(Max.) define the time at which the output achieves the open circuit condition and is not referenced
to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is a 4-bit parallel test function. CA0 and CA1 are not used. In a read cycle, if all internal bits are equal,
the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating state by a /RAS only
refresh or /CAS before /RAS refresh cycle.
10. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.
9/9
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