MSM5117805D-70TS-K [OKI]
EDO DRAM, 2MX8, 70ns, CMOS, PDSO28;
| 型号： | MSM5117805D-70TS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | EDO DRAM, 2MX8, 70ns, CMOS, PDSO28 动态存储器 光电二极管 |
| 文件： | 总15页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Semiconductor
MSM5117805D
This version:Apr.1999
2,097,152-Word 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
´
DESCRIPTION
The MSM5117805D is a 2,097,152-word ´ 8-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS
technology. The MSM5117805D achieves high integration, high-speed operation, and low-power consumption
because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The
MSM5117805D is available in a 28-pin plastic SOJ, 28-pin plastic TSOP.
FEATURES
·
·
·
·
·
·
·
·
·
2,097,152-word ´ 8-bit configuration
Single 5V power supply, ±10% tolerance
Input
: TTL compatible, low input capacitance
Output
: TTL compatible, 3-state
Refresh : 2048 cycles/32 ms
Fast page mode, read modify write capability
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
Multi-bit test mode capability
Package options:
28-pin 400mil plastic SOJ
28-pin 400mil plastic TSOP
(SOJ28-P-400-1.27)
(Product : MSM5117805D-xxJS)
(Product : MSM5117805D-xxTS-K)
(Product : MSM5117805D-xxTS-L)
xx : indicates speed rank.
(TSOPII28-P-400-1.27-K)
(TSOPII28-P-400-1.27-L)
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation
Operating (Max.) Standby (Max.)
550mW
Cycle Time
(Min.)
Family
t
t
t
t
OEA
RAC
AA
CAC
MSM5117805D-50
MSM5117805D-60
MSM5117805D-70
50ns
60ns
70ns
25ns
30ns
35ns
13ns
15ns
20ns
13ns
15ns
20ns
84ns
104ns
124ns
495mW
440mW
5.5mW
1/14
MSM5117805D
PIN CONFIGRATION (TOP VIEW)
VCC
1
28 VSS
27 DQ8
26 DQ7
25 DQ6
24 DQ5
23 CAS
22 OE
21 A9
VCC
1
28 VSS
27 DQ8
26 DQ7
25 DQ6
24 DQ5
23 CAS
22 OE
21 A9
VSS 28
DQ8 27
DQ7 26
DQ6 25
DQ5 24
CAS 23
OE 22
A9 21
1 VCC
2 DQ1
3 DQ2
4 DQ3
5 DQ4
6 WE
7 RAS
8 NC
DQ1 2
DQ2 3
DQ3 4
DQ4 5
WE 6
RAS 7
NC 8
DQ1 2
DQ2 3
DQ3 4
DQ4 5
WE 6
RAS 7
NC 8
A10R 9
A0 10
20 A8
A10R 9
A0 10
20 A8
A8 20
9 A10R
10 A0
19 A7
19 A7
A7 19
A1 11
18 A6
A1 11
18 A6
A6 18
11 A1
A2 12
17 A5
A2 12
17 A5
A5 17
12 A2
A3 13
16 A4
A3 13
16 A4
A4 16
13 A3
VCC 14
15 VSS
VCC 14
15 VSS
VSS 15
14 VCC
28-Pin Plastic TSOP
(K Type)
28-Pin Plastic TSOP
(L Type)
28-Pin Plastic SOJ
Pin Name
Function
A0 – A9, A10R
Address Input
Row Address Strobe
Column Address Strobe
Data Input/Data Output
Output Enable
RAS
CAS
DQ1 – DQ8
OE
WE
Write Enable
VCC
Power Supply (5V)
Ground (0V)
VSS
NC
No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same
GND voltage level must be provided to every VSS pin.
2/14
MSM5117805D
BLOCK DIAGRAM
Timing
Generator
WE
OE
RAS
I/O
Controller
CAS
Output
Buffers
8
8
8
8
DQ1 – DQ8
Column
Address
Buffers
10
Column Decoders
Sense Amplifiers
Input
Buffers
I/O
Selector
Internal
Address
Counter
8
8
Refresh
Control Clock
A0 – A9
10
1
Row
Address
Buffers
Row
Deco-
ders
11
Word
Drivers
Memory
Cells
A10R
VCC
On Chip
VBB Generator
On Chip
IVCC Generator
VSS
3/14
MSM5117805D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Voltage VCC supply Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
0.5 to V
Unit
V
-
+
0.5
CC
0.5 to 7.0
50
V
IOS
mA
W
PD*
1
Topr
Operating Temperature
0 to 70
-55 to 150
°C
°C
Tstg
Storage Temperature
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Symbol
VCC
VSS
Min.
Typ.
Max.
Unit
V
4.5
0
5.0
0
5.5
0
Power Supply Voltage
V
Input High Voltage
Input Low Voltage
2.4
-0.5*2
V
¾
¾
VIH
VCC 0.5*1
+
0.8
V
VIL
Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VCC is applied).
*2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to
the point at which VSS is applied).
Capacitance
(VCC = 5V ± 10%, Ta = 25°C, f=1MHz)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 – A9, A10R)
5
pF
¾
CIN1
Input Capacitance
7
7
pF
pF
CIN2
CI/O
¾
¾
(RAS, CAS, WE, OE)
Output Capacitance (DQ1 – DQ8)
4/14
MSM5117805D
DC Characteristics
(VCC = 5V ± 10%, Ta = 0°C to 70°C)
MSM5117805 MSM5117805 MSM5117805
D-50 D-60 D-70
Symbol
Parameter
Condition
Unit Note
Max Max Max
Min.
2.4
0
Min.
2.4
0
Min.
2.4
0
V
I
= -5.0mA
Output High Voltage
Output Low Voltage
VCC
0.4
VCC
0.4
VCC
0.4
V
V
OH
OH
V
I
OL
= 4.2mA
OL
0V £ V £ 6.5V ;
I
Input Leakage
Current
I
LI
10
10
10
10
90
10
10
80
-10
-10
¾
-10
-10
¾
-10
-10
¾
mA
mA
All other pins not
under test = 0V
DQ disable
Output Leakage
Current
I
LO
0V £ V £ V
O
CC
Average Power
Supply Current
RAS, CAS cycling,
= Min.
I
I
I
100
mA
mA
mA
1,2
1
CC1
CC2
CC3
t
RC
(Operating)
RAS, CAS = V
2
1
2
1
2
1
¾
¾
¾
¾
¾
¾
IH
Power Supply
Current
RAS, CAS ³
– 0.2V
(Standby)
V
CC
RAS cycling,
Average Power
Supply Current
CAS = V ,
100
5
90
5
80
5
1,2
IH
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
(RAS-only Refresh)
t
= Min.
RC
RAS = V ,
IH
Power Supply
Current
I
I
I
CAS = V ,
mA
mA
mA
1
CC5
CC6
CC7
IL
(Standby)
DQ = enable
Average Power
Supply Current
RAS = cycling,
100
100
90
90
80
80
1,2
1,3
(CAS before RAS
Refresh)
CAS before RAS
RAS = V ,
IL
Average Power
Supply Current
CAS cycling,
(Fast Page Mode)
t
= Min.
PC
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
5/14
MSM5117805D
AC Characteristic (1/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
MSM5117805
D-50
MSM5117805
D-60
MSM5117805
D-70
Parameter
Symbol
Unit Note
Min.
84
Max.
¾
Min.
104
135
25
Max.
¾
Min.
124
160
30
Max.
¾
t
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
ns
ns
ns
RC
t
110
20
¾
¾
¾
RWC
t
¾
¾
¾
HPC
Fast Page Mode Read Modify Write
Cycle Time
t
58
68
78
ns
¾
¾
¾
HPRWC
t
Access Time from RAS
50
13
25
30
13
60
15
30
35
15
70
20
35
40
20
ns 4,5,6
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
RAC
t
Access Time from CAS
ns
ns
ns
ns
4,5
4,6
4
CAC
t
AA
Access Time from Column Address
Access Time from CAS Precharge
Access Time from OE
t
CPA
t
4
OEA
Output Low Impedance Time from
CAS
t
0
5
0
0
5
0
0
5
0
ns
ns
ns
4
¾
¾
13
¾
¾
15
¾
¾
20
CLZ
t
Data Output Hold After CAS Low
DOH
CAS to Data Output Buffer Turn-off
Delay Time
t
7,8
7,8
7
CEZ
RAS to Data Output Buffer Turn-off
Delay Time
t
0
0
0
13
13
13
0
0
0
15
15
15
0
0
0
20
20
20
ns
ns
ns
REZ
OE to Data Output Buffer Turn-off
Delay Time
t
OEZ
WE to Data Output Buffer Turn-off
Delay Time
t
7
3
WEZ
t
T
Transition Time
1
¾
30
50
50
7
50
32
1
50
32
1
50
32
¾
ns
ms
ns
t
Refresh Period
¾
40
60
60
10
10
¾
50
70
70
13
13
REF
t
RAS Precharge Time
RAS Pulse Width
¾
¾
RP
t
10,000
100,000
¾
10,000
100,000
¾
10,000 ns
100,000 ns
RAS
t
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
RASP
t
ns
ns
¾
¾
RSH
t
RAS Hold Time referenced to OE
7
¾
¾
ROH
CAS Precharge Time
(Fast Page Mode)
t
7
10
10
ns
¾
¾
¾
CP
t
CAS Pulse Width
7
35
5
10,000
¾
10
40
5
10,000
¾
13
45
5
10,000 ns
CAS
t
CAS Hold Time
ns
ns
ns
ns
ns
ns
¾
¾
¾
¾
50
35
CSH
t
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
OE Hold Time from CAS (DQ Disable)
RAS to CAS Delay Time
¾
¾
CRP
t
30
5
35
5
40
5
¾
¾
RHCP
t
¾
¾
CHO
t
11
9
37
14
12
45
14
12
5
6
RCD
t
25
30
RAS to Column Address Delay Time
RAD
6/14
MSM5117805D
AC Characteristic (2/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
MSM5117805
D-50
MSM5117805
D-60
MSM5117805
D-70
Note
Symbol
Parameter
Unit
Min.
0
Max.
¾
Min.
0
Max.
¾
Min.
0
Max.
¾
t
Row Address Set-up Time
Row Address Hold Time
ns
ns
ns
ns
ns
ns
ns
ASR
t
7
10
0
10
0
¾
¾
¾
RAH
t
Column Address Set-up Time
Column Address Hold Time
0
¾
¾
¾
ASC
t
7
10
30
0
13
35
0
¾
¾
¾
CAH
t
Column Address to RAS Lead Time
Read Command Set-up Time
Read Command Hold Time
25
0
¾
¾
¾
RAL
t
¾
¾
¾
RCS
t
0
0
0
9
9
¾
¾
¾
RCH
Read Command Hold Time
referenced to RAS
t
0
0
0
ns
¾
¾
¾
RRH
t
Write Command Set-up Time
Write Command Hold Time
Write Command Pulse Width
WE Pulse Width (DQ Disable)
OE Command Hold Time
OE Precharge Time
0
7
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
WCS
t
10
10
10
10
10
10
10
10
0
13
10
10
13
10
10
13
13
0
WCH
t
7
WP
t
7
WPE
t
7
OEH
t
7
OEP
t
OE Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
7
OCH
t
7
RWL
t
7
CWL
t
0
11
11
DS
t
Data-in Hold Time
7
10
15
34
49
79
54
13
20
44
59
94
64
DH
t
OE to Data-in Delay Time
CAS to WE Delay Time
13
30
42
67
47
OED
t
10
10
10
10
CWD
t
Column Address to WE Delay Time
RAS to WE Delay Time
AWD
t
RWD
t
CAS Precharge WE Delay Time
CPWD
CAS Active Delay Time from RAS
Precharge
t
5
5
5
ns
ns
ns
ns
ns
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
RPC
RAS to CAS Set-up Time
(CAS before RAS)
t
5
5
5
CSR
RAS to CAS Hold Time
(CAS before RAS)
t
10
10
10
10
10
10
10
10
10
CHR
WE to RAS Precharge Time
(CAS before RAS)
t
WRP
WE Hold Time from RAS
(CAS before RAS)
t
WRH
t
RAS to WE Set-up Time (Test Mode)
RAS to WE Hold Time (Test Mode)
10
10
10
10
10
10
ns
ns
¾
¾
¾
¾
¾
¾
WTS
t
WTH
7/14
MSM5117805D
Notes: 1. A start-up delay of 200ms is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 2ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition
times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
t
RCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.)
limit, then the access time is controlled by tCAC
.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
RAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.)
limit, then the access time is controlled by tAA.
t
7.
t
CEZ (Max), tREZ (Max), tWEZ (Max), tOEZ (Max) define the time at which the output achived the
open circuit condition and are not referenced to output voltage levels.
8.
9.
t
t
CEZ and tREZ must be satisfied for open circuit condition.
RCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If tWCS ³ tWCS (Min.), then the cycle is an early write
cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If
tCWD ³ tCWD (Min.), tRWD ³ tRWD(Min.), tAWD ³ tAWD (Min.) and tCPWD ³ tCPWD (Min.), then the cycle
is a read modify write cycle and data out will contain data read from the selected cell; if neither
of the above sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data
sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal,
the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a
low level. The test mode is cleared and the memory device returned to its normal operating state
by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified
value. These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
8/14
MSM5117805D
Timing Chart
·
Read Cycle
tRC
tRAS
VIH
RAS
tRP
tCRP
VIL
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
VIL
tRAL
tASR tRAH
tASC
tCAH
VIH
Address
VIL
Row
Column
tRCS
tRRH
tRCH
VIH
WE
tAA
VIL
tROH
tREZ
tAOE
tCAC
VIH
OE
VIL
tCEZ
tRAC
tOEZ
tCLZ
VOH
DQ
Valid Data-out
Open
VOL
“H” or “L”
·
Write Cycle (Early Write)
tRC
tRAS
VIH
RAS
tRP
tCRP
VIL
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
VIL
tRAL
tASR tRAH
tASC
tCAH
VIH
VIL
Row
Column
Address
tCWL
tWCH
tWCS
tWP
VIH
VIL
WE
OE
DQ
tRWL
VIH
VIL
tDS
tDH
VIH
VIL
Valid Data-in
Open
“H” or “L”
9/14
MSM5117805D
·
Read Modify Write Cycle
tRWC
tRAS
tCSH
VIH
RAS
tRP
VIL
tCRP
tRCD
tRSH
tCAS
tCRP
VIH
CAS
tRAD
tRAH
VIL
tCWL
tRWL
tASR
tASC
tCAH
VIH
Row
Column
Address
VIL
tRCS
tCWD
tWP
tRWD
VIH
VIL
WE
OE
tAWD
tAA
tOEH
tOEA
VIH
VIL
tOED
tOEZ
tDH
tDS
tCAC
tRAC
tCLZ
VI/OH
VI/OL
Valid
Data-out
Valid
Data-in
DQ
“H” or “L”
10/14
MSM5117805D
tRP
·
Fast Page Mode Read Cycle (Part-1)
tRASP
tRCD
tHPC
tRHCP
VIH
RAS
VIL
tCSH
tCP
tCP
tCRP
tCAS
tCAH
tCAS
tCAS
VIH
CAS
tRAD
VIL
tASC
tASR
tASC
tASC
tCAH
tRAH
tCAH
VIH
VIL
Row
Column
Column
Column
Address
WE
tRCS
tOCH
tRRH
VIH
VIL
tAA
tCHO
tOEP
tCAC
tOEP
tCAC
tRAC
tOEA
tAA
tAA
VIH
VIL
OE
tCPA
tDOH
tOEA
tOEA
tOEZ
tREZ
tOEZ
tCAC
VOH
VOL
Valid
Data-out
Valid*
Data-out
Valid*
Data-out
Valid
Data-out
DQ
tCLZ
* : Same Dada,
“H” or “L”
·
Fast Page Mode Read Cycle (Part-2)
tRASP
tRP
tRCD
tHPC
tRHCP
VIH
RAS
VIL
tCRP
tCSH
tCP
tCP
tCAS
tCAH
tCAS
tCAH
tCAS
VIH
VIL
CAS
Address
WE
tRAD
tRAH
tASR
tASC
tASC
tASC
tCAH
VIH
VIL
Row
Column
Column
Column
tRCS
tRCS
VIH
VIL
tAA
tRCH
tWPE
tOEA
tRAC
tCPA
tAA
tAA
VIH
VIL
OE
tCAC
tCEZ
tCAC
tWEZ
tCAC
tDOH
VOH
VOL
Valid *
Data-out
Valid *
Data-out
Valid *
Data-out
DQ
tCLZ
* : Same Data,
“H” or “L”
11/14
MSM5117805D
tRP
·
Fast Page Mode Write Cycle (Early Write)
tRASP
tCSH
tHPC
tHPC
VIH
RAS
VIL
tCRP
tRCD
tCP
tCP
tRSH
tCAS
tCAS
tCAH
tCAS
tCAH
VIH
VIL
CAS
Address
WE
tRAD
tRAH
tASR
tASC
tASC
tASC
tCAH
VIH
VIL
Row
Column
Column
Column
tWCS
tWCH
tWCS tWCH
tWCS tWCH
VIH
VIL
VIH
VIL
OE
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
Valid *
Data-in
Valid *
Data-in
Valid *
Data-in
DQ
“H” or “L”
·
Fast Page Mode Read Modify Write Cycle
tRASP
tRWD
tCPWD
VIH
RAS
VIL
tCRP
tRCD
tCP
tRWL
tCWD
VIH
VIL
CAS
tASC
tASC
tRAD
tRAH
tHPRWC
tCAH
tCAH
tCPA
tASR
tCWL
VIH
VIL
Row
Column
Column
Address
WE
tCWD
tAWD
tRCS
tRCS
VIH
VIL
tAWD
tAA
tWP
tWP
tDS
tDS
tRAC
tOEA
VIH
VIL
OE
DQ
tOED
tOEH
tOED
tOEH
tCAC
tOEZ
tDH
tCAC
tOEZ
tDH
VI/OH
VI/OL
Valid *
Data-out
Valid *
Data-in
Valid *
Data-out
Valid *
Data-in
tCLZ
tCLZ
“H” or “L”
12/14
MSM5117805D
·
RAS-Only Refresh Cycle
tRC
tRAS
VIH
RAS
tRP
VIL
tCRP
tRPC
VIH
VIL
CAS
tASR tRAH
VIH
VIL
Row
Address
DQ
tCEZ
VOH
VOL
Open
Note: WE, OE = “H” or “L”
“H” or “L”
·
CAS before RAS Refresh Cycle
tRP
tRC
tRAS
VIH
RAS
tRPC
VIL
tRP
tCP
tCSR
tRPC
tCHR
VIH
CAS
VIL
tCEZ
VOH
VOL
Open
Note: WE, OE, Address = “H” or “L”
DQ
13/14
MSM5117805D
·
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRAS
VIH
RAS
VIL
tCRP
tRP
tRCD
tRSH
tRP
tCHR
VIH
CAS
tRAD
tRAH
VIL
tASR
tASC
tCAH
VIH
VIL
Row
Column
Address
WE
tRCS
tCAC tRRH
tRAL
VIH
VIL
tWRH
tWRP
tAA
tROH
tOEA
VIH
VIL
OE
DQ
tRAC
tOEZ
tCLZ
VOH
VOL
Open
Valid Data-out
“H” or “L”
·
Hidden Refresh Write Cycle
tRC
tRC
tRAS
tRAS
VIH
RAS
VIL
tCRP
tRP
tRCD
tRSH
tRP
tCHR
VIH
CAS
tRAD
tRAH
VIL
tASR
tASC
tCAH
VIH
VIL
Row
Column
Address
tRAL
tRWL
tWP
VIH
VIL
WE
OE
DQ
tWCH
tWCS
VIH
VIL
tDS
tDH
VIH
VIL
Valid Data-in
“H” or “L”
14/14
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit and assembly designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. OKI assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
oraccident,improperhandling,orunusualphysicalorelectricalstressincluding,butnot
limitedto,exposuretoparametersbeyondthespecifiedmaximumratingsoroperation
outside the specified operating range.
5. Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurementequipment, consumerelectronics, etc.). Theseproductsarenotauthorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to:traffic control, automotive, safety, aerospace,
nuclear power control, and medical, including lift support and maintenance.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8. Nopartofthecontentscontainedhereinmaybereprintedorreproducedwithoutourprior
permission.
Copyright 1997 OKI ELECTRIC INDUSTRY CO.,LTD.
相关型号：
MSM5117805D-70TS-L
EDO DRAM, 2MX8, 70ns, CMOS, PDSO28, 0.400 INCH, 1.27 MM PITCH, PLASTIC, TSOP2-28
OKI
©2020 ICPDF网 联系我们和版权申明