MSM66Q577-999TB [OKI]
Microcontroller, 16-Bit, FLASH, 30MHz, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100;
| 型号： | MSM66Q577-999TB |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Microcontroller, 16-Bit, FLASH, 30MHz, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100 微控制器 |
| 文件： | 总485页 (文件大小：2787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEUL66577-01
MSM66577 FAMILY
User's Manual
CMOS 16-bit microcontroller
Issue Date: Jun. 2002
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
8.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
Printed in Japan
Preface
This user's manual describes the hardware of Oki-original CMOS 16-bit microcontrollers
MSM66577 family. In addition to this manual, Oki also provides the following manuals which
should be read with regard to the MSM66577 family.
nX-8/500S Core Instruction Manual
• nX-8/500S core instruction set
• Addressing modes
CC665S User's Manual
• Optimized compiler CC665S operation
• C-language specifications in CC665S
CL665S User's Manual
• Compiler loader CL665S operation
RTL665S Run Time Library Reference
• C run time library explanation
MAC66K Assembler Package User’s Manual
• Package overview
• RAS66K (relocatable assembler) operation
• RAS66K assembly language explanation
• RL66K (linker) operation
• LIB66K (librarian) operation
• OH66K (object converter) operation
Macroprocessor MP User’s Manual
• MP operation
• Macro language
Ultra-66K/E502 User’s Manual
• Ultra-66K (Emulator) explanation
• PathFinder-66K (Debugger) explanation
PW66K Flash Writer System User’s Manual
• PW66K Flash Writer System operation
This document is subject to change without notice.
Notation
Classification
Notation
Description
n Numeric value
xxH, xxhex
xxb
Represents a hexadecimal number
Represents a binary number
n Unit
Word, W
byte, B
1 word = 16 bits
1 byte = 2 nibbles = 8 bits
1 nibble = 4 bits
nibble, N
mega-, M
kilo-, K
kilo-, k
milli-, m
micro-, m
nano-, n
second, s
KB
6
10
2
10
= 1024
3
10 = 1000
-3
10
-6
10
-9
10
second
1KB = 1 kilobyte = 1024 bytes
1MB = 1 megabyte = 2 bytes
20
MB
= 1,048,576 bytes
n Terminology
“H” level
“L” level
The signal level of the high side of the
voltage;
indicates the voltage level of V and V
IH
OH
described in the electrical characteristics.
The signal level of the low side of the
voltage; indicates voltage level of V and
IL
V
OL
described in the electrical characteristics.
Opcode trap
Operation code trap. Occurs when an empty
area that has not been assigned an
instruction is fetched, or when an instruction
code combination that does not contain an
instruction is addressed.
n Register description
Register name Invalid bit
Fixed bit
Bit name
1
Bit number
0
7
—
1
6
5
4
3
"0"
0
2
Address: 009C [H]
R/W access: R/W
ADSNM02ADSNM01ADSNM00
SCNC0 SNEX0 ADRUN0
ADCON0L
At reset
0
0
0
0
0
0
Initial value when reset Read/Write attribute
Invalid bit
Fixed bit
:
:
Indicates that the bit does not exist. Writing into this bit is invalid.
When writing, always write the specified value. If read, the specified
value will be read. Values of fixed bits are specified as “0” or “1.”
Read/write attribute : R indicates that reading is possible and W indicates that writing is
possible.
Contents
Chapter 1
Overview
1.1 Overview ............................................................................................................ 1-1
1.2 Features ............................................................................................................. 1-1
1.3 Block Diagram .................................................................................................... 1-4
1.4 Pin Configuration................................................................................................ 1-5
1.5 Pin Descriptions ................................................................................................. 1-6
1.5.1 Description of Each Pin ................................................................................ 1-6
1.5.2 Pin Configuration.......................................................................................... 1-9
1.5.3 Connections for Unused Pins..................................................................... 1-11
1.6 Basic Operational Timing ................................................................................. 1-12
Chapter 2
CPU Architecture
2.1 Overview ............................................................................................................ 2-1
2.2 Memory Space ................................................................................................... 2-1
2.2.1 Memory Space Expansion .......................................................................... 2-1
2.2.2 Program Memory Space ............................................................................. 2-3
(1) Accessing program memory space ............................................................ 2-5
(2) Vector table area ........................................................................................ 2-5
(3) VCAL table area ......................................................................................... 2-8
(4) ACAL area .................................................................................................. 2-9
2.2.3 Data Memory Space ................................................................................. 2-10
(1) Special function register (SFR) area......................................................... 2-12
(2) Reserved area .......................................................................................... 2-12
(3) Internal RAM area..................................................................................... 2-12
(4) Fixed page (FIX) area ............................................................................... 2-12
(5) Local register setting area ........................................................................ 2-14
(6) External data memory area ...................................................................... 2-14
(7) Common area ........................................................................................... 2-15
2.2.4 Data Memory Access ................................................................................. 2-15
(1) Byte operations ......................................................................................... 2-15
(2) Word operations ....................................................................................... 2-16
2.3 Registers .......................................................................................................... 2-17
2.3.1 Arithmetic Register (ACC) ........................................................................ 2-17
2.3.2 Control Registers ...................................................................................... 2-18
(1) Program status word (PSW) ..................................................................... 2-18
(2) Program counter (PC)............................................................................... 2-22
Contents-1
(3) Local register base (LRB) ......................................................................... 2-22
(4) System stack pointer (SSP) ...................................................................... 2-23
2.3.3 Pointing Register (PR) .............................................................................. 2-24
2.3.4 Local Registers (R0 to R7, ER0 to ER3) .................................................. 2-25
2.3.5 Segment Registers ................................................................................... 2-26
(1) Code segment register (CSR) .................................................................. 2-26
(2) Table segment register (TSR) .................................................................. 2-26
(3) Data segment register (DSR) ................................................................... 2-27
2.4 Addressing Modes ........................................................................................... 2-27
2.4.1 RAM Addressing ....................................................................................... 2-27
(1) Register addressing .................................................................................. 2-28
(2) Page addressing....................................................................................... 2-30
(3) Direct data addressing.............................................................................. 2-33
(4) Pointing register indirect addressing......................................................... 2-34
(5) Special bit area addressing ...................................................................... 2-41
2.4.2 ROM Addressing ...................................................................................... 2-43
(1) Immediate addressing .............................................................................. 2-43
(2) Table data addressing .............................................................................. 2-43
(3) Program code addressing......................................................................... 2-45
(4) ROM window addressing .......................................................................... 2-46
Chapter 3
CPU Control Functions
3.1 Overview ............................................................................................................ 3-1
3.2 Standby Functions ............................................................................................. 3-1
3.2.1 Standby Function Registers........................................................................ 3-3
3.2.2 Description of Standby Function Registers................................................. 3-3
(1) Stop code acceptor (STPACP) ................................................................... 3-3
(2) Standby control register (SBYCON) ........................................................... 3-4
3.2.3 Examples of Standby Function Register Settings....................................... 3-6
• HALT mode setting ..................................................................................... 3-6
• HOLD mode setting .................................................................................... 3-6
• STOP mode setting .................................................................................... 3-6
3.2.4 Operation of Each Standby Mode............................................................... 3-6
(1) HALT mode................................................................................................. 3-6
(2) HOLD mode ................................................................................................ 3-7
(3) STOP mode ................................................................................................ 3-8
3.3 Reset Function ................................................................................................. 3-10
Contents-2
Chapter 4
Memory Control Functions
4.1 Overview .......................................................................................................... 4-1
4.2 Memory Control Function Registers ................................................................ 4-1
4.3 ROM Window Function .................................................................................... 4-2
4.4 READY Function .............................................................................................. 4-4
4.4.1 ROM Ready Control Register (ROMRDY).................................................. 4-4
4.4.2 RAM Ready Control Register (RAMRDY) .................................................. 4-5
4.5 WAIT Function .................................................................................................. 4-7
Chapter 5
Port Functions
5.1 Overview .......................................................................................................... 5-1
5.2 Hardware Configuration of Each Port .............................................................. 5-3
5.2.1 Type A (P0)................................................................................................. 5-3
5.2.2 Type B (P1, P2, P3_0, P3_1, P4) ............................................................... 5-4
5.2.3 Type C (P3_2, P3_3) .................................................................................. 5-5
5.2.4 Type D
(P5, P6, P7, P8, P9, P10, P11, P14_0 to P14_2, P15) .............................. 5-6
5.2.5 Type E (P14_6, P14_7) .............................................................................. 5-7
5.2.6 Type F (P12)............................................................................................... 5-7
5.3 Port Registers .................................................................................................. 5-8
5.3.1 Port Data Registers (Pn:n = 0 to 12, 14, 15) ............................................ 5-10
5.3.2 Port Mode Registers (PnIO:n = 0 to 11, 14, 15) ....................................... 5-10
5.3.3 Port Secondary Function Control Registers (PnSF:n = 0 to 11, 14, 15) ... 5-11
5.4 Port 0 (P0)...................................................................................................... 5-12
5.5 Port 1 (P1)...................................................................................................... 5-14
5.6 Port 2 (P2)...................................................................................................... 5-16
5.7 Port 3 (P3)...................................................................................................... 5-18
5.8 Port 4 (P4)...................................................................................................... 5-20
5.9 Port 5 (P5)...................................................................................................... 5-22
5.10 Port 6 (P6)...................................................................................................... 5-24
5.11 Port 7 (P7)...................................................................................................... 5-26
5.12 Port 8 (P8)...................................................................................................... 5-28
5.13 Port 9 (P9)...................................................................................................... 5-30
5.14 Port 10 (P10).................................................................................................. 5-32
5.15 Port 11 (P11).................................................................................................. 5-34
5.16 Port 12 (P12).................................................................................................. 5-36
5.17 Port 14 (P14).................................................................................................. 5-37
5.18 Port 15 (P15).................................................................................................. 5-39
Contents-3
Chapter 6
Clock Oscillation Circuit
6.1 Overview ............................................................................................................ 6-1
6.2 Clock Oscillation Circuit Configuration ............................................................... 6-1
6.3 Clock Oscillation Circuit Registers ..................................................................... 6-2
6.4 OSC Oscillation Circuit ...................................................................................... 6-2
6.5 XT Oscillation Circuit.......................................................................................... 6-5
Chapter 7
Time Base Counter (TBC)
7.1 Overview ............................................................................................................ 7-1
7.2 Time Base Counter (TBC) Configuration ........................................................... 7-1
7.3 Time Base Counter Registers ............................................................................ 7-2
7.4 1/n Counter ........................................................................................................ 7-2
7.4.1 Description of 1/n Counter Registers .......................................................... 7-2
(1) TBC clock dividing counter (TBCKDV upper 8 bits) ................................... 7-2
(2) TBC clock divider register (TBCKDVR) ...................................................... 7-3
7.4.2 Example of 1/n Counter-related Register Settings ..................................... 7-4
7.5 Time Base Counter (TBC) Operation................................................................. 7-4
Chapter 8
General-Purpose 8/16 Bit Timers
8.1 Overview ............................................................................................................ 8-1
8.2 General-purpose 8-bit/16-bit Timer Configurations............................................ 8-1
8.3 General-purpose 8-bit/16-bit Timer Registers.................................................... 8-2
8.4 Timer 0 ............................................................................................................... 8-3
8.4.1 Timer 0 Configuration ................................................................................. 8-3
8.4.2 Description of Timer 0 Registers ................................................................ 8-4
(1) General-purpose 16-bit timer 0 counter (TM0C)......................................... 8-4
(2) General-purpose 16-bit timer 0 register (TM0R)......................................... 8-4
(3) General-purpose 16-bit timer 0 control register (TM0CON) ....................... 8-4
8.4.3 Example of Timer 0-related Register Settings ............................................ 8-6
(1) Port 5 mode register (P5IO)........................................................................ 8-6
(2) Port 5 secondary function control register (P5SF) ...................................... 8-6
(3) General-purpose 16-bit timer 0 counter (TM0C)......................................... 8-6
(4) General-purpose 16-bit timer 0 register (TM0R)......................................... 8-6
(5) General-purpose 16-bit timer 0 control register (TM0CON) ....................... 8-6
8.4.4 Timer 0 Operation....................................................................................... 8-7
8.4.5 Timer 0 Interrupt ......................................................................................... 8-8
8.5 Timers 1 and 2 ................................................................................................... 8-9
8.5.1 Timers 1 and 2 Configurations.................................................................... 8-9
Contents-4
8.5.2 Description of Timer 1 and 2 Registers .................................................... 8-10
(1) General-purpose 8-bit timer 1 and 2 counters (TM1C, TM2C) ................. 8-10
(2) General-purpose 8-bit timer 1 and 2 registers (TM1R, TM2R) ................. 8-10
(3) General-purpose 8-bit timer 1 control register (TM1CON) ....................... 8-10
(4) General-purpose 8-bit timer 2 control register (TM2CON) ....................... 8-11
8.5.3 Example of Timer 1- and 2-related Register Settings ............................... 8-13
• 8-bit auto-reload timer mode (Timer 1) ..................................................... 8-13
(1) Port 6 mode register (P6IO)...................................................................... 8-13
(2) Port 6 secondary function control register (P6SF) .................................... 8-13
(3) General-purpose 8-bit timer 1 counter (TM1C)......................................... 8-13
(4) General-purpose 8-bit timer 1 register (TM1R)......................................... 8-13
(5) General-purpose 8-bit timer 1 control register (TM1CON) ....................... 8-13
• 8-bit auto-reload timer mode (Timer 2) ..................................................... 8-13
(1) Port 6 mode register (P6IO)...................................................................... 8-13
(2) Port 6 secondary function control register (P6SF) .................................... 8-13
(3) General-purpose 8-bit timer 2 counter (TM2C)......................................... 8-13
(4) General-purpose 8-bit timer 2 register (TM2R)......................................... 8-14
(5) General-purpose 8-bit timer 2 control register (TM2CON) ....................... 8-14
• 16-bit auto-reload timer mode................................................................... 8-14
(1) Port 6 mode register (P6IO)...................................................................... 8-14
(2) Port 6 secondary function control register (P6SF) .................................... 8-14
(3) General-purpose 16-bit timer 12 counter (TM12C)................................... 8-14
(4) General-purpose 16-bit timer 12 register (TM12R)................................... 8-14
(5) General-purpose 8-bit timer 1 control register (TM1CON) ....................... 8-14
(6) General-purpose 8-bit timer 2 control register (TM2CON) ....................... 8-14
• PWM mode ............................................................................................... 8-15
(1) Port 6 mode register (P6IO)...................................................................... 8-15
(2) Port 6 secondary function control register (P6SF) .................................... 8-15
(3) General-purpose 16-bit timer 12 counter (TM12C)................................... 8-15
(4) General-purpose 16-bit timer 12 register (TM12R)................................... 8-15
(5) General-purpose 8-bit timer 1 control register (TM1CON) ....................... 8-15
(6) General-purpose 8-bit timer 2 control register (TM2CON) ....................... 8-15
8.5.4 Timer 1 and 2 Operation ........................................................................... 8-16
• 8-bit auto-reload timer mode..................................................................... 8-16
• 16-bit auto-reload timer mode................................................................... 8-17
• PWM mode ............................................................................................... 8-18
8.5.5 Timer 1 and 2 Interrupts ........................................................................... 8-19
• Timer 1 interrupt ....................................................................................... 8-19
• Timer 2 interrupt ....................................................................................... 8-20
Contents-5
8.6 Timer 3 ............................................................................................................. 8-21
8.6.1 Timer 3 Configuration ............................................................................... 8-21
8.6.2 Description of Timer 3 Registers .............................................................. 8-22
(1) General-purpose 8-bit timer 3 counter (TM3C)......................................... 8-22
(2) General-purpose 8-bit timer 3 register (TM3R)......................................... 8-22
(3) General-purpose 8-bit timer 3 control register (TM3CON) ....................... 8-22
8.6.3 Example of Timer 3-related Register Settings .......................................... 8-24
(1) General-purpose 8-bit timer 3 counter (TM3C)......................................... 8-24
(2) General-purpose 8-bit timer 3 register (TM3R)......................................... 8-24
(3) General-purpose 8-bit timer 3 control register (TM3CON) ....................... 8-24
8.6.4 Timer 3 Operation..................................................................................... 8-25
8.6.5 Timer 3 Interrupt ....................................................................................... 8-26
8.7 Timer 4 ............................................................................................................. 8-27
8.7.1 Timer 4 Configuration ............................................................................... 8-27
8.7.2 Description of Timer 4 Registers .............................................................. 8-28
(1) General-purpose 8-bit timer 4 counter (TM4C)......................................... 8-28
(2) General-purpose 8-bit timer 4 register (TM4R)......................................... 8-28
(3) General-purpose 8-bit timer 4 control register (TM4CON) ....................... 8-28
8.7.3 Example of Timer 4-related Register Settings .......................................... 8-30
(1) Port 8 mode register (P8IO)...................................................................... 8-30
(2) Port 8 secondary function control register (P8SF) .................................... 8-30
(3) General-purpose 8-bit timer 4 counter (TM4C)......................................... 8-30
(4) General-purpose 8-bit timer 4 register (TM4R)......................................... 8-30
(5) General-purpose 8-bit timer 4 control register (TM4CON) ....................... 8-30
8.7.4 Timer 4 Operation..................................................................................... 8-31
8.7.5 Timer 4 Interrupt ....................................................................................... 8-32
8.8 Timer 5 ............................................................................................................. 8-33
8.8.1 Timer 5 Configuration ............................................................................... 8-33
8.8.2 Description of Timer 5 Registers .............................................................. 8-34
(1) General-purpose 8-bit timer 5 counter (TM5C)......................................... 8-34
(2) General-purpose 8-bit timer 5 register (TM5R)......................................... 8-34
(3) General-purpose 8-bit timer 5 control register (TM5CON) ....................... 8-34
8.8.3 Example of Timer 5-related Register Settings .......................................... 8-36
(1) General-purpose 8-bit timer 5 counter (TM5C)......................................... 8-36
(2) General-purpose 8-bit timer 5 register (TM5R)......................................... 8-36
(3) General-purpose 8-bit timer 5 control register (TM5CON) ....................... 8-36
8.8.4 Timer 5 Operation..................................................................................... 8-37
8.8.5 Timer 5 Interrupt ....................................................................................... 8-38
8.9 Timer 6 ............................................................................................................. 8-39
8.9.1 Timer 6 Configuration ............................................................................... 8-39
Contents-6
8.9.2 Description of Timer 6 Registers .............................................................. 8-40
(1) General-purpose 8-bit timer 6 counter (TM6C)......................................... 8-40
(2) General-purpose 8-bit timer 6 register (TM6R)......................................... 8-40
(3) General-purpose 8-bit timer 6 control register (TM6CON) ....................... 8-41
8.9.3 Example of Timer 6-related Register Settings .......................................... 8-43
• Auto-reload timer mode settings ............................................................... 8-43
(1) General-purpose 8-bit timer 6 counter (TM6C)......................................... 8-43
(2) General-purpose 8-bit timer 6 register (TM6R)......................................... 8-43
(3) General-purpose 8-bit timer 6 control register (TM6CON) ....................... 8-43
• Watchdog timer (WDT) mode settings...................................................... 8-43
(1) General-purpose 8-bit timer 6 register (TM6R)......................................... 8-43
(2) General-purpose 8-bit timer 6 control register (TM6CON) ....................... 8-43
(3) General-purpose 8-bit timer 6 counter (TM6C)......................................... 8-43
8.9.4 Timer 6 Operation..................................................................................... 8-44
• Auto-reload timer mode ............................................................................ 8-44
• Watchdog timer (WDT) mode ................................................................... 8-44
8.9.5 Timer 6 Interrupt (During Auto-Reload Timer Mode) ................................ 8-47
8.10 Timer 9 ........................................................................................................... 8-48
8.10.1 Timer 9 Configuration ............................................................................... 8-48
8.10.2 Description of Timer 9 Registers .............................................................. 8-49
(1) General-purpose 8-bit timer 9 counter (TM9C)......................................... 8-49
(2) General-purpose 8-bit timer 9 register (TM9R)......................................... 8-49
(3) General-purpose 8-bit timer 9 control register (TM9CON) ....................... 8-49
8.10.3 Example of Timer 9-related Register Settings .......................................... 8-51
(1) General-purpose 8-bit timer 9 counter (TM9C)......................................... 8-51
(2) General-purpose 8-bit timer 9 register (TM9R)......................................... 8-51
(3) General-purpose 8-bit timer 9 control register (TM9CON) ....................... 8-51
8.10.4 Timer 9 Operation..................................................................................... 8-52
8.10.5 Timer 9 Interrupt ....................................................................................... 8-53
Chapter 9
Capture/Compare Timer
9.1 Overview ............................................................................................................ 9-1
9.2 Capture/Compare Timer Configuration .............................................................. 9-1
9.3 Capture/Compare Timer Registers .................................................................... 9-2
9.4 16-Bit Free Running Counter (FRC) .................................................................. 9-3
9.4.1 16-Bit Free Running Counter Configuration ............................................... 9-3
9.4.2 Description of 16-bit Free Running Counter Register ................................. 9-3
(1) 16-bit free running counter (FRC) ............................................................... 9-3
(2) Free running counter control register (FRCON) ........................................ 9-4
Contents-7
9.5 Capture/Compare Out Modules ......................................................................... 9-5
9.5.1 Capture/Compare Out Module Configuration ............................................. 9-5
9.5.2 Description of Capture/Compare Out Module Registers ............................ 9-6
(1) Capture/compare registers (CPCMR0, CPCMR1) ..................................... 9-6
(2) Capture/compare control registers (CPCMCON0, CPCMCON1) ............... 9-6
(3) Capture control register (CAPCON) ........................................................... 9-7
(4) Capture/compare buffer registers (CPCMBFR0, CPCMBFR1) .................. 9-8
9.6 Example of Capture/Compare Timer-related Register Settings......................... 9-8
9.6.1 Capture Mode Settings ............................................................................... 9-8
(1) Port 5 mode register (P5IO)........................................................................ 9-8
(2) Port 5 secondary function control register (P5SF) ...................................... 9-8
(3) Capture control register (CAPCON) ........................................................... 9-8
(4) Free running counter (FRC)........................................................................ 9-8
(5) Free running counter control register (FRCON) ......................................... 9-8
9.6.2 Compare Out Mode Settings ...................................................................... 9-9
(1) Port 5 mode register (P5IO)........................................................................ 9-9
(2) Port 5 secondary function control register (P5SF) ...................................... 9-9
(3) Capture/compare control registers (CPCMCON0, CPCMCON1) ............... 9-9
(4) Free running counter (FRC)........................................................................ 9-9
(5) Capture/compare registers (CPCMR0, CPCMR1) ..................................... 9-9
(6) Capture/compare buffer registers (CPCMBFR0, CPCMBFR1) .................. 9-9
(7) Free running counter control register (FRCON) ......................................... 9-9
9.7 Capture/Compare Timer Operation ................................................................. 9-10
9.7.1 Capture Mode Operation .......................................................................... 9-10
9.7.2 Compare Out Mode Operation ................................................................. 9-11
9.8 Example Timings for Changing the Output Level of Compare Out .................. 9-12
9.9 Capture/Compare Timer Interrupt .................................................................... 9-14
Chapter 10
Real-Time Counter (RTC)
10.1 Overview ........................................................................................................ 10-1
10.2 Real-Time Counter Configuration .................................................................. 10-1
10.3 Real-Time Counter Control Register (RTCCON) ........................................... 10-2
10.4 Example of Real-Time Counter Register Settings ......................................... 10-3
10.5 Real-Time Counter Operation ........................................................................ 10-3
10.6 Real-Time Counter Interrupt .......................................................................... 10-4
Chapter 11
PWM Function
11.1 Overview ........................................................................................................ 11-1
11.2 PWM Configuration ........................................................................................ 11-1
Contents-8
11.3 PWM Register ................................................................................................ 11-2
11.3.1 Description of PWM Registers.................................................................. 11-3
(1) PWM counters (PWC0, PWC1) ................................................................ 11-3
(2) PWM cycle registers (PWCY0, PWCY1) .................................................. 11-3
(3) PWM registers (PWR0 to PWR3) ............................................................. 11-4
(4) PWM control register 0 (PWCON0) .......................................................... 11-4
(5) PWM control register 1 (PWCON1) .......................................................... 11-6
11.3.2 Example of PWM-related Register Settings ............................................. 11-7
• 8-bit PWM settings.................................................................................... 11-7
(1) Port 7 mode register (P7IO)...................................................................... 11-7
(2) Port 8 mode register (P8IO)...................................................................... 11-7
(3) Port 7 secondary function control register (P7SF) .................................... 11-7
(4) Port 8 secondary function control register (P8SF) .................................... 11-7
(5) PWM counters (PWC0, PWC1) ................................................................ 11-7
(6) PWM cycle registers (PWCY0, PWCY1) .................................................. 11-7
(7) PWM registers (PWR0 to PWR3) ............................................................. 11-7
(8) PWM control register 0 (PWCON0) .......................................................... 11-8
• 16-bit PWM settings.................................................................................. 11-8
(1) Port 7 mode register (P7IO)...................................................................... 11-8
(2) Port 8 mode register (P8IO)...................................................................... 11-8
(3) Port 7 secondary function control register (P7SF) .................................... 11-8
(4) Port 8 secondary function control register (P8SF) .................................... 11-8
(5) PWM counters (PWC0, PWC1) ................................................................ 11-8
(6) PWM cycle register (PWCY)..................................................................... 11-8
(7) PWM registers (PWR01, PWR23) ............................................................ 11-8
(8) PWM control register 0 (PWCON0) .......................................................... 11-9
(9) PWM control register 1 (PWCON1) .......................................................... 11-9
11.4 PWM Operation ............................................................................................. 11-9
11.4.1 PWM Operation During 8-bit Mode........................................................... 11-9
11.4.2 PWM Operation During 16-bit Mode....................................................... 11-10
11.4.3 PWM Operation During High-Speed Mode............................................. 11-12
11.5 PWM Interrupts ............................................................................................ 11-14
Chapter 12
Serial Port Functions
12.1 Overview ........................................................................................................ 12-1
12.2 Serial Port Configuration ................................................................................ 12-1
12.3 Serial Port Registers ...................................................................................... 12-2
12.4 SIO1 ...............................................................................................................12-3
12.4.1 SIO1 Configuration ................................................................................... 12-3
Contents-9
12.4.2 Description of SIO1 Registers .................................................................. 12-4
(1) SIO1 transmit control register (ST1CON) ................................................. 12-4
(2) SIO1 receive control register (SR1CON) .................................................. 12-6
(3) SIO1 status register (S1STAT) ................................................................. 12-8
(4) SIO1 transmit-receive buffer register (S1BUF) ....................................... 12-10
(5) SIO1 transmit shift register, receive shift register ................................... 12-10
12.4.3 Example of SIO1-related Register Settings ............................................ 12-11
12.4.3.1 UART Mode Settings .................................................................... 12-11
• Transmit settings .................................................................................... 12-11
(1) Port 8 mode register (P8IO).................................................................... 12-11
(2) Port 8 secondary function control register (P8SF) .................................. 12-11
(3) SIO1 transmit control register (ST1CON) ............................................... 12-11
(4) SIO1 receive control register (SR1CON) ................................................ 12-11
(5) SIO1 transmit-receive buffer register (S1BUF) ....................................... 12-11
• Receive settings ..................................................................................... 12-11
(1) Port 8 mode register (P8IO).................................................................... 12-11
(2) Port 8 secondary function control register (P8SF) .................................. 12-11
(3) SIO1 receive control register (SR1CON) ................................................ 12-12
12.4.3.2 Synchronous Mode Settings ......................................................... 12-12
• Transmit settings .................................................................................... 12-12
(1) Port 8 mode register (P8IO).................................................................... 12-12
(2) Port 8 secondary function control register (P8SF) .................................. 12-12
(3) SIO1 transmit control register (ST1CON) ............................................... 12-12
(4) SIO1 transmit-receive buffer register (S1BUF) ....................................... 12-12
• Receive settings ..................................................................................... 12-13
(1) Port 8 mode register (P8IO).................................................................... 12-13
(2) Port 8 secondary function control register (P8SF) .................................. 12-13
(3) SIO1 receive control register (SR1CON) ................................................ 12-13
12.4.3.3 Baud Rate Generator (Timer 4) Settings ...................................... 12-13
(1) General-purpose 8-bit timer 4 counter (TM4C)....................................... 12-13
(2) General-purpose 8-bit timer 4 control register (TM4CON) ..................... 12-13
12.4.4 SIO1 Interrupt ......................................................................................... 12-14
12.5 SIO6 ............................................................................................................. 12-15
12.5.1 SIO6 Configuration ................................................................................. 12-15
12.5.2 Description of SIO6 Registers ................................................................ 12-16
(1) SIO6 transmit control register (ST6CON) ............................................... 12-16
(2) SIO6 receive control register (SR6CON) ................................................ 12-18
(3) SIO6 status register (S6STAT) ............................................................... 12-20
(4) SIO6 transmit-receive buffer register (S6BUF) ....................................... 12-22
(5) SIO6 transmit shift register, receive shift register ................................... 12-22
Contents-10
12.5.3 Example of SIO6-related Register Settings ............................................ 12-23
12.5.3.1 UART Mode Settings ..................................................................... 12-23
• Transmit settings .................................................................................... 12-23
(1) Port 15 mode register (P15IO)................................................................ 12-23
(2) Port 15 secondary function control register (P15SF) .............................. 12-23
(3) SIO6 transmit control register (ST6CON) ............................................... 12-23
(4) SIO6 receive control register (SR6CON) ................................................ 12-23
(5) SIO6 transmit-receive buffer register (S6BUF) ....................................... 12-23
• Receive settings ..................................................................................... 12-23
(1) Port 15 mode register (P15IO)................................................................ 12-23
(2) Port 15 secondary function control register (P15SF) .............................. 12-23
(3) SIO6 receive control register (SR6CON) ................................................ 12-24
12.5.3.2 Synchronous Mode Settings ......................................................... 12-24
• Transmit settings .................................................................................... 12-24
(1) Port 15 mode register (P15IO)................................................................ 12-24
(2) Port 15 secondary function control register (P15SF) .............................. 12-24
(3) SIO6 transmit control register (ST6CON) ............................................... 12-24
(4) SIO6 transmit-receive buffer register (S6BUF) ....................................... 12-24
• Receive settings ..................................................................................... 12-25
(1) Port 15 mode register (P15IO)................................................................ 12-25
(2) Port 15 secondary function control register (P15SF) .............................. 12-25
(3) SIO6 receive control register (SR6CON) ................................................ 12-25
12.5.3.3 Baud Rate Generator (Timer 3) Settings ...................................... 12-25
(1) General-purpose 8-bit timer 3 counter (TM3C)....................................... 12-25
(2) General-purpose 8-bit timer 3 control register (TM3CON) ..................... 12-25
12.5.4 SIO6 Interrupt ......................................................................................... 12-26
12.6 SIO1, SIO6 Operation .................................................................................. 12-27
12.6.1 Transmit Operation ................................................................................. 12-27
• UART mode ............................................................................................ 12-27
• Synchronous mode ................................................................................. 12-28
12.6.2 Receive Operation .................................................................................. 12-35
• UART mode ............................................................................................ 12-35
• Synchronous mode ................................................................................. 12-36
12.7 SIO4 ............................................................................................................. 12-40
12.7.1 SIO4 Configuration ................................................................................. 12-40
12.7.2 Description of SIO4 Registers ................................................................ 12-41
(1) SIO4 control register (SIO4CON) ........................................................... 12-41
(2) FIFO control register (FIFOCON) ........................................................... 12-43
(3) Serial input FIFO data register (SIN4) .................................................... 12-45
(4) Serial output FIFO data register (SOUT4) .............................................. 12-45
Contents-11
12.7.3 Example of SIO4-related Register Settings ............................................ 12-46
• Master mode settings ............................................................................. 12-46
(1) Port 10 mode register (P10IO)................................................................ 12-46
(2) Port 10 secondary function control register (P10SF) .............................. 12-46
(3) Serial output FIFO data register (SOUT4) .............................................. 12-46
(4) SIO4 control register (SIO4CON) ........................................................... 12-46
• Slave mode settings ............................................................................... 12-47
(1) Port 10 mode register (P10IO)................................................................ 12-47
(2) Port 10 secondary function control register (P10SF) .............................. 12-47
(3) Sserial output FIFO data register (SOUT4) ............................................ 12-47
(4) SIO4 control register (SIO4CON) ........................................................... 12-47
12.7.4 SIO4 Interrupt ......................................................................................... 12-48
12.7.5 SIO4 Operation ....................................................................................... 12-49
12.8 SIO5 ............................................................................................................. 12-51
12.8.1 SIO5 Configuration ................................................................................. 12-51
12.8.2 Description of SIO5 Registers ................................................................ 12-52
(1) SIO5 control register (SIO5CON) ........................................................... 12-52
(2) Serial input FIFO data register (SIN5) .................................................... 12-54
(3) Serial output FIFO data register (SOUT5) .............................................. 12-54
(4) FIFO mode control register (FIFOMOD) ................................................. 12-54
12.8.3 Example of SIO5-related Register Settings ............................................ 12-57
• Master mode settings ............................................................................. 12-57
(1) Port 14 mode register (P14IO)................................................................ 12-57
(2) Port 14 secondary function control register (P14SF) .............................. 12-57
(3) Serial output FIFO data register (SOUT5) .............................................. 12-57
(4) SIO5 control register (SIO5CON) ........................................................... 12-57
• Slave mode settings ............................................................................... 12-58
(1) Port 14 mode register (P14IO)................................................................ 12-58
(2) Port 14 secondary function control register (P14SF) .............................. 12-58
(3) Serial output FIFO data register (SOUT5) .............................................. 12-58
(4) SIO5 control register (SIO5CON) ........................................................... 12-58
12.8.4 SIO5 Interrupt ......................................................................................... 12-59
12.8.5 SIO5 Operation ....................................................................................... 12-60
Chapter 13
A/D Converter Functions
13.1 Overview ........................................................................................................ 13-1
13.2 A/D Converter Configuration .......................................................................... 13-1
13.3 A/D Converter Registers ................................................................................ 13-2
13.3.1 Description of A/D Converter Registers .................................................... 13-3
(1) A/D control register 0L (ADCON0L).......................................................... 13-3
Contents-12
(2) A/D control register 0H (ADCON0H) ........................................................ 13-5
(3) A/D interrupt control register (ADINT0)..................................................... 13-7
(4) A/D result registers (ADR00 to ADR07).................................................... 13-8
13.3.2 Example of A/D Converter-related Register Settings ............................... 13-9
• Scan mode setting .................................................................................... 13-9
(1) A/D control register 0H (ADCON0H) ........................................................ 13-9
(2) A/D interrupt control register (ADINT0)..................................................... 13-9
(3) A/D control register 0L (ADCON0L).......................................................... 13-9
• Select mode setting .................................................................................. 13-9
(1) A/D interrupt control register (ADINT0)..................................................... 13-9
(2) A/D control register 0H (ADCON0H) ........................................................ 13-9
13.4 A/D Converter Operation ............................................................................. 13-10
13.5 Notes Regarding Usage of A/D Converter ................................................... 13-11
13.5.1 Considerations When Setting the Conversion Time ............................... 13-11
13.5.2 Noise-Suppression Measures................................................................. 13-13
13.6 A/D Converter Interrupt ................................................................................ 13-14
Chapter 14
D/A Converter Functions
14.1 Overview ........................................................................................................ 14-1
14.2 D/A Converter Configuration .......................................................................... 14-1
14.3 D/A Converter Registers ................................................................................ 14-2
14.3.1 Description of D/A Converter Registers .................................................... 14-2
(1) DA registers (DAR0, DAR1) ..................................................................... 14-2
(2) DA control register (DACON).................................................................... 14-2
14.3.2 Example of D/A Converter-related Register Settings ............................... 14-3
(1) Port 14 mode register (P14IO).................................................................. 14-3
(2) Port 14 secondary function control register (P14SF) ................................ 14-3
(3) DA registers (DAR0, DAR1) ..................................................................... 14-3
(4) DA control register (DACON).................................................................... 14-3
14.3.3 D/A Converter Operation .......................................................................... 14-4
Chapter 15
Peripheral Functions
15.1 Overview ........................................................................................................ 15-1
15.2 Description of Each Peripheral Function........................................................ 15-1
15.2.1 Clock Out Function ................................................................................... 15-1
15.2.2 External XTCLK Input Control Function.................................................... 15-1
15.2.3 HOLD Input Control Function ................................................................... 15-1
15.2.4 WAIT Input Control Function .................................................................... 15-1
15.3 Peripheral Control Register (PRPHCON) ...................................................... 15-2
Contents-13
Chapter 16
External Interrupt Functions
16.1 Overview ........................................................................................................ 16-1
16.2 External Interrupt Registers ........................................................................... 16-1
16.2.1 Description of External Interrupt Registers ............................................... 16-2
(1) External interrupt control register 0 (EXI0CON) ....................................... 16-2
(2) External interrupt control register 1 (EXI1CON) ....................................... 16-3
(3) External interrupt control register 2 (EXI2CON) ....................................... 16-4
16.2.2 Example of External Interrupt-related Register Settings........................... 16-5
(1) Port 6 mode register (P6IO)...................................................................... 16-5
(2) Port 9 mode register (P9IO)...................................................................... 16-5
(3) Port 6 secondary function control register (P6SF) .................................... 16-5
(4) Port 9 secondary function control register (P9SF) .................................... 16-5
(5) External interrupt control register 0 (EXI0CON) ....................................... 16-5
(6) External interrupt control register 1 (EXI1CON) ....................................... 16-5
(7) External interrupt control register 2 (EXI2CON) ....................................... 16-5
16.3 EXINT0 to EXINT7 Interrupts......................................................................... 16-6
Chapter 17
Interrupt Processing Functions
17.1 Overview ........................................................................................................ 17-1
17.2 Interrupt Function Registers........................................................................... 17-2
17.3 Description of Interrupt Processing ................................................................ 17-3
17.3.1 Non-Maskable Interrupt (NMI) .................................................................. 17-3
17.3.2 Maskable Interrupts .................................................................................. 17-5
(1) Interrupt request registers (IRQ0 to IRQ4) ............................................... 17-5
(2) Interrupt enable registers (IE0 to IE4)....................................................... 17-5
(3) Master interrupt enable flag (MIE) ............................................................ 17-5
(4) Master interrupt priority flag (MIPF) .......................................................... 17-5
(5) Interrupt priority control registers (IP0 to IP9) ........................................... 17-6
17.3.3 Priority Control of Maskable Interrupts ................................................... 17-10
(1) Basic interrupt control ............................................................................. 17-10
(2) Multiple interrupt control ......................................................................... 17-10
17.4 IRQ, IE and IP Register Configurations for Each Interrupt .......................... 17-12
17.4.1 Interrupt Request Registers (IRQ0 to IRQ4)........................................... 17-12
(1) Interrupt request register 0 (IRQ0).......................................................... 17-12
(2) Interrupt request register 1 (IRQ1).......................................................... 17-13
(3) Interrupt request register 2 (IRQ2).......................................................... 17-14
(4) Interrupt request register 3 (IRQ3).......................................................... 17-15
(5) Interrupt request register 4 (IRQ4).......................................................... 17-16
17.4.2 Interrupt Enable Registers (IE0 to IE4) ................................................... 17-17
(1) Interrupt enable register 0 (IE0) .............................................................. 17-17
Contents-14
(2) Interrupt enable register 1 (IE1) .............................................................. 17-18
(3) Interrupt enable register 2 (IE2) .............................................................. 17-19
(4) Interrupt enable register 3 (IE3) .............................................................. 17-20
(5) Interrupt enable register 4 (IE4) .............................................................. 17-21
17.4.3 Interrupt Priority Control Registers (IP0 to IP9) ...................................... 17-22
(1) Interrupt priority control register 0 (IP0) .................................................. 17-22
(2) Interrupt priority control register 1 (IP1) .................................................. 17-23
(3) Interrupt priority control register 2 (IP2) .................................................. 17-24
(4) Interrupt priority control register 3 (IP3) .................................................. 17-25
(5) Interrupt priority control register 4 (IP4) .................................................. 17-26
(6) Interrupt priority control register 5 (IP5) .................................................. 17-27
(7) Interrupt priority control register 6 (IP6) .................................................. 17-28
(8) Interrupt priority control register 7 (IP7) .................................................. 17-29
(9) Interrupt priority control register 8 (IP8) .................................................. 17-30
(10) Interrupt priority control register 9 (IP9) .................................................. 17-31
Chapter 18
Bus Port Functions
18.1 Overview ........................................................................................................ 18-1
18.2 Port Operation................................................................................................ 18-1
18.2.1 Port Operation When Accessing Program Memory .................................. 18-1
18.2.2 Port Operation When Accessing Data Memory ........................................ 18-4
18.3 External Memory Access ............................................................................... 18-6
18.3.1 External Program Memory Access ........................................................... 18-6
18.3.2 External Data Memory Access ................................................................. 18-8
18.4 External Memory Access Timing ................................................................. 18-10
18.4.1 External Program Memory Access Timing ............................................. 18-10
18.4.2 External Data Memory Access Timing.................................................... 18-12
18.5 Notes Regarding Usage of Bus Port Function ............................................. 18-16
18.5.1 Dummy Read Strobe Output .................................................................. 18-16
18.5.2 External Bus Access Timing ................................................................... 18-18
Chapter 19
Flash Memory
19.1 Overview ........................................................................................................ 19-1
19.2 Features .........................................................................................................19-1
19.3 Programming Modes...................................................................................... 19-2
19.4 Parallel Mode ................................................................................................. 19-4
19.4.1 Overview of the Parallel Mode .................................................................. 19-4
19.4.2 PROM Writer Setting ................................................................................ 19-4
19.4.3 Flash Memory Programming Conversion Adapter.................................... 19-4
Contents-15
19.5 Serial Mode .................................................................................................... 19-5
19.5.1 Overview of the Serial Mode..................................................................... 19-5
19.5.2 Serial Mode Settings................................................................................. 19-5
(1) Pins used in serial mode........................................................................... 19-5
(2) Serial mode connection circuit .................................................................. 19-6
(3) Serial mode programming method ........................................................... 19-8
(4) Setting of security function........................................................................ 19-8
(5) Notes on use of serial mode ..................................................................... 19-8
19.6 User Mode ..................................................................................................... 19-9
19.6.1 Overview of the User Mode ...................................................................... 19-9
19.6.2 User Mode Programming Registers ....................................................... 19-10
19.6.3 Description of User Mode Registers ....................................................... 19-11
(1) Flash memory address register (FLAADRS) .......................................... 19-11
(2) Flash memory acceptor (FLAACP)......................................................... 19-11
(3) Flash memory control register (FLACON) .............................................. 19-12
19.6.4 User Mode Programming Example......................................................... 19-15
(1) User mode programming flowchart example .......................................... 19-15
(2) User mode programming program example ........................................... 19-16
19.6.5 Notes on Use of User Mode ................................................................... 19-16
19.7 Notes on Program ........................................................................................ 19-17
(1) Programming of flash memory immediately after power-on ................... 19-17
(2) Note on STOP mode release.................................................................. 19-17
(3) Supply voltage sense reset function ....................................................... 19-17
Chapter 20
Electrical Characteristics
20.1 Absolute Maximum Ratings ........................................................................... 20-1
20.2 Recommended Operating Conditions ............................................................ 20-1
20.3 Allowable Output Current Values ................................................................... 20-2
20.4 Internal Flash ROM Programming Conditions ............................................... 20-2
20.5 DC Characteristics ......................................................................................... 20-3
20.5.1 DC Characteristics (V = 4.5 to 5.5 V) ................................................... 20-3
DD
20.5.2 DC Characteristics (V = 2.4 to 3.6 V) ................................................... 20-5
DD
20.6 AC Characteristics ......................................................................................... 20-7
20.6.1 AC Characteristics (V = 4.5 to 5.5 V) ................................................... 20-7
DD
20.6.2 AC Characteristics (V = 2.4 to 3.6 V) ................................................. 20-15
DD
20.7 A/D Converter Characteristics ..................................................................... 20-23
20.7.1 A/D Converter Characteristics (V = 4.5 to 5.5 V)................................ 20-23
DD
20.7.2 A/D Converter Characteristics (V = 2.4 to 3.6 V)................................ 20-23
DD
20.8 D/A Converter Characteristics ..................................................................... 20-25
Contents-16
Chapter 21
Special Function Registers (SFRs)
21.1 Overview ........................................................................................................ 21-1
21.2 List of SFRs ................................................................................................... 21-1
Chapter 22
Package Dimensions.................................................................. 22-1
Note on Programming ............................................................................................... A-1
Revision History ......................................................................................................... R-1
Contents-17
Contents-18
1
Chapter 1
Overview
MSM66577 Family User's Manual
Chapter 1 Overview
1. Overview
1
1.1 Overview
TheMSM66577familyofhighlyfunctionalCMOS16-bitsinglechipmicrocontrollersutilizes
the nX-8/500S, Oki’s proprietary CPU core.
Four channels of serial ports, consisting of two channels of synchronous serial ports with
32-byte FIFO registers and two channels of UART/synchronous serial ports, enable easy
interfacing with external peripheral LSI devices such as an encoder/decoder or
servocontroller.
A switching function permits selection of separate address and data lines or multiplexed
lines for the bus interface to correspond to various peripheral LSI devices.
With features such as a dual clock function, programmable pull-up ports in which individual
bitscanbeprogrammed,andasmall,thinpackage,theMSM66577familyofmicrocontrollers
is optimally suited for the system control of small-sized devices.
Reprogrammable Flash ROM versions (MSM66Q577LY/MSM66Q577) that operate on a
single power supply (V = 3.0 to 3.6 V/4.5 to 5.5 V) are available.
DD
1.2 Features
The MSM66577 family has the following features.
l
Instruction set with a wide variety of instructions
• Dual instruction set
• 8- and 16-bit arithmetic instructions
• Multiply and divide instructions
(High speed multiplier is not provided)
• Bit manipulate instructions
• Bit logical instructions
• ROM table reference instructions
l
Variety of addressing modes
• Register addressing
• Page addressing
• Pointing register indirect addressing
• Stack addressing
• Immediate addressing
l
l
Minimum instruction cycles
• 67 ns at 30 MHz (4.5 to 5.5 V)
• 143 ns at 14 MHz (2.4 to 3.6 V)
• 61 ms at 32.768 kHz (2.4 to 3.6 V/4.5 to 5.5 V)
Clock oscillation circuits
• Main clock : 30 MHz (max.) crystal oscillator or ceramic resonator oscillator circuit
• Subclock : 32.768 kHz crystal oscillator circuit
1-1
MSM66577 Family User's Manual
Chapter 1 Overview
l
l
l
l
Program memory (ROM)
• Internal 128KB
• External 1MB
(in the case of EA pin activated)
Data memory (RAM)
• Internal
4KB
• External 1020KB
I/O ports
• Input ports
• I/O ports
8 ports (secondary function is an analog input port)
74 ports max. (with programmable pull-up resistors)
Timers
• Free-running counter
16 bits ¥ 1
• General-purpose auto reload timer 16 bits ¥ 1, 8 bits ¥ 1
• 8-bit auto reload timer ¥ 2
Also functions as a 16-bit auto reload timer ¥ 1
• Baud rate generator and 8-bit auto reload timer ¥ 3
• Watchdog timer ¥ 1
Also functions as an 8-bit auto reload timer
l
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8-bit PWM ¥ 4
(can also be used as two 16-bit PWMs)
8-bit serial ports
• UART/Synchronous
• Synchronous, with 32-byte FIFO
¥ 2
¥ 2
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A/D converter
• 10-bit resolution, 8 channels
D/A converter
• 8-bit resolution, 2 channels
Interrupts
• Non-maskable: 1
• Maskable: 8 external, 30 internal (29 vectors)
• Three levels of priority
l
l
ROM window function
Standby modes
• HALT mode
• HOLD mode
• STOP mode
1-2
MSM66577 Family User's Manual
Chapter 1 Overview
l
Package
• 100-pin plastic TQFP (TQFP100-P-1414-0.50-K)
(For external dimensions, refer to Chapter 22)
1
Table 1-1 MSM66577 Family of Products
Parameter
MSM66577L
MSM66577
Operating temperature range
Power supply voltage/
maximum operating frequency
Minimum instruction
–30°C to +70°C
V
DD = 2.4 to 3.6 V/
f = 14 MHz
VDD = 4.5 to 5.5 V/
f = 30 MHz
143 ns at 14 MHz
(2.4 to 3.6 V)
67 ns at 30 MHz
(4.5 to 5.5 V)
execution time
61 ms at 32.768 kHz (2.4 to 3.6/4.5 to 5.5 V)
128KB
Internal ROM size
(max. external)
(1MB)
Internal RAM size
(max. external)
4KB
(1MB)
74 I/O pins
I/O ports
(with programmable pull-up resistors)
8 input-only pins
16-bit free running timer ¥ 1 ch
Compare out/capture input ¥ 2 ch
16-bit timer (auto reload/timer out) ¥ 1 ch
8-bit auto reload timer ¥ 2 ch
(can also be used as 16-bit timer ¥ 1 ch)
8-bit auto reload timer ¥ 1 ch
8-bit auto reload timer ¥ 3 ch
(also functions as serial communication baud rate generator)
Watchdog timer (also functions as 8-bit auto reload timer)
Watch timer (Real-time counter) ¥ 1 ch
8-bit PWM ¥ 4 ch
Timers
(can also be used as 16-bit PWM ¥ 2 ch)
UART/Synchronous ¥ 2 ch
Synchronous, with 32-byte FIFO ¥ 2 ch
10-bit A/D converter ¥ 8
Serial port
A/D converter
D/A converter
8-bit D/A converter ¥ 2
Non-maskable ¥ 1 ch
External interrupt
Interrupt priority
Maskable ¥ 8 ch
3 levels
External bus interface
(separate address/data bus type/multiplexed bus type)
Others
Bus release function
Dual clock function
Clock gear function
FLASH ROM version
MSM66Q577LY (3.0 to 3.6 V)
MSM66Q577
1-3
MSM66577 Family User's Manual
Chapter 1 Overview
1.3 Block Diagram
TM0OUT
16bit Timer0
TM0EVT
XT0
CPU Core
TM1OUT
TM1EVT
XT1
8bit Timer1
8bit Timer2
OSC0
OSC1
HOLD
HLDACK
RES
TM2OUT
TM2EVT
System
Control
CLKOUT
XTOUT
ALU
Peripheral
Control
Registers
RXD1
TXD1
RXC1
TXC1
SIO1
(UART/SYNC)
SSP
LRB
PSW
PC
ALU Control
ACC
DSR TSR CSR
TM4OUT
8bit Timer4/BRG
RXD6
TXD6
RXC6
TXC6
SIO6
(UART/SYNC)
Memory Control
Pointing Registers
Local Registers
8bit Timer3/BRG
Instruction
Decoder
SIOI4
SIOO4
SIO4
(32byte FIFO SYNC)
EA
SIOCK4
RAM
4K
ROM
128K
SELMBUS
PSEN
RD
8bit Timer5/BRG
SIOI5
SIOO5
SIO5
WR
(32byte FIFO SYNC)
WAIT
SIOCK5
D0-7
(AD0-7)
8bit Timer6/WDT
Note)
PWMOUT0
PWMOUT2
8bit PWM0
8bit PWM1
A0-19
PWMOUT1
PWMOUT3
P0
P1
TBC
RTC
8bit Timer9
CAP/CMP
16bit FRC
P2
P3
CPCM0
CPCM1
P4
P5
P6
P7
P8
VREF
AGND
10bit A/D
Converter
P9
P10
P11
P12
P14
P15
AI0-7
AO0
AO1
8bit D/A Converter
Interrupt
NMI
EXINT0-7
(Note) When selecting a multiplexed bus
Figure 1-1 MSM66577 Family Block Diagram
1-4
MSM66577 Family User's Manual
Chapter 1 Overview
1.4 Pin Configuration (Top View)
1
75
70
65
60
55
A16/P2_0
A17/P2_1
A18/P2_2
A19/P2_3
VDD
50
45
40
35
30
P3_3/WR
P3_2/RD
P3_1/PSEN
P3_0/ALE
SELMBUS
P11_3/XTOUT
P11_2/CLKOUT
P11_1/HOLD
P11_0/WAIT
VDD
OSC1
OSC0
GND
XT1
80
85
90
95
VREF
AI0/P12_0
AI1/P12_1
AI2/P12_2
AI3/P12_3
AI4/P12_4
AI5/P12_5
AI6/P12_6
AI7/P12_7
AGND
XT0
VDD
EA
NMI
AO1/P14_7
AO0/P14_6
GND
SIOI5/P14_2
SIOO5/P14_1
SIOCK5/P14_0
RXD6-P15_0
TXD6/P15_1
RXC6/P15_2
TXC6/P15_3
RES
P5_7/TM0EVT
P5_6/TM0OUT
P5_5/CPCM1
P5_4/CPCM0
P6_7/TM2OUT
P6_6/TM2EVT
100
1
5
10
15
20
25
[Note] When selecting a multiplexed bus
Figure 1-2 MSM66577 Family Pin Configuration (100-pin TQFP package)
*
Fortheexternaldimensionsofthepackage,refertoChapter22,"PackageDimensions".
For the connections of unused pins, refer to Section 1.5.3.
1-5
MSM66577 Family User's Manual
Chapter 1 Overview
1.5 Pin Descriptions
1.5.1 Description of Each Pin
Table 1-2 lists the function of each pin in the MSM66577 family.
In the I/O column, "I" indicates an input pin, "O" indicates an output pin, and "I/O" indicates
an I/O pin.
Table 1-2 Pin Descriptions (1/3)
Function
Classification
Port
Pin name
I/O
Primary function
I/O
Secondary function
P0_0/D0 (AD0) I/O 8-bit I/O port
I/O External memory access
Data I/O port
to
10 mA sink capability
(Address output/data I/O port
when a multiplexed bus is selected )
P0_7/D7 (AD7)
Pull-up resistors can be
specified for each individual bit
P1_0/A8
to
I/O 8-bit I/O port
O
O
External memory access
Address output port
Pull-up resistors can be
P1_7/A15
P2_0/A16
to
specified for each individual bit
I/O 4-bit I/O port
External memory access
Address output port
Pull-up resistors can be
P2_3/A19
P3_0/ALE
specified for each individual bit
I/O 4-bit I/O port
O
O
O
O
O
External memory access
Address latch enable signal output pin
External program memory access
Read strobe output pin
External memory access
Read strobe output pin
External memory access
Write strobe output pin
External memory access
Address output port
10 mA sink capability
P3_1/PSEN
P3_2/RD
Pull-up resistors can be
specified for each individual bit
P3_3/WR
P4_0/A0
to
I/O 8-bit I/O port
Pull-up resistors can be
(
when a separate bus is selected)
P4_7/A7
specified for each individual bit
P5_4/CPCM0 I/O 4-bit I/O port
I/O Capture 0 input/ Compare
Pull-up resistors can be
0 output pin
specified for each individual bit I/O Capture 1 input/ Compare
1 output pin
P5_5/CPCM1
P5_6/TM0OUT
Timer 0 timer output pin
O
I
P5_7/TM0EVT
Timer 0 external event input pin
External interrupt 0 input pin
External interrupt 1 input pin
External interrupt 2 input pin
External interrupt 3 input pin
Timer 1 external event input pin
Timer 1 timer output pin
P6_0/EXINT0 I/O 8-bit I/O port
I
P6_1/EXINT1
P6_2/EXINT2
P6_3/EXINT3
P6_4/TM1EVT
P6_5/TM1OUT
P6_6/TM2EVT
P6_7/TM2OUT
Pull-up resistors can be
I
specified for each individual bit
I
I
I
O
I
Timer 2 external event input pin
Timer 2 timer output pin
O
1-6
MSM66577 Family User's Manual
Chapter 1 Overview
Table 1-2 Pin Descriptions (2/3)
1
Function
Classification
Port
Pin name
I/O
Primary function
I/O
O
Secondary function
PWM0 output pin
P7_6/PWM0OUT I/O 2-bit I/O port
P7_7/PWM1OUT
Pull-up resistors can be
specified for each individual bit
I/O 7-bit I/O port
Pull-up resistors can be
O
PWM1 output pin
P8_0/RXD1
I
SIO1 receive data input pin
SIO1 transmit data output pin
P8_1/TXD1
O
P8_2/RXC1
specified for each individual bit I/O SIO1 receive clock I/O pin
I/O SIO1 transmit clock I/O pin
P8_3/TXC1
P8_4/TM4OUT
P8_6/PWM2OUT
P8_7/PWM3OUT
P9_0/EXINT4ExIt/eOrna5l-bit I/O port
O
O
O
I
Timer 4 timer output pin
PWM2 output pin
PWM3 output pin
interrupt
P9_1/EXINT5
P9_2/EXINT6
P9_3/EXINT7
P9_7/HLDACK
Pull-up resistors can be
specified for each individual bit
I
External interrupt 5 input pin
External interrupt 6 input pin
External interrupt 7 input pin
HOLD mode output pin
I
I
O
P10_3/SIOCK4 I/O 3-bit I/O port
I/O SIO4 transmit-receive clock I/O pin
P10_4/SIOO4
P10_5/SIOI4
Pull-up resistors can be
specified for each individual bit
I
O
I
SIO4 receive data input pin
SIO4 transmit data output pin
External data memory access
wait input pin
P11_0/WAIT I/O 4-bit I/O port
10 mA sink capability
P11_1/HOLD
P11_2/CLKOUT
P11_3/XTOUT
P12_0/AI0
to
Pull-up resistors can be
I
HOLD mode request input pin
Main clock pulse output pin
Subclock pulse output pin
A/D converter analog input port
specified for each individual bit
O
O
I
I
8-bit input port
P12_7/AI7
P14_0/SIOCK5 I/O 5-bit I/O port
I/O SIO5 transmit-receive clock I/O pin
Pull-up resistors can be
specified for each individual bit
P14_1/SIOO5
P14_2/SIOI5
P14_6/AO0
P14_7/AO1
O
I
SIO5 transmit data output pin
SIO5 receive data input pin
D/A converter analog output port
D/A converter analog output port
SIO6 receive data input pin
SIO6 transmit data output pin
O
O
I
P15_0/RXD6 I/O 4-bit I/O port
Pull-up resistors can be
P15_1/TXD6
P15_2/RXC6
P15_3/TXC6
O
specified for each individual bit
I/O SIO6 receive clock I/O pin
I/O SIO6 transmit clock I/O pin
1-7
MSM66577 Family User's Manual
Chapter 1 Overview
Table 1-2 Pin Descriptions (3/3)
Classification
Power
Pin name
VDD
I/O
I
Function
Power supply pin
supply
Connect all VDD pins to the power supply. *
GND pin
GND
I
Connect all GND pins to GND. *
VREF
I
I
I
Analog reference voltage pin
AGND
Analog GND pin
Oscillation XT0
Subclock oscillation input pin
Connect to a crystal oscillator of f = 32.768 kHz.
Subclock oscillation output pin
XT1
O
I
Connect to a crystal oscillator of f = 32.768 kHz.
The clock output is opposite in phase to XT0.
Main clock oscillation input pin
OSC0
Connect to a crystal or ceramic oscillator.
When an external clock is used, this pin is configured to be clock input.
Main clock oscillation output pin
OSC1
O
Connect to a crystal or ceramic oscillator.
The clock output is opposite in phase to OSC0.
Leave this pin unconnected when an external clock is used.
Reset input pin
Reset
RES
NMI
EA
I
I
I
Others
Non-maskable interrupt input pin
External program memory access input pin
If the EA pin is enabled (low level), the internal program memory is
masked and the CPU executes the program code in external program
memory through all address space.
SELMBUS
I
External bus interface setting input pin
SELMBUS = H: Address/data separate bus type
SELMBUS = L: Multiplexed bus type
* Each of the family devices has unique pattern routes for the internal power and ground.
Connect the power supply voltage to all V pins and the ground potential to all GND pins. If
DD
a device may have one or more V or GND pins to which the power supply voltage or the
DD
ground potential is not connected, it cannot be guaranteed for normal operation.
1-8
MSM66577 Family User's Manual
Chapter 1 Overview
1.5.2 Pin Configuration
A simplified pin configuration for each pin of the MSM66577 family is shown in Table 1-3
and Figure 1-3.
1
Table 1-3 Configuration of Each Pin
Pin name
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_3
P3_0, P3_1
Type
Pin name
P9_0 to P9_3, P9_7
P10_3 to P10_5
P11_0 to P11_3
P12_0 to P12_7
P14_0 to P14_2
P14_6, P14_7
P15_0 to P15_3
RES
Type
6
5
5
4
5
5
5
5
5
5
5
5
5
3
5
7
5
2
1
P3_2, P3_3
P4_0 to P4_7
P5_4 to P5_7
P6_0 to P6_7
P7_6, P7_7
SELMBUS, NMI, EA
P8_0 to P8_4, P8_6, P8_7
1-9
MSM66577 Family User's Manual
Chapter 1 Overview
Type 4, 5, 6
Type 1
IN
VDD
VDD
PULL UP
Schmitt inverter input
DATA
IN/
OUT
Type 2
VDD
Hiz. CONT.
IN
Schmitt inverter input with
pull-up resistor
Output: Push-pull output that can output
high impedance
Type 3
Type 4 input: Schmitt inverter input (CMOS level)
If both the EA and RES pins are at
A/DON
a low level, the input is pulled-up
IN
Type 5 input: Schmitt inverter input (CMOS level)
Type 6 input: Schmitt inverter input (TTL level)
With programmable pull-up resistor
Ø
Ø
A/DON
Type 7
VDD
VDD
PULL UP
DATA
IN/
OUT
Hiz. CONT.
DAOUT
DAON
DAON
Figure 1-3 Types of Pin Configurations
1-10
MSM66577 Family User's Manual
Chapter 1 Overview
1.5.3 Connections for Unused Pins
Table 1-4 lists the pin connections for unused pins.
1
Table 1-4 Connections for Unused Pins
Pin
P0_0 to 0_7
Pin connection
P1_0 to 1_7
P2_0 to 2_3
P3_0 to 3_3
P4_0 to 4_7
When a programmable pull-up resistor is set: Open
When input is set: High or Low level
When output is set: Open
P5_4 to 5_7
P6_0 to 6_7
P7_6, P7_7
P8_0 to P8_4, P8_6, P8_7
P9_0 to 9_3, P9_7
P10_3 to 10_5
P11_0 to 11_3
P14_0 to 14_2, P14_6, P14_7
P15_0 to 15_3
P12_0 to 12_7
VREF
VREF or AGND
V
DD
AGND
GND
NMI
High or Low level
EA
XT0
High level
GND*
Open
OSC1, XT1
GND or VDD (Note)
SELMBUS
* If the subclock (XT0, XT1) is not used, in addition to connecting the XT0 pin to GND and leaving
XT1 unconnected, the peripheral control register (PRPHCON) must be set. For details refer
to Chapter 6, "Clock Oscillation Circuit."
[Note] For SELMBUS,
0: Multiplexed bus
1: Separate bus
1-11
MSM66577 Family User's Manual
Chapter 1 Overview
1.6 Basic Operational Timing
The MSM66577 family is configured such that one pulse of the main clock (CLK) is one
state. In other words, one state is 33.3 ns (at 30 MHz). One instruction cycle consists of
more than one state (S1, S2, ..., Sn).
Thenumberofstatesrequiredforprogramexecutiondiffersdependingupontheinstruction.
The minimum is 2 states and the maximum is 48 states. (For details, refer to the nX-8/500S
Core Instruction Manual.)
To achieve high-speed execution of instructions, one byte of the instruction is pre-fetched.
While one instruction is being executed, the next instruction will be fetched.
Figure 1-4 through Figure 1-7 show basic timing examples.
If program memory is accessed externally, a number of wait cycles (0 to 3 cycles) specified
by the ROM ready control register (ROMRDY) are inserted. If data memory is accessed
externally, 2 or 3 cycles (1 cycle = 1 state) are automatically inserted for a 1 byte read or
write. In addition, the number of wait cycles (0 to 7 cycles) specified by the RAM ready
control register (RAMRDY) will also be inserted.
For external memory access timings, refer to Chapter 18, "Bus Port Functions."
1-12
CPUCLK
State
S3
S4S1
S2
S3
S4S1
S2
= M1S1
S3
S4S5
S6
S7
S8
S1
= M1S1
= M1S1
PC (internal)
P1 (port)
n
n + 1
n + 2
n + 3
n + 4
n + 5
P1 DATA
SAMPLING
P4 (port)
P4 DATA
SAMPLING
Execute
next
instruction
Execute LB A, P1 instruction
Execute MOVB off N8,[DP] instruction (DP = 0024H, LRB: internal RAM)
AL¨P1
off N8¨[DP] (RAM¨P4)
Fetch LB A, P1
instruction
Fetch 2nd
byte of LB A, P1 MOVB off N8,[DP]
instruction instruction
Fetch
Fetch 2nd byte of
MOVB off N8,[DP]
instruction
Fetch 3rd byte of
MOVB off N8,[DP]
instruction
Fetch next
instruction
Figure 1-4 Basic Operation Timing Example (Reading Port Data)
CPUCLK
State
S3
S4S1
S2
S3
S4S1
S2
= M1S1
S3
S4S5
S6
S1
= M1S1
= M1S1
2
PC (internal)
P1 (port)
n
n
+
1
n
+
n
OLD DATA
OLD DATA
NEW DATA (value of AL)
NEW DATA (value of #N8)
P4 (port)
Execute next
instruction
Execute STB A, P1 instruction
Execute MOVB P4, #N8 instruction
P1¨AL
P4¨#N8
Fetch STB A, P1
instruction
Fetch 2nd
byte of STB A, P1 MOVB P4, #N8
instruction instruction
Fetch
Fetch 2nd byte of Fetch 3rd byte of
Fetch next
instruction
Fetch 2nd
byte of next
instruction
MOVB P4, #N8
instruction
MOVB P4, #N8
instruction
Figure 1-5 Basic Operation Timing Example (Writing Port Data)
CPUCLK
State
S4
S1
S2
S3
S4
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S1
S2
= M1S1
= M1S1
= M1S1
= M1S1
TM0C
count clock
TM0RUN
TM0C
ACC
m
m + 1
m + 2
m + 3
m + 4
m + 5
Read TM0C
m + 4 DATA
m + 6
OLD DATA
STB A,TM0CON
STB A,N16[X1]
L A,TM0C
N16[X1]¨ACCL
A¨TM0C
TM0CON¨ACCL
ACCL = 08H
[Note]
• The timing when the TM0RUN bit becomes "1" differs depending upon the instruction used.
• The timing for reading TM0C differs depending upon the instruction used.
• The TM0C count timing differs depending upon the selected TM0C clock.
Figure 1-6 Timer 0 Operation Timing Example
CPUCLK
State
S4
S1
S2
S3
S4
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S1
S2
= M1S1
= M1S1
= M1S1
= M1S1
TM0C
count clock
FFFD
FFFE
FFFF
0000
0001
0002
0003
0004
FFFC
TM0C
IRQ
Interrupt
transfer cycle
Instruction A
Instruction B
0001
Instruction C
TM0C
IRQ
FFFE
FFFF
0000
0002
0003
0004
0005
FFFD
Instruction B
Interrupt transfer cycle
Instruction A
[Note]
• There are 14 interrupt transfer cycles. However, if the program memory space has been
extended 1MB, then there will be 17 cycles.
• IRQ is reset to "0" at the 3rd interrupt transfer cycle.
Figure 1-7 Interrupt Transfer Timing Example
Chapter 2
2
CPU Architecture
MSM66577 Family User's Manual
Chapter 2 CPU Architecture
2. CPU Architecture
2.1 Overview
The MSM66577 microcontroller family utilize the nX-8/500S, Oki’s proprietary 16-bit CPU
core.
2
The nX-8/500S performs various operations mainly by using an accumulator and register
set. Almost all instructions and addressing modes are applicable both to byte-format and
word-format data. And it also has bit processing functions.
Program memory space and data memory space are separated and provided respectively.
Each can be expanded up to 1MB. In addition, special dedicated addressing modes are
provided for some specific portion of data space such as Special Function Registers area,
fixedpagearea, andcurrentpageareaandsoon, forthepurposeofefficientprogramming.
For further details, refer to the "nX-8/500S CPU Core Instruction Manual".
2.2 Memory Space
Program memory space and data memory space are set independently. At reset, up to 64
KB (max.) can be accessed for each. By changing settings of the memory size control
register (MEMSCON), located in the SFR area, the program memory space and the data
memory space can each be expanded up to 1MB.
2.2.1Memory Space Expansion
The memory size control register (MEMSCON) is located in the SFR register and specifies
the size of the memory space. The program memory space can be expanded to 1MB by
setting the LROM bit (bit 1) to "1". The data memory space can be expanded to 1MB by
setting the LRAM bit (bit 0) to "1".
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
0
Address:0011 [H]
R/W access:R/W
LROM LRAM
MEMSCON
At reset
0
0
Data memory space
64KB
0
1
Data memory space
1MB
Program memory
space 64KB
0
1
Program memory
space 1MB
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 2-1 MEMSCON Configuration
2-1
MSM66577 Family User's Manual
Chapter 2 CPU Architecture
To write to the LROM bit of MEMSCON, write "5H" and then "0AH" to the upper 4 bits of
the memory size acceptor (MEMSACP) register located in the SFR area. Likewise, to write
to the LRAM bit of MEMSCON, first write "5H" and then "0AH" to the lower 4 bits of the
memory size acceptor (MEMSACP).
7
6
5
4
3
2
1
0
Address:0010 [H]
R/W access:W
MEMSACP
Writing to LRAM is
enabled by writing "5H"
and "0AH" consecutively.
Writing to LROM is
enabled by writing "5H"
and "0AH" consecutively.
Figure 2-2 MEMSACP Configuration
Note: If the FJ, FCAL, or FRT instruction is executed while the LROM bit is being reset to "0",
the op code trap is generated and system reset will be executed.
If the LROM or LRAM bits are set to "1", the memory space expansion is actually enabled
after execution of the instruction that follows the LROM or LRAM bit write instruction.
Programming examples to expand the program memory space are listed below.
• SMALL memory space (64KB program memory space, 64KB data memory space)
MOVB MEMSACP, #05H
MOVB MEMSACP, #0AH
MOVB MEMSCON, #00H (initial value)
• COMPACT memory space (64KB program memory space, 1MB data memory space)
MOVB MEMSACP, #05H
MOVB MEMSACP, #0AH
MOVB MEMSCON, #01H
• MEDIUM memory space (1MB program memory space, 64KB data memory space)
MOVB MEMSACP, #50H
MOVB MEMSACP, #0A0H
MOVB MEMSCON, #02H
• LARGE memory space (1MB program memory space, 1MB data memory space)
MOVB MEMSACP, #55H
MOVB MEMSACP, #0AAH
MOVB MEMSCON, #03H
MEMSCON can be written only once after reset (due to a RES input, BRK instruction
execution, watchdog timer overflow, or opcode trap). Therefore, to change the memory
space model once set to the other, reset and write again to the MEMSCON.
2-2
MSM66577 Family User's Manual
Chapter 2 CPU Architecture
2.2.2 Program Memory Space
The program memory space is also called "ROM space".
The MSM66577 family can access a maximum of 1MB (1,048,576 bytes) of program
memoryin64KB(65,536bytes)unitsegmentsfromsegment0to15. However,ifmorethan
64KB(segments1to15)aretobeaccessed, theLROMbitoftheMEMSCON(memorysize
control register) SFR must be set to "1".
2
The code segment register (CSR) specifies the segment to be used, and the program
counter (PC) specifies the address in the segment. However, the segment to be used in
theexecutionofROMtablereferenceinstructions(suchasLCA, obj)andtheROMwindow
function is specified by the table segment register (TSR).
The128KB(131,072bytes)areainsegments0and1constitutestheinternalROMareaand
the 64KB areas in segments 2 to 15 form the external ROM area.
The following areas are assigned to segment 0:
• Vector table area (84 bytes)
• VCAL table area (32 bytes)
In addition, the following area is assigned to each segment.
• ACAL area (2,048 bytes)
Figure 2-3 shows a memory map of the program memory space.
2-3
MSM66577 Family User's Manual
Chapter 2 CPU Architecture
Segment 2 to 15
Segment 1
Segment 0
0000H
0000H
0000H
Vector table area
(74 bytes)
0049H
004AH
Vector table area
(32 bytes)
External
ROM area
Internal
ROM area
Internal
ROM area
0069H
006AH
Vector table area
(10 bytes)
0073H
0074H
0FFFH
1000H
0FFFH
1000H
0FFFH
1000H
ACAL area
(2 KB)
ACAL area
(2 KB)
ACAL area
(2 KB)
17FFH
1800H
17FFH
1800H
17FFH
1800H
FFFFH
FFFFH
FFFFH
Figure 2-3 Memory Map of Program Memory Space
2-4
MSM66577 Family User's Manual
Chapter 2 CPU Architecture
(1) Accessing program memory space
Program memory space is accessed by the program counter (PC) and the code segment
register (CSR). However, when a ROM table reference instruction (such as LC A, obj) or
a ROM window function (refer to Section 4.3) is executed, program memory space is
accessed according to the contents of the table segment register (TSR) and the register
specified by the instruction.
2
Access of the internal ROM area and the external memory area of the program memory
space is automatically switched by internal device operation depending on the status of the
EA pin and program addresses.
When a high level is input to the EA pin, the internal ROM area is accessed if the program
address is between 0000H and 1FFFFH, and the external ROM area is accessed if the
address is between 20000H to FFFFFH. When the external ROM area is to be accessed,
the secondary functions of the external memory control pins (port 0, 1, 2, 3 and 4) must be
set.
The area from 0000H to 1FFFDH can be fetched by the internal program. Be careful that
the final address of instruction code does not exceed 1FFFDH. The final address of the
table data is 1FFFFH.
When a low level is input to the EA pin, the external program memory area is accessed for
all program addresses.
If the external memory area of the program memory space is accessed in a separate bus
type, Port 0 (data input), Port 4 (addresses A0 to A7 outputs), Port 1 (addresses A8 to A15
outputs) and Port 2 (addresses A16 to A19 outputs) operate as bus ports, and the P3_1/
PSEN pin becomes active.
If the external memory area of the program memory space is accessed in a multiplexed bus
type, Port 0 (address output and data input),Port 1 (addresses A8 to A15 outputs) and Port
2 (addresses A16 to A19 outputs) operate as bus ports, and P3_0/ALE pin and P3_1/PSEN
pin become active.
(2) Vector table area
The 74-byte area of addresses from 0000H to 0049H and the 10-byte area of addresses
from 006AH to 0073H in segment 0 of program memory space are used as the vector table
area that stores branch addresses for all types of resets and interrupts (29 types) as shown
in Table 2-1.
If a reset or interrupt occurs, the corresponding 2-byte branch address, stored in the vector
table, is loaded into the PC. (The even address contains the lower order data and the odd
address contains the upper order data.) At the same time, "0" is loaded into the Code
Segment Register (CSR) and program execution starts from the loaded segment 0
address. Therefore, if a reset or interrupt occurs during execution of an instruction in
segment 1 (or segment other than 0), program control will branch to an address in segment
0.
With reasons described above, reset routine and interrupt routines must be located in
segment 0. This fact is important for medium and large memory model programming.
Proper alignment attribute must be applied to your relocatable interrupt routines.
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InmediumandlargememorymodelyouspecifiedbyMEMSCONsetting,CPUautomatically
provides extra stack area for the CSR contents. When RTI instruction is executed, CSR
contents in stack are re-stored into CSR and program execution is continued in the same
program segment.
If this area is not used as a vector table area, it can be used as a normal program area.
Table 2-1 lists the vector table addresses for each type of reset or interrupt.
[Example] Program starting address of 0200H due to RES pin input
Program address
0000H
Data code
00H
(lowerorderdataforprogramstartaddress)
(upperorderdataforprogramstartaddress)
0001H
02H
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Table 2-1 Vector Table List
Vector table
starting address
[H]
Interrupt or reset factor
2
0000
Reset by RES pin input
0002
Reset by execution of BRK instruction
0004
Reset by overflow of watchdog timer
0006
Reset by opcode trap
0008
Interrupt by NMI pin input (non-maskable interrupt)
Interrupt by EXINT0 pin input (external interrupt 0)
Interrupt by overflow of free running counter
Interrupt by CPCM0 event input, compare match
Interrupt by CPCM1 event input, compare match
Interrupt by overflow of timer 0
000A
000C
0016
0018
001A
001C
001E
0020
Interrupt by EXINT1 pin input (external interrupt 1)
Interrupt by EXINT2 pin input (external interrupt 2)
Interrupt by EXINT3 pin input (external interrupt 3)
Interrupt by overflow of timer 1
0022
0024
Interrupt by overflow of timer 2
0026
Interrupt by overflow of timer 3
0028
Interrupt by SIO0 transmit buffer empty, transmit completion, receive completion
Interrupt by EXINT4 pin input (external interrupt 4)
Interrupt by EXINT5 pin input (external interrupt 5)
Interrupt by EXINT6 pin input (external interrupt 6)
Interrupt by EXINT7 pin input (external interrupt 7)
Interrupt by overflow of timer 4
002A
002C
002E
0030
0036
0038
Interrupt by SIO1 transmit buffer empty, transmit completion, receive completion
Interrupt by overflow of timer 5
003A
003C
003E
0040
Interrupt by SIO5 transfer completion
Interrupt by SIO6 transmit buffer empty, transmit completion, receive completion
Interrupt by SIO4 transfer completion
0042
Interrupt by overflow of timer 6
0044
Interrupt by A/D conversion scan channel cycle completion/select mode completion
Interrupt by real-time counter output (interval: 0.125 to 1 s)
Interrupt by PWC0 overflow, PWC0 and PWR0 match
Interrupt by PWC1 overflow, PWC1 and PWR1 match
Interrupt by PWC0 and PWR2 match
0048
006A
006C
006E
0070
Interrupt by PWC1 and PWR3 match
0072
Interrupt by overflow of timer 9
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(3) VCAL table area
The VCAL table area is assigned to the 32-byte area of program memory space in segment
0 from address 004AH to 0069H and stores branch addresses for 1-byte call instructions
(VCAL: 16 types).
If a VCAL instruction is executed, the next address after the VCAL instruction is saved onto
thesystemstack,thesystemstackpointer(SSP)isdecrementedby2,andthecorresponding
2-byte address stored in the vector table is loaded into the PC. (The even address contains
the lower data and the odd address contains the upper data). The program begins
execution from the loaded address.
However, if the program memory space has been expanded to 1MB, the SSP is
decremented by 4 because the CSR value is also saved at the same time that the PC is
saved. Also, the CSR is loaded with "0" at the same time as the branch address is loaded
into the PC. Therefore, if a VCAL instruction is executed in segment 1, program control will
branch to a branch address in segment 0.
If the program memory space is up to 64KB (the LROM bit of MEMSCON is "0"), execution
of a RT instruction will return program control from the subroutine branched to by the VCAL
instruction. If the program memory space is 1MB (the LROM bit is "1"), execution of a FRT
instructionreturnsprogramcontrolfromthesubroutinebranchedtobytheVCALinstruction.
If this area is not used as the VCAL table area, it can be used as a normal program area.
Table 2-2 lists the VCAL vector addresses.
[Example] Program starting address of 0400H due to VCAL 4AH instruction
Program address
004AH
Data code
00H
(lower order data for subroutine start address)
(upper order data for subroutine start address)
004BH
04H
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Table 2-2 VCAL Vector Address List
VCAL table starting address [H]
VCAL instruction
VCAL 4AH
VCAL 4CH
VCAL 4EH
VCAL 50H
VCAL 52H
VCAL 54H
VCAL 56H
VCAL 58H
VCAL 5AH
VCAL 5CH
VCAL 5EH
VCAL 60H
VCAL 62H
VCAL 64H
VCAL 66H
VCAL 68H
004A
004C
004E
0050
0052
0054
0056
0058
005A
005C
005E
0060
0062
0064
0066
0068
2
(4) ACAL area
The 2KB area from 1000H to 17FFH of each program segment is called ACAL area. The
subroutines located in this area can be called by 2-byte call instruction (ACAL).
ACAL is an in-segment call instruction which does not rewrite the CSR contents.
If an ACAL instruction is executed, the address following the next address after the ACAL
instruction is saved onto the system stack, the system stack pointer (SSP) is decremented
by 2, and 11-bit data included in the ACAL instruction code is loaded into the PC. Program
execution begins at the loaded address (1000H to 17FFH).
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2.2.3 Data Memory Space
A maximum of 1MB (1,048,576 bytes) of data memory can be accessed.
Thefollowingareasareassignedtothedatamemoryspace:aspecialfunctionregisterarea
(SFR: 256 bytes), a reserved area (256 bytes), a fixed page area (FIX: 256 bytes), an
internal RAM area (4,096 bytes), a local register setting area (2,048 bytes) and an external
memory area (1,043,968 bytes).
A pointing register area (PR: 64 bytes) and a special bit addressing area (sbafix: 64 bytes)
are assigned to the fixed page area. The ROM window setting area (1200H to 0FFFFH of
segment 0 and 1000H to 0FFFFH of segments 1 to 15) is assigned to the external data
memory area.
SothatdatacanbeexchangedbetweentwoormoredatasegmentswithoutchangingDSR,
there is a common area that starts at data memory address 0H. The SFR area, reserved
area and fixed page area always belong to the common area.
Figure 2-4 shows a memory map of the data memory space.
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Segment 0
Segments 1 to 15
0000H
0000H
Range of
common area
SFR area
Reserved area
FIX area
BCB
00FFH
0100H
0
1
2
3
0 to 03FFH
0 to 1FFFH
0 to 3FFFH
0 to 7FFFH
2
01FFH
0200H
Common area
02FFH
0300H
03FFH
Internal
Local register
RAM area setting area
External data
memory area
09FFH
0A00H
0FFFH
1000H
11FFH
1200H
1FFFH
3FFFH
7FFFH
8000H
7FFFH
ROM window
setting area
ROM window
setting area
External data
memory area
0FFFFH
0FFFFH
Figure 2-4 Memory Map of Data Memory Space
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(1) Special function register (SFR) area
The group of registers with special functions such as mode registers for internal peripheral
hardware, controlregistersandcountersareassignedtothe256-byteareaindatamemory
space from 0000H to 00FFH. Refer to Chapter 21, "Special Function Registers (SFRs)" for
a more detailed description.
(2) Reserved area
The 256-byte data memory space from 0100H to 01FFH is reserved for future use as an
expanded SFR area. This area cannot be used.
(3) Internal RAM area
Internal RAM is assigned to the 4,096-byte area in data memory space from 0200H to
11FFH.
(4) Fixed page (FIX) area
A pointing register (PR) area and a special bit addressing (sbafix) area are assigned to the
256-byte area in data memory from 0200H to 02FFH.
The pointing register area is assigned to addresses 0200H to 023FH and contains 8 sets
of the following 4 registers.
• Index register (X1, X2)
• Data pointer (DP)
• User stack pointer (USP)
All of the above are 16-bit registers. Even addresses contain lower order data and odd
addresses contain higher order data.
The special bit address area is assigned to addresses 02C0H to 02FFH. SB, RB, JBR and
JBS instructions to this area can be implemented in a small number of bytes.
Figure 2-5 shows the map of the fixed page area.
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Reserved area
01FFH
0200H
X1
X2
DP
USP
X1
SCB = 0
SCB = 1
2
0208H
X2
Pointing
register set
DP
USP
X1
0210H
0238H
Fixed
page area
USP
X1
X2
SCB = 7
DP
USP
0240H
02C0H
0300H
This area can be used by
SB, RB, JBS, and JBR
instructions with sba. bit
as the object.
SBA area
64 bytes
Figure 2-5 Map of Fixed Page Area
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(5) Local register setting area
The local register setting area is the 2KB area of data memory from 0200H to 09FFH. Local
registers are set in 8-byte units, as specified by the lower 8 bits of LRB (LRBL).
Figure 2-6 shows the map of the local register setting area.
0000H
0100H
0200H
0300H
SFR area
Reserved area
FIX area
R0
R1
R2
R3
R4
R5
R6
R7
R0
R1
0200H
0208H
ER0
ER1
ER2
ER3
ER0
Local register setting area:
Specified by 8 bits of LRBL,
in 8-byte units
Internal
RAM area
LRBL =
00H
0A00H
1200H
LRBL =
01H
External
data memory
area
LRBL =
FFH
R6
R7
ER3
0FFFFFH
0A00H
Figure 2-6 Map of Local Register Setting Area
(6) External data memory area
The external data memory area is the 1,043,968-byte area of data memory from 1200H to
0FFFFFH(Note1). Ifthisexternaldatamemoryistobeaccessed, thesecondaryfunctions
of memory related pins (ports 0, 1, 2, 3 and 4) must be set. In a separate bus type, the
external data memory is accessed by Port 0 (data I/O: D0 to D7), Port 4 (address output:
A0 to A7), Port 1 (address output: A8 to A15), Port 2 (address output: A16 to A19), P3_3/
WR (write strobe output function) and P3_2/RD (read strobe output function) signals.
In a multiplexed bus type, the external data memory is accessed by Port 0 (combined I/O
of data input and address output: AD0 to AD7), Port 1 (address output: A8 to A15), Port
2 (address output: A16 to A19), P3_0/ALE (address latch enable output function), P3_2/
RD (read strobe output function) and P3_3/WR (write strobe output function) signals.
The 1,043,968-byte area from 1200H to 0FFFFFH of data memory is the external data
memory area. However, the ROM window function can be set by the ROM window setting
register. If the ROM window function is used in the specified area (address 1200H and
above), insteadofaccessingdatainthedatamemoryspace, instructions(readoperations)
will access data in the program memory space at the same address.
The ROM window function is valid if the register (ROMWIN) that enables the ROM window
function is set and the accessed (read) address is in external data memory.
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(7) Common area
Thereisacommonareainthedatamemoryspacetoenabletheexchangeofdatabetween
two or more data segments. The common area is located at the bottom of data memory,
beginning at offset address 0H in each segment. The range of the common area is
determined by the value of BCB in the PSW.
2
B C B
BCB range of
common area
1
0
0
1
0
1
0H to 03FFH
0H to 1FFFH
0H to 3FFFH
0H to 7FFFH
0
0
1
1
2.2.4 Data Memory Access
Examples of memory access are presented below for the cases when an instruction
performs a byte operation and a word operation in the data memory space.
(1) Byte operations
In the case of a byte operation, the address obtained from the instruction points to the
targeted 8-bit data.
[Example] LB A, [DP]: where the contents of DP are 0335H
15
ACC
0
0332H
0333H
0334H
0335H
0336H
0337H
0338H
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(2) Word operations
Inthecaseofawordoperation, correspondingtotheaddressobtainedfromtheinstruction,
theaddresswithleastsignificantbit(LSB)setto"0"(evenaddress)pointstothelowerorder
8-bit data and the address with LSB set to "1" (odd address) points to the upper order 8-
bit data to form the targeted 16-bit data.
Therefore, a targeted 16-bit data formed with upper oder 8-bit data for the odd address and
lower oder 8-bit for the even address can not be accessed. (The boundary exists between
two bytes in word operation.)
Yet such a boundary limit does not exist for the program memory space.
[Example] L A, [DP]: where the contents of DP are 0334H (or 0335H)
15
ACC
0
0331H
0332H
0333H
0334H
0335H
0336H
0337H
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2.3 Registers
Registers are classified by function as the arithmetic register, control registers, pointing
registers, special function registers, local registers and segment registers.
Figure 2-7 shows the configuration of each register.
2
Arithmetic register
15
Control registers
15
0
0
0
ACC
PSW
P C
LRB
SSP
Pointing registers
15
X1
X2
Segment registers
7
0
DP
CSR
TSR
DSR
USP
Special function registers (SFRs)
0 7
Local registers
7
0
7
0 7
0
1
3
0
2
R1
R3
R5
R7
R0
R2
R4
R6
(ER0)
(ER1)
(ER2)
(ER3)
253
255
252
254
Figure 2-7 Register Configurations
2.3.1 Arithmetic Register (ACC)
The arithmetic register is a 16-bit accumulator (ACC), central to all type of arithmetic
operations.
If a transfer or arithmetic operation is:
• a word operation, all 16 bits (bits 15 to 0) are accessed,
• a byte operation, the lower 8 bits (bits 7 to 0) are accessed, or
• a nibble operation, the lower 4 bits (bits 3 to 0) are accessed.
IfthetargetedbitinabitinstructionisspecifiedbyACC(suchasSBR, RBR, etc.), theupper
5 bits (bits 7 to 3) within the lower 8 bits specify the address offset, and the lower 3 bits (bits
2 to 0) specify the bit position.
ACC is assigned to the SFR area. At reset (due to a RES input, BRK instruction execution,
watchdog timer overflow, or opcode trap), the contents of ACC become 0000H.
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2.3.2 Control Registers
Control registers are a group of four 16-bit registers with dedicated functions for program
status, program sequence, local registers and stack control.
(1) Program status word (PSW)
PSW is a 16-bit register consisting of the following.
• A flag (DD) that is referenced when executing instructions
• Flags (CY, ZF, HC, S, OV) that are set to "1" or reset to "0" depending upon instruction
execution results
• Flags (SCB0 to SCB2) that specify the pointing register setting
• A flag (MIE) that enables ("1") or disables ("0") all maskable interrupts
• Flags (BCB0, BCB1) that specify the segment 0 common area
• Flags (F0 to F2) that the user can freely utilize
• A flag for use with future expanded CPU core functions. This flag (MAB) can be freely
utilized by the user.
In addition to 16-bit PSW operations, 8-bit operations can also be performed with the PSW
divided into the 8-bit units of PSWH (bits 15 to 8) and PSWL (bits 7 to 0).
Figure 2-8 shows the PSW configuration.
Address: 0005 [H]
R/W access: R/W
Address: 0004 [H]
R/W access: R/W
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BCB
SCB
1
PSW
CY ZF HC DD
S
0
F2 OV MIE MAB F1
F0
1
0
0
0
2
0
0
0
At reset
0
0
0
0
0
0
0
0
0
0
0
PSWH
PSWL
PSW
Figure 2-8 PSW Configuration
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The upper 8 bits of the PSW (PSWH) contain:
• a flag (DD) that is referenced when executing instructions and
• flags (CY, ZF, HC, S, OV) that are set to "1" or reset to "0" depending upon instruction
execution results.
2
Therefore, ifthefollowinginstructionsareperformedonPSWorPSWH, flagoperationmay
change from its original function.
(i) Instructions that load the contents of PSW or PSWH into ACC
(contents of ZF become undefined)
(ii) Bit operation instructions on ZF
(ZF changes depending on its value immediately before execution of the bit operation
instruction.)
(iii) Increment, decrement, arithmetic, logic and compare instructions on PSW or PSWH
(ThecontentsofPSWorPSWHimmediatelyafterinstructionexecutionareundefined.)
If an interrupt occurs, PSW is automatically saved during interrupt processing and
automatically restored by execution of a RTI instruction.
PSW is assigned to the SFR area. At reset (due to a RES input, BRK instruction execution,
watchdog timer overflow, or opcode trap), the contents of PSW become 0000H.
Each bit in the PSW is described below.
Bit 15: Carry flag (CY)
The carry flag is set to "1" if:
• carry from bit 7 occurs in a byte operation,
• borrow to bit 7 occurs in a byte operation,
• carry from bit 15 occurs in a word operation, or
• borrow to bit 15 occurs in a word operation
as the result of executing an arithmetic or comparison instruction. Otherwise it is reset to
"0". The carry flag can be set or reset directly by instructions and can be used to transmit
or receive data for bits specified by registers. In addition, the carry flag can be tested by
conditional branch instructions.
Bit 14: Zero flag (ZF)
The zero flag is set to "1" when:
• the result of an arithmetic instruction is zero,
• an instruction to load the ACC is executed and the load contents are zero, or
• a bit operation instruction is executed and the target bit is zero.
Otherwise,itisresetto"0". Thezeroflagcanbetestedbyconditionalbranchinstructions.
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Bit 13: Half carry flag (HC)
The half carry flag is set to "1" if a carry or borrow from bit 3 occurs as a result of executing
an arithmetic or comparison instruction (either a byte and word instruction). Otherwise,
it is reset to "0".
Bit 12: Data descriptor (DD)
This flag indicates the attributes of data stored in ACC.
• When DD is "1", the 16 bits of data in ACC are determined to be valid.
• When DD is "0", the lower 8 bits of data in ACC are determined to be valid.
InstructionsthatreferenceDDwhenperformingarithmeticordatatransferinstructionswith
ACC are executed as follows.
• When DD is "1", the arithmetic or transfer operation is performed in word units.
• When DD is "0", the arithmetic or transfer operation is performed in byte units.
DD is set to "1" or reset to "0" when a data transfer instruction to ACC is executed and when
dedicated set and reset instructions are executed.
• DDissetto"1"whenexecutingaword-typeloadinstructiontoACCandwhenexecuting
a SDD instruction.
• DD is reset to "0" when executing a byte-type load instruction to ACC and when
executing a RDD instruction.
If DD is modified (set or reset) while executing a load instruction to ACC or a dedicated set
or reset instruction, and if the next instruction references DD, the modified DD will be
referenced.
Since DD is assigned to PSW, DD can be overwritten by instructions other than those
mentioned above. In this case, if the next instruction references DD, it will reference the
state of DD prior to modification. If DD is to be used in this manner, insert a NOP instruction
after the instruction that directly modifies the state of DD.
Bit 11: Sign flag (S)
The sign flag is set to "1" if the MSB of the result of executing an arithmetic or logic
instruction is "1". If the MSB of the result is "0", the sign flag is reset to "0".
Bit 10: User flag 2 (F2)
Bit 6: User flag 1 (F1)
Bit 3: User flag 0 (F0)
These flags can be set to "1" or reset to "0" by instructions.
Bit 9: Overflow flag (OV)
The overflow flag is set to "1" if the result of executing an arithmetic instruction exceeds
a range expressed in 2’s compliment format (–128 to +127 for byte operations and
–32,768 to +32,767 for word operations). Otherwise the overflow flag is reset to "0".
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Bit 8: Master interrupt enable flag (MIE)
The master interrupt enable flag enables ("1") or disables ("0") all maskable interrupts.
During a maskable interrupt transfer cycle, after this flag is saved onto the system stack
as part of PSW, it is reset to "0", and then restored by execution of a RTI instruction. If
MIE is set to "1", the generation of all maskable interrupts is enabled from the next
instruction. If reset to "0", the generation of all maskable interrupts is disabled from the
next instruction.
2
Bit 7: Product-sum function bank flag (MAB)
The MSM66577 family does not have the product-sum function, so this can be utilized as
a user flag.
Bit 5: Bank common base 1 (BCB1)
Bit 4: Bank common base 0 (BCB0)
These flags specify the last address of the common area between segments in data
memory space. The table below shows the relation between BCB value and selected
common area.
B C B
BCB range of
common area
1
0
0
1
0
1
0H to 03FFH
0H to 1FFFH
0H to 3FFFH
0H to 7FFFH
0
0
1
1
Bit 2: System control base 2 (SCB2)
Bit 1: System control base 1 (SCB1)
Bit 0: System control base 0 (SCB0)
These flags specify the pointing register (PR) set assigned to the fixed page area.
S C B
SCB pointing register set
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
PR0(0200H to 0207H)
PR1(0208H to 020FH)
PR2(0210H to 0217H)
PR3(0218H to 021FH)
PR4(0220H to 0227H)
PR5(0228H to 022FH)
PR6(0230H to 0237H)
PR7(0238H to 023FH)
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(2) Program counter (PC)
The PC is a 16-bit counter that stores the next address to be executed in the program
segment. The PC is normally incremented according to the number of bytes in the
instruction to be executed. If a branch instruction or an instruction that requires a branch
is executed, the PC is loaded with immediate data, register contents, etc. The CSR value
does not change even if the PC is incremented so that it overflows.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), or when an interrupt is generated, a value from the vector table is loaded into the PC.
(3) Local register base (LRB)
LRB is a 16-bit register. The lower 8 bits (LRBL) specify the 2KB data memory space from
0200Hto09FFHin8-byteunits(localregisteraddressing). Theupper8bits(LRBH)specify
the64KBdatamemoryspacein256-byteunitsofthesegment(segments0to15)arbitrarily
specified by the data segment register (DSR) (current page addressing). SB, RB, JBR and
JBS instructions whose object is sba.bit can be used in the 64-byte area of the current page
from xxC0H to xxFFH.
Both LRBL (02H) and LRBH (03H) are assigned to the SFR area. At reset (due to a RES
input, BRK instruction execution, watchdog timer overflow, or opcode trap), their value is
undefined.
Address: 0003 [H]
R/W access: R/W
Address: 0002 [H]
R/W access: R/W
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
LRB
At reset
Undefined
LRBH
LRBL
LRB
Figure 2-9 LRB Configuration
• The 8 bits of LRBL specify the 2KB data memory space from 0200H to 09FFH in 8-byte
units.
7
6
5
4
3
2
1
0
¥
¥
¥
LRBL
The 8 bits of LRBL specify the 2KB data
memory space from 0200H to 09FFH in 8-byte
units. (Value ¥ is included in the instruction code.)
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• The 8 bits of LRBH specify 64KB of data memory space in 256-byte units.
7
6
5
4
3
2
1
0
¥
¥
¥
¥
¥
¥
¥
¥
2
LRBH
The 8 bits of LRBH specify the 64KB data memory space
from 0000H to 0FFFFH in 256-byte units.
(Value ¥ is included in the instruction code.)
(4) System stack pointer (SSP)
SSP is a 16-bit register that indicates the stack address at which to save or restore the PC,
registers,etc.whileprocessinginterruptsorexecutingcall,push,return,orpopinstructions.
SSP is automatically incremented or decremented depending upon the process to be
executed.
Since save and restore operations at the address indicated by the SSP are performed in
word units, the least significant bit (LSB) of the SSP is addressed as "0". The SFR area and
the Expanded SFR area can not be used as a stack area.
SSP (00H) is assigned to the SFR area. At reset (due to a RES input, BRK instruction
execution,watchdogtimeroverflow,oropcodetrap),thecontentsofSSPbecome0FFFFH.
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2.3.3 Pointing Register (PR)
The PR has 8 sets of registers. One set consists of the following four 16-bit registers.
• Index register 1 (X1)
• Index register 2 (X2)
• Data pointer (DP)
• User stack pointer (USP)
PR is assigned to the internal RAM space from 0200H to 023FH. One of the eight register
sets is selected by SCB0 to SCB2 of PSWL.
If the PR function is not used, this area can be used as normal internal RAM.
For all X1, X2, DP and USP, even addresses are the lower 8 bits and the following odd
addresses are the upper 8 bits.
Reserved area
01FFH
0200H
X1
X2
DP
USP
X1
SCB = 0
SCB = 1
0208H
X2
Pointing register sets
DP
USP
X1
0210H
0238H
USP
X1
X2
SCB = 7
DP
USP
0240H
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2.3.4 Local Registers (R0 to R7, ER0 to ER3)
The local register Rn (n = 0 to 7) is an 8-bit register and the expanded local register ERm
(m = 0 to 3) is a 16-bit register. The 2KB area in data memory space from 0200H to 09FFH
is specified in 8-byte units by the lower 8 bits of local register base (LRBL). Rn accesses
1 byte of the specified 8 bytes according to the 3 bits of data included in the local register
instruction. (ERm accesses 2 bytes according to the 2 bits of data included in the local
register instruction.)
2
0200H
R0
R1
R2
R3
R4
R5
R6
R7
ER0
ER1
ER2
ER3
ER0
LRBL =
00H
R0
R1
0208H
LRBL =
01H
Specified in 8-byte units
by the 8 bits of LRBL.
R0 to R7 are specified by
3 bits included in the
instruction code. ER0 to
ER3 are specified by 2
bits included in the
instruction code.
R6
R7
LRBL =
0FFH
ER3
0A00H
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2.3.5 Segment Registers
There are three 8-bit segment registers: the code segment register (CSR), the table
segment register (TSR) and the data segment register (DSR). These registers select
segments in the program memory space.
However, since the program memory space has only segments 0 to 15, only bits 0 to 3 are
valid. Bits 4 to 7 are fixed to "0".
(1) Code segment register (CSR)
7
6
5
4
3
0
2
0
1
0
0
0
"0" "0" "0" "0"
CSR
0
0
0
0
At reset
CSR specifies the segment in program memory space to which the program code currently
being executed belongs. CSR exists as an independent 8-bit register and is not assigned
to the SFR area. The CSR contents can be overwritten by FJ, FCAL, VCAL, FRT and RTI
instructionsandinterrupts. NoothermethodscanbeusedtooverwritethecontentsofCSR.
For FJ and FCAL instructions, use branch destination addresses that are within segments
0 to 15.
Eachsegmentisassignedaninternalsegmentoffsetaddressof0to0FFFFH. Theaddress
calculation to determine the addressed target is performed with a 16-bit offset address and
any resulting overflow or underflow is ignored so that CSR does not change. Similarly,
overflowofthePCneverupdatestheCSR. Therefore, withouttheuseoftheCSRoverwrite
method described above, program execution does not advance beyond the code segment
boundary. The CSR value at reset is 00H.
When an interrupt occurs after program memory space has been expanded to 1MB, both
the current CSR value and the PC are automatically saved on the stack. Executing a RTI
instruction restores the saved value to CSR. (Refer to Section 2.2.1, "Memory Space
Expansion".)
(2) Table segment register (TSR)
7
6
5
4
3
0
2
0
1
0
0
0
Address: 0008 [H]
R/W access: R/W
"0" "0" "0" "0"
TSR
At reset
0
0
0
0
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
TSR specifies the segment in program memory to which the table data belongs. TSR is an
8-bit register and is assigned to the SFR area. The contents of TSR can be overwritten by
instructions that use SFR addressing. Data in the table segment can be accessed by using
ROM reference instructions (LC, LCB, CMPC and CMPCB). If the ROM window function
is used, RAM addressing can be utilized for this table segment. Only bits 0 to 3 of TSR are
valid. If read, a value of "0" will be obtained for bits 4 to 7. If writing to TSR, "0" must be
written to bits 4 to 7.
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Eachsegmentisassignedaninternalsegmentoffsetaddressof0to0FFFFH. Theaddress
calculation to determine the addressed target is performed with a 16-bit offset address and
any resulting overflow or underflow is ignored, so TSR does not change. The TSR value
at reset is 00H.
2
(3) Data segment register (DSR)
7
6
5
4
3
0
2
0
1
0
0
0
Address: 0009 [H]
R/W access: R/W
"0" "0" "0" "0"
DSR
0
0
0
0
At reset
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
DSR specifies the segment in data memory space to which the data currently in use
belongs. DSR is an 8-bit register and is assigned to the SFR area. The contents of DSR
can be overwritten by instructions that use SFR addressing. Only bits 0 to 3 of DSR are
valid. If read, a value of "0" will be obtained for bits 4 to 7. If writing to DSR, "0" must be
written to bits 4 to 7.
2.4 Addressing Modes
The MSM66577 family has two independent memory spaces, the data memory space and
the program memory space. Addressing can be roughly classified into two modes,
corresponding to each memory space.
Thedatamemoryspaceisreferredtoas"RAMspace", sinceitnormallyconsistsofrandom
access memory (RAM). The addressing for this space is referred to as "RAM addressing".
The program memory space is referred to as "ROM space", since it normally consists of
read-only memory (ROM). The addressing for this space is referred to as "ROM
addressing".
ROM addressing is classified as immediate addressing contained in instruction codes,
tabledataaddressingfordata(normallyread-onlydata)inaROMspacetable,andprogram
code addressing for programs in the ROM space.
ROM window addressing is a unique method of addressing. It involves accessing table
dataintheROMspaceusingtheaboveRAMaddressingmethods. Datainatablesegment
is read through a data segment window specified and opened by the program.
2.4.1 RAM Addressing
This addressing mode specifies addresses for program variables in the RAM space.
Available addressing formats include: register addressing, page addressing, direct
addressing, pointing register indirect addressing and special bit area addressing.
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(1) Register addressing
A. Accumulator addressing
B. Control register addressing
C. Pointing register addressing
D. Local register addressing
A
PSW, LRB, SSP
X1, X2, DP, USP
ERn, Rn
A. Accumulator addressing
In the case of a word-format instruction, the contents of the accumulator (A) will be
accessed. In the case of byte and bit-format instructions, the lower byte of the accumulator
(AL) will be accessed.
[Word format]
L
ST
A, #1234H
A, VAR
[Byte format]
LB
STB
A, #12H
A, VAR
[Bit format]
MB
C, A.3
JBS
A.3, LABEL
B. Control register addressing
The contents of the registers will be accessed.
SSP:
LRB:
PSW:
PSWH:
PSWL:
C:
System Stack Pointer
Local Register Base
Program Status Word
Program Status Word High Byte
Program Status Word Low Byte
Carry Flag
[Word format]
FILL
SSP
MOV
CLR
LRB, #401H
PSW
[Byte format]
CLRB
PSWH
PSWL
INCB
[Bit format]
MB
C, BITVAR
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C. Pointing register addressing
The contents of the pointing register are accessed.
There are 8 sets of pointing registers (PR0 to PR7: every 8 bytes from 200H to 23FH in data
memory). The set addressed by this mode is specified by the value of the system control
base (SCB) field in PSW.
2
X1:
X2:
DP:
Index Register 1
Index Register 2
Data Pointer
The low byte of the data pointer is used only for a "JRNZ DP radr" instruction
(to maintain compatibility among nX-8/100 to nX-8/400 CPU cores).
User Stack Pointer
USP:
X1L:
Index Register 1 Low Byte
X2L:
Index Register 2 Low Byte
DPL:
USPL:
Data Pointer Low Byte
User Stack Pointer Low Byte
[Word format]
L
A, X1
ST
A, X2
MOV
CLR
DP, #2000H
USP
[Byte format]
DJNZ
X1L, LOOP
X2L, LOOP
DPL, LOOP
USPL, LOOP
DP, LOOP
DJNZ
DJNZ
DJNZ
JRNZ
D. Local register addressing
The contents of the local register are accessed.
There are 256 sets of local registers (every 8 bytes from 200H to 9FFH in data memory).
The set addressed by this mode is specified by the value of the low byte of the local register
base (LRB).
ER0 to ER3: Expanded Local Registers
R0 to R7:
Local Registers
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[Word format]
L
A, ER0
ER2, ER1
ER3
MOV
CLR
[Byte format]
LB
A, R0
R1, A
R2, #12H
R3
ADDB
CMPB
INCB
ROR
R4
MOVB
R5, R6
[Bit format]
SB
R0.0
RB
R1.7
JBRS
R7.3, LABEL
(2) Page addressing
A. SFR page addressing
B. FIXED page addressing
C. Current page addressing
sfr Dadr
fix Dadr
off Dadr
A. SFR page addressing
One byte of the instruction code specifies an offset within a SFR page (data memory
addresses0to0FFH). Word-format, byte-formatorbit-formatdataatthespecifiedaddress
is accessed.
The operand is described using a format that has a sfr addressing descriptor. The sfr
descriptor can be omitted, however in that case, the assembler will use SFR page
addressing only when it recognizes an address within the SFR page area.
The SFR has address symbols for each type of device. These symbols are normally used
for addressing the SFR.
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[Word format]
RAM
L
L
A, sfr P0
A, P0
0000H
00xxH
2
SFR page
00FFH
If an odd address is specified, word-format data is accessed starting at the following even
address. (’word boundary) However, depending upon the SFR, there are some
exceptions.
[Byte format]
RAM
LB A, sfr P0
0000H
LB A, P0
00xxH
00FFH
SFR page
[Bit format]
RAM
SB sfr P0_3
0000H
00xxH
SB P0_3
SFR page
00FFH
B. FIXED page addressing
One byte of the instruction code specifies an offset within a FIXED page (data memory
addresses 200H to 2FFH). Word-format, byte-format or bit-format data at the specified
address is accessed.
The operand is described using a format that has a fix addressing descriptor. The fix
descriptor can be omitted, however in that case, the assembler will use FIXED page
addressing only when it recognizes an address within the FIXED page area.
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[Word format]
RAM
L
L
A, fix FIX_VAR
A, FIX_VAR
0200H
02xxH
FIXED page
02FFH
If an odd address is specified, word-format data is accessed starting at the following even
address.
[Byte format]
RAM
LB A, fix FIX_VAR
0200H
LB A, FIX_VAR
02xxH
FIXED page
02FFH
[Bit format]
RAM
SB fix FIX_VAR.3
0200H
SB FIX_VAR.3
02xxH
FIXED page
02FFH
C. Current page addressing
One byte of the instruction code specifies an offset within the current page (one of the 256
pages in data memory specified by the LRBH value). Word-format, byte-format or bit-
format data at the specified address is accessed.
Theoperandisdescribedusingaformatthathasanoffaddressingdescriptor. \canbeused
instead of the off descriptor, however if bit-format data is accessed in the SBA area,
operation will be slightly different. (sbaoff Badr)
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[Word format]
RAM
L
L
A, off VAR
A, \VAR
xx00H
xxxxH
2
Current page
xxFFH
If an odd address is specified, word-format data is accessed starting at the following even
address.
[Byte format]
RAM
LB A, off VAR
LB A, \VAR
xx00H
xxxxH
Current page
xxFFH
[Bit format]
RAM
SB off VAR.3
SB \VAR.3
xx00H
xxxxH
Current page
xxFFH
(3) Direct data addressing
Twobytesoftheinstructioncodespecifyanaddressinthecurrentphysicalsegmentofdata
memory (address 0 to 0FFFFH: 64KB). Word-format, byte-format or bit-format data at the
specified address is accessed.
The operand is described using a format that has a dir addressing descriptor. The dir
descriptor can be omitted, however in this case, if an address in a SFR page or FIXED page
is specified, the assembler may interpret direct data addressing as SFR page addressing
or FIXED page addressing.
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[Word format]
RAM
L
L
A, dir VAR
A, VAR
0000H
xxxxH
64KB
FFFFH
If an odd address is specified, word-format data is accessed starting at the following even
address.
[Byte format]
RAM
LB A, dir VAR
LB A, VAR
0000H
xxxxH
64KB
FFFFH
[Bit format]
RAM
SB dir VAR.3
SB VAR.3
0000H
xxxxH
64KB
FFFFH
(4) Pointing register indirect addressing
A. DP/X1 indirect addressing
[DP], [X1]
B. DP indirect addressing with post increment
C. DP indirect addressing with post decrement
[DP+]
[DP-]
D. DP/USP indirect addressing with 7-bit displacement
E. X1/X2 indirect addressing with 16-bit base
F. X1 indirect addressing with 8-bit register displacement
n7[DP], n7[USP]
D16[X1], D16[X2]
[X1+R0], [X1+A]
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A. DP/X1 indirect addressing
The contents of the pointing register specify an address in the current physical segment of
data memory (address 0 to 0FFFFH: 64KB). Word-format, byte-format or bit-format data
at the specified address is accessed.
2
[DP]:
[X1]:
DP indirect addressing
X1 indirect addressing
[Word format]
RAM
L
L
A, [DP]
A, [X1]
0000H
xxxxH
DP or X1
64KB
FFFFH
If an odd address is specified, word-format data is accessed starting at the following even
address.
[Byte format]
RAM
LB A, [DP]
LB A, [X1]
0000H
xxxxH
DP or X1
64KB
FFFFH
[Bit format]
RAM
SB [DP].3
RB [X1].3
0000H
xxxxH
DP or X1
64KB
FFFFH
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B. DP indirect addressing with post increment
The contents of the pointing register specify an address in the current physical segment of
data memory (address 0 to 0FFFFH: 64KB). Word-format, byte-format or bit-format data
at the specified address is accessed.
After accessing the target, the contents of the pointing register are incremented. For word-
format instructions, DP is incremented by two. For byte and bit instructions, DP is
incremented by one.
This addressing mode is used primarily to consecutively access an array of elements.
[DP+]:
DP indirect addressing with post increment
[Word format]
RAM
0000H
xxxxH
L
A, [DP+]
DP
64KB
Incremented by 2
after access
FFFFH
If an odd address is specified, word-format data is accessed starting at the following even
address.
[Byte format]
RAM
0000H
xxxxH
LB A, [DP+]
DP
64KB
Incremented by 1
after access
FFFFH
[Bit format]
RAM
0000H
xxxxH
SB [DP+].3
DP
64KB
Incremented by 1
after access
FFFFH
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C. DP indirect addressing with post decrement
The contents of the pointing register specify an address in the current physical segment of
datamemory(addresses0to0FFFFH:64KB). Word-format, byte-formatorbit-formatdata
at the specified address is accessed.
2
Afteraccessingthetarget, thecontentsofthepointingregisteraredecremented. Forword-
format instructions, DP is decremented by two. For byte and bit instructions, DP is
decremented by one.
[DP-]:
DP indirect addressing with post decrement
[Word format]
RAM
0000H
xxxxH
L
A, [DP-]
DP
64KB
Decremented by 2
after access
FFFFH
If an odd address is specified, word-format data is accessed starting at the following even
address.
[Byte format]
RAM
0000H
xxxxH
LB A, [DP-]
DP
64KB
Decremented by 1
after access
FFFFH
[Bit format]
RAM
0000H
xxxxH
SB [DP-].3
DP
64KB
Decremented by 1
after access
FFFFH
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D. DP/USP indirect addressing with 7-bit displacement
7 bits in the instruction code (bit 6 to bit 0) are used as a signed displacement (bit 6 is the
sign bit) from the pointing register contents (the base value) to specify an address in the
current physical data segment (address 0 to 0FFFFH: 64KB). The accessible range is
–64to+63fromthecontentsofthepointingregister. Word-format,byte-formatorbit-format
data at the specified address is accessed.
Numerical expression[DP]:
Numerical expression[USP]:
DP indirect addressing with 7-bit displacement
USP indirect addressing with 7-bit displacement
The numerical expression has a value in the range of –64 to +63.
DP and USP can be used as pointing registers.
[Word format]
RAM
L
L
A,12[DP]
0000H
xxxxH
A,12[USP]
64KB
DP or USP
FFFFH
If an odd address is specified, word-format data is accessed starting at the following even
address.
[Byte format]
RAM
LB A,12[DP]
0000H
xxxxH
LB A,12[USP]
64KB
DP or USP
FFFFH
[Bit format]
SB
RB
12[DP].3
RAM
0000H
12[USP].3
xxxxH
FFFFH
64KB
DP or USP
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E. X1/X2 indirect addressing with 16-bit base
The contents of an index register (X1 or X2) are added to a base of two bytes in the
instruction code (D16). The value that is generated specifies an address in the current
physical data segment (address 0 to 0FFFFH: 64KB). The addition operation to generate
the address is performed in word-format (16-bit) and since overflow is ignored, the
generated value is in the range from 0 to 0FFFFH. Word-format, byte-format or bit-format
data at the specified address is accessed.
2
Address expression[X1]: X1 indirect addressing with 16-bit base
Address expression[X2]: X2 indirect addressing with 16-bit base
The address expression has a value in the range of 0 to 0FFFFH. However, the assembler
allows values in the range of –8000H to +0FFFFH. This means that D16 can also be
regarded as a displacement, instead of a base address.
[Word format]
RAM
L
A,1234H[X1]
0000H
xxxxH
ST A,1234H[X2]
64KB
X1 or X2
FFFFH
If an odd address is specified, word-format data is accessed starting at the following even
address.
[Byte format]
RAM
LB
A,1234H[X1]
0000H
xxxxH
STB A,1234H[X2]
64KB
X1 or X2
FFFFH
[Bit format]
RAM
SB 1234H[X1].3
RB 1234H[X2].3
0000H
xxxxH
FFFFH
64KB
X1 or X2
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F. X1 indirect addressing with 8-bit register displacement
The contents of the low byte of the accumulator (AL) or local register 0 (R0) are added to
thepointingregistercontents(thebasevalue)togenerateavaluethatspecifiesanaddress
in the current physical data segment (address 0 to 0FFFFH: 64KB). The addition operation
to generate the address is performed in word-format (16-bit). At this time, the 8-bit
displacement obtained from the register is expanded unsigned. Since overflow resulting
from the addition is ignored, the generated value is in the range from 0 to 0FFFFH. Word-
format, byte-format or bit-format data at the specified address is accessed.
[X1+A]:
[X1+R0]:
X1 indirect addressing with 8-bit register displacement (AL)
X1 indirect addressing with 8-bit register displacement (R0)
[Word format]
L
L
A, [X1+A]
RAM
A, [X1+R0]
0000H
AL or R0
xxxxH
64KB
X1
FFFFH
If an odd address is specified, word-format data is accessed starting at the following even
address.
LB A, [X1+A]
RAM
LB A, [X1+R0]
0000H
AL or R0
xxxxH
64KB
X1
FFFFH
[Byte format]
RAM
SB [X1+A].3
RB [X1+R0].3
0000H
xxxxH
AL or R0
X1
64KB
FFFFH
[Bit format]
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(5) Special bit area addressing
A. FIXED page SBA area addressing
B. Current page SBA area addressing
sbafix Badr
sbaoff Badr
A. FIXED page SBA area addressing
2
This addressing mode specifies a bit address in the 512-bit SBA area (2C0H.0 to 2FFH.7)
located in a FIXED page. Bit format data at the specified address is accessed.
This addressing mode can be written by the following 4 instructions: SB, RB, JBS and JBR.
[Bit format]
SB sbafix 2C0H.0
RB sbafix 1600H
JBS sbafix VAR,LABEL
JBR sbafix 2EFH.7
SB 2C0H.0
RB 1600H
JBS VAR,LABEL
JBR 2EFH.3,LABEL
RAM
02C0H
02xxH
FIXED page SBA area
02FFH
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B. Current page SBA area addressing
Thisaddressingmodespecifiesabitaddressinthe512-bitSBAarea(xxC0H.0toxxFFH.7)
located in the current page. Bit format data at the specified address is accessed.
This addressing mode can be written by the following 4 instructions: SB, RB, JBS and JBR.
[Bit format]
SB sbaoff 4C0H.0
RB sbaoff 2E80H
JBS sbaoff VAR,LABEL
JBR sbaoff 0FFFFH.3,LABEL
SB 2C0H.0
RB 2E80H
JBS VAR,LABEL
JBR 0FFFFH.3,LABEL
RAM
xxC0H
xxxxH
Current page SBA area
xxFFH
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2.4.2 ROM Addressing
This addressing mode specifies addressing for program variables in the ROM space.
Available addressing formats include: immediate addressing, table data addressing and
program code addressing.
2
(1) Immediate addressing
Thisaddressingmodespecifiesaccessforimmediatedataincludedintheinstructioncode.
For word-format instructions, 2 bytes (N16) of the instruction code are accessed. For byte-
format instructions, 1 byte (N8) of the instruction code is accessed.
In the word-format, expressions have values in the range of 0 to 0FFFFH. In the byte-
format, expressions have values in the range of 0 to 0FFH. The assembler allows a range
of signed and unsigned expressions for immediate addressing. The word-format range is
from -8000H to +0FFFFH and the byte-format range is from -80H to +0FFH.
[Word format]
L
A, #1234H
MOV
X1, #WORD_ARRAY_BASE
[Byte format]
LB
A, #12H
MOV
X1, #BYTE_ARRAY_BASE
(2) Table data addressing
This addressing mode specifies access for 64KB in the table segment specified by TSR in
ROMmemoryspace. ThismodeisusedwiththeoperandsofLC, LCB, CMPCandCMPCB
instructions.
A. Direct table addressing
B. RAM addressing indirect table addressing
C. RAM addressing indirect addressing with 16-bit base
Tadr
[**]
T16[**]
A. Direct table addressing
Two bytes of the instruction code specify an address (address 0 to 0FFFFH: 64KB) in the
table segment specified by TSR. Word-format or byte-format data at the specified address
is accessed.
This addressing mode can be written by the following 4 instructions: LC, LCB, CMP and
CMPCB.
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[Word format]
LC
CMPC
A, VAR
A, VAR
[Byte format]
LCB
A, VAR
CMPCB A, VAR
B. RAM addressing indirect table addressing
This indirect addressing mode uses the word-format data specified by RAM addressing as
apointertothetablesegmentspecifiedbyTSR. Tablememorycanbeaccessedbyplacing
a pointer to table memory in a register or in data memory.
This addressing mode can be written by the following 4 instructions: LC, LCB, CMPC and
CMPCB.
[Word format]
LC
A, [A]
CMPC
A, [1234[X1]]
[Byte format]
LCB
A, [ER0]
CMPCB A, [VAR]
C. RAM addressing indirect addressing with 16-bit base
The contents of word-format data specified by RAM addressing are added to a base of two
bytes of the instruction code (D16). The value that is generated specifies an address in the
table segment specified by TSR (address 0 to 0FFFFH: 64KB). The addition operation to
generate the address is performed in word-format (16-bit) and since overflow is ignored,
the generated value is in the range from 0 to 0FFFFH. Word-format or byte-format data at
the specified address is accessed.
This addressing mode can be written by the following 4 instructions: LC, LCB, CMPC and
CMPCB.
[Word format]
LC
A, 2000H[A]
CMPC
A, 2000H[1234[X1]]
[Byte format]
LCB
A, 2000H[ER0]
CMPCB A, 2000H[VAR]
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(3) Program code addressing
This mode specifies access for the current program code in ROM space.
Program code addressing is used with operands for branch instructions.
2
A. NEAR code addressing
B. FAR code addressing
C. Relative code addressing
D. ACAL code addressing
E. VCAL code addressing
Cadr
Fadr
radr
Cadr11
Vadr
[**]
F. RAM addressing indirect code addressing
A. NEAR code addressing
Two bytes of the instruction code specify an address (address 0 to 0FFFFH: 64KB) in the
current code segment.
This addressing mode can be written by two instructions, J and CAL.
[Usage example]
J
CAL
3000H
LABEL
B. FAR code addressing
Three bytes of the instruction code specify an address (0:0 to F:0FFFFH: 1MB) in the
program memory space.
This addressing mode can be written by two instructions, FJ and FCAL.
[Usage example]
FJ
1:3000H
FCAL
FARLABEL
C. Relative code addressing
The sign extended value of 8 bits or 7 bits of the instruction code is added to the base value
of the current program counter (PC). The generated value specifies an address in the
current code segment (0 to 0FFFFH: 64KB). The addition operation to generate the
address is performed in word-format (16-bit) and since overflow is ignored, the generated
value is in the range from 0 to 0FFFFH. This addressing mode can be written by an SJ
instruction, conditional branch instructions, etc.
[Usage example]
SJ
LABEL
DJNZ
JC
R0, LABEL
LT, LABEL
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Chapter 2 CPU Architecture
D. ACAL code addressing
11 bits of the instruction code specify the ACAL area (1000H to 17FFH: 2KB) in the current
code segment.
This addressing mode can be written only by an ACAL instruction.
[Usage example]
ACAL
ACAL
1000H
ACALLABEL
E. VCAL code addressing
4 bits of the instruction code specify the vector table address for a VCAL instruction (word-
formatdata). Thevectortableislocatedatevenaddressesintherangeof004AHto0069H.
This addressing mode can be written only by a VCAL instruction.
[Usage example]
VCAL
VCAL
VCAL
4AH
0:4AH
VECTOR
F. RAM addressing indirect code addressing
This indirect addressing mode uses the word-format data specified by RAM addressing as
a pointer to the code segment. Indirect jumps and calls can be performed by placing a
pointer to code memory in a register or in data memory.
This addressing mode can be written by two instructions, J and CAL.
[Usage example]
J
[A]
CAL
[1234[X1]]
(4) ROM window addressing
This addressing mode uses RAM addressing to access table data in the ROM space. In
this mode, data in the table segment specified by TSR is read through a data segment
window specified and opened by the program.
The ROM window area allows addressing of the data memory, however, results cannot be
guaranteed if an instruction that writes to the ROM window area is executed.
2-46
Chapter 3
3
CPU Control Functions
MSM66577 Family User's Manual
Chapter 3 CPU Control Functions
3. CPU Control Functions
3.1 Overview
The MSM66577 family has two CPU control functions, a standby function and a reset
function.
3
The standby function consists of the three functions of HALT mode, HOLD mode, and
STOPmode. Thesefunctionscanbeusedtoreducetheamountofpowerconsumedduring
operation. The HOLD mode has a bus release function, and the STOP mode has a quick
activating STOP mode in which the main clock continues oscillation.
The reset function is activated by the RES signal input, BRK (break) instruction execution,
or execution of an invalid instruction (opcode trap). In addition, reset is also activated by
overflow of the watchdog timer. Reset can minimize the effect of program errors on the
system.
3.2 Standby Functions
The standby functions have three types:
• HALT mode: activated by software, clock supply to CPU is terminated
• HOLD mode: activated by hardware, clock supply to CPU is terminated
• STOP mode: activatedbysoftware,clocksupplytoCPUandinternalperipheralmodules
is terminated
Corresponding to each of dual clocks, each of these functions has a high-speed and low-
speed mode.
Figure 3-1 shows a transition diagram of the CPU operating states. Table 3-1 lists a
summary of the standby modes.
High-speed
HOLD mode
HOLD input = 1
(when HOLD is enabled)
HOLD input = 0
High-speed main
clock (OSC) operation
Initial state when RESET
High-speed STOP mode
(Terminate main clock oscillation: OSCS = 1)
(Operate main clock oscillation: OSCS = 0)
STP = 1
HLT = 1
High-speed
HALT mode
Interrupt
generated
Interrupt
generated
Subclock
(XT) selection
Main clock
(OSC) selection
HLT = 1
Low-speed
HALT mode
Low-speed subclock (XT) operation
(Terminate main clock oscillation: OSCS = 1)
(Operate main clock oscillation: OSCS = 0)
Low-speed STOP mode
(Terminate main clock oscillation: OSCS = 1)
(Operate main clock oscillation: OSCS = 0)
STP = 1
Interrupt
generated
Interrupt
generated
HOLD input = 1
(When HOLD is enabled)
(Notes)
• Oscillation operation or termination is for the main clock (OSC) only.
The subclock (XT) is not terminated.
Low-speed
• The initial value of OSCS (bit 3 of SBYCON) is "1."
HOLD mode
HOLD input = 0
Figure 3-1 Transition Diagram of CPU Operating States
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MSM66577 Family User's Manual
Chapter 3 CPU Control Functions
Table 3-1 Standby Mode Summary
Standby mode
Set conditions
HALT mode
Bit 1 (HLT) of
HOLD mode
STOP mode *1
Bit 5 (HOLD) of
Bit 2 (FLT) of
Bit 2 (FLT) of
SBYCON is set to
"1"
PRPHCON is set to SBYCON is set to
"1" and the HOLD "1" and bit 0 (STP)
SBYCON is reset to
"0" and bit 0 (STP)
input pin has a high- of SBYCON is set to of SBYCON is set to
level input
"1"
"1"
Interrupt
HOLD pin low-level Interrupt
Interrupt
RES pin input
RES pin input
WDT
input
RES pin input
Release conditions
RES pin input
No change
P0 to P2, P4
No change
High impedance
Pull-up
No change
Pull-up
(primary function)
P0 to P2, P4
Pull-up
Pull-up *2
(secondary function)
P3_0 (primary function) No change
No change
Low level
High impedance
High impedance
No change
Low level
P3_0
Low level
(secondary function)
P3_1 (primary function) No change
No change
Pull-up *2
High impedance
High impedance
No change
High level
P3_1
High level
No change
Pull-up
(secondary function)
P3_2, P3_3
No change
Pull-up *2
High impedance
High impedance
No change
Pull-up
(primary function)
P3_2, P3_3
(secondary function)
P5 to P11
No change
No change
No change
No change
Operate
High impedance
High impedance
Terminate
No change
No change
P14, P15
Time base counter (TBC) Operate
Capture/compare timer Operate
Operate
Terminate
8/16-bit timers
(including WDT)
SIO1, SIO6
Operate
Operate
Terminate
(terminate WDT)
Operate
Operate
Operate
Operate
Operate
Terminate
Operate
Real-time counter
A/D converter
PWM
Operate
Operate
Terminate
Terminate
Operate
*1 The condition for setting the STOP mode is that the stop code acceptor (STPACP)
has already been set to "1".
*2 During the HOLD mode, if P0 to P4 are to be used as bus ports (output setting of
secondary function), the bus will be released.
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MSM66577 Family User's Manual
Chapter 3 CPU Control Functions
3.2.1 Standby Function Registers
Table 3-2 lists a summary of the SFRs for standby function control.
Table 3-2 Summary of SFRs for Standby Function Control
Address
[H]
Symbol
(byte)
Symbol
(word)
—
8/16
Initial
Reference
page
3-3
Name
R/W
Operation value [H]
3
000E
000F
Stop code acceptor
STPACP
SBYCON
W
8
8
8
"0"
08
Standby control register
—
R/W
R/W
3-4
0015I Peripheral control register PRPHCON
—
8C
15-2
[Notes]
1. Addresses are not consecutive in some places.
2. A star (P) in the address column indicates a missing bit.
3. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
3.2.2 Description of Standby Function Registers
(1) Stop code acceptor (STPACP)
The stop code acceptor (STPACP) is configured from 8 bits and is an acceptor used to set
the STOP mode.
STPACPissetto"1"whentheprogramwritesn5HandnAH(n=0toF)consecutively. After
STPACP is set to "1", setting bit 0 (STP) of the standby control register (SBYCON) to "1"
will change the mode to the STOP mode. At the same time the mode changes to the STOP
mode, STPACP is reset to "0".
STPACP is write-only.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), STPACP is reset to "0".
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MSM66577 Family User's Manual
Chapter 3 CPU Control Functions
(2) Standby control register (SBYCON)
The standby control register (SBYCON) is an 8-bit register that sets the standby mode and
the CPU operating clock (CPUCLK).
The program can read from and write to SBYCON.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), SBYCON is 08H.
Figure 3-2 shows the configuration of SBYCON.
[Description of each bit]
• STP (bit 0)
Setting the stop code acceptor (STPACP) to "1", and then setting STP to "1" will change
the mode to the STOP mode. When an interrupt is generated or the RES input causes
a reset, STP is reset to "0" and the STOP mode is released.
• HLT (bit 1)
Setting HLT to "1" changes the mode to the HALT mode. When an interrupt is generated,
the RES input causes a reset, or overflow of the watchdog timer causes a reset, HLT is
reset to "0" and the HALT mode is released.
• FLT (bit 2)
Setting FLT to "1" will cause the output ports (all pins set to output mode) to go to a high
impedance state when the STOP mode is entered.
Attheinputports, acircuitoperatestopreventcurrentflowbetweenthepowersupplyand
GND, eveniftheinputsareleftunconnected. Therefore, itisnotnecessarytofixtheinput
pin levels during the STOP mode. However, if the following pins are used as inputs
(regardless of whether they are primary or secondary functions), the circuit to prevent
current flow will not operate. Thus, to prevent undefined input states, use either pull-up
or pull-down resistors (to fix the input levels) during the STOP mode.
• P6_0 to P6_3, P9_0 to P9_3: External interrupt pins (EXINT0 to EXINT7)
Usingtheabovepinsassecondaryfunctioninputs,eveniftheSTOPmodeisenteredwith
FLT set ("1"), the STOP mode can be released by an external interrupt input. For details,
refer to Section 3.2.4, "Operation of Each Standby Mode," (3) STOP Mode.
• OSCS (bit 3)
During the STOP mode and when the subclock (XTCLK) has been selected as the CPU
operating clock (CPUCLK), OSCS specifies whether to terminate or continue oscillation
of the main clock (OSCCLK).
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MSM66577 Family User's Manual
Chapter 3 CPU Control Functions
• OST0, OST1 (bits 4 and 5)
InthecaseswhenaninterruptcausestheSTOPmodetobereleased,andwhentheclock
has been changed from the subclock (XTCLK) to the main clock (OSCCLK), OST0 and
OST1 specify the oscillation stabilization time from the oscillation start of the main clock
(OSCCLK) until clock supply to the CPU. During the STOP mode, even if oscillation of
the main clock (OSCCLK) is not terminated, the settings of these bits are valid.
3
[Note]
Do not set OST0 or OST1 to "1", in the case of changing to the operation mode in which
oscillation of the main clock (OSCCLK) is terminated.
For the Flash ROM version, set the oscillation stabilization time of 50 µs or more when
the STOP mode (only when oscillation of the main clock is terminated) is released.
• CLK0, CLK1 (bits 6 and 7)
CLK0andCLK1specifytheclocktobeusedastheCPUoperatingclock(CPUCLK). With
considerationoftheoperatingspeedrequirementsofproductapplications,anappropriate
speed for the internal CPU clock that runs the microcontroller is selected to reduce power
consumption.
7
6
5
4
3
2
1
0
Address:000F [H]
R/W access:R/W
SBYCON CLK1 CLK0 OST1 OST0 OSCS FLT HLT STP
at reset
0
0
0
0
1
0
0
0
0
1
CPU operating state
STOP mode
0
1
CPU operating state
HALT mode
0
1
During STOP mode, output does not change
During STOP mode, high impedance output
0
1
Main clock (OSC) oscillation
Terminate main clock (OSC) oscillation
OST
Main clock oscillation
1
0
0
1
1
0
0
1
0
1
stabilization time (No. of clocks)
32768
16384
8192
0
CLK
CPU operating clock
(CPUCLK)
1
0
0
1
1
0
0
1
0
1
OSCCLK
1/2 OSCCLK
1/4 OSCCLK
XTCLK
Figure 3-2 SBYCON Configuration
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Chapter 3 CPU Control Functions
3.2.3 Examples of Standby Function Register Settings
• HALT mode setting
(1) Standby control register (SBYCON)
Setting bit 1 (HLT) to "1" changes the mode to the HALT mode.
• HOLD mode setting
(1) Port 9 mode register (P9IO)
If HLDACK (HOLD mode transfer output pin) is to be used, set bit 7 (P9IO7) to "1" to
configure that port as an output.
(2) Port 9 secondary function control register (P9SF)
If HLDACK (HOLD mode transfer output pin) is to be used, set bit 7 (P9SF7) to "1" to
configure that port as a secondary function output.
(3) Peripheral control register (PRPHCON)
Setbit5(HOLD)to"1"toenabletheHOLDpininput. ThemodechangestotheHOLDmode
when an external device inputs a high level to the HOLD pin. After the transfer to the HOLD
mode is complete, the HLDACK output is set to "1" as an acknowledge signal.
• STOP mode setting
(1) Stop code acceptor (STPACP)
Write n5H, nAH (n = 0 to F) consecutively.
(2) Standby control register (SBYCON)
If output ports are to be high impedance during the STOP mode, set bit 2 (FLT) to "1". If
oscillationofthemainclock(OSCCLK)isnottobeterminatedduringtheSTOPmode, reset
bit 3 (OSCS) to "0". To terminate oscillation of the main clock (OSCCLK), set bit 3 (OSCS)
to "1" and specify with bits 4 and 5 (OST0 and OST1) the oscillation stabilization time after
the main clock resumes. Setting bit 0 (STP) to "1" changes the mode to the STOP mode.
3.2.4 Operation of Each Standby Mode
(1) HALT mode
Setting bit 1 (HLT) of the standby control register (SBYCON) to "1" changes the mode to
the HALT mode.
In the HALT mode, the clock (CPUCLK) supply to the CPU is terminated, but the clock
(CPUCLK) is supplied to internal peripheral modules (TBC, WDT, general-purpose 8/16-
bit timers, serial ports, etc.) so their operation continues. Because the CPU is halted,
instructions are not executed. Instruction execution stops at the beginning of the next
instruction (following the instruction that set bit 1 (HLT) of SBYCON to "1").
HALT mode is released when any of the following occur: an interrupt request, reset by the
RES pin input, or reset by overflow of the watchdog timer.
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Chapter 3 CPU Control Functions
When HALT mode is released due to an interrupt request, if the interrupt is non-maskable,
the HALT mode is released unconditionally, and the CPU processes the non-maskable
interrupt. In the case of a maskable interrupt, the interrupt is released when both the
interruptrequestflag(IRQbit)andtheinterruptenableflag(IEbit)havebeensetto"1". After
the HALT mode is released, if the master interrupt enable flag (MIE in PSW) has been set
to "1", processing of the requested maskable interrupt is performed. If the master interrupt
enableflag(MIEinPSW)hasbeenresetto"0",thenextinstruction(followingtheinstruction
that set the HALT mode (that set bit 1 (HLT) of SBYCON to "1") is executed.
3
If the HALT mode is released by reset due to the RES pin input or overflow of the watchdog
timer, the CPU will perform the reset processing.
(2) HOLD mode
When a high level is input to the HOLD pin after bit 5 (HOLD) of the peripheral control
register (PRPHCON) is set to "1", the mode will change to the HOLD mode after the
completion of the current instruction execution. Figure 3-3 shows the HOLD mode timing
diagram.
In the HOLD mode, the clock (CPUCLK) supply to the CPU is terminated, but the clock
(CPUCLK) is supplied to internal peripheral modules (TBC, general-purpose 8/16-bit
timers, serial ports, etc.) so their operation continues. However, operation of the watchdog
timer (WDT) is terminated. Because the CPU is halted, instructions are not executed.
Instruction execution stops at the beginning of the next instruction (following the instruction
that changed the mode to the HOLD mode).
If bus port functions (P0 to P4 set as secondary function outputs) are being used, the bus
will be released during the HOLD mode.
If an interrupt occurs during the HOLD mode, because instructions are not being executed,
interrupt processing will be suspended until the HOLD mode is released.
The HOLD mode is released when either a low level is input to the HOLD pin or the RES
pin input causes a reset.
If a low level is input to the HOLD pin, instruction execution will resume starting from the
nextinstruction(followingtheinstructionthatchangedthemodetotheHOLDmode). When
an interrupt request occurs during the HOLD mode, if the interrupt is non-maskable, the
non-maskable interrupt will be processed immediately after the HOLD mode is released.
In the case of a maskable interrupt, if the corresponding interrupt enable flag (IE bit) and
the master interrupt enable flag (MIE in PSW) have been set to "1", the maskable interrupt
will be processed immediately after the HOLD mode is released. If multiple interrupt
requests are generated, they are processed in order of priority.
If the HOLD mode is released by reset due to the RES pin input, the CPU will perform the
reset processing.
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MSM66577 Family User's Manual
Chapter 3 CPU Control Functions
CPUCLK
CPUCLK
(CPU internal clock)
M1S1
(Signal that indicates
beginning of instruction)
HOLD input
HLDACK
Execution of
HOLD mode
Execution of
prior instruction
next instruction
Figure 3-3 HOLD Mode Timing Diagram
(3) STOP mode
Setting the stop code acceptor (STPACP) to "1" by consecutively writing n5H, nAH (where
n = 0 to F) and then setting bit 0 (STP) of the standby control register (SBYCON) to "1" will
change the mode to the STOP mode.
IntheSTOPmode, theCPUandinternalperipheralmodules(TBC, WDT, general-purpose
8/16-bit timers, serial ports, etc.) are halted. However, when dual clocks are being used,
the real-time counter (RTC) will operate as usual.
Because the clock supply to the CPU is halted, instructions are not executed. Instruction
execution stops at the beginning of the next instruction (following the instruction that set bit
0 (STP) of SBYCON to "1").
The STOP mode is released when either an interrupt occurs or input to the RES pin causes
a reset.
When the STOP mode is released due to an interrupt request, if the interrupt is non-
maskable, the STOP mode is released unconditionally, and the CPU processes the non-
maskable interrupt.
Inthecaseofamaskableinterrupt, theinterruptisreleasediftheinterruptrequestflag(IRQ
bit) and the interrupt enable flag (IE bit) have been set to "1".
During the STOP mode, the following factors generate maskable interrupt requests.
• Interrupt caused by input of the valid edge to an external interrupt pin (EXINT0 to EXINT5)
• Interrupt caused by real-time counter output (when dual clocks are used)
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MSM66577 Family User's Manual
Chapter 3 CPU Control Functions
After the STOP mode is released, if the master interrupt enable flag (MIE in PSW) has been
set to "1", processing of the requested maskable interrupt is performed.
If the master interrupt enable flag (MIE in PSW) has been reset to "0", the next instruction
(following the instruction that set the STOP mode (that set bit 0 (STP) of SBYCON to "1")
is executed. However, if the STOP mode has been set during the processing of a non-
maskable interrupt routine, the STOP mode can be released by an interrupt request. After
being released, the next instruction in the non-maskable interrupt routine (following the
instruction that changed the mode to the STOP mode) will be executed. If interrupt priority
is set (bit 7 (MIPF) of EXI2CON set to "1") and the STOP mode is set during a high priority
interrupt routine, a low priority interrupt request can release the STOP mode. However,
after release the low priority interrupt is suspended and the next instruction in the high
priority interrupt routine will be executed.
3
If an interrupt request from the high-speed STOP mode (main clock oscillation terminated)
causes the STOP mode to be released, operation will continue after waiting for the
oscillation stabilization time of the main clock (OSCCLK) as set by SBYCON. The STOP
mode can also be entered while the main clock continues to oscillate (quick activating
STOP mode). In this case, when returning from the STOP mode, activation is possible
without waiting for the oscillation stabilization time of the main clock.
Figure 3-4 shows the STOP mode timing diagram.
If the STOP mode is released by reset due to the RES pin input, the CPU will perform the
reset processing. If the RES pin input is to be used to release the STOP mode with main
clock oscillation halted, apply a low level to the RES pin until the main clock oscillation
stabilizes.
For the Flash ROM version products, apply a low level to the RES pin for at least 50 ms.
STOP mode
Main clock
(OSCCLK)
M1S1
(Signal that indicates
beginning of instruction)
SBYCON.STP
Interrupt request
(NMI, IRQ and IE)
Instruction
execution
Dummy cycle
Oscillation
halted
*Oscillation
stabilization time
Dummy cycle
Instruction
execution
Timer operation
Timer halted
Port floating
(when FLT = "1")
Timer operation
Operating state
Port output mode
Port output mode
* Oscillation stabilization time is the time until the main clock starts oscillating, plus the time of
the number of clocks set by OST0 and OST1.
Figure 3-4 STOP Mode Timing Diagram
(When released by an interrupt)
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Chapter 3 CPU Control Functions
3.3 Reset Function
The MSM66577 family is reset by the following four factors.
• Low-level input to the RES input pin
• Execution of a break (BRK) instruction
• Overflow of the watchdog timer (WDT)
• Opcode trap (OPTRP) due to execution of invalid instruction
Resets caused to the above four factors are processed in the same way except that the
address of the vector address to be loaded in the program counter is different.
Table 3-3 lists the vector addresses for each reset factor.
Table 3-3 Vector Address for Each Reset Factor
Reset factor
Vector address [H]
Reset caused by low level input to the RES input pin
Reset caused by execution of BRK instruction
Reset caused by overflow of watchdog timer
Reset caused by opcode trap
0000
0002
0004
0006
During the reset processing, arithmetic registers, control registers, mode registers, etc. are
initialized, and the contents of the address pointed to by the vector address is loaded into
the program counter.
For the initial values of different registers, refer to Chapter 21, "Special Function Registers
(SFRs)".
Resethaspriorityoverallotherprocessing(interruptprocessingandinstructionexecution).
Since all processing is aborted, register and RAM contents at that time cannot be
guaranteed.
[Notes]
1. If the RES pin input is to be used to for reset, apply a low level at the RES pin until the
main clock oscillation stabilizes.
2. Because the internal state and output state at power-on reset are undefined, be sure to
reset the CPU after power is turned on.
3. When applying power to, or disconnecting power from, the V and V
pins, apply or
DD
REF
disconnect the power at the same time for these pins.
The Flash ROM version is reset by the supply voltage sense reset function when the power
supply voltage is dropped, in the same way that the MSM66577 family is reset by low level
input to the RES input pin. The supply voltage sense reset function is implemented when
the supply voltage for the version operating in the range of 4.5 to 5.5 V is 3.0 V or less and
the supply voltage for the version operating in the range of 3.0 to 3.6 V is 1.5 V or less.
The reset function is not implemented during the STOP mode (only when oscillation clock
is terminated).
Figure 3-5 shows an example of reset pin connection. Table 3-4 lists that status of I/O ports
during reset.
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MSM66577 Family User's Manual
Chapter 3 CPU Control Functions
VDD
VDD
Rpull
=
50 kW (VDD = 5 V)
Di
C
RES
SW
R
Reset processing circuit
3
Example of external circuit
for manual reset
Internal
Figure 3-5 Reset Pin Connection Example
Table 3-4 I/O Port Status During Reset
Low level EA pin
High level EA pin
Name
Status
Other ports
P3_0, P3_1
P3_0, P3_1
Pulled-up
High impedance
High impedance
[Note]
If the EA pin is at a low level, after reset P0, P1, P2, P3_0, P3_1 and P4 automatically change
to secondary function output states (bus port function).
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3-12
Chapter 4
4
Memory Control Functions
MSM66577 Family User's Manual
Chapter 4 Memory Control Functions
4. Memory Control Functions
4.1 Overview
There are two independent memory spaces, the program memory space and the data
memory space. The following three functions make the memory functions easier to use.
• ROM Window Function : This function enables various instructions that have been
stored in the data memory space to also be used by the
program in the program memory space.
4
• READY Function :
If both memory spaces are to be used as external memory,
this function allows the program to insert wait cycles into the
external memory timing, according to the access times of the
external memory.
• WAIT Function :
This function enables an external device to control the
insertion of wait cycles.
4.2 Memory Control Function Registers
Table 4-1 lists a summary of the SFRs for memory control functions.
Table 4-1 Summary of SFRs for Memory Control Functions
Address
[H]
Symbol
(byte)
Symbol
(word)
—
8/16
Initial
Reference
page
4-2
Name
R/W
Operation value [H]
000B
ROM Window Register
ROMWIN
R/W
R/W
R/W
R/W
8
8
8
8
Undefined
8B
000CI ROM Ready Control Register ROMRDY
—
4-4
000DI RAM Ready Control Register
0015I Peripheral Control Register
RAMRDY
—
FF
4-5
PRPHCON
—
8C
15-2
[Notes]
1. Addresses are not consecutive in some places.
2. A star (I) in the address column indicates a missing bit.
3. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
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Chapter 4 Memory Control Functions
4.3 ROM Window Function
The ROM window function reads the contents of the program memory space specified by
the ROM window register (ROMWIN), located in the SFR area, by using the same address
in the data memory space as a window.
In other words, when the ROM window function is enabled and an instruction that accesses
(reads) the data memory space is executed, instead of accessing (reading) data in the data
memory space, data will be accessed (read) at the same addresses in the segment that is
specified by TSR in the program memory space.
Compared to the number of instruction cycles to be required to access normal data
memory,accessingtheROMwindowoncerequiresadditional3cyclesforabyteinstruction
and additional 6 cycles for a word instruction.
[Note]
If the ROM window function is enabled and a write instruction is executed, that result will
not be guaranteed. However, in this case additional cycles will not be added.
• ROM Window Register (ROMWIN)
The ROM window register (ROMWIN) is an 8-bit register. The lower 4 bits indicate the
start address of the ROM window and the upper 4 bits indicate the end address of the
ROM window. (Bits 4 and 5 of the upper 4 bits must be written as "1"s.) When 64KB of
the program memory space is represented in hexadecimal number (HEX), each of above
4-bit registers specifies the upper 1 digit of 4 digits. If the value of the lower 4 bits is all
zeros, the ROM window function will not operate.
Figure 4-1 shows the configuration of ROMWIN.
7
6
5
4
3
2
1
0
Address: 000B [H]
ROMWIN
"1"
"1"
R/W access: R/W
(W is only performed once after reset)
At reset
(undefined)
These 4 bits specify the start
address of the ROM window.
(The upper 1 digit of 4 digits when
the 64KB memory space is represented
in hexadecimal format (HEX).)
These 4 bits specify the end
address of the ROM window.
(The upper 1 digit of 4 digits when
the 64KB memory space is represented
in hexadecimal format (HEX).)
Bits 4 and 5 must be set to "1".
Figure 4-1 ROMWIN Configuration
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MSM66577 Family User's Manual
Chapter 4 Memory Control Functions
If internal RAM is located in the data memory area specified as the ROM window, the data
memory’s internal RAM will have priority.
The data memory space specified as the ROM window area cannot be used as normal
external data memory.
The ROM window start address is 1200H or above for segment 0, and 1000H or above for
segments 1 to 15. The end address can be selected among the four end addresses listed
in Table 4-2.
4
Table 4-2 End Address List
ROMWIN
End address [H]
Bit 7 Bit 6
3FFF
7FFF
BFFF
FFFF
0
0
1
1
0
1
0
1
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer,opcodetrap),ROMWINisundefinedandtheROMwindowfunctiondoesnotoperate.
ROMWIN can be written to once after reset. Additional writing attempts will be ignored.
Therefore, aftertheROMwindowfunctionhasbeensetitcanonlybemodifiedafterareset.
ROMWIN can be read as many times as desired.
[Note]
The relative sizes of the start address "X" and the end address "Y" written to ROMWIN
are not evaluated by the hardware. Therefore, be sure that X ≤ Y within the program.
4-3
MSM66577 Family User's Manual
Chapter 4 Memory Control Functions
4.4 READY Function
So that memory and general-purpose ICs with slow access speeds can be connected
externally, wait cycles can be specified to be inserted during external memory accesses.
There are two registers that specify the number of wait cycles, the ROM ready control
register (ROMRDY) and the RAM ready control register (RAMRDY).
ROMRDY specifies wait cycles when the external ROM mode is used for the program
memory space. By setting the IRORDY flag to "1", the same wait cycles specified for the
external ROM are also applied to the internal ROM.
RAMRDY specifies wait cycles when the data memory space is extended externally.
Memory can be divided into the two areas of address 0000H to 7FFFH and 8000H to
FFFFH, and wait cycles can be specified for each area.
Table 4-3 lists the number of wait cycles that can be specified for RAMRDY and ROMRDY.
Table 4-3 Wait Cycles
Control register
ROMRDY
Number of wait cycles to be inserted
0 to 3
0 to 7
RAMRDY
4.4.1 ROM Ready Control Register (ROMRDY)
The ROM ready control register (ROMRDY) consists of two bits. ROMRDY specifies the
number of wait cycles with bits 0 and 1 (ORDY0 and ORDY1) and insertion or no insertion
of READY to the internal ROM with bit 2 (IRORDY).
ROMRDY can be read from and written to by the program. However, write operations are
invalid for bits 3 and 7. Also, if writing to bits 4 to 6, they must be written as "0". When read,
bits 3 and 7 are always "1" and bits 4 to 6 are "0".
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), ROMRDY becomes 8BH and the largest number of wait cycles are set.
Therefore, three wait cycles will be added and inserted when external program memory is
accessed.
Figure 4-2 shows the configuration of ROMRDY.
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MSM66577 Family User's Manual
Chapter 4 Memory Control Functions
7
6
"0"
0
5
"0"
0
4
"0"
0
3
2
IRORDY
0
1
0
Address: 000C [H]
R/W access: R/W
—
—
ORDY1ORDY0
ROMRDY
At reset
1
1
1
1
Number of wait cycles to be
added and inserted during an
ORDY
external program memory access
1
0
0
1
1
0
0
1
0
1
0 cycles
1 cycle
2 cycles
3 cycles
4
IRORDY
Internal ROM READY
Not inserted
0
1
Inserted
"—" indicates a nonexistent bit.
When read, its value will be "1".
"0" indicates that the value "0" must always
be written to this bit. When read, its value
will be "0".
1 cycle is 1 CPUCLK.
Figure 4-2 ROMRDY Configuration
4.4.2 RAM Ready Control Register (RAMRDY)
The RAM ready control register (RAMRDY) consists of 6 bits. Bits 0 to 2 (ARDY00 to
ARDY02) of RAMRDY specify the number of wait cycles for the external RAM area from
0000H to 7FFFH. Bits 4 to 6 (ARDY10 to ARDY12) specify the number of wait cycles for
the external RAM area from 8000H to FFFFH. The number of wait cycles is uniform for all
segments and settings are divided into the two areas of 0000H to 7FFFH (segment 0 is
1200H to 7FFFH) and 8000H to FFFFH.
RAMRDY can be read from and written to by the program. However, write operations are
invalid for bits 3 and 7. When read, bits 3 and 7 are always "1".
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), RAMRDY becomes FFH and the largest number of wait cycles are set.
Therefore, seven wait cycles will be added and inserted when external data memory is
accessed.
Figure 4-3 shows the configuration of RAMRDY.
[Note]
In contrast to an internal data memory access, when external data memory is accessed,
2 or 3 cycles are automatically inserted for each 1 byte access. RAMRDY specifies the
number of cycles to be inserted in addition to the 2 or 3 cycles that are inserted
automatically inserted.
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MSM66577 Family User's Manual
Chapter 4 Memory Control Functions
7
6
5
4
3
2
1
0
Address: 000D [H]
R/W access: R/W
—
—
ARDY12 ARDY11ARDY10
ARDY02 ARDY01ARDY00
RAMRDY
At reset
1
1
1
1
1
1
1
1
Number of wait cycles to be added
and inserted when accessing external
data memory 0000H to 7FFFH
ARDY0
2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 cycles
1 cycle
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
Number of wait cycles to be added
and inserted when accessing external
data memory 8000H to FFFFH
ARDY1
2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 cycles
1 cycle
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
"—" indicates a nonexistent bit.
When read, its value will be "1".
1 cycle is 1 CPUCLK.
Figure 4-3 RAMRDY Configuration
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MSM66577 Family User's Manual
Chapter 4 Memory Control Functions
4.5 WAIT Function
When accessing the external data memory area, in addition to the READY function that
inserts wait cycles from the CPU, there is a WAIT function that can insert wait cycles via
control from the external device. (This is applicable only to the data memory space.)
At the falling edge of CPUCLK shown in Figure 4-4 and 4-5, the high level of pin P11_0/
WAIT is sampled and wait cycles are inserted into WR and RD strobe signals.
As shown in the sample timing of Figure 4-4, the WAIT function is released 1 tfw after pin
P11_0/WAIT is sample twice consecutively at a low level.
4
If the WAIT function is used with the READY function, the wait time that is largest will be
valid.
In order to use the WAIT function, set bit 6 (WAIT) of the peripheral control register
(PRPHCON) to "1". (Refer to Chapter 15, "Peripheral Functions".)
tøw
CPUCLK
P11_0/WAIT
No WAIT
P3_2/RD
A0 to A19
(P1_0 to P1_7,
P2_0 to P2_3,
P4_0 to P4_7)
RAP 0 to 19
D0 to D7
(P0_0 to P0_7)
Din 0 to 7
Figure 4-4 Sample Timing When Using the WAIT Function
(Separate Bus Type)
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MSM66577 Family User's Manual
Chapter 4 Memory Control Functions
tøw
CPUCLK
P11_0/WAIT
P3_0/ALE
No WAIT
P3_2/RD
AD0 to AD7
(P0_0 to P0_7)
RAP 0 to 7
Din 0 to 7
A8 to A15
(P1_0 to P1_7,
P2_0 to P2_3)
RAP 8 to 19
Figure 4-5 Sample Timing When Using the WAIT Function
(Multiplexed Bus Type)
4-8
Chapter 5
5
Port Functions
MSM66577 Family User's Manual
Chapter 5 Port Functions
5. Port Functions
5.1 Overview
The MSM66577 family has 14 sets of I/O port from P0 to P11, P14 and P15 (74 ports) and
1 set of input-only port at P12 (8 ports).
Each individual bit of all the I/O ports can be specified as input or output. All I/O ports have
internal pull-up resistors that can be programmed for each individual bit.
The 3 sets of P0, P3 and P11 (16 ports) are capable of providing the sink current of 10 mA
for driving LEDs.
5
If configured as inputs, the pins are high impedance inputs. If configured as outputs, they
are push-pull outputs. In addition to the port function, some ports are assigned an internal
function (secondary function).
Table 5-1 shows Port Function Summary.
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-1 Port Function Summary
Port name
Port 0*
Port 1
Pin
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_3
P3_0
Type Number I/O
Secondary function
A
B
B
B
B
C
C
B
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
F
8
8
4
1
1
1
1
8
2
1
1
4
1
1
1
1
2
1
1
1
1
1
2
4
1
1
1
1
1
1
1
1
8
1
1
1
2
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
External memory access address data bus AD0 to AD7 (I/O)
External memory access A8 to A15 (output)
External memory access A16 to A19 (output)
External memory access ALE (output)
Port 2
Port 3*
P3_1
External program memory access PSEN (output)
External data memory access RD (output)
External data memory access WR (output)
External memory access A0 to A7 (output)
Capture/compare CPCM0, CPCM1 (I/O)
Timer 0 timer output TM0OUT (output)
Timer 0 external event input TM0EVT (input)
External interrupt EXINT0 to EXINT3 (input)
Timer 1 external event input TM1EVT (input)
Timer 1 timer output TM1OUT (output)
Timer 2 external event input TM2EVT (input)
Timer 2 timer output TM2OUT (output)
PWM output PWM0OUT, PWM1OUT (output)
SIO1 receive data input RXD1 (input)
SIO1 transmit data output TXD1 (output)
SIO1 receive clock RXC1 (I/O)
P3_2
P3_3
Port 4
Port 5
P4_0 to P4_7
P5_4, P5_5
P5_6
P5_7
Port 6
P6_0 to P6_3
P6_4
P6_5
P6_6
P6_7
P7_6, P7_7
P8_0
Port 7
Port 8
P8_1
P8_2
P8_3
SIO1 transmit clock TXC1 (I/O)
P8_4
Timer 4 timer output TM4OUT (output)
PWM output PWM2OUT, PWM3OUT (output)
External interrupt EXINT4 to EXINT7 (input)
HOLD mode transfer output HLDACK (output)
SIO4 transmit-receive clock SIOCK4 (I/O)
SIO4 receive data output SIOO4 (output)
SIO4 transmit data input SIOI4 (input)
External data memory access WAIT (input)
HOLD mode request input HOLD (input)
Main clock pulse output CLKOUT (output)
Subclock pulse output XTOUT (output)
A/D converter analog input AI0 to AI7 (input)
SIO5 transmit-receive clock SIOCK5 (I/O)
SIO5 transmit data output SIOO5 (output)
SIO5 receive data input SIOI5 (input)
P8_6, P8_7
P9_0 to P9_3
P9_7
Port 9
Port 10
P10_3
P10_4
P10_5
Port 11*
P11_0
P11_1
P11_2
P11_3
Port 12
Port 14
P12_0 to P12_7
P14_0
D
D
D
E
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P14_1
P14_2
P14_6, P14_7
P15_0
D/A converter analog output AO0, AO1 (output)
SIO6 transmit-receive data input RXD6 (input)
SIO6 transmit data output TXD6 (output)
SIO6 receive clock RXC6 (I/O)
Port 15
D
D
D
D
P15_1
P15_2
P15_3
SIO6 transmit clock TXC6 (I/O)
*Ports marked with an asterisk are capable of providing the sink current of 10 mA.
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.2 Hardware Configuration of Each Port
Ports (P0 to P12, P14, and P15) are divided into six categories, corresponding to each
function.
5.2.1 Type A (P0)
The type A port has a secondary function and functions as an I/O pin. Depending on the
state of the port mode registers (P0IOn) and the port secondary function control registers
(P0SFn), the port configuration is switched between input, pulled-up input, output, and
secondary function I/O (external memory data I/O in a separate bus type, and external
memory data I/O and address output in a multiplexed bus type).
5
Because type A ports access external program memory as a secondary function, the port
status is determined by the status of the EA pin (that specifies external memory access).
When reset (due to RES input, BRK instruction execution, watchdog timer overflow or an
opcode trap), the pin status will be as follows:
EA pin status
Port initial status
H
L
High impedance input port
Secondary function I/O port
Figure 5-1 shows the type A configuration.
Pull-up
control
P0SFn
P0_n
P0_n
P0IOn
Secondary
function control
Read
control
Secondary
function input
Secondary
function output
EA
Figure 5-1 Type A Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.2.2 Type B (P1, P2, P3_0, P3_1, P4)
The type B port has a secondary function and functions as an I/O pin. Depending on the
state of the port mode registers (PmIOn) and the port secondary function control registers
(PmSFn), the port configuration is switched between input, pulled-up input, output, and
secondary function output (external memory access).
Because type B ports access external program memory as a secondary function, the port
status is determined by the status of the EA pin (that specifies external memory access).
When reset (due to RES input, BRK instruction execution, watchdog timer overflow or an
opcode trap), the pin status will be as follows:
EA pin status
Port initial status
H
L
High impedance input port
Secondary function I/O port
Figure 5-2 shows the type B configuration.
Pull-up
control
PmSFn
Pm_n
Pm_n
m = 1, n = 0 to 7
m = 2, n = 0 to 3
m = 3, n = 0, 1
m = 4, n = 0 to 7
PmIOn
Read
control
Secondary
function output
EA
Figure 5-2 Type B Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.2.3 Type C (P3_2, P3_3)
ThetypeCporthasasecondaryfunction. Dependingonthestateoftheportmoderegisters
(P3IOn) and the port secondary function control registers (P3SFn), the port configuration
is switched between input, pulled-up input, output, and secondary function output (external
memory access).
When reset (due to RES input, BRK instruction execution, watchdog timer overflow or an
opcode trap), the initial value of P3IOn and P3SFn is "0" and the port will be configured as
a high impedance input port.
Figure 5-3 shows the type C configuration.
5
Pull-up
control
P3SFn
P3_n
P3_n
n = 2, 3
P3IOn
Read
control
Secondary
function output
Figure 5-3 Type C Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.2.4 Type D (P5, P6, P7, P8, P9, P10, P11, P14_0 to P14_2, P15)
ThetypeDporthasasecondaryfunction. Dependingonthestateoftheportmoderegisters
(PmIOn) and the port secondary function control registers (PmSFn), the port configuration
isswitchedbetweeninput(primary/secondaryfunction),pulled-upinput(primary/secondary
function), output, and secondary function output.
When reset (due to RES input, BRK instruction execution, watchdog timer overflow or an
opcode trap), the initial value of PmIOn and PmSFn is "0" and the port will be configured
as a high impedance input port.
Figure 5-4 shows the type D configuration.
PmSFn
Pm_n
Pm_n
m = 5, n = 4 to 7
PmIOn
m = 6, n = 0 to 3, 4 to 7
m = 7, n = 6, 7
m = 8, n = 0 to 4, 6, 7
m = 9, n = 0, 1, 7
Read
Secondary
Secondary
control
function input
function output
m = 10, n = 3 to 5
m = 11, n = 0 to 3
m = 14, n = 0 to 2
m = 15, n = 0 to 3
Figure 5-4 Type D Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.2.5 Type E (P14_6, P14_7)
ThetypeEporthasasecondaryfunction. Dependingonthestateoftheportmoderegisters
(PmIOn) and the port secondary function control registers (PmSFn), the port configuration
isswitchedbetweeninput(primary/secondaryfunction),pulled-upinput(primary/secondary
function), output, and secondary function output.
When reset (due to RES input, BRK instruction execution, watchdog timer overflow or an
opcode trap), the initial value of PI4IOn and PI4SFn is "0" and the port will be configured
as a high impedance input port.
Figure 5-5 shows the type E configuration.
5
P14SFn
P14_n
P14_n
n = 6, 7
P14IOn
DAON
DAON
Read
Secondary function output
control
Figure 5-5 Type E Configuration
5.2.6 Type F (P12)
The type F port has a secondary function input, but is an input-only port that is not assigned
a port mode register (PnIO) and a port secondary function control register (PnSF).
P12 also functions as the analog input of the A/D converter.
Figure 5-6 shows the type F configuration.
ADON
Analog input
Data bus
P12_n
n = 0 to 7
ADON
Read
control
Figure 5-6 Type F Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.3 Port Registers
There are three types of port control registers:
• Port data registers (Pn: n = 0 to 12, 14, 15)
• Port mode registers (PnIO: n = 0 to 11, 14, 15)
• Port secondary function control registers (PnSF: n = 0 to 11, 14, 15)
These registers are allocated as SFRs.
Table 5-2 lists a summary of the port control SFRs.
Table 5-2 Port Control SFR Summary (1/2)
Address
[H]
Symbol
(byte)
P0
Symbol
(word)
—
8/16
Initial
Reference
page
5-12
5-14
5-16
5-18
5-20
5-22
5-24
5-26
5-28
5-30
5-32
5-34
5-36
5-37
5-39
5-12
5-14
5-16
5-18
5-20
5-22
5-24
5-26
5-28
5-30
5-32
5-34
5-37
5-39
Name
R/W
operation value [H]
0018
0019
Port 0 data register
Port 1 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
00
00
P1
—
001AI Port 2 data register
001BI Port 3 data register
P2
—
00
P3
—
00
001C
001DI Port 5 data register
001E Port 6 data register
Port 4 data register
P4
—
00
P5
—
00
P6
—
00
001FI Port 7 data register
00B8I Port 8 data register
00B9I Port 9 data register
00BAI Port 10 data register
00BBI Port 11 data register
P7
—
00
P8
—
00
P9
—
00
P10
—
00
P11
—
00
00BC
Port 12 data register
P12
—
Undefined
00
00BEI Port 14 data register
00BFI Port 15 data register
P14
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P15
—
00
0020
0021
Port 0 mode register
Port 1 mode register
P0IO
P1IO
P2IO
P3IO
P4IO
P5IO
P6IO
P7IO
P8IO
P9IO
P10IO
P11IO
P14IO
P15IO
—
00/FF
00/FF
00/0F
00/02
00/FF
00
—
0022I Port 2 mode register
0023I Port 3 mode register
—
—
0024
0025I Port 5 mode register
0026 Port 6 mode register
Port 4 mode register
—
—
—
00
0027I Port 7 mode register
00C0I Port 8 mode register
00C1I Port 9 mode register
00C2I Port 10 mode register
00C3I Port 11 mode register
00C4I Port 14 mode register
00C5I Port 15 mode register
—
00
—
00
—
00
—
00
—
00
—
00
—
00
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-2 Port Control SFR Summary (2/2)
Address
[H]
Symbol
(byte)
Symbol
(word)
8/16
Initial
Reference
page
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
operation value [H]
Port 0 secondary function
control register
0028
0029
P0SF
P1SF
P2SF
P3SF
P4SF
P5SF
P6SF
P7SF
P14SF
P15SF
P8SF
P9SF
P10SF
P11SF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
8
8
8
8
8
8
8
8
8
8
8
8
8
00/FF
00/FF
00/0F
00/03
00/FF
00
5-12
5-14
5-16
5-18
5-20
5-22
5-24
5-26
5-37
5-39
5-28
5-30
5-32
5-34
Port 1 secondary function
control register
Port 2 secondary function
control register
002AI
002BI
002C
5
Port 3 secondary function
control register
Port 4 secondary function
control register
Port 5 secondary function
control register
002DI
002E
Port 6 secondary function
control register
00
Port 7 secondary function
control register
002FI
00C6I
00C7I
00C8I
00C9I
00CAI
00CBI
[Notes]
00
Port 14 secondary function
control register
00
Port 15 secondary function
control register
00
Port 8 secondary function
control register
00
Port 9 secondary function
control register
00
Port 10 secondary function
control register
00
Port 11 secondary function
control register
00
1. Addresses are not consecutive in some places.
2. A star (I) in the address column indicates a missing bit.
3. Initial values may change depending upon the status of the EA pin (mode registers
and secondary control registers for port 0 to port 4). Listings are in the order of EA
= high-level/low-level.
4. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.3.1 Port Data Registers (Pn : n = 0 to 12, 14, 15)
Port data registers (Pn : n = 0 to 12, 14, 15) store the port output data.
Pn registers are allocated as SFRs and when reset (due to a RES input, BRK instruction
execution, watchdog timer overflow, or opcode trap), their value becomes 00H.
If an instruction to read Pn is executed, for ports specified as inputs, the pin status ("0" or
"1") will be read. For ports specified as outputs, the Pn status ("0" or "1") will be read. If
an instruction to write to Pn is executed, regardless whether the port is input or output, data
will be written to Pn. Because P12 is an input-only port, only read instructions can be
executed. If a read instruction is executed, the pin status ("0" or "1") will be read.
[Note]
If a bit specified as input by the port mode register (PnIO) is read, the pin status will be
read. Whenwritingdatatoaportdataregister(Pn), ifread-modify-writeinstructionssuch
asarithmetic,logicalandbitmanipulationinstructionsareused,theportdataregister(Pn)
of the bit specified as an input will be overwritten.
5.3.2 Port Mode Registers (PnIO : n = 0 to 11, 14, 15)
Port mode registers (PnIO : n = 0 to 11, 14, 15) specify whether I/O ports are inputs or
outputs.
PnIO registers are allocated as SFRs and when reset (due to a RES input, BRK instruction
execution, watchdog timer overflow, opcode trap), their value becomes 00H and all ports
will be set to the input mode. However, if the EA pin is at a low level, ports used to access
external memory will automatically be set to the output mode.
Setting each individual bit of PnIO to "0" configures the input mode and "1" configures the
output mode.
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.3.3 Port Secondary Function Control Registers (PnSF : n = 0 to 11, 14, 15)
Port secondary function control registers (PnSF : n = 0 to 11, 14, 15) specify the secondary
function output for ports.
PnSF registers are allocated as SFRs and when reset (due to RES input, BRK instruction
execution, watchdogtimer overflow, or opcode trap) their values become 00H and the
primary function will be selected for all ports. However, if the EA pin is at a low level, ports
used to access external memory will automatically be configured as secondary function
outputs.
When the port is in input mode, if PnSF is set to "1", the input will be pulled-up. When the
port is in output mode, if PnSF is set to "1", the secondary function output will be selected.
The secondary function input does not depend upon PnSF, and can be read in the same
manner as the primary function input with PnIO = 0.
5
Table 5-3 lists the port status due to the settings of the port mode register and the port
secondary function control register.
Table 5-3 Port Settings
PnIO
PnSF
Function
0
0
1
1
0
1
0
1
Input (primary/secondary function)
Pulled-up input (primary/secondary function)
Output (primary function)
Output (secondary function)
If a port that is not assigned a secondary function is set to secondary function output (PnIO
= 1, PnSF = 1), "0" will be output to that port.
Table 5-4 lists the values read when reading the port data register (Pn : n = 0 to 11, 14, 15)
according to the settings of port mode register (PnIO) and port secondary control register
(PnSF).
Table 5-4 Port Data Register Read Data
PnIO
PnSF
Read data
0
1
1
*
Pin status
0
1
Pn (value of port data register)
Output secondary function data
*: "0" or "1," n: 0 to 11, 14, 15
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.4 Port 0 (P0)
Port 0 is an 8-bit I/O port. Each individual bit can be specified as input or output by the port
0 mode register (P0IO). When output is specified (corresponding bits of P0IO = "1"), the
value of the corresponding bits in the port 0 data register (P0) will be output from their
appropriate pins.
In addition to its port function, P0 is assigned a secondary function (external memory data
I/O when selecting a separate bus type, and external memory data I/O and address output
when selecting a multiplexed bus type). If the secondary function is to be used, set the
corresponding bits of the port 0 mode register (P0IO) and the port 0 secondary function
control register (P0SF) to "1".
Iftheportisspecifiedasaninput(correspondingbitsofP0IO="0")andtheport0secondary
function control register (P0SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
Figure 5-7 shows the configuration of the port 0 data register (P0), port 0 mode register
(P0IO) and the port 0 secondary function control register (P0SF).
7
6
5
4
3
2
1
0
Address: 0018 [H]
R/W access: R/W
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P0
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 0020 [H]
R/W access: R/W
P0IO7 P0IO6 P0IO5 P0IO4 P0IO3 P0IO2 P0IO1 P0IO0
P0IO
At reset
(EA = H/L)
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
7
6
5
4
3
2
1
0
XAD1
P0SF1 P0SF0
XAD0
XAD7
XAD6
XAD5
XAD4
XAD3
XAD2
Address: 0028 [H]
R/W access: R/W
P0SF
At reset
(EA = H/L)
P0SF7 P0SF6 P0SF5 P0SF4 P0SF3 P0SF2
0 / 1 0 / 1 0 / 1 0 / 1 0 / 1 0 / 1
0 / 1 0 / 1
0 (Input setting)
Not pulled-up
1 (Output setting)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Primary function P0_0 output
Secondary function Data 0 I/O *
Primary function P0_1 output
Secondary function Data 1 I/O *
Primary function P0_2 output
Secondary function Data 2 I/O *
Primary function P0_3 output
Secondary function Data 3 I/O *
Primary function P0_4 output
Secondary function Data 4 I/O *
Primary function P0_5 output
Secondary function Data 5 I/O *
Primary function P0_6 output
Secondary function Data 6 I/O *
Primary function P0_7 output
Secondary function Data 7 I/O *
P0_0 input
Pulled-up
Not pulled-up
Pulled-up
P0_1 input
P0_2 input
P0_3 input
P0_4 input
P0_5 input
P0_6 input
P0_7 input
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
"*" indicates data I/O in a separate bus type. In a multiplexed bus type,
it will be data I/O and address output.
Figure 5-7 P0, P0IO, P0SF Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-5 lists the data that is read, depending on the settings of P0IO and P0SF, when
executing an instruction to read P0.
At reset (due to RES input, BRK instruction execution, watchdog timer overflow, or opcode
trap), if the EA pin is at a high level, P0 will become a high impedance input port (P0IO =
00H, P0SF = 00H) and the contents of P0 will be 00H. If the EA pin is at a low level, P0 will
be set as a secondary function I/O port (P0IO = FFH, P0SF = FFH) and the contents of P0
will be 00H.
Table 5-5 P0 Read Data
P0IO
0
P0SF
Read data
5
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
P0_0 pin state
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
1
Value of bit 0 of P0 (port data register)
P0_1 pin state
0
1
Value of bit 1 of P0 (port data register)
P0_2 pin state
0
1
Value of bit 2 of P0 (port data register)
P0_3 pin state
0
1
Value of bit 3 of P0 (port data register)
P0_4 pin state
0
1
Value of bit 4 of P0 (port data register)
P0_5 pin state
0
1
Value of bit 5 of P0 (port data register)
P0_6 pin state
0
1
Value of bit 6 of P0 (port data register)
P0_7 pin state
0
1
Value of bit 7 of P0 (port data register)
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P0,
depending on the settings of P0IO and P0SF, values will be read as listed in Table 5-5.
The modified values will be written to P0 (port 0 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.5 Port 1 (P1)
Port 1 is an 8-bit I/O port. Each individual bit can be specified as input or output by the port
1 mode register (P1IO). When output is specified (corresponding bits of P1IO = "1"), the
value of the corresponding bits in the port 1 data register (P1) will be output from their
appropriate pins.
In addition to its port function, P1 is assigned a secondary function (external memory
address output). If the secondary function is to be used, set the corresponding bits of the
port1moderegister(P1IO)andtheport1secondaryfunctioncontrolregister(P1SF)to"1".
Iftheportisspecifiedasaninput(correspondingbitsofP1IO="0")andtheport1secondary
function control register (P1SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
Figure 5-8 shows the configuration of the port 1 data register (P1), port 1 mode register
(P1IO) and the port 1 secondary function control register (P1SF).
7
6
5
4
3
2
1
0
Address: 0019 [H]
R/W access: R/W
P1
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 0021 [H]
R/W access: R/W
P1IO
P1IO7 P1IO6 P1IO5 P1IO4 P1IO3 P1IO2 P1IO1 P1IO0
At reset
(EA = H/L)
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
7
6
5
4
3
2
1
0
Address: 0029 [H]
R/W access: R/W
XDM9 XDM8
P1SF1 P1SF0
XDM15 XDM14 XDM13 XDM12 XDM11 XDM10
P1SF7 P1SF6 P1SF5 P1SF4 P1SF3 P1SF2
P1SF
At reset
(EA = H/L)
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 (Input setting)
Not pulled-up
1 (Output setting)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Primary function P1_0 output
Secondary function Address 8 output
Primary function P1_1 output
Secondary function Address 9 output
Primary function P1_2 output
Secondary function Address 10 output
Primary function P1_3 output
Secondary function Address 11 output
Primary function P1_4 output
Secondary function Address 12 output
Primary function P1_5 output
Secondary function Address 13 output
Primary function P1_6 output
Secondary function Address 14 output
Primary function P1_7 output
Secondary function Address 15 output
P1_0 input
Pulled-up
Not pulled-up
Pulled-up
P1_1 input
P1_2 input
P1_3 input
P1_4 input
P1_5 input
P1_6 input
P1_7 input
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Figure 5-8 P1, P1IO, P1SF Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-6 lists the data that is read, depending on the settings of P1IO and P1SF, when
executing an instruction to read P1.
At reset (due to RES input, BRK instruction execution, watchdog timer overflow, or opcode
trap), if the EA pin is at a high level, P1 will become a high impedance input port (P1IO =
00H, P1SF = 00H) and the contents of P1 will be 00H. If the EA pin is at a low level, P1 will
be set as a secondary function output port (P1IO = FFH, P1SF = FFH) and the contents of
P1 will be 00H.
Table 5-6 P1 Read Data
P1IO
0
P1SF
Read data
5
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
P1_0 pin state
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
1
Value of bit 0 of P1 (port data register)
P1_1 pin state
0
1
Value of bit 1 of P1 (port data register)
P1_2 pin state
0
1
Value of bit 2 of P1 (port data register)
P1_3 pin state
0
1
Value of bit 3 of P1 (port data register)
P1_4 pin state
0
1
Value of bit 4 of P1 (port data register)
P1_5 pin state
0
1
Value of bit 5 of P1 (port data register)
P1_6 pin state
0
1
Value of bit 6 of P1 (port data register)
P1_7 pin state
0
1
Value of bit 7 of P1 (port data register)
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P1,
depending on the settings of P1IO and P1SF, values will be read as listed in Table 5-6.
The modified values will be written to P1 (port 1 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.6 Port 2 (P2)
Port 2 is a 4-bit I/O port. Each individual bit can be specified as input or output by the port
2 mode register (P2IO). When output is specified (corresponding bits of P2IO = "1"), the
value of the corresponding bits in the port 2 data register (P2) will be output from their
appropriate pins.
In addition to its port function, P2 is assigned a secondary function (external memory
address output). If the secondary function is to be used, set the corresponding bits of the
port2moderegister(P2IO)andtheport2secondaryfunctioncontrolregister(P2SF)to"1".
Iftheportisspecifiedasaninput(correspondingbitsofP2IO="0")andtheport2secondary
function control register (P2SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
Figure 5-9 shows the configuration of the port 2 data register (P2), port 2 mode register
(P2IO) and the port 2 secondary function control register (P2SF).
7
6
5
4
3
2
1
0
Address: 001A [H]
R/W access: R/W
P2
—
—
—
—
P2_3
P2_2
P2_1
P2_0
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 0022 [H]
R/W access: R/W
P2IO
—
—
—
—
P2IO3 P2IO2 P2IO1 P2IO0
At reset
(EA = H/L)
0
0
0
0
0 / 1
0 / 1
0 / 1
0 / 1
7
6
5
4
3
2
1
0
Address: 002A [H]
R/W access: R/W
XDM19 XDM18 XDM17 XDM16
P2SF3 P2SF2 P2SF1 P2SF0
P2SF
At reset
(EA = H/L)
—
—
—
—
0
0
0
0
0 / 1
0 / 1
0 / 1
0 / 1
0 (Input setting)
Not pulled-up
1 (Output setting)
0
1
0
1
0
1
0
1
Primary function P2_0 output
Secondary function Address 16 output
Primary function P2_1 output
Secondary function Address 17 output
Primary function P2_2 output
Secondary function Address 18 output
Primary function P2_3 output
Secondary function Address 19 output
P2_0 input
Pulled-up
Not pulled-up
Pulled-up
P2_1 input
P2_2 input
P2_3 input
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-9 P2, P2IO, P2SF Configuration
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Chapter 5 Port Functions
Table 5-7 lists the data that is read, depending on the settings of P2IO and P2SF, when
executing an instruction to read P2.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), if the EA pin is at a high level, P2 will become a high impedance input port (P2IO =
00H, P2SF = 00H) and the contents of P2 will be 00H. If the EA pin is at a low level, P2 will
be set as a secondary function output port (P2IO = 0FH, P2SF = 0FH) and the contents of
P2 will be 00H.
Table 5-7 P2 Read Data
P2IO
P2SF
Read data
5
0
1
0
1
0
1
0
1
*
*
*
*
*
*
*
*
P2_0 pin state
P2_0
P2_1
P2_2
P2_3
Value of bit 0 of P2 (port data register)
P2_1 pin state
Value of bit 1 of P2 (port data register)
P2_2 pin state
Value of bit 2 of P2 (port data register)
P2_3 pin state
Value of bit 3 of P2 (port data register)
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P2,
depending on the settings of P2IO and P2SF, values will be read as listed in Table 5-7.
The modified values will be written to P2 (port 2 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.7 Port 3 (P3)
Port 3 is a 4-bit I/O port. Each individual bit can be specified as input or output by the port
3 mode register (P3IO). When output is specified (corresponding bits of P3IO = "1"), the
value of the corresponding bits in the port 3 data register (P3) will be output from their
appropriate pins.
In addition to its port function, P3 is assigned secondary functions (ALE, PSEN, RD, and
WR outputs). If a secondary function is to be used, set the corresponding bits of the port
3 mode register (P3IO) and the port 3 secondary function control register (P3SF) to "1".
Iftheportisspecifiedasaninput(correspondingbitsofP3IO="0")andtheport3secondary
function control register (P3SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
Figure 5-10 shows the configuration of the port 3 data register (P3), port 3 mode register
(P3IO) and the port 3 secondary function control register (P3SF).
7
6
5
4
3
2
1
0
Address: 001B [H]
R/W access: R/W
P3
—
—
—
—
P3_3
P3_2
P3_1
P3_0
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 0023 [H]
R/W access: R/W
P3IO
—
—
—
—
P3IO3 P3IO2 P3IO1 P3IO0
At reset
(EA = H/L)
0
0
0
0
0
0
0 / 1
0
7
6
5
4
3
2
1
0
Address: 002B [H]
R/W access: R/W
WR
RD
PSEN
ALE
P3SF
At reset
(EA = H/L)
—
—
—
—
P3SF3 P3SF2 P3SF1 P3SF0
0
0
0
0
0
0
0 / 1 0/1
0 (Input setting)
Not pulled-up
1 (Output setting)
0
1
Primary function P3_0 output
Secondary function ALE output
P3_0 input
Pulled-up
0
1
0
1
0
1
Not pulled-up
Pulled-up
Primary function P3_1 output
Secondary function PSEN output
Primary function P3_2 output
Secondary function RD output
Primary function P3_3 output
Secondary function WR output
P3_1 input
P3_2 input
P3_3 input
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-10 P3, P3IO, P3SF Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-8 lists the data that is read, depending on the settings of P3IO and P3SF, when
executing an instruction to read P3.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), if the EA pin is at a high level, P3 will become a high impedance input port (P3IO =
00H, P3SF = 00H) and the contents of P3 will be 00H. If the EA pin is at a low level, only
P3_0 and P3_1 will be set as a secondary function I/O port (P3IO = 03H, P3SF = 03H) and
the contents of P3 will be 00H.
Table 5-8 Read Data
P3IO
P3SF
Read data
5
0
1
0
1
0
1
0
1
*
*
*
*
*
*
*
*
P3_0 pin state
P3_0
P3_1
P3_2
P3_3
Value of bit 0 of P3 (port data register)
P3_1 pin state
Value of bit 1 of P3 (port data register)
P3_2 pin state
Value of bit 2 of P3 (port data register)
P3_3 pin state
Value of bit 3 of P3 (port data register)
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P3,
depending on the settings of P3IO and P3SF, values will be read as listed in Table 5-8.
The modified values will be written to P3 (port 3 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.8 Port 4 (P4)
Port 4 is an 8-bit I/O port. Each individual bit can be specified as input or output by the port
4 mode register (P4IO). When output is specified (corresponding bits of P4IO = "1"), the
value of the corresponding bits in the port 4 data register (P4) will be output from their
appropriate pins.
In addition to its port function, P4 is assigned a secondary function (external memory
addressoutputwhenselectingaseparatebustype). Ifthesecondaryfunctionistobeused,
set the corresponding bits of the port 4 mode register (P4IO) and the port 4 secondary
function control register (P4SF) to "1".
Iftheportisspecifiedasaninput(correspondingbitsofP4IO="0")andtheport4secondary
function control register (P4SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
Figure 5-11 shows the configuration of the port 4 data register (P4), port 4 mode register
(P4IO) and the port 4 secondary function control register (P4SF).
7
6
5
4
3
2
1
0
Address: 001C [H]
R/W access: R/W
P4
P4_7
P4_6
P4_5
P4_4
P4_3
P4_2
P4_1
P4_0
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 0024 [H]
R/W access: R/W
P4IO
P4IO7 P4IO6 P4IO5 P4IO4 P4IO3 P4IO2 P4IO1 P4IO0
At reset
(EA = H/L)
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
0 / 1
7
6
5
4
3
2
1
0
Address: 002C [H]
R/W access: R/W
XDM1 XDM0
P4SF1 P4SF0
XDM7
XDM6
XDM5
XDM4 XDM3 XDM2
P4SF
At reset
(EA = H/L)
P4SF7 P4SF6 P4SF5 P4SF4 P4SF3 P4SF2
0 / 1 0 / 1 0 / 1 0 / 1 0 / 1 0 / 1
0 / 1
0 / 1
0 (Input setting)
Not pulled-up
1 (Output setting)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Primary function P4_0 output
Secondary function Address 0 output
Primary function P4_1 output
Secondary function Address 1 output
Primary function P4_2 output
Secondary function Address 2 output
Primary function P4_3 output
Secondary function Address 3 output
Primary function P4_4 output
Secondary function Address 4 output
Primary function P4_5 output
Secondary function Address 5 output
Primary function P4_6 output
Secondary function Address 6 output
Primary function P4_7 output
Secondary function Address 7 output
P4_0 input
Pulled-up
Not pulled-up
Pulled-up
P4_1 input
P4_2 input
P4_3 input
P4_4 input
P4_5 input
P4_6 input
P4_7 input
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Figure 5-11 P4, P4IO, P4SF Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-9 lists the data that is read, depending on the settings of P4IO and P4SF, when
executing an instruction to read P4.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), if the EA pin is at a high level, P4 will become a high impedance input port (P4IO =
00H, P4SF = 00H) and the contents of P4 will be 00H. If the EA pin is at a low level, P4 will
be set as a secondary function output port (P4IO = FFH, P4SF = FFH) and the contents of
P4 will be 00H.
Table 5-9 P4 Read Data
P4IO
0
P4SF
Read data
5
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
P4_0 pin state
P4_0
P4_1
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
1
Value of bit 0 of P4 (port data register)
P4_1 pin state
0
1
Value of bit 1 of P4 (port data register)
P4_2 pin state
0
1
Value of bit 2 of P4 (port data register)
P4_3 pin state
0
1
Value of bit 3 of P4 (port data register)
P4_4 pin state
0
1
Value of bit 4 of P4 (port data register)
P4_5 pin state
0
1
Value of bit 5 of P4 (port data register)
P4_6 pin state
0
1
Value of bit 6 of P4 (port data register)
P4_7 pin state
0
1
Value of bit 7 of P4 (port data register)
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P4,
depending on the settings of P4IO and P4SF, values will be read as listed in Table 5-9.
The modified values will be written to P4 (port 4 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.9 Port 5 (P5)
Port 5 is a 4-bit I/O port. Each individual bit can be specified as input or output by the port
5 mode register (P5IO). When output is specified (corresponding bits of P5IO = "1"), the
value of the corresponding bits in the port 5 data register (P5) will be output from their
appropriate pins.
In addition to its port function, P5 is assigned secondary functions (such as capture/
compare I/O). If a secondary function output is to be used, set the corresponding bits of
the port 5 mode register (P5IO) and the port 5 secondary function control register (P5SF)
to "1". If a secondary function input is to be used, reset the corresponding bits of the port
5 mode register (P5IO) to "0" to configure the input mode (same input as the primary
function input).
Iftheportisspecifiedasaninput(correspondingbitsofP5IO="0")andtheport5secondary
function control register (P5SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
If bit 7 of port 5 is set to secondary function output (P5IO7 = 1, P5SF7 = 1), the output will
be fixed at "0", regardless of the value of the port 5 data register.
Figure 5-12 shows the configuration of the port 5 data register (P5), port 5 mode register
(P5IO) and the port 5 secondary function control register (P5SF).
7
6
5
4
3
2
1
0
Address: 001D [H]
R/W access: R/W
P5_7
P5_6
P5_5
P5_4
—
—
—
—
P5
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 0025 [H]
R/W access: R/W
P5IO
P5IO7 P5IO6 P5IO5 P5IO4
—
—
—
—
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 002D [H]
R/W access: R/W
PTM0OUT CPCM1 CPCM0
P5SF6 P5SF5 P5SF4
P5SF
At reset
P5SF7
—
—
—
—
0
0
0
0
0
0
0
0
0 (Input setting)
1 (Output setting)
P5_4 input
0
1
0
1
0
1
0
1
Not pulled-up
Pulled-up
Primary function P5_4 output
Secondary function Compare 0 output
Primary function P5_5 output
Secondary function Compare 1 output
Primary function P5_6 output
Secondary function Timer 0 output
Primary function P5_7 output
Capture 0 input
P5_5 input
Not pulled-up
Pulled-up
Capture 1 input
Not pulled-up
Pulled-up
P5_6 input
P5_7 input, timer 0
External event input
Not pulled-up
Pulled-up
Secondary function
0 output*
0 output*: "0" is output, regardless of the value of the port data register
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-12 P5, P5IO, P5SF Configuration
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Chapter 5 Port Functions
Table 5-10 lists the data that is read, depending on the settings of P5IO and P5SF, when
executing an instruction to read P5.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), P5 will become a high impedance input port (P5IO = 00H, P5SF = 00H) and the
contents of P5 will be 00H.
Table 5-10 P5 Read Data
P5IO
0
P5SF
Read data
*
0
1
*
P5_4/CPCM0 pin state
Value of bit 4 of P5 (port data register)
CPCM0 output data
P5_4
P5_5
P5_6
P5_7
1
5
1
0
P5_5/CPCM1 pin state
Value of bit 5 of P5 (port data register)
CPCM1 output data
1
0
1
*
1
0
P5_6 pin state
1
0
1
*
Value of bit 6 of P5 (port data register)
TM0OUT output data
1
0
P5_7/TM0EVT pin state
Value of bit 7 of P5 (port data register)
"0"
1
0
1
1
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P5,
depending on the settings of P5IO and P5SF, values will be read as listed in Table 5-10.
The modified values will be written to P5 (port 5 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.10 Port 6 (P6)
Port 6 is an 8-bit I/O port. Each individual bit can be specified as input or output by the port
6 mode register (P6IO). When output is specified (corresponding bits of P6IO = "1"), the
value of the corresponding bits in the port 6 data register (P6) will be output from their
appropriate pins.
In addition to its port function, P6 is assigned a secondary function (such as external
interrupt input). If the secondary function output is to be used, set the corresponding bits
of the port 6 mode register (P6IO) and the port 6 secondary function control register (P6SF)
to "1". If the secondary function input is to be used, reset the corresponding bits of the port
6 mode register (P6IO) to "0" to configure the input mode (same input as the primary
function input).
If the port is set as an input (corresponding bits of P6IO = "0") and the port 6 secondary
function control register (P6SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
If bits 0 to 4 and bit 6 of port 6 are set as a secondary function output (P6IOn = 1, P6SFn
= 1), the output will be fixed at "0", regardless of the value of the port 6 data register.
Figure 5-13 shows the configuration of the port 6 data register (P6), port 6 mode register
(P6IO) and the port 6 secondary function control register (P6SF).
7
6
5
4
3
2
1
0
Address: 001E [H]
R/W access: R/W
P6_7
P6_6
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
P6
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 0026 [H]
R/W access: R/W
P6IO7 P6IO6 P6IO5 P6IO4 P6IO3 P6IO2 P6IO1 P6IO0
P6IO
At reset
0
0
0
0
0
0
0
0
7
6
P6SF6
0
5
4
3
2
1
0
PTM2OUT
P6SF7
PTM1OUT
P6SF5
Address: 002E [H]
R/W access: R/W
P6SF4 P6SF3 P6SF2 P6SF1 P6SF0
P6SF
At reset
0
0
0
0
0
0
0
0 (Input setting)
1 (Output setting)
P6_0 input
External interrupt
0 input
P6_1 input
External interrupt
1 input
P6_2 input
External interrupt
2 input
P6_3 input
External interrupt
3 input
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Not pulled-up
Pulled-up
Primary function P6_0 output
Secondary function
0 output*
Not pulled-up
Pulled-up
Primary function P6_1 output
Secondary function
0 output*
Not pulled-up
Pulled-up
Primary function P6_2 output
Secondary function
0 output*
Not pulled-up
Pulled-up
Primary function P6_3 output
Secondary function
0 output*
P6_4 input
Timer 1 external
event input
Not pulled-up
Pulled-up
Primary function P6_4 output
Secondary function
0 output*
Not pulled-up
Pulled-up
Primary function P6_5 output
Secondary function Timer 1 output
Primary function P6_6 output
P6_5 input
P6_6 input
Timer 2 external
event input
Not pulled-up
Pulled-up
Secondary function
0 output*
Not pulled-up
Pulled-up
Primary function P6_7 output
Secondary function Timer 2 output
P6_7 input
0 output*: "0" is output, regardless of the value of the port data register
Figure 5-13 P6, P6IO, P6SF Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-11 lists the data that is read, depending on the settings of P6IO and P6SF, when
executing an instruction to read P6.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), P6 will become a high impedance input port (P6IO = 00H, P6SF = 00H) and the
contents of P6 will be 00H.
Table 5-11 P6 Read Data
P6IO
0
P6SF
Read data
*
0
1
*
P6_0/EXINT0 pin state
Value of bit 0 of P6 (port data register)
"0"
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
1
5
1
0
P6_1/EXINT1 pin state
Value of bit 1 of P6 (port data register)
"0"
1
0
1
*
1
0
P6_2/EXINT2 pin state
Value of bit 2 of P6 (port data register)
"0"
1
0
1
*
1
0
P6_3/EXINT3 pin state
Value of bit 3 of P6 (port data register)
"0"
1
0
1
*
1
0
P6_4/TM1EVT pin state
Value of bit 4 of P6 (port data register)
"0"
1
0
1
*
1
0
P6_5 pin state
1
0
1
*
Value of bit 5 of P6 (port data register)
TM1OUT output data
P6_6 pin state
1
0
1
0
1
*
Value of bit 6 of P6 (port data register)
"0"
1
0
P6_7 pin state
1
0
1
Value of bit 7 of P6 (port data register)
TM2OUT output data
1
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P6,
depending on the settings of P6IO and P6SF, values will be read as listed in Table 5-11.
The modified values will be written to P6 (port 6 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.11 Port 7 (P7)
Port 7 is a 7-bit I/O port. Each individual bit can be specified as input or output by the port
7 mode register (P7IO). When output is specified (corresponding bits of P7IO = "1"), the
value of the corresponding bits in the port 7 data register (P7) will be output from their
appropriate pins.
In addition to its port function, P7 is assigned secondary functions (such as PWM0 output).
If a secondary function output is to be used, set the corresponding bits of the port 7 mode
register (P7IO) and the port 7 secondary function control register (P7SF) to "1".
If the port is set as an input (corresponding bits of P7IO = "0") and the port 7 secondary
function control register (P7SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
Figure 5-14 shows the configuration of the port 7 data register (P7), port 7 mode register
(P7IO) and the port 7 secondary function control register (P7SF).
7
6
5
4
3
2
1
0
Address: 001F [H]
R/W access: R/W
P7_7
P7_6
—
—
—
—
—
—
P7
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 0027 [H]
R/W access: R/W
—
P7IO7 P7IO6
—
—
—
—
—
P7IO
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PWM0OUT
P7SF6
PWM1OUT
P7SF7
Address: 002F [H]
R/W access: R/W
—
—
—
—
—
—
P7SF
At reset
0
0
0
0
0
0
0
0
0 (Input setting)
Not pulled-up
1 (Output setting)
Primary function P7_6 output
Secondary function PWM0 output
Primary function P7_7 output
Secondary function PWM1 output
0
1
0
1
P7_6 input
Pulled-up
Not pulled-up
Pulled-up
P7_7 input
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-14 P7, P7IO, P7SF Configuration
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Chapter 5 Port Functions
Table 5-12 lists the data that is read, depending on the settings of P7IO and P7SF, when
executing an instruction to read P7.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), P7 will become a high impedance input port (P7IO = 00H, P7SF = 00H) and the
contents of P7 will be 00H.
Table 5-12 P7 Read Data
P71IO
P71SF
Read data
0
1
1
0
1
1
*
P7_6 pin state
P7_6
P7_7
0
1
*
Value of bit 6 of P7 (port data register)
PWM0OUT output data
P7_7 pin state
5
0
1
Value of bit 7 of P7 (port data register)
PWM1OUT output data
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P7,
depending on the settings of P7IO and P7SF, values will be read as listed in Table 5-12.
The modified values will be written to P7 (port 7 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.12 Port 8 (P8)
Port 8 is a 7-bit I/O port. Each individual bit can be specified as input or output by the port
8 mode register (P8IO). When output is specified (corresponding bits of P8IO = "1"), the
value of the corresponding bits in the port 8 data register (P8) will be output from their
appropriate pins.
In addition to its port function, P8 is assigned secondary functions (such as SIO1 receive
data input). If a secondary function output is to be used, set the corresponding bits of the
port8moderegister(P8IO)andtheport8secondaryfunctioncontrolregister(P8SF)to"1".
If a secondary function input is to be used, reset corresponding bits of the port 8 mode
register(P8IO)to"0"toconfiguretheinputmode(sameinputastheprimaryfunctioninput).
If the port is set as an input (corresponding bits of P8IO = "0") and the port 8 secondary
function control register (P8SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
If bit 0 of port 8 is set as a secondary function output (P8IO0 = 1, P8SF0 = 1), the output
will be fixed at "0", regardless of the value of the port 8 data register.
Figure 5-15 shows the configuration of the port 8 data register (P8), port 8 mode register
(P8IO) and the port 8 secondary function control register (P8SF).
7
6
5
4
3
2
1
0
Address: 00B8 [H]
R/W access: R/W
P8_7
P8_6
—
P8_4
P8_3
P8_2
P8_1
P8_0
P8
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 00C0 [H]
R/W access: R/W
P8IO7 P8IO6
—
P8IO4 P8IO3 P8IO2 P8IO1 P8IO0
P8IO
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PWM3OUT PWM2OUT
P8SF7 P8SF6
PTM4OUT TXC1
P8SF4 P8SF3 P8SF2 P8SF1
RXC1
TXD1
Address: 00C8 [H]
R/W access: R/W
—
P8SF0
P8SF
At reset
0
0
0
0
0
0
0
0
0 (Input setting)
1 (Output setting)
P8_0 input
SIO1 receive
data input
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Not pulled-up
Pulled-up
Primary function P8_0 output
Secondary function
0 output*
Not pulled-up
Pulled-up
Primary function P8_1 output
Secondary function SIO1 transmit data output
Primary function P8_2 output
Secondary function SIO1 receive clock output
Primary function P8_3 output
Secondary function SIO1 transmit clock output
Primary function P8_4 output
Secondary function Timer 4 output
Primary function P8_6 output
Secondary function PWM2 output
Primary function P8_7 output
Secondary function PWM3 output
P8_1 input
P8_2 input
SIO1 receive
clock input
P8_3 input
SIO1 transmit
clock input
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
P8_4 input
P8_6 input
P8_7 input
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
0 output*: "0" is output, regardless of the value of the port data register
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-15 P8, P8IO, P8SF Configuration
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Chapter 5 Port Functions
Table 5-13 lists the data that is read, depending on the settings of P8IO and P8SF, when
executing an instruction to read P8.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), P8 will become a high impedance input port (P8IO = 00H, P8SF = 00H) and the
contents of P8 will be 00H.
Table 5-13 P8 Read Data
P8IO
0
P8SF
Read data
*
0
1
*
P8_0/RXD1 pin state
P8_0
P8_1
P8_2
P8_3
P8_4
P8_6
P8_7
1
Value of bit 0 of P8 (port data register)
"0"
5
1
0
P8_1 pin state
1
0
1
*
Value of bit 1 of P8 (port data register)
TXD1 output data
1
0
P8_2/RXC1 pin state
1
0
1
*
Value of bit 2 of P8 (port data register)
RXC1 output data
1
0
P8_3/TXC1 pin state
1
0
1
*
Value of bit 3 of P8 (port data register)
TXC1 output data
1
0
P8_4 pin state
1
0
1
*
Value of bit 4 of P8 (port data register)
TM4OUT output data
1
0
P8_6 pin state
1
0
1
*
Value of bit 6 of P8 (port data register)
PWM2OUT output data
P8_7 pin state
1
0
1
0
1
Value of bit 7 of P8 (port data register)
PWM3OUT output data
1
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P8,
depending on the settings of P8IO and P8SF, values will be read as listed in Table 5-13.
The modified values will be written to P8 (port 8 data register).
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Chapter 5 Port Functions
5.13 Port 9 (P9)
Port 9 is a 5-bit I/O port. Each individual bit can be specified as input or output by the port
9 mode register (P9IO). When output is specified (corresponding bits of P9IO = "1"), the
value of the corresponding bits in the port 9 data register (P9) will be output from their
appropriate pins.
In addition to its port function, P9 is assigned secondary functions (such as external
interrupt input). If a secondary function output is to be used, set the corresponding bits of
the port 9 mode register (P9IO) and the port 9 secondary function control register (P9SF)
to"1". Ifasecondaryfunctioninputistobeused,resetcorrespondingbitsoftheport9mode
register(P9IO)to"0"toconfiguretheinputmode(sameinputastheprimaryfunctioninput).
If the port is set as an input (corresponding bits of P9IO = "0") and the port 9 secondary
function control register (P9SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
If bits 0 to 3 of port 9 are set as secondary function outputs (P9IOn = 1, P9SFn = 1), the
output will be fixed at "0", regardless of the value of the port 9 data register.
Figure 5-16 shows the configuration of the port 9 data register (P9), port 9 mode register
(P9IO) and the port 9 secondary function control register (P9SF).
7
6
5
4
3
2
1
0
Address: 00B9 [H]
R/W access: R/W
P9_7
—
—
—
P9_3
P9_2
P9_1
P9_0
P9
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 00C1 [H]
R/W access: R/W
P9IO7
—
—
—
P9IO3 P9IO2 P9IO1 P9IO0
P9IO
At reset
0
0
0
0
0
0
0
0
7
6
—
0
5
—
0
4
—
0
3
2
1
0
HLDACK
P9SF7
Address: 00C9 [H]
R/W access: R/W
P9SF3 P9SF2 P9SF1 P9SF0
P9SF
At reset
0
0
0
0
0
0 (Input setting)
1 (Output setting)
P9_0 input
External interrupt
4 input
P9_1 input
External interrupt
5 input
P9_2 input
External interrupt
6 input
0
1
0
1
0
1
0
1
0
1
Not pulled-up
Pulled-up
Primary function P9_0 output
Secondary function
0 output*
Primary function P9_1 output
Secondary function 0 output*
Primary function P9_2 output
Secondary function 0 output*
Primary function P9_3 output
Secondary function 0 output*
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
P9_3 input
P9_7 input
External interrupt
7 input
Not pulled-up
Pulled-up
Primary function P9_7 output
Secondary function HLDACK output
0 output*: "0" is output, regardless of the value of the port data register
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-16 P9, P9IO, P9SF Configuration
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Chapter 5 Port Functions
Table 5-14 lists the data that is read, depending on the settings of P9IO and P9SF, when
executing an instruction to read P9.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), P9 will become a high impedance input port (P9IO = 00H, P9SF = 00H) and the
contents of P9 will be 00H.
Table 5-14 P9 Read Data
P9IO
0
P9SF
Read data
*
0
1
*
P9_0/EXINT4 pin state
Value of bit 0 of P9 (port data register)
"0"
P9_0
P9_1
P9_2
P9_3
P9_7
1
5
1
0
P9_1/EXINT5 pin state
Value of bit 1 of P9 (port data register)
"0"
1
0
1
*
1
0
P9_2/EXINT6 pin state
Value of bit 2 of P9 (port data register)
"0"
1
0
1
*
1
0
P9_3/EXINT7 pin state
Value of bit 3 of P9 (port data register)
"0"
1
0
1
*
1
0
P9_7 pin state
1
0
1
Value of bit 7 of P9 (port data register)
HLDACK output
1
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P9,
depending on the settings of P9IO and P9SF, values will be read as listed in Table 5-14.
The modified values will be written to P9 (port 9 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.14 Port 10 (P10)
Port 10 is a 3-bit I/O port. Each individual bit can be specified as input or output by the port
10 mode register (P10IO). When output is specified (corresponding bits of P10IO = "1"),
the value of the corresponding bits in the port 10 data register (P10) will be output from their
appropriate pins.
In addition to its port function, P10 is assigned secondary functions (such as SIO4 transmit-
receive clock I/O). If a secondary function output is to be used, set the corresponding bits
of the port 10 mode register (P10IO) and the port 10 secondary function control register
(P10SF) to "1". If a secondary function input is to be used, reset corresponding bits of the
port 10 mode register (P10IO) to "0" to configure the input mode (same input as the primary
function input).
If the port is set as an input (corresponding bits of P10IO = "0") and the port 10 secondary
function control register (P10SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
If bit 5 of port 10 is set as secondary function outputs (P10IOn = 1, P10SFn = 1), the output
will be fixed at "0", regardless of the value of the port 10 data register.
Figure5-17showstheconfigurationoftheport10dataregister(P10), port10moderegister
(P10IO) and the port 10 secondary function control register (P10SF).
7
6
5
4
3
2
1
0
Address: 00BA [H]
R/W access: R/W
—
—
P10_5 P10_4
P10_3
—
—
—
P10
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 00C2 [H]
R/W access: R/W
—
—
P10IO5 P10IO4 P10IO3
—
—
—
P10IO
At reset
0
0
0
0
0
0
0
0
7
6
—
0
5
P10SF3
0
4
3
2
1
0
SIOO4 SIOK4
P10SF3 P10SF3
Address: 00CA [H]
R/W access: R/W
—
—
—
—
P10SF
At reset
0
0
0 (Input setting)
1 (Output setting)
P10_3 input
SIO4 transmit-
receive clock input
Not pulled-up
Pulled-up
Primary function P10_3 output
SIO4 transmit-
0
1
0
1
0
1
Secondary function
receive clock output
Not pulled-up
Pulled-up
Primary function P10_4 output
SIO4 transmit
P10_4 input
Secondary function
data output
P10_5 input
SIO4 receive
cata input
Not pulled-up
Pulled-up
Primary function P10_5 output
Secondary function
0 output*
0 output*: "0" is output, regardless of the value of the port data register
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-17 P10, P10IO, P10SF Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-15 lists the data that is read, depending on the settings of P10IO and P10SF, when
executing an instruction to read P10.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), P10 will become a high impedance input port (P10IO = 00H, P10SF = 00H) and the
contents of P10 will be 00H.
Table 5-15 P10 Read Data
P10IO
P10SF
Read data
0
1
1
0
1
1
0
1
1
*
0
1
*
P10_3/SIOCK4 pin state
Value of bit 3 of P10 (port data register)
SIOCK4 output data
P10_3
P10_4
P10_5
5
P10_4 pin state
0
1
*
Value of bit 4 of P10 (port data register)
SIOO4 output data
P10_5/SIO14 pin state
Value of bit 5 of P10 (port data register)
"0"
0
1
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P10,
depending on the settings of P10IO and P10SF, values will be read as listed in Table 5-
15. The modified values will be written to P10 (port 10 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.15 Port 11 (P11)
Port 11 is a 4-bit I/O port. Each individual bit can be specified as input or output by the port
11 mode register (P11IO). When output is specified (corresponding bits of P11IO = "1"),
the value of the corresponding bits in the port 11 data register (P11) will be output from their
appropriate pins.
In addition to its port function, P11 is assigned secondary functions (such as WAIT input).
If a secondary function output is to be used, set the corresponding bits of the port 11 mode
register (P11IO) and the port 11 secondary function control register (P11SF) to "1". If a
secondaryfunctioninputistobeused, resetcorrespondingbitsoftheport11moderegister
(P11IO) to "0" to configure the input mode (same input as the primary function input).
If the port is set as an input (corresponding bits of P11IO = "0") and the port 11 secondary
function control register (P11SF) is set to "1", the pin inputs corresponding to those bits will
be pulled-up.
If bits 0 and 1 of port 11 are set as secondary function outputs (P11IOn = 1, P11SFn = 1),
the output will be fixed at "0", regardless of the value of the port 11 data register.
Figure5-18showstheconfigurationoftheport11dataregister(P11), port11moderegister
(P11IO) and the port 11 secondary function control register (P11SF).
7
6
5
4
3
2
1
0
Address: 00BB [H]
R/W access: R/W
—
—
—
—
P11_3 P11_2 P11_1 P11_0
P11
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 00C3 [H]
R/W access: R/W
—
—
—
—
P11IO3 P11IO2 P11IO1 P11IO0
P11IO
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
XTOUT CLKOUT
P11SF3 P11SF2
Address: 00CB [H]
R/W access: R/W
—
—
—
—
P11SF1 P11SF0
P11SF
At reset
0
0
0
0
0
0
0
0
0 (Input setting)
1 (Output setting)
0
1
0
1
0
1
0
1
Not pulled-up
Pulled-up
P11_0 input Primary function P11_0 output
WAIT input
Secondary function
Primary function P11_1 output
Secondary function 0 output*
0 output*
P11_1 input
HOLD mode
request input
Not pulled-up
Pulled-up
Not pulled-up
Pulled-up
Primary function P11_2 output
Secondary function Main clock output
Primary function P11_3 output
Secondary function Sub clock output
P11_2 input
P11_3 input
Not pulled-up
Pulled-up
0 output*: "0" is output, regardless of the value of the port data register
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-18 P11, P11IO, P11SF Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-16 lists the data that is read, depending on the settings of P11IO and P11SF, when
executing an instruction to read P11.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), P11 will become a high impedance input port (P11IO = 00H, P11SF = 00H) and the
contents of P11 will be 00H.
Table 5-16 P11 Read Data
P11IO
P11SF
Read data
0
1
1
0
1
1
0
1
1
0
1
1
*
0
1
*
P11_0/WAIT pin state
Value of bit 0 of P11 (port data register)
"0"
P11_0
P11_1
P11_2
P11_3
5
P11_1/HOLD pin state
Value of bit 1 of P11 (port data register)
"0"
0
1
*
P11_2 pin state
0
1
*
Value of bit 2 of P11 (port data register)
CLKOUT output data
P11_3 pin state
0
1
Value of bit 3 of P11 (port data register)
XTOUT output data
"*" indicates "0" or "1"
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed for P11,
depending on the settings of P11IO and P11SF, values will be read as listed in Table 5-
16. The modified values will be written to P11 (port 11 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.16 Port 12 (P12)
Port 12 is an 8-bit input-only port. Therefore, there is no mode register or secondary
function control register.
The pin status can be read by the port 12 data register (P12).
In addition to its port function, a secondary function (analog input for A/D converter) is
assigned to P12 (same input as the primary function input).
There are no pulled-up inputs at port 12.
Figure 5-19 shows the configuration of the port 12 data register (P12). Table 5-17 lists the
P12 read data.
7
6
5
4
3
2
1
0
Address: 00BC [H]
R/W access: R
P12
P12_7 P12_6 P12_5 P12_4
P12_3 P12_2 P12_1 P12_0
Figure 5-19 P12 Configuration
Table 5-17 P12 Read Data
Read data
P12_0
P12_0/AI0 pin state
P12_1/AI1 pin state
P12_2/AI2 pin state
P12_3/AI3 pin state
P12_4/AI4 pin state
P12_5/AI5 pin state
P12_6/AI6 pin state
P12_7/AI7 pin state
P12_1
P12_2
P12_3
P12_4
P12_5
P12_6
P12_7
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.17 Port 14 (P14)
Port 14 is a 5-bit I/O port. Each individual bit can be specified as input or output by the port
14 mode register (P14IO). When output is specified (corresponding bits of P14IO = "1"),
the value of the corresponding bits in the port 14 data register (P14) will be output from their
appropriate pins.
In addition to its port function, P14 is assigned secondary functions (such as SIO5 receive
data input). If a secondary function output is to be used, set the corresponding bits of the
port 14 mode register (P14IO) and the port 14 secondary function control register (P14SF)
to "1". If a secondary function input is to be used, reset corresponding bits of the port 14
moderegister(P14IO)to"0"toconfiguretheinputmode(sameinputastheprimaryfunction
input).
5
If the port is configured as an input (corresponding bits of P14IO = "0") and the port 14
secondary function control register (P14SF) is set to "1", inputs will be pulled-up at the pins
corresponding to those bits.
If bit 2 of port 14 is configured as a secondary function output (P14IO0 = 1, P14SF0 = 1),
the output will be fixed at "0", regardless of the value of the port 14 data register.
Figure5-20showstheconfigurationoftheport14dataregister(P14), port14moderegister
(P14IO) and the port 14 secondary function control register (P14SF).
7
6
5
4
3
2
1
0
Address: 00BF [H]
R/W access: R/W
P14_7 P14_6
—
—
—
P14_2 P14_1 P14_0
P14
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 00C4 [H]
R/W access: R/W
P14IO7 P14IO6
—
—
—
P14IO2 P14IO1 P14IO0
P14IO
At reset
0
0
0
0
0
0
0
0
7
6
5
—
0
4
—
0
3
2
1
0
SIOO5
P14SF1
AO1
P14SF7 P14SF6
AO0
SIOCK5
P14SF0
Address: 00C6 [H]
R/W access: R/W
—
P14SF2
P14SF
At reset
0
0
0
0
0
0
0 (Input setting)
1 (Output setting)
0
1
Not pulled-up
Pulled-up
Primary function P14_0 output
P14_0 input
SIO5 transmit-
receive clock input
Secondary function SIO5 transmit-
receive clock output
P14_1 input
0
1
Not pulled-up
Pulled-up
Primary function P14_1 output
Secondary function SIO5 transmit
data output
P14_2 input
SIO5 receive
data input
Not pulled-up
Pulled-up
Primary function P14_2 output
0
1
0
1
0
1
Secondary function
0 output*
P14_6 input
Not pulled-up
Pulled-up
Primary function P14_6 output
Secondary function DA0 data output
Primary function P14_7 output
Secondary function DA1 data output
P14_7 input
Not pulled-up
Pulled-up
0 output*: "0" is output, regardless of the value of the port data register
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-20 P14, P14IO, P14SF Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-18 lists the data that is read, depending on the settings of P14IO and P14SF, when
executing an instruction to read P14.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), P14 will become a high impedance input port (P14IO = 00H, P14SF = 00H) and the
contents of P14 will be 00H.
Table 5-18 P14 Read Data
P14IO
P14SF
Read data
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
*
0
1
*
P14_0/SIOCK5 pin state
Value of bit 0 of P14 (port data register)
SIOCK5 output data
P14_0
P14_1
P14_2
P14_6
P14_7
P14_1 pin state
0
1
*
Value of bit 1 of P14 (port data register)
SIOO5 output data
P14_2/SIOI5 pin state
Value of bit 2 of P14 (port data register)
"0"
0
1
*
P14_6 pin state
0
1
*
Value of bit 6 of P14 (port data register)
AO0 output data
P14_7 pin state
0
1
Value of bit 7 of P14 (port data register)
AO1 output data
"*" indicates "0" or "1"
[Note]
If arthmetic, SB, RB, XORB or other read-modify-write instructions are executed for P14,
depending on the settings of P14IO and P14SF, values will be read as listed in Table 5-
18. The modified values will be written to P14 (port 14 data register).
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MSM66577 Family User's Manual
Chapter 5 Port Functions
5.18 Port 15 (P15)
Port 15 is a 4-bit I/O port. Each individual bit can be specified as input or output by the port
15 mode register (P15IO). When output is specified (corresponding bits of P15IO = "1"),
the value of the corresponding bits in the port 15 data register (P15) will be output from their
appropriate pins.
In addition to its port function, P15 is assigned secondary functions (such as SIO6 receive
data input). If a secondary function output is to be used, set the corresponding bits of the
port 15 mode register (P15IO) and the port 15 secondary function control register (P15SF)
to "1". If a secondary function input is to be used, reset corresponding bits of the port 15
moderegister(P15IO)to"0"toconfiguretheinputmode(sameinputastheprimaryfunction
input).
5
If the port is configured as an input (corresponding bits of P15IO = "0") and the port 15
secondary function control register (P15SF) is set to "1", inputs will be pulled-up at the pins
corresponding to those bits.
If bit 0 of port 15 is configured as a secondary function output (P15IO0 = 1, P15SF0 = 1),
the output will be fixed at "0", regardless of the value of the port 15 data register.
Figure5-21showstheconfigurationoftheport15dataregister(P15), port15moderegister
(P15IO) and the port 15 secondary function control register (P15SF).
7
6
5
4
3
2
1
0
Address: 00BF [H]
R/W access: R/W
—
—
—
—
P15_3 P15_2 P15_1 P15_0
P15
At reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Address: 00C5 [H]
R/W access: R/W
—
—
—
—
P15IO3 P15IO2 P15IO1 P15IO0
P15IO
At reset
0
0
0
0
0
0
0
0
7
—
0
6
—
0
5
—
0
4
—
0
3
2
1
0
P15SF0
0
TXC6
RXC6
TXD6
Address: 00C7 [H]
R/W access: R/W
P15SF
At reset
P15SF3 P15SF2 P15SF1
0
0
0
0 (Input setting)
1 (Output setting)
P15_0 input
SIO6 receive
data input
0
1
0
1
Not pulled-up
Pulled-up
Primary function P15_0 output
Secondary function
0 output*
P15_1 input
Not pulled-up
Pulled-up
Primary function P15_1 output
Secondary function SIO6 transmit
data output
P15_2 input
SIO6 receive
clock input
Not pulled-up
Pulled-up
Primary function P15_2 output
0
1
Secondary function SIO6 receive
clock output
P15_3 input
SIO6 transmit
clock input
Not pulled-up
Pulled-up
Primary function P15_3 output
0
1
Secondary function SIO6 transmit
clock output
0 output*: "0" is output, regardless of the value of the port data register
"—" indicates a bit that does not exist. If read, the value will be "0."
Figure 5-21 P15, P15IO, P15SF Configuration
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MSM66577 Family User's Manual
Chapter 5 Port Functions
Table 5-19 lists the data that is read, depending on the settings of P15IO and P15SF, when
executing an instruction to read P15.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), P15 will become a high impedance input port (P15IO = 00H, P15SF = 00H) and the
contents of P15 will be 00H.
Table 5-19 P15 Read Data
P15IO
P15SF
Read data
0
1
1
0
1
1
0
1
1
0
1
1
*
0
1
*
P15_0/RXD6 pin state
Value of bit 0 of P15 (port data register)
"0"
P15_0
P15_1
P15_2
P15_3
P15_1 pin state
0
1
*
Value of bit 1 of P15 (port data register)
TXD6 output data
P15_2/RXC6 pin state
Value of bit 2 of P15 (port data register)
RXC6 output data
0
1
*
P15_3/TXC6 pin state
Value of bit 3 of P15 (port data register)
TXC6 output data
0
1
"*" indicates "0" or "1"
[Note]
If arthmetic, SB, RB, XORB or other read-modify-write instructions are executed for P15,
depending on the settings of P15IO and P15SF, values will be read as listed in Table 5-
19. The modified values will be written to P15 (port 15 data register).
5-40
Chapter 6
Clock Oscillation Circuit
6
MSM66577 Family User's Manual
Chapter 6 Clock Oscillation Circuit
6. Clock Oscillation Circuit
6.1 Overview
The MSM66577 family has two systems of internal clock oscillation circuits, OSC and XT.
Four types of clocks can be selected as the CPU operating clock (CPUCLK): OSCCLK
(main clock), frequency divided clocks (1/2OSCCLK, 1/4OSCCLK), and XTCLK (sub
clock). The current consumed during operation can be reduced by changing the clock in
response to the operating conditions. XT is used mainly for the real-time counter.
Externally generated clocks can be input directly to both OSC and XT.
6.2 Clock Oscillation Circuit Configuration
Figure 6-1 shows the configuration of the clock oscillation circuit.
6
SBYCON
OSCCLK
Clock control circuit
1/2_ frequency
CPUCLK
1/4_ frequency
XTCLK
To real-time
counter
PRPHCON
OSC oscillation circuit
XT oscillation circuit
Internal
External
OSC0
OSC1
XT0
XT1
Crystal or ceramic
oscillator
Crystal oscillator
(32.768 kHz)
OSCCLK: Main clock
XTCLK: Subclock (32.768 kHz)
CPUCLK: CPU operating clock
SBYCON: Standby control register
PRPHCON: Peripheral control register
Figure 6-1 Clock Oscillation Circuit Configuration
6-1
MSM66577 Family User's Manual
Chapter 6 Clock Oscillation Circuit
6.3 Clock Oscillation Circuit Registers
Table 6-1 lists a summary of the SFRs for clock oscillation circuit control.
Table 6-1 Summary of SFRs for Clock Oscillation Circuit Control
Address
[H]
Symbol
(byte)
Symbol
(word)
—
8/16
Initial
Reference
page
Name
R/W
Operation value [H]
000F
Standby control register
SBYCON
R/W
R/W
8
8
08
3-4
0015I Peripheral control register PRPHCON
—
8C
15-2
[Notes]
1. A star (P) in the address column indicates a missing bit.
2. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
6.4 OSC Oscillation Circuit
The OSC oscillation circuit generates the main clock pulse (OSCCLK). A crystal oscillator
and other required elements are connected to OSC0 and OSC1.
Figure 6-2 shows the configuration of the OSC oscillation circuit. Figure 6-3 shows an
example connection of an OSC crystal oscillation circuit.
Internal
Oscillation
control circuit
OSCCLK
OSC0
OSC1
Figure 6-2 OSC Oscillation Circuit Configuration
6-2
MSM66577 Family User's Manual
Chapter 6 Clock Oscillation Circuit
Microcontroller
OSC0
C0
C1
XTAL
Rd
OSC1
Figure 6-3 OSC Crystal Oscillation Circuit Connection Example
[Notes]
1. The values of C0 and C1 must be set based on the specifications of the external
crystal (XTAL).
6
2. Instead of XTAL, a ceramic resonator may be used.
3. Dependinguponthefrequencybandused, additionalcomponents(notshown)may
be required.
Table 6-2 shows examples of circuit constants in the case of using a ceralock of Murata
MFG. make.
Table 6-2 Examples of Circuit Constants
Recommended constants
Operating conditions
Frequency
[Hz]
Temperature
Power supply
voltage range
[V]
Rd
C0
C1
Product number
range
[W]
[pF]
[pF]
[∞C]
CSTLS2M00G56-B0/CSTCC2M00G56-R0
(built-in load capacitor type)
—
—
—
—
2 MHz
4 MHz
10 MHz
680
220
0
CSTLS4M00G56-B0/CSTCK4M00G55-R0
(built-in load capacitor type)
2.4 to 3.6/
4.5 to 5.5
CSTLS10M0G56-B0/CSTCC10M0G056-R0
(built-in load capacitor type)
—
—
–30 to +70
CSACV14M0X55J-R0
14 MHz
20 MHz
10
15
10
15
0
0
CSA20.00MXZ040, CST20.00MXW040
(built-in load capacitor type)
CSA24.00MXZ040, CST24.00MXW0H1
(built-in load capacitor type)
24 MHz
30 MHz
5
5
5
5
0
0
4.5 to 5.5
CSA30.00MXZ040, CST30.00MXW040
(built-in load capacitor type)
6-3
MSM66577 Family User's Manual
Chapter 6 Clock Oscillation Circuit
If the main clock pulse (OSCCLK) is to be supplied externally, connect it directly to the
OSC0 pin input. Leave the OSC1 pin open (unconnected).
Figure 6-4 shows an example connection when the OSC clock is input externally.
Microcontroller
OSC0
External clock
Open
OSC1
Figure 6-4 Connection Example for External OSC Clock Input
[Note]
If an external clock is to be used for operation, keep the clock pulse width as specified by
the AC characteristics.
Thestandbycontrolregister(SBYCON)canbesettohalttheOSCoscillationcircuit. When
resuming oscillation of the OSC oscillation circuit from a halted state, the main clock pulse
(OSCCLK) will be transmit after waiting for the oscillation stabilization time, the number of
clock cycles specified by OST0 and OST1 (bits 4 and 5) of SBYCON. Because the
oscillation stabilization time differs depending upon the oscillator used, externally mounted
components, and the frequency band, first verify the actual oscillation stabilization time of
the circuit board in the product application, and then set SBYCON with the wait time until
suitable oscillation stabilization is achieved.
6-4
MSM66577 Family User's Manual
Chapter 6 Clock Oscillation Circuit
6.5 XT Oscillation Circuit
The XT oscillation circuit generates the subclock pulse (XTCLK). A crystal oscillator of
32.768 kHz and other required elements are connected to XT0 and XT1.
To reduce power consumption, the XT oscillation circuit operates at a voltage level that is
regulated internally. Before an external clock is to be input, set EXTXT (bit 4) of the
peripheral control register (PRPHCON) to "1" (refer to Section 15.3). This switches the
internally regulated voltage to V and turns OFF the oscillation feedback resistors.
DD
Figure 6-5 shows the configuration of the XT oscillation circuit. Figure 6-6 shows an
example connection of the XT crystal oscillation circuit.
Internal
V
DD
Regulator circuit
6
XTCLK
XT
*
XT
*If the EXTXT flag of PRPHCON is set to "1", feedback resistors are OFF.
Figure 6-5 XT Oscillation Circuit Configuration
Microcontroller
XT0
C2
C3
XTAL
XT1
Figure 6-6 XT Crystal Oscillation Circuit Connection Example
[Notes]
1. ThevaluesofC2andC3mustbesetbasedonthespecificationoftheexternalXTAL
(32.768 kHz).
2. BecausetheXToscillationcircuitwasdesignedtobeconnectedtoanextremelylow
powercrystal,theremaynotbeanyoscillationifanothertypeofcrystalisconnected.
6-5
MSM66577 Family User's Manual
Chapter 6 Clock Oscillation Circuit
If the subclock pulse (XTCLK) is to be supplied externally, connect it to the XT0 pin input
and leave the XT1 pin open (unconnected).
Figure 6-7 shows an example connection when the XT clock is input externally.
Microcontroller
XT0
External clock
Open
XT1
Figure 6-7 Connection Example for External XT Clock Input
[Note]
Before an external clock is to be used in the XT oscillation circuit, set EXTXT (bit 4) of
PRPHCON to "1".
The XT oscillation circuit cannot be halted by the program. Because there is no circuit to
controltheoscillationstabilizationtime,fromthetimewhenpoweristurnedonuntiloverflow
ofthereal-timecountercausesbit12(RTC12)tobeset,donotselectthesubclock(XTCLK)
as the CPU operation clock (CPUCLK).
If the sub clock (XTCLK) is not used, fix the XT0 pin at GND level and set EXTXT (bit 4) of
PRPHCON to "1".
6-6
Chapter 7
Time Base Counter (TBC)
7
MSM66577 Family User's Manual
Chapter 7 Time Base Counter (TBC)
7. Time Base Counter (TBC)
7.1 Overview
The MSM66577 family has an 8-bit internal time base counter (TBC) to generate a
reference clock for internal peripheral modules.
The front stage of the TBC has an auto-reload type 4-bit 1/n counter. Base clocks can be
generated for internal peripheral from the wide-ranging CPUCLK frequency.
7.2 Time Base Counter (TBC) Configuration
Figure 7-1 shows the TBC configuration.
TBCOVF
TBCCLK
Frequency
divider
TBC (8bit)
CPUCLK
1/n (4bit)
7
PWM
SIO4, 5
16-bit FRC
16-bit timer 0
8-bit timer 1, 2
8-bit timer 3/BRG
8-bit timer 4/BRG
8-bit timer 5/BRG
8-bit timer 6/WDT
8-bit timer 9
Figure 7-1 TBC Configuration
7-1
MSM66577 Family User's Manual
Chapter 7 Time Base Counter (TBC)
7.3 Time Base Counter Registers
Table 7-1 lists a summary of SFRs for time base counter control.
Table 7-1 Summary of SFRs for Time Base Counter Control
Address
[H]
Symbol
(byte)
Symbol
(word)
8/16
Initial
Reference
page
7-3
Name
R/W
Operation value [H]
0060I TBC clock divider register TBCKDVR
R/W
R
8/16
16
F0
F0
TBCKDV
0061I TBC clock divider counter
—
7-2
[Notes]
1. A star (I) in the address column indicates a missing bit.
2. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
7.4 1/n Counter
To generate base clocks for internal peripheral modules from the wide ranging CPUCLK
frequency, the MSM66577 family is equipped with a 4-bit auto-reload timer into which
CPUCLK is input.
This 1/n counter consists of a 4-bit counter (TBC clock dividing counter) and a 4-bit register
that stores the reload value (TBC clock divider register).
7.4.1 Description of 1/n Counter Registers
(1) TBC clock dividing counter (TBCKDV upper 8 bits)
The TBC clock dividing counter (upper 8 bits of TBCKDV) is a 4-bit counter and its input is
CPUCLK. WhenthecounteroverflowsitisloadedwiththecontentsoftheTBCclockdivider
register (TBCKDVR).
The TBC clock dividing counter (upper 8 bits of TBCKDV) can be accessed only in word
sized units. The value of the TBC clock dividing counter is read from the four bits of bit 8
through bit 11. If the upper 4 bits are read, a value of "1" will always be obtained. The TBC
clock divider register (TBCKDVR) is read from the lower 8 bits of TBCKDV.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the upper 8 bits of TBCKDV become F0H.
Figure 7-2 shows the configuration of the upper 8 bits of TBCKDV.
7-2
MSM66577 Family User's Manual
Chapter 7 Time Base Counter (TBC)
15
—
14
—
13
—
12
—
11
0
10
0
9
8
Address: 0061 [H]
TBCKDV
At reset
R/W access: R (word access only)
0
1
1
1
1
0
Count value of the 1/n
counter can be read
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 7-2 Configuration of Upper 8 Bits of TBCKDV
(2) TBC clock divider register (TBCKDVR)
The TBC clock divider register (TBCKDVR) consists of 4 bits. This register stores the value
to be reloaded into the TBC clock dividing counter.
7
TBCKDVR can be read from or written to by the program. However, write operations are
not valid for bits 4 through 7. If read, bits 4 through 7 are always "1".
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), TBCKDVR becomes F0H.
[Note]
When reset, the 1/n counter divides CPUCLK by 16 and 1/16CPUCLK is supplied to TBC
as TBCCLK. Therefore, after writing a reload value to TBCKDVR, there may be at most
a delay of 16 CPUCLK pulses before the start of the division operation (as per the written
value).
Figure 7-3 shows the configuration of TBCKDVR. Table 7-2 lists the correspondence
between TBCKDVR settings and TBCCLK.
7
—
1
6
—
1
5
—
1
4
—
1
3
0
2
0
1
0
0
0
Address: 0060 [H]
R/W access: R/W
TBCKDVR
At reset
Write/read reload value
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 7-3 TBCKDVR (Lower 8 Bits of TBCKDV) Configuration
7-3
MSM66577 Family User's Manual
Chapter 7 Time Base Counter (TBC)
Table 7-2 Correspondence between TBCKDVR Settings and TBCCLK
Value of TBCKDVR settings [H]
TBCCLK
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1/16 CPUCLK
1/15 CPUCLK
1/14 CPUCLK
1/13 CPUCLK
1/12 CPUCLK
1/11 CPUCLK
1/10 CPUCLK
1/9 CPUCLK
1/8 CPUCLK
1/7 CPUCLK
1/6 CPUCLK
1/5 CPUCLK
1/4 CPUCLK
1/3 CPUCLK
1/2 CPUCLK
1/1 CPUCLK
7.4.2 Example of 1/n Counter-related Register Settings
• TBC clock divider register (TBCKDVR)
This register stores the reload value to the TBC clock dividing counter. When reset (RES
signalinput, executionofaBRKinstruction, overflowofthewatchdogtimer, opcodetrap),
the reload value becomes F0H, and TBCCLK becomes CPUCLK divided by 16 (1/
16CPUCLK). If TBCCLK is set to 1/1CPUCLK, the reload value becomes FFH.
7.5 Time Base Counter (TBC) Operation
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the time base counter (TBC) is reset to "0". Thereafter, as long as the
original oscillation (CPCLK) supply is not halted, operation will continue by TBCCLK that
has been divided by the front stage 1/n counter.
OverflowofTBCisdividedfurtherbyafrequencydividercircuit,andsuppliedtothegeneral-
purpose 8-bit timer 6 (that also functions as the watchdog timer).
7-4
Chapter 8
General-Purpose 8/16 Bit Timers
8
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8. General-Purpose 8/16 Bit Timers
8.1 Overview
The MSM66577 family has the following internal general-purpose timers: a 16-bit auto-
reload timer (timer 0), six 8-bit auto-reload timers (timers 1, 2, 3, 4, 5, and 9), and an 8-bit
auto-reload timer that also functions as a watchdog timer (timer 6). Timers 1 and 2 can be
combined and used as a 16-bit timer.
8.2 General-purpose 8-bit/16-bit Timer Configurations
Table 8-1 lists a summary of the function of each general-purpose timer. Marks ( ) within
the table indicate that a function can be selected. Dashes (—) indicate that the function
cannot be selected.
Table 8-1 Timer Configurations and Functions
Timer
name
External
Timer
PWM clock Baud rate
Watchdog
8/16 bits Auto-reload
event input
output
output
—
generator
—
timer
—
8
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 9
16
8/16
8/16
8
—
—
—
—
—
—
—
—
—
—
—
—
—
(SIO6)
(SIO1)
(SIO4, 5)
—
—
8
—
—
8
—
—
—
—
—
8
—
8
—
—
[Note]
TMOUT of timers 3, 5 and 9 are not output on ports, but can be used by software as a flag.
8-1
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.3 General-purpose 8-bit/16-bit Timer Registers
Table8-2listsasummaryofSFRsforthecontrolofgeneral-purpose8-bitand16-bittimers.
Table 8-2 Summary of SFRs for General-Purpose 8-bit/16-bit Timer Control
Address
[H]
Symbol
(byte)
Symbol
(word)
8/16
Initial
Reference
page
Name
R/W
Operation value [H]
0062
0063
0064
0065
General-purpose 16-bit
timer 0 counter
—
—
TM0C R/W
TM0R R/W
16
16
16
8/16
8/16
8
Undefined
Undefined
70
8-4
General-purpose 16-bit
timer 0 register
8-4
General-purpose 16-bit
timer 0 control register
General-purpose 8-bit
timer 12 counter
0066I
TM0CON
—
R/W
8-4
0068
0069
006A
006B
TM1C
TM2C
TM1R
TM2R
TM12C R/W
TM12R R/W
Undefined
Undefined
70
8-10
8-10
8-10
8-11
8-22
8-22
8-22
8-28
8-28
8-28
8-34
8-34
8-34
8-40
8-40
8-41
8-49
8-49
8-49
General-purpose 8-bit
timer control register
General-purpose 8-bit
timer 1 control register
General-purpose 8-bit
timer 2 control register
General-purpose 8-bit
timer 3 counter
006CI
006DI
0070
TM1CON
TM2CON
TM3C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
40
8
Undefined
Undefined
70
General-purpose 8-bit
timer 3 register
0071
TM3R
8
General-purpose 8-bit
timer 3 control register
General-purpose 8-bit
timer 4 counter
0072I
0074
TM3CON
TM4C
8
8
Undefined
Undefined
70
General-purpose 8-bit
timer 4 register
0075
TM4R
8
General-purpose 8-bit
timer 4 control register
General-purpose 8-bit
timer 5 counter
0076I
0078
TM4CON
TM5C
8
8
Undefined
Undefined
Undefined
Undefined
Undefined
10
General-purpose 8-bit
timer 5 register
0079
TM5R
8
General-purpose 8-bit
timer 5 control register
General-purpose 8-bit
timer 6 counter
007AI
007C
TM5CON
TM6C
8
8
General-purpose 8-bit
timer 6 register
007D
TM6R
8
General-purpose 8-bit
timer 6 control register
General-purpose 8-bit
timer 9 counter
007EI
00CC
00CD
00CEI
TM6CON
TM9C
8
8
Undefined
Undefined
70
General-purpose 8-bit
timer 9 register
TM9R
8
General-purpose 8-bit
timer 9 control register
TM9CON
8
[Notes]
1. Addresses are not consecutive in some places.
2. A star (P) in the address column indicates a missing bit.
3. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
4. Bits 5 and 6 of the TM6COM register allow read only access (W is invalid). Bits 0
to 3 and 7 allow R/W access.
8-2
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.4 Timer 0
Timer 0 is a 16-bit auto-reload timer that has functions for external event input and timer
output.
8.4.1 Timer 0 Configuration
Figure 8-1 shows the timer 0 configuration.
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
OVF
Interrupt request
TM0C (16bit)
≠
1/16 TBCCLK
1/32 TBCCLK
1/64 TBCCLK
TM0EVT falling edge
(P5_7)
D
TM0OUT (P5_6)
Q
CK
Q
TM0R (16bit)
TM0CON
8
TM0C: General-purpose 16-bit timer 0 counter
TM0R: General-purpose 16-bit timer 0 register
TM0CON: General-purpose 16-bit timer 0 control register
TM0EVT: Timer 0 external event input pin (P5_7)
TM0OUT: Timer 0 output pin (P5_6)
Figure 8-1 Timer 0 Configuration
8-3
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.4.2 Description of Timer 0 Registers
(1) General-purpose 16-bit timer 0 counter (TM0C)
The general-purpose 16-bit timer 0 counter (TM0C) is a 16-bit up-counter. When this
counter overflows, an interrupt request is generated and it is loaded with the contents of
general-purpose 16-bit timer 0 register (TM0R).
TM0C can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM0C are undefined.
[Note]
Writing a timer value to TM0C causes the same value to also be written to the general-
purpose 16-bit timer 0 register (TM0R).
(2) General-purpose 16-bit timer 0 register (TM0R)
The general-purpose 16-bit timer 0 register (TM0R) consists of 16 bits. This register stores
the value to be reloaded into the general-purpose 16-bit timer 0 counter (TM0C).
TM0R can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM0R are undefined.
(3) General-purpose 16-bit timer 0 control register (TM0CON)
The general-purpose 16-bit timer 0 control register (TM0CON) consists of 5 bits. Bits 0 to
2 (TM0C0 to TM0C2) of TM0CON select the timer 0 count clock, bit 3 (TM0RUN) starts or
halts the counting, and bit 7 (TM0OUT) specifies the initial timer output level (High or Low)
at start-up.And each time TM0C overflows, the content of bit 7 (TM0OUT) is reversed.
TM0CON can be read from and written to by the program. However, write operations are
invalid for bits 4 to 6. If read, a value of "1" will always be obtained for bits 4 to 6.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), TM0CON becomes 70H.
Figure 8-2 shows the TM0CON configuration.
[Note]
Just before TM0C overflows, if an SB, RB, XORB or other read-modify-write instruction
is performed on TM0CON, then TM0OUT may not operate correctly.
8-4
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
7
6
—
1
5
—
1
4
—
1
3
2
1
0
Address: 0066 [H]
R/W access: R/W
TM0CON TM0OUT
TM0RUN TM0C2 TM0C1 TM0C0
At reset
0
0
0
0
0
TM0C
Timer 0 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/16 TBCCLK
1/32 TBCCLK
1/64 TBCCLK
TM0EVT (falling edge)
0
1
Timer 0 halt counting
Timer 0 start counting
0
1
Low level output
High level output
8
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 8-2 TM0CON Configuration
8-5
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.4.3 Example of Timer 0-related Register Settings
(1) Port 5 mode register (P5IO)
If TM0OUT (timer output) is to be used, set bit 6 (P5IO6) to "1" to configure the port as an
output. If TM0EVT (event input) is to be used, reset bit 7 (P5IO7) to "0" to configure the port
as an input.
(2) Port 5 secondary function control register (P5SF)
If TM0OUT (timer output) is to be used, set bit 6 (P5SF6) to "1" to configure the port as a
secondaryfunctionoutput. IfTM0EVT(eventinput)istobeused,disableorenablethepull-
up resistor with bit 7 (P5SF7).
(3) General-purpose 16-bit timer 0 counter (TM0C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM0C,thesame
value will also be simultaneously and automatically written to the general-purpose 16-bit
timer 0 register (TM0R).
(4) General-purpose 16-bit timer 0 register (TM0R)
This register sets the value to be loaded after general-purpose 16-bit timer 0 counter
(TM0C)overflows. Ifthetimervalue(TM0C)andthereloadvalue(TM0R)areidentical, this
register will automatically be set just by setting TM0C. If the values are different or are to
be modified, this register must be set explicitly.
(5) General-purpose 16-bit timer 0 control register (TM0CON)
Bits 0 to 2 (TM0C0 to TM0C2) of this register set the count clock for timer 0. If TM0OUT
(timer output) is to be used, specify the initial value with bit 7 (TM0OUT). If bit 3 (TM0RUN)
is set to "1", timer 0 will begin counting. If reset to "0", timer 0 will halt counting.
8-6
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.4.4 Timer 0 Operation
When the TM0RUN bit is set to "1", timer 0 will begin counting upward, running on the count
clock selected by TM0CON. If external event input is selected as the count clock, timer 0
can also be used as an event counter. When TM0C overflows, an interrupt request is
generated,thecontentsofTM0RareloadedintoTM0CandtheTM0OUToutputisinverted.
The initial value of the TM0OUT pin is specified by bit 7 (TM0OUT) of TM0CON. This
operation is repeated until the TM0RUN bit is reset to "0". Figure 8-3 shows an operation
example (for settings of 1/n counter frequency division ratio 1/1and 1/4 TBCCLK).
CPUCLK
TM count CLK
(1/4 TBCCLK)
TM0R
0055H
0055H
TM0C
FFFEH
FFFFH
0056H
Overflow signal
8
TM0OUT
Interrupt request generated
Figure 8-3 Timer 0 Operation
[Note]
Set the minimum pulse width of the external event input to at least 1 CPU clock
(CPUCLK). The external event input signal is sampled at the falling edge of the CPUCLK
to create the count clock for the timer.
8-7
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.4.5 Timer 0 Interrupt
When a timer 0 interrupt factor occurs, the interrupt request flag (QTM0OV) is set to "1".
The interrupt request flag (QTM0OV) is located in interrupt request register 1 (IRQ1).
Interrupts can be enabled or disabled by the interrupt enable flag (ETM0OV). The interrupt
enable flag (ETM0OV) is located in interrupt enable register 1 (IE1).
Three levels of priority can be set with the interrupt priority setting flags (P0TM0OV and
P1TM0OV). The interrupt priority setting flags are located in interrupt priority control
register 2 (IP2).
Table 8-3 lists the vector address of the timer 0 interrupt factor and the interrupt processing
flags.
Table 8-3 Timer 0 Vector Address and Interrupt Processing Flags
Vector
address [H]
001A
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
1
0
Overflow of timer 0
QTM0OV
ETM0OV
P1TM0OV
P0TM0OV
Symbols (byte) of registers that
contain interrupt processing flags
IRQ1
IE1
IP2
17-24
Reference page
17-13
17-18
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
8-8
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.5 Timers 1 and 2
Timers 1 and 2 are 8-bit auto-reload timers. Timers 1 and 2 can be combined and used
in a 16-bit auto-reload mode. Timers 1 and 2 have functions for external event input, timer
output, and PWM mode.
8.5.1 Timers 1 and 2 Configurations
Figure 8-4 shows the configuration of timers 1 and 2.
Interrupt request
D
Q
TM1OUT
(P6_5)
TBC
1/2 TBC
OVF
Q
R
TM1C (8bit)
1/4 TBC
1/8 TBC
1/32 TBC
S
R
Q
Load
MODPWM controller
Q
1/256 TBC
TM1EVT rising edge
TM1R
TM1EVT falling edge
(P6_4)
8
TM2OUT
(P6_7)
D
Q
TM1CON
Q
R
TM2C (8bit)
TBC
1/2 TBC
1/4 TBC
OVF
≠
1/8 TBC
1/32 TBC
1/256 TBC
TM2R
Interrupt
request
TM2EVT rising edge
TM2EVT falling edge
(P6_6)
TM2CON
MOD16
Reset signal
MODPWN
TM1C:
TM2C:
TM1R:
TM2R:
General-purpose 8-bit timer 1 counter
General-purpose 8-bit timer 2 counter
General-purpose 8-bit timer 1 register
General-purpose 8-bit timer 2 register
TM1CON: General-purpose 8-bit timer 1 control register
TM2CON: General-purpose 8-bit timer 2 control register
TM1EVT: Timer 1 external event input pin (P6_4)
TM2EVT: Timer 2 external event input pin (P6_6)
TM1OUT: Timer 1 output pin (P6_5)
TM2OUT: Timer 2 output pin (P6_7)
Figure 8-4 Timer 1 and 2 Configurations
8-9
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.5.2 Description of Timer 1 and 2 Registers
(1) General-purpose 8-bit timer 1 and 2 counters (TM1C, TM2C)
The general-purpose 8-bit timer 1 and 2 counters (TM1C, TM2C) are 8-bit up-counters.
When each counter overflows, an interrupt request is generated and that counter is loaded
with the contents of the general-purpose 8-bit timer 1 or 2 register (TM1R, TM2R).
TM1C and TM2C can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM1C and TM2C are undefined.
[Note]
Writing a timer value to TM1C or TM2C causes the same value to also be written to the
general-purpose 8-bit timer 1 and 2 registers (TM1R, TM2R).
(2) General-purpose 8-bit timer 1 and 2 registers (TM1R, TM2R)
The general-purpose 8-bit timer 1 and 2 registers (TM1R, TM2R) consist of 8 bits. These
registers store the value to be reloaded into the general-purpose 8-bit timer 1 or 2 counter
(TM1C, TM2C).
TM1R and TM2R can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM1R and TM2R are undefined.
(3) General-purpose 8-bit timer 1 control register (TM1CON)
The general-purpose 8-bit timer 1 control register (TM1CON) consists of 5 bits. Bits 0 to
2 (TM1C0 to TM1C2) of TM1CON select the timer 1 count clock, bit 3 (TM1RUN) starts or
stops the counting, and bit 7 (TM1OUT) specifies the initial timer output level (High or Low)
at start-up. The value of bit 7 (TM1OUT) is inverted when TM1C overflows.
TM1CON can be read from and written to by the program. However, write operations are
invalid for bits 4 to 6. If read, a value of "1" will always be obtained for bits 4 to 6.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), TM1CON becomes 70H.
Figure 8-5 shows the TM1CON configuration.
8-10
MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
7
6
—
1
5
—
1
4
—
1
3
2
1
0
Address: 006C [H]
R/W access: R/W
TM1CON TM1OUT
TM1RUN TM1C2 TM1C1 TM1C0
At reset
0
0
0
0
0
TM1C
Timer 1 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
TM1EVT (rising edge)
TM1EVT ( falling edge)
0
1
Timer 1 halt counting
Timer 1 start counting
0
1
Low level output
High level output
"—" indicates a nonexistent bit.
When read, its value will be "1".
8
Figure 8-5 TM1CON Configuration
(4) General-purpose 8-bit timer 2 control register (TM2CON)
The general-purpose 8-bit timer 2 control register (TM2CON) consists of 7 bits. TM2CON
can be read from and written to by the program. However, write operation are invalid for
bit 6. If read, a value of "1" will always be obtained for bit 6.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), TM2CON becomes 40H.
Figure 8-6 shows the TM2CON configuration.
[Description of each bit]
• TM2C0 to TM2C2 (bits 0 to 2)
These bits specify the timer 2 count clock.
• TM2RUN (bit 3)
This bit starts or stops the counting.
• MOD16 (bit 4)
Setting this bit combines timer 1 and 2 into the 16-bit auto-reload mode. While this bit is
set, the settings of TM2C0 to TM2C2 and TM2RUN are invalid.
• MODPWM (bit 5)
Settingthisbitcombinestimer1and2intothePWMmode. Whilethisbitisset, thesetting
of TM2RUN is invalid, and if TM1RUN is set, timer 1 and 2 will count simultaneously.
• TM2OUT (bit 7)
This bit specifies the initial timer output level (High or Low) at start-up. The value of bit
7 (TM2OUT) is inverted whenever TM2C overflows.
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Chapter 8 General-Purpose 8/16 Bit Timers
7
6
—
1
5
4
3
2
1
0
Address: 006D [H]
R/W access: R/W
TM2CON TM2OUT
MODPWM MOD16 TM2RUN TM2C2 TM2C1 TM2C0
At reset
0
0
0
0
0
0
0
TM2C
Timer 2 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
TM2EVT (rising edge)
TM2EVT (falling edge)
0
1
Timer 2 halt counting
Timer 2 start counting
0
1
8-bit auto-reload timer mode
16-bit auto-reload timer mode
0
1
Auto-reload timer mode
PWM mode
0
1
Low level output
High level output
"—" indicates a nonexistent bit.
When read, its value will be "1".
Figure 8-6 TM2CON Configuration
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Chapter 8 General-Purpose 8/16 Bit Timers
8.5.3 Example of Timer 1- and 2-related Register Settings
• 8-bit auto-reload timer mode (Timer 1)
(1) Port 6 mode register (P6IO)
If TM1OUT (timer output) is to be used, set bit 5 (P6IO5) to "1" to configure the port as an
output. If TM1EVT (event input) is to be used, reset bit 4 (P6IO4) to "0" to configure the port
as an input.
(2) Port 6 secondary function control register (P6SF)
If TM1OUT (timer output) is to be used, set bit 5 (P6SF5) to "1" to configure the port as a
secondaryfunctionoutput. IfTM1EVT(eventinput)istobeused,disableorenablethepull-
up resistor with bit 4 (P6SF4).
(3) General-purpose 8-bit timer 1 counter (TM1C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM1C,thesame
value will also be simultaneously and automatically written to the general-purpose 8-bit
timer 1 register (TM1R).
(4) General-purpose 8-bit timer 1 register (TM1R)
Thisregistersetsthevaluetobeloadedaftergeneral-purpose8-bittimer1counter(TM1C)
overflows. Ifthetimervalue(TM1C)andthereloadvalue(TM1R)areidentical, thisregister
will automatically be set just by setting TM1C. If the values are different or are to be
modified, this register must be set explicitly.
8
(5) General-purpose 8-bit timer 1 control register (TM1CON)
Bits 9 to 0 (TM1C0 to TM1C2) of this register specify the count clock for timer 1. If TM1OUT
(timer output) is to be used, specify the initial value with bit 7 (TM1OUT). If bit 3 (TM1RUN)
is set to "1", timer 1 will begin counting. If reset to "0", timer 1 will halt counting.
• 8-bit auto-reload timer mode (Timer 2)
(1) Port 6 mode register (P6IO)
If TM2OUT (timer output) is to be used, set bit 7 (P6IO7) to "1" to configure the port as an
output. If TM2EVT (event input) is to be used, reset bit 6 (P6IO6) to "0" to configure the port
as an input.
(2) Port 6 secondary function control register (P6SF)
If TM2OUT (timer output) is to be used, set bit 7 (P6SF7) to "1" to configure the port as a
secondaryfunctionoutput. IfTM2EVT(eventinput)istobeused,disableorenablethepull-
up resistor with bit 6 (P6SF6).
(3) General-purpose 8-bit timer 2 counter (TM2C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM2C,thesame
value will also be simultaneously and automatically written to the general-purpose 8-bit
timer 2 register (TM2R).
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Chapter 8 General-Purpose 8/16 Bit Timers
(4) General-purpose 8-bit timer 2 register (TM2R)
Thisregistersetsthevaluetobeloadedaftergeneral-purpose8-bittimer2counter(TM2C)
overflows. Ifthetimervalue(TM2C)andthereloadvalue(TM2R)areidentical, thisregister
will automatically be set just by setting TM2C. If the values are different or are to be
modified, this register must be set explicitly.
(5) General-purpose 8-bit timer 2 control register (TM2CON)
Bits 0 to 2 (TM2C0 to TM2C2) of this register specify the count clock for timer 2. If TM2OUT
(timer output) is to be used, specify the initial value with bit 7 (TM2OUT). If bit 3 (TM2RUN)
is set to "1", timer 2 will begin counting. If reset to "0", timer 2 will halt counting.
• 16-bit auto-reload timer mode
(1) Port 6 mode register (P6IO)
If TM1OUT (timer 1 output) and TM2OUT (timer 2 output) are to be used, set bits 5 and 7
(P6IO5, P6IO7) to "1" to configure the ports as outputs. If TM1EVT (event input) is to be
used, reset bit 4 (P6IO4) to "0" to configure the port as an input.
(2) Port 6 secondary function control register (P6SF)
If TM1OUT (timer 1 output) and TM2OUT (timer 2 output) are to be used, set bits 5 and 7
(P6SF5, P6SF7) to "1" to configure the ports as secondary function outputs. If TM1EVT
(event input) is to be used, disable or enable the pull-up resistor with bit 4 (P6SF4).
(3) General-purpose 16-bit timer 12 counter (TM12C)
Set the timer value that will be valid at the start of counting. When writing to TM12C, the
same value will also be simultaneously and automatically written to the general-purpose 8-
bit timer 12 register (TM12R).
(4) General-purpose 16-bit timer 12 register (TM12R)
This register sets the value to be loaded after general-purpose 16-bit timer 12 counter
(TM12C)overflows. Ifthetimervalue(TM12C)andthereloadvalue(TM12R)areidentical,
this register will automatically be set just by setting TM12C. If the values are different or
are to be modified, this register must be set explicitly.
(5) General-purpose 8-bit timer 1 control register (TM1CON)
Bits 0 to 2 (TM1C0 to TM1C2) of this register specify the count clock for timer 1. If TM1OUT
(timer1output)istobeused,specifytheinitialvaluewithbit7(TM1OUT). Ifbit3(TM1RUN)
is set to "1", timer 1 will begin counting. If reset to "0", timer 1 will halt counting.
(6) General-purpose 8-bit timer 2 control register (TM2CON)
Setting bit 4 (MOD16) to "1" sets the 16-bit timer mode. While this bit is set, bits 0 to 2
(TM2C0 to TM2C2) and bit 3 (TM2RUN) settings are invalid and setting bit 3 (TM1RUN)
of the timer 1 control register (TM1CON) to "1" starts simultaneous counting of timers 1 and
2. If TM2OUT (timer 2 output) is to be used, specify the initial value with bit 7 (TM2OUT).
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Chapter 8 General-Purpose 8/16 Bit Timers
• PWM mode
(1) Port 6 mode register (P6IO)
If TM1OUT (timer 1 output) and TM2OUT (timer 2 output) are to be used, set bits 5 and 7
(P6IO5, P6IO7) to "1" to configure the ports as outputs. If TM1EVT and TM2EVT (event
inputs) are to be used, reset bit 4 and 6 (P6IO4, P6IO6) to "0" to configure the ports inputs.
(2) Port 6 secondary function control register (P6SF)
If TM1OUT (timer 1 output) and TM2OUT (timer 2 output) are to be used, set bits 5 and 7
(P6SF5,P6SF7)to"1"toconfiguretheportsassecondaryfunctionoutputs. IfTM1EVTand
TM2EVT (event input) are to be used, disable or enable the pull-up resistor with bits 4 and
6 (P6SF4, P6SF6).
(3) General-purpose 16-bit timer 12 counter (TM12C)
Set the timer value that will be valid at the start of counting. When writing to TM12C, the
same value will also be simultaneously and automatically written to the general-purpose 8-
bit timer 12 register (TM12R).
8
(4) General-purpose 16-bit timer 12 register (TM12R)
This register sets the value to be loaded after general-purpose 16-bit timer 12 counter
(TM12C)overflows. Ifthetimervalue(TM12C)andthereloadvalue(TM12R)areidentical,
this register will automatically be set just by setting TM12C. If the values are different or
are to be modified, this register must be set explicitly.
(5) General-purpose 8-bit timer 1 control register (TM1CON)
Bits 0 to 2 (TM1C0 to TM1C2) of this register specify the count clock for timer 1. If TM1OUT
(timer1output)istobeused,specifytheinitialvaluewithbit7(TM1OUT). Ifbit3(TM1RUN)
is set to "1", timer 1 will begin counting. If reset to "0", timer 1 will halt counting.
(6) General-purpose 8-bit timer 2 control register (TM2CON)
Setting bit 5 (MODPWM) to "1" sets the PWM mode. While this bit is set, bit 3 (TM2RUN)
settings are invalid; setting bit 3 (TM1RUN) of the timer 1 control register (TM1CON) to "1",
starts simultaneous counting of timers 1 and 2. If TM2OUT (timer 2 output) is to be used,
specify the initial value with bit 7 (TM2OUT).
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Chapter 8 General-Purpose 8/16 Bit Timers
8.5.4 Timer 1 and 2 Operation
• 8-bit auto-reload timer mode
When the RUN bits corresponding to TM1 and TM2 are set to "1", timers 1 and 2 will begin
counting upward, running on the count clocks selected by TM1CON and TM2CON. When
TM1CandTM2Coverflow,individualinterruptrequestsaregenerated,andthecorresponding
contents of TM1R and TM2R are loaded into TM1C and TM2C. In addition, the output of
TM1OUT and TM2OUT is inverted. This operation is repeated until the RUN bits are reset
to "0". Figure 8-7 shows an example of 8-bit auto-reload timer mode operation.
CPUCLK
TM count CLK
(1/4 CLK)
TM1R, TM2R
55H
TM1C, TM2C
FEH
FFH
55H
56H
Overflow signal
TMOUT
Interrupt request generated
Figure 8-7 8-Bit Auto-Reload Timer Mode Operation Example
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Chapter 8 General-Purpose 8/16 Bit Timers
• 16-bit auto-reload timer mode
Setting the MOD16 bit of TM2CON to "1" combines TM1 and TM2 to set the 16-bit auto-
reload timer mode. TM2C counts upward, using overflow of TM1C as the count clock.
When TM2C overflows, a timer 2 interrupt request is generated, and the contents of TM1R
and TM2R are loaded into TM1C and TM2C respectively. In addition, the output of
TM2OUT is inverted.
During this mode, overflow of TM1C does not cause the contents of TM1R to be loaded.
However, a timer 1 interrupt request will be generated and the output of TM1OUT will
change.
CLK
TM count CLK
(1/4 CLK)
55H
99H
TM1R
TM2R
8
00H
A1H
FFH
55H
99H
FEH
FFH
TM1C
TM1 overflow signal
FFH
A0H
TM2C
TM2 overflow signal
TM1OUT
TM2OUT
Interrupt request generated
TM1, TM2 interrupt
requests generated
Figure 8-8 16-Bit Auto-Reload Timer Mode Operation Example
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Chapter 8 General-Purpose 8/16 Bit Timers
• PWM mode
Setting the MODPWM bit of TM2CON to "1" sets the PWM mode that uses TM1 and TM2.
During the PWM mode, since the following operation is performed, use TM2C as the PWM
cycle counter and TM1C as the duty control counter.
When TM1C overflows, an interrupt request is generated, and the PWM F/F is set. When
TM2C overflows, an interrupt request is generated, the contents of TM1R and TM2R are
loaded into TM1C and TM2C respectively, and the PWM F/F is reset. If "set" and "reset"
of the PWM F/F are simultaneously generated, priority is given to the "reset".
The Q output (positive phase) of the PWM F/F is output from TM1OUT and the Q output
of the PWM F/F (inverted phase) is output from TM2OUT.
Note that if the count clock selected for TM1C is faster than the TM2C count clock, interrupt
requests due to TM1C overflow may occur two or more times in a single cycle.
Also note that if the count clock selected for TM1C is slower than the TM2C count clock,
at the start of counting (when TM1RUN is set), and when TM2C overflows, a synchronous
shift will occur, and the TM1C overflow cycle may shift. (The same count clocks are
recommended.)
FFH = OVF
Reload value
TM1C
00H
FFH = OVF
TM2C
Reload value
00H
TM1OUT
TM2OUT
TM1RUN
set
TM1OVF
TM2OVF
TM1OVF
TM2OVF
TM1OVF
Interrupt Interrupt Interrupt Interrupt Interrupt
request request request request request
Figure 8-9 PWM Timer Mode Operation Example
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Chapter 8 General-Purpose 8/16 Bit Timers
8.5.5 Timer 1 and 2 Interrupts
• Timer 1 interrupt
Whenatimer1interruptfactoroccurs,theinterruptrequestflag(QTM1OV)issetto"1". The
interrupt request flag (QTM1OV) is located in interrupt request register 1 (IRQ1).
Interrupts can be enabled or disabled by the interrupt enable flag (ETM1OV). The interrupt
enable flag (ETM1OV) is located in interrupt enable register 1 (IE1).
Three levels of priority can be set with the interrupt priority setting flags (P0TM1OV and
P1TM1OV). The interrupt priority setting flags are located in interrupt priority control
register 3 (IP3).
Table 8-4 lists the vector address and interrupt processing flags for the timer 1 interrupt
factor.
Table 8-4 Timer 1 Vector Address and Interrupt Processing Flags
Priority level
Vector address
[H]
Interrupt
request
Interrupt
enable
Interrupt factor
1
0
8
Overflow of timer 1
0022
QTM1OV
ETM1OV
P1TM1OV
P0TM1OV
Symbols (byte) of registers that contain
interrupt processing flags
Reference page
IRQ1
IE1
IP3
17-25
17-13
17-18
Forfartherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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Chapter 8 General-Purpose 8/16 Bit Timers
• Timer 2 interrupt
Whenatimer2interruptfactoroccurs,theinterruptrequestflag(QTM2OV)issetto"1". The
interrupt request flag (QTM2OV) is located in interrupt request register 1 (IRQ1).
Interrupts can be enabled or disabled by the interrupt enable flag (ETM2OV). The interrupt
enable flag (ETM2OV) is located in interrupt enable register 1 (IE1).
Three levels of priority can be set with the interrupt priority setting flags (P0TM2OV and
P1TM2OV). The interrupt priority setting flags are located in interrupt priority control
register 3 (IP3).
Table 8-5 lists the vector address and interrupt processing flags for the timer 2 interrupt
factor.
Table 8-5 Timer 2 Vector Address and Interrupt Processing Flags
Priority level
Vector address
[H]
Interrupt
request
Interrupt
enable
Interrupt factor
1
0
Overflow of timer 2
0024
QTM2OV
ETM2OV
P1TM2OV
P0TM2OV
Symbols (byte) of registers that contain
interrupt processing flags
Reference page
IRQ1
IE1
IP3
17-25
17-13
17-18
Forfartherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.6 Timer 3
Timer 3 is an 8-bit auto-reload timer that has a baud rate generator function for SIO6.
TM3OUT is not output on ports, but can be used by software as a flag.
8.6.1 Timer 3 Configuration
Figure 8-10 shows the timer 3 configuration.
OVF
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
Interrupt request
TM3C (8bit)
≠
TM3OUT
D
Q
CK
Q
TM3R (8bit)
Baud rate for
SIO6
TM3CON
8
TM3C: General-purpose 8-bit timer 3 counter
TM3R: General-purpose 8-bit timer 3 register
TM3CON: General-purpose 8-bit timer 3 control register
Figure 8-10 Timer 3 Configuration
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Chapter 8 General-Purpose 8/16 Bit Timers
8.6.2 Description of Timer 3 Registers
(1) General-purpose 8-bit timer 3 counter (TM3C)
Thegeneral-purpose8-bittimer3counter(TM3C)isan8-bitup-counter. Whenthiscounter
overflows, an interrupt request is generated and it is loaded with the contents of general-
purpose 8-bit timer 3 register (TM3R). TM3C can also be used as a baud rate generator
for SIO6.
TM3C can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM3C are undefined.
[Note]
Writing a timer value to TM3C causes the same value to also be written to the general-
purpose 8-bit timer 3 register (TM3R).
(2) General-purpose 8-bit timer 3 register (TM3R)
The general-purpose 8-bit timer 3 register (TM3R) consists of 8 bits. This register stores
the value to be reloaded into the general-purpose 8-bit timer 3 counter (TM3C).
TM3R can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM3R are undefined.
(3) General-purpose 8-bit timer 3 control register (TM3CON)
The general-purpose 8-bit timer 3 control register (TM3CON) consists of 5 bits. Bits 0 to
2 (TM3C0 to TM3C2) of TM3CON select the timer 3 count clock, bit 3 (TM3RUN) starts or
halts the counting, and bit 7 (TM3OUT) specifies the initial timer output level (High or Low)
at start-up. And each time TM3C overflows, the content of bit 7 (TM3OUT) is reversed.
TM3CON can be read from and written to by the program. However, write operations are
invalid for bits 4 to 6. If read, a value of "1" will always be obtained for bits 4 to 6.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), TM3CON becomes 70H.
Figure 8-11 shows the TM3CON configuration.
[Note]
Just before TM3C overflows, if an SB, RB, XORB or other read-modify-write instruction
is performed on TM3CON, then TM3OUT may not operate correctly.
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Chapter 8 General-Purpose 8/16 Bit Timers
7
TM3OUT
0
6
—
1
5
—
1
4
—
1
3
2
1
0
Address: 0072 [H]
R/W access: R/W
TM3RUN TM3C2 TM3C1 TM3C0
TM3CON
At reset
0
0
0
0
TM3C
Timer 3 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
Prohibited setting
Prohibited setting
0
1
Timer 3 halt counting
Timer 3 start counting
0
1
Low level output
High level output
8
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 8-11 TM3CON Configuration
[Note]
Do not select a timer 3 count clock setting that is prohibited. If a "prohibited setting" is
selected, timer 3 will not operate properly.
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Chapter 8 General-Purpose 8/16 Bit Timers
8.6.3 Example of Timer 3-related Register Settings
(1) General-purpose 8-bit timer 3 counter (TM3C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM3C,thesame
value will also be simultaneously and automatically written to the general-purpose 8-bit
timer 3 register (TM3R).
(2) General-purpose 8-bit timer 3 register (TM3R)
Thisregistersetsthevaluetobeloadedaftergeneral-purpose8-bittimer3counter(TM3C)
overflows. Ifthetimervalue(TM3C)andthereloadvalue(TM3R)areidentical, thisregister
will automatically be set just by setting TM3C. If the values are different or are to be
modified, this register must be set explicitly.
(3) General-purpose 8-bit timer 3 control register (TM3CON)
Bits 0 to 2 (TM3C0 to TM3C2) of this register specify the count clock for timer 3. If TM3OUT
(timer output) is to be used, specify the initial value with bit 7 (TM3OUT). If bit 3 (TM3RUN)
is set to "1", timer 3 will begin counting. If reset to "0", timer 3 will halt counting.
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Chapter 8 General-Purpose 8/16 Bit Timers
8.6.4 Timer 3 Operation
When the TM3RUN bit is set to "1", timer 3 will begin counting upward, running on the count
clock selected by TM3CON. When TM3C overflows, an interrupt request is generated, the
contents of TM3R are loaded into TM3C and the TM3OUT output is inverted. The initial
value of the TM3OUT pin is specified by bit 7 (TM3OUT) of TM3CON. This operation is
repeated until the TM3RUN bit is reset to "0". Overflow of TM3C can be used as a baud
rate generator for SIO6. Figure 8-12 shows an operation example (for settings of 1/n
counter frequency division ratio 1/1 and 1/4 TBCCLK).
CPUCLK
TM count CLK
(1/4 TBCCLK)
TM3R
55H
TM3C
FEH
FFH
55H
56H
Overflow signal
8
(SIO6 baud rate)
TM3OUT
Interrupt request generated
Figure 8-12 Timer 3 Operation Example
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Chapter 8 General-Purpose 8/16 Bit Timers
8.6.5 Timer 3 Interrupt
When a timer 3 interrupt factor occurs, the interrupt request flag (QTM3OV) is set to "1".
The interrupt request flag (QTM3OV) is located in interrupt request register 1 (IRQ1).
Interrupts can be enabled or disabled by the interrupt enable flag (ETM0OV). The interrupt
enable flag (ETM3OV) is located in interrupt enable register 1 (IE1).
Three levels of priority can be set with the interrupt priority setting flags (P0TM3OV and
P1TM3OV). The interrupt priority setting flags are located in interrupt priority control
register 3 (IP3).
Table 8-6 lists the vector address of the timer 3 interrupt factor and the interrupt processing
flags.
Table 8-6 Timer 3 Vector Address and Interrupt Processing Flags
Vector
address [H]
0026
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
1
0
Overflow of timer 3
QTM3OV
ETM3OV
P1TM3OV
P0TM3OV
Symbols (byte) of registers that
contain interrupt processing flags
IRQ1
IE1
IP3
17-25
Reference page
17-13
17-18
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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Chapter 8 General-Purpose 8/16 Bit Timers
8.7 Timer 4
Timer 4 is an 8-bit auto-reload timer that has functions for timer output and a baud rate
generator for SIO1.
8.7.1 Timer 4 Configuration
Figure 8-13 shows the timer 4 configuration.
TBCCLK
OVF
Interrupt request
TM4C (8bit)
≠
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
TM4OUT (P8_4)
D
Q
CK
Q
TM4R (8bit)
Baud rate for SIO1
TM4CON
8
TM4C: General-purpose 8-bit timer 4 counter
TM4R: General-purpose 8-bit timer 4 register
TM4CON: General-purpose 8-bit timer 4 control register
TM4OUT: Timer 4 output pin (P8_4)
Figure 8-13 Timer 4 Configuration
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Chapter 8 General-Purpose 8/16 Bit Timers
8.7.2 Description of Timer 4 Registers
(1) General-purpose 8-bit timer 4 counter (TM4C)
Thegeneral-purpose8-bittimer4counter(TM4C)isan8-bitup-counter. Whenthiscounter
overflows, an interrupt request is generated and it is loaded with the contents of general-
purpose 8-bit timer 4 register (TM4R). TM4C can also be used as a baud rate generator
for SIO1.
TM4C can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM4C are undefined.
[Note]
Writing a timer value to TM4C causes the same value to also be written to the general-
purpose 8-bit timer 4 register (TM4R).
(2) General-purpose 8-bit timer 4 register (TM4R)
The general-purpose 8-bit timer 4 register (TM4R) consists of 8 bits. This register stores
the value to be reloaded into the general-purpose 8-bit timer 4 counter (TM4C).
TM4R can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM4R are undefined.
(3) General-purpose 8-bit timer 4 control register (TM4CON)
The general-purpose 8-bit timer 4 control register (TM4CON) consists of 5 bits. Bits 0 to
2 (TM4C0 to TM4C2) of TM4CON select the timer 4 count clock, bit 3 (TM4RUN) starts or
halts the counting, and bit 7 (TM4OUT) specifies the initial timer output level (High or Low)
at start-up. And each time TM4C overflows, the content of bit 7 (TM4OUT) is reversed.
TM4CON can be read from and written to by the program. However, write operations are
invalid for bits 4 to 6. If read, a value of "1" will always be obtained for bits 4 to 6.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), TM4CON becomes 70H.
Figure 8-14 shows the TM4CON configuration.
[Note]
Just before TM4C overflows, if an SB, RB, XORB or other read-modify-write instruction
is performed on TM4CON, then TM4OUT may not operate correctly.
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Chapter 8 General-Purpose 8/16 Bit Timers
7
6
—
1
5
—
1
4
—
1
3
2
1
0
Address: 0076 [H]
R/W access: R/W
TM4CON TM4OUT
TM4RUN TM4C2 TM4C1 TM4C0
At reset
0
0
0
0
0
TM4C
Timer 4 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
Prohibited setting
Prohibited setting
0
1
Timer 4 halt counting
Timer 4 start counting
0
1
Low level output
High level output
8
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 8-14 TM4CON Configuration
[Note]
Do not select a timer 4 count clock setting that is prohibited. If a "prohibited setting" is
selected, timer 4 will not operate properly.
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Chapter 8 General-Purpose 8/16 Bit Timers
8.7.3 Example of Timer 4-related Register Settings
(1) Port 8 mode register (P8IO)
If TM4OUT (timer output) is to be used, set bit 4 (P8IO4) to "1" to configure the port as an
output.
(2) Port 8 secondary function control register (P8SF)
If TM4OUT (timer output) is to be used, set bit 4 (P8SF4) to "1" to configure the port as a
secondary function output.
(3) General-purpose 8-bit timer 4 counter (TM4C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM4C,thesame
value will also be written simultaneously and automatically to the general-purpose 8-bit
timer 4 register (TM4R).
(4) General-purpose 8-bit timer 4 register (TM4R)
Thisregistersetsthevaluetobeloadedaftergeneral-purpose8-bittimer4counter(TM4C)
overflows. Ifthetimervalue(TM4C)andthereloadvalue(TM4R)areidentical, thisregister
will automatically be set just by setting TM4C. If the values are different or are to be
modified, this register must be set explicitly.
(5) General-purpose 8-bit timer 4 control register (TM4CON)
Bits 0 to 2 (TM4C0 to TM4C2) of this register specify the count clock for timer 4. If TM4OUT
(timer output) is to be used, specify the initial value with bit 7 (TM4OUT). If bit 3 (TM4RUN)
is set to "1", timer 4 will begin counting. If reset to "0", timer 4 will halt counting.
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Chapter 8 General-Purpose 8/16 Bit Timers
8.7.4 Timer 4 Operation
When the TM4RUN bit is set to "1", timer 4 will begin counting upward, running on the count
clock selected by TM4CON. When TM4C overflows, an interrupt request is generated, the
contents of TM4R are loaded into TM4C and the TM4OUT output is inverted. The initial
value of the TM4OUT pin is specified by bit 7 (TM4OUT) of TM4CON. This operation is
repeated until the TM4RUN bit is reset to "0". Overflow of TM4C can be used as a baud
rate generator for SIO1. Figure 8-15 shows an operation example (for settings of 1/n
counter frequency division ratio 1/1 and 1/4 TBCCLK).
CPUCLK
TM count CLK
(1/4 TBCCLK)
TM4R
55H
TM4C
FEH
FFH
55H
56H
Overflow signal
(SIO1 baud rate)
8
TM4OUT
Interrupt request generated
Figure 8-15 Timer 4 Operation Example
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Chapter 8 General-Purpose 8/16 Bit Timers
8.7.5 Timer 4 Interrupt
When a timer 4 interrupt factor occurs, the interrupt request flag (QTM4OV) is set to "1".
The interrupt request flag (QTM4OV) is located in interrupt request register 2 (IRQ2).
Interrupts can be enabled or disabled by the interrupt enable flag (ETM4OV). The interrupt
enable flag (ETM4OV) is located in interrupt enable register 2 (IE2).
Three levels of priority can be set with the interrupt priority setting flags (P0TM4OV and
P1TM4OV). The interrupt priority setting flags are located in interrupt priority control
register 5 (IP5).
Table 8-7 lists the vector address of the timer 4 interrupt factor and the interrupt processing
flags.
Table 8-7 Timer 4 Vector Address and Interrupt Processing Flags
Vector
address [H]
0036
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
1
0
Overflow of timer 4
QTM4OV
ETM4OV
P1TM4OV
P0TM4OV
Symbols (byte) of registers that
contain interrupt processing flags
IRQ2
IE2
IP5
17-27
Reference page
17-14
17-19
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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Chapter 8 General-Purpose 8/16 Bit Timers
8.8 Timer 5
Timer 5 is an 8-bit auto-reload timer that has a baud rate generator function for SIO4 and
5. TM5OUT is not output on ports, but can be used by software as a flag.
8.8.1 Timer 5 Configuration
Figure 8-16 shows the timer 5 configuration.
TBCCLK
OVF
Interrupt request
TM5OUT
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
TM5C (8bit)
≠
D
Q
CK
Q
TM5R (8bit)
Baud rate for SIO4, 5
8
TM5CON
TM5C: General-purpose 8-bit timer 5 counter
TM5R: General-purpose 8-bit timer 5 register
TM5CON: General-purpose 8-bit timer 5 control register
Figure 8-16 Timer 5 Configuration
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Chapter 8 General-Purpose 8/16 Bit Timers
8.8.2 Description of Timer 5 Registers
(1) General-purpose 8-bit timer 5 counter (TM5C)
Thegeneral-purpose8-bittimer5counter(TM5C)isan8-bitup-counter. Whenthiscounter
overflows, an interrupt request is generated and it is loaded with the contents of general-
purpose 8-bit timer 5 register (TM5R). TM5C can also be used as a baud rate generator
for SIO4 and 5.
TM5C can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), contents of TM5C are undefined.
[Note]
Writing a timer value to TM5C causes the same value to also be written to the general-
purpose 8-bit timer 5 register (TM5R).
(2) General-purpose 8-bit timer 5 register (TM5R)
The general-purpose 8-bit timer 5 register (TM5R) consists of 8 bits. This register stores
the value to be reloaded into the general-purpose 8-bit timer 5 counter (TM5C).
TM5R can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM5R are undefined.
(3) General-purpose 8-bit timer 5 control register (TM5CON)
The general-purpose 8-bit timer 5 control register (TM5CON) consists of 5 bits. Bits 0 to
2 (TM5C0 to TM5C2) of TM5CON select the timer 5 count clock and bit 3 (TM5RUN) starts
or halts the counting. Specify the initial timer output level (High or Low) at start-up with bit
7 (TM5OUT). The contents of bit 7 (TM5OUT) are reversed each time TM5C overflows.
TM5CON can be read from and written to by the program. However, write operations are
invalid for the upper 4 bits. If read, a value of "1" will always be obtained for bits 4 to 6. The
value read from bit 7 is undefined.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM5CON are undefined.
Figure 8-17 shows the TM5CON configuration.
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Chapter 8 General-Purpose 8/16 Bit Timers
7
TM5OUT
0
6
—
1
5
—
1
4
—
1
3
2
1
0
Address: 007A [H]
R/W access: R/W
TM5RUN TM5C2 TM5C1 TM5C0
TM5CON
At reset
0
0
0
0
TM5C
Timer 5 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
Prohibited setting
Prohibited setting
0
1
Timer 5 halt counting
Timer 5 start counting
0
1
Low level
High Level
"—" indicates a nonexistent bit.
When read, its value will be "1."
8
Figure 8-17 TM5CON Configuration
[Note]
Do not select a timer 5 count clock setting that is prohibited. If a "prohibited setting" is
selected, timer 5 will not operate properly.
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Chapter 8 General-Purpose 8/16 Bit Timers
8.8.3 Example of Timer 5-related Register Settings
(1) General-purpose 8-bit timer 5 counter (TM5C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM5C,thesame
value will also be simultaneously and automatically written to the general-purpose 8-bit
timer 5 register (TM5R).
(2) General-purpose 8-bit timer 5 register (TM5R)
Thisregistersetsthevaluetobeloadedaftergeneral-purpose8-bittimer5counter(TM5C)
overflows. Ifthetimervalue(TM5C)andthereloadvalue(TM5R)areidentical, thisregister
will automatically be set just by setting TM5C. If the values are different or are to be
modified, this register must be set explicitly.
(3) General-purpose 8-bit timer 5 control register (TM5CON)
Bits 0 to 2 (TM5C0 to TM5C2) of this register specify the count clock for timer 5. If TM5OUT
(timer output) is used, specify the initial value with bit 7 (TM5OUT). If bit 3 (TM5RUN) is
set to "1", timer 5 will begin counting. If reset to "0", timer 5 will halt counting.
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Chapter 8 General-Purpose 8/16 Bit Timers
8.8.4 Timer 5 Operation
When the TM5RUN bit is set to "1", timer 5 will begin counting upward, running on the count
clock selected by TM5CON. When TM5C overflows, an interrupt request is generated and
the contents of TM5R are loaded into TM5C. This operation is repeated until the TM5RUN
bit is reset to "0". Overflow of TM5C can be used as a baud rate generator for SIO4 and
5. Figure 8-18 shows an operation example (for settings of 1/n counter frequency division
ratio 1/1 and 1/4 TBCCLK).
CPUCLK
TM count CLK
(1/4 TBCCLK)
TM5R
55H
TM5C
FEH
FFH
55H
56H
Overflow signal
(Baud rate for SIO4)
8
TM5OUT
Interrupt request generated
Figure 8-18 Timer 5 Operation Example
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Chapter 8 General-Purpose 8/16 Bit Timers
8.8.5 Timer 5 Interrupt
When a timer 5 interrupt factor occurs, the interrupt request flag (QTM5OV) is set to "1".
The interrupt request flag (QTM5OV) is located in interrupt request register 3 (IRQ3).
Interrupts can be enabled or disabled by the interrupt enable flag (ETM5OV). The interrupt
enable flag (ETM5OV) is located in interrupt enable register 3 (IE3).
Three levels of priority can be set with the interrupt priority setting flags (P0TM5OV and
P1TM5OV). The interrupt priority setting flags are located in interrupt priority control
register 6 (IP6).
Table 8-8 lists the vector address of the timer 5 interrupt factor and the interrupt processing
flags.
Table 8-8 Timer 5 Vector Address and Interrupt Processing Flags
Vector
address [H]
003A
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
1
0
Overflow of timer 5
QTM5OV
ETM5OV
P1TM5OV
P0TM5OV
Symbols (byte) of registers that
contain interrupt processing flags
IRQ3
IE3
IP6
17-28
Reference page
17-15
17-20
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.9 Timer 6
Timer 6 is an 8-bit auto-reload timer that has two operating modes, auto-reload timer mode
and watchdog timer (WDT) mode. If the counter overflows during the WDT mode, the
system will be reset.
8.9.1 Timer 6 Configuration
Figure 8-19 shows the timer 5 configuration.
1/8 TBCCLK
1/16 TBCCLK
1/32 TBCCLK
1/64 TBCCLK
1/128 TBCCLK
1/256 TBCCLK
1/1024 TBCCLK
1/4096 TBCCLK
OVF
TM6C (8bit)
Interrupt request
Reset request
≠
TM6R (8bit)
MODWDT
Software alternates
writing n3H and nCH
TM6CON
8
TM6C: General-purpose 8-bit timer 6 counter
TM6R: General-purpose 8-bit timer 6 register
TM6CON: General-purpose 8-bit timer 6 control register
MODWDT: WDT mode setting signal
Figure 8-19 Timer 6 Configuration
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Chapter 8 General-Purpose 8/16 Bit Timers
8.9.2 Description of Timer 6 Registers
(1) General-purpose 8-bit timer 6 counter (TM6C)
The general-purpose 8-bit timer 6 counter (TM6C) is an 8-bit up-counter.
• During auto-reload timer mode
When an interrupt request is generated due to overflow of the counter, the contents of
general-purpose 8-bit timer 6 register (TM6R) are loaded into TM6C.
• During WDT mode
Counter overflow causes the system to be reset. When starting or initializing WDT, a
special write operation to TM6C is necessary (so that WDT will not be easily initialized
by an out-of-control program). The count value can be read during WDT operation, but
once WDT is started, it is not possible to write to TM6C.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), the contents of TM6C are undefined.
[Note]
Writing a timer value to TM6C causes the same value to be also written to general-
purpose 8-bit timer 6 register (TM6R).
(2) General-purpose 8-bit timer 6 register (TM6R)
The general-purpose 8-bit timer 6 register (TM6R) consists of 8 bits. This register stores
the value to be reloaded into the general-purpose 8-bit timer 6 counter (TM6C).
During the auto-reload timer mode, the program can read from and write to TM6R. During
the WDT mode, TM6R is read-only.
Atreset(duetoaRESinput,BRKinstructionexecution,watchdogtimeroverflow,oropcode
trap), the contents of TM6R are undefined.
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Chapter 8 General-Purpose 8/16 Bit Timers
(3) General-purpose 8-bit timer 6 control register (TM6CON)
The general-purpose 8-bit timer 6 control register (TM6CON) consists of 7 bits.
During the auto-reload timer mode, the program can read from and write to TM6CON.
However, write operations are invalid for bits 4 to 6. If read, a value of "1" will always be
obtained for bit 4.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), TM6CON becomes 10H.
Figure 8-20 shows the TM6CON configuration.
[Description of each bit]
• WDTC0 to WDTC2 (bits 0 to 2)
WDTC0 to WDTC2 specify the count clock for timer 6.
• ATMRUN (bit 3)
During the auto-reload timer mode, ATMRUN specifies whether the count is running or
halted.
During the WDT mode, the value that has been written will be read.
8
• WDTRUN (bit 5)
This read-only flag is read as "1" during counting in the WDT mode. With this flag, it is
possible to determine whether the count operation in the WDT mode has started.
• WDTLDE (bit 6)
During the WDT mode, WDT is initialized within a fixed period by loading the value of
TM6R into TM6C. This load operation (WDT initialization) is performed by alternately
writing "n3H" and "nCH" (where n is an arbitrary value from 0 to F) to TM6C.
WDTLDEisaread-onlyflagusedduringinitializationtodeterminewhetherthenextvalue
to be written to TM6C will be "n3H" or "nCH".
• MODWDT (bit 7)
This bit specifies the timer 6 operating mode (auto-reload timer mode or WDT mode).
[Note]
Before setting MODWDT to "1" to enter the WDT mode, set the WDT overflow period with
TM6C, TM6R and TM6CON (WDTC0 to WDTC2). It is not possible to modify the period
once MODWDT is set to "1" and the WDT mode is entered. (Writes become invalid).
SinceMODWDTislocatedwithinTM6CON,byteinstructionscanbeusedtosimultaneously
write to MODWDT and WDTC0 through WDTC2.
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Chapter 8 General-Purpose 8/16 Bit Timers
7
6
5
4
—
1
3
ATMRUN
0
2
1
0
Address: 007E [H]
R/W access: R/W
MODWDT WDTLDE WDTRUN
WDTC2 WDTC1 WDTC0
TM6CON
At reset
0
0
0
0
0
0
WDTC
Timer 6 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1/8 TBCCLK
1/16 TBCCLK
1/32 TBCCLK
1/64 TBCCLK
1/128 TBCCLK
1/256 TBCCLK
1/1024 TBCCLK
1/4096 TBCCLK
0
1
Timer 6 halt counting
Timer 6 start counting
0
1
WDT count halted (read-only)
WDT count in progress (read-only)
0
1
Initialize by writing n3H (read-only)
Initialize by writing nCH (read-only)
0
1
Auto-reload timer mode
WDT mode
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 8-20 TM6CON Configuration
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Chapter 8 General-Purpose 8/16 Bit Timers
8.9.3 Example of Timer 6-related Register Settings
• Auto-reload timer mode settings
(1) General-purpose 8-bit timer 6 counter (TM6C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM6C,thesame
value will also be simultaneously and automatically written to the general-purpose 8-bit
timer 6 register (TM6R).
(2) General-purpose 8-bit timer 6 register (TM6R)
Thisregistersetsthevaluetobeloadedaftergeneral-purpose8-bittimer6counter(TM6C)
overflows. Ifthetimervalue(TM6C)andthereloadvalue(TM6R)areidentical, thisregister
will automatically be set just by setting TM6C. If the values are different or are to be
modified, this register must be set explicitly.
(3) General-purpose 8-bit timer 6 control register (TM6CON)
Bits 0 to 2 (WDTC0 to WDTC2) of this register specify the count clock for timer 6. If bit 3
(ATMRUN) is set to "1", timer 6 will begin counting. If reset to "0", timer 6 will halt counting.
8
• Watchdog timer (WDT) mode settings
(1) General-purpose 8-bit timer 6 register (TM6R)
This register sets the value to be loaded into general-purpose 8-bit timer 6 counter (TM6C).
(2) General-purpose 8-bit timer 6 control register (TM6CON)
(i) Specify the count clock for timer 6 with bits 0 to 2 (WDTC0 to WDTC2) of this register.
(ii) Set bit 7 (MODWDT) to "1" to enter the WDT mode.
(Settings (i) and (ii) can be performed simultaneously by using a byte instruction such as
MOVB.)
(3) General-purpose 8-bit timer 6 counter (TM6C)
Write the WDT activation code, "n3H", to start WDT counting.
(At this time, the contents of TM6C are not modified. "n3H" is only used to activate WDT.)
Thereafter, WDT is initialized by alternately writing "nCH" and "n3H" before overflow.
WDTLDE (bit 6) of TM6CON can be read to determine whether the value to be written for
the next initialization is "nCH" or "n3H". "WDT initialization" is defined as loading the value
of TM6R into TM6C. (n is an arbitrary value from 0 to F.)
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Chapter 8 General-Purpose 8/16 Bit Timers
8.9.4 Timer 6 Operation
• Auto-reload timer mode
When the MODWDT bit in TM6CON is reset to "0", the mode changes to the auto-reload
timer mode. If the ATMRUN bit is set to "1", timer 6 will begin counting upward, running on
the count clock selected by TM6CON. When TM6C overflows, an interrupt request is
generatedandthecontentsofTM6RareloadedintoTM6C. Thisoperationisrepeateduntil
the ATMRUN bit is reset to "0". Figure 8-21 shows an operation example (for settings of
1/n counter frequency division ratio 1/1 and 1/8 TBCCLK).
CPUCLK
TM count CLK
(1/8 TBCCLK)
TM6R
55H
TM6C
FEH
FFH
55H
56H
Overflow signal
Interrupt request generated
Figure 8-21 Timer 6 Operation (During Auto-Reload Timer Mode)
• Watchdog timer (WDT) mode
When the MODWDT bit in TM6CON is set to "1", the mode changes to the WDT mode.
Once the WDT mode is set, it is not possible to return to the auto-reload timer mode until
the system is reset. In the WDT mode, writing "n3H" to TM6C will cause the WDT count
operation to begin. Thereafter, alternately writing "nCH" and "n3H" by the program will
cause the contents of TM6R to be loaded into TM6C and initialize WDT.
IfWDTinitializationisnotimplementedwithinthefixedamountoftimesetbythecountclock
and the reload value, then TM6C will overflow and the system will be reset. To process a
system reset, the branch address (2 bytes) stored in addresses 0004 to 0005 (vector
address for reset by WDT) is loaded into the program counter.
The time (tWDT) until TM6C overflows can be expressed by the below equation, where f
[MHz] is the fundamental clock (CPUCLK), T is the TM6C count clock (divided value of
TBCCLK), n is the divisor for the 1/n counter at the TBC front stage, and R is the value of
TM6R.
t
= (1/f) ¥ T ¥ n ¥ (256 – R) [ms] (R: 0 to 255)
WDT
Figure 8-22 shows timing diagrams of an out-of-control program and detection by WDT.
Figure 8-23 shows an example of an out-of-control program.
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Chapter 8 General-Purpose 8/16 Bit Timers
Direction of program execution
TM6C
contents
Write n3H
WDT starts
Write nCH
TM6RÆTM6C
Write n3H
TM6RÆTM6C
Write nCH
TM6RÆTM6C
OVF
TM6R
t
Within
tWDT
Within
tWDT
Within
tWDT
8
(a) Correct program execution
Direction of program execution
TM6C
contents
Write n3H
WDT starts
Write nCH
TM6RÆTM6C
OVF
TM6C overflows
(System reset by WDT)
TM6R
t
tWDT
(b) Program runs out-of-control
Figure 8-22 Timing Diagram of Out-of-Control Program Detection
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Chapter 8 General-Purpose 8/16 Bit Timers
WDT initialization by
writing nCH to TM6C
WDT initialization by
writing nCH to TM6C
WDT initialization by
writing n3H to TM6C
WDT initialization by
writing n3H to TM6C
(a) Execution of writing nCH only
(b) Execution of writing n3H only
Abnormal program running
Normal program running
WDT initialization by
writing nCH to TM6C
WDT initialization by
writing n3H to TM6C
(c) No writing to TM6C
Figure 8-23 Example of Out-of-Control Program Detection
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Chapter 8 General-Purpose 8/16 Bit Timers
8.9.5 Timer 6 Interrupt (During Auto-Reload Timer Mode)
When a timer 6 interrupt factor occurs (during the auto-reload timer mode), the interrupt
request flag (QTM6OV) is set to "1". The interrupt request flag (QTM6OV) is located in
interrupt request register 3 (IRQ3).
Interrupts can be enabled or disabled by the interrupt enable flag (ETM6OV). The interrupt
enable flag (ETM6OV) is located in interrupt enable register 3 (IE3).
Three levels of priority can be set with the interrupt priority setting flags (P0TM6OV and
P1TM6OV). The interrupt priority setting flags are located in interrupt priority control
register 7 (IP7).
Table 8-9 lists the vector address of the timer 6 interrupt factor and the interrupt processing
flags.
Table 8-9 Timer 6 Vector Address and Interrupt Processing Flags
Vector
address [H]
0042
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
1
0
Overflow of timer 6
QTM6OV
ETM6OV
P1TM6OV
P0TM6OV
8
Symbols (byte) of registers that
contain interrupt processing flags
IRQ3
IE3
IP7
17-29
Reference page
17-15
17-20
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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MSM66577 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
8.10 Timer 9
Timer 9 is an 8-bit auto-reload timer that has the function for clock output for PWM.
TM9OUT is not output on ports, but can be used by software as a flag.
8.10.1 Timer 9 Configuration
Figure 8-24 shows the timer 9 configuration.
TBCCLK
OVF
Interrupt request
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
TM9C (8bit)
≠
D
TM9OUT
Q
CK
Q
TM9R (8bit)
Clock output
for PWM
TM9CON
TM9C: General-purpose 8-bit timer 9 counter
TM9R: General-purpose 8-bit timer 9 register
TM9CON: General-purpose 8-bit timer 9 control register
Figure 8-24 Timer 9 Configuration
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Chapter 8 General-Purpose 8/16 Bit Timers
8.10.2 Description of Timer 9 Registers
(1) General-purpose 8-bit timer 9 counter (TM9C)
Thegeneral-purpose8-bittimer9counter(TM9C)isan8-bitup-counter. Whenthiscounter
overflows, an interrupt request is generated and it is loaded with the contents of general-
purpose 8-bit timer 9 register (TM9R). This counter can also be used as a clock for PWM.
TM9C can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM9C are undefined.
[Note]
Writing a timer value to TM9C causes the same value to also be written to the general-
purpose 8-bit timer 9 register (TM9R).
(2) General-purpose 8-bit timer 9 register (TM9R)
The general-purpose 8-bit timer 9 register (TM9R) consists of 8 bits. This register stores
the value to be reloaded into the general-purpose 8-bit timer 9 counter (TM9C).
TM9R can be read from and written to by the program.
8
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of TM9R are undefined.
(3) General-purpose 8-bit timer 9 control register (TM9CON)
The general-purpose 8-bit timer 9 control register (TM9CON) consists of 5 bits. Bits 0 to
2 (TM9C0 to TM9C2) of TM9CON select the timer 9 count clock, bit 3 (TM9RUN) specifies
starting or halting the counting, and bit 7 (TM9OUT) specifies the initial timer output level
(High or Low) at start-up. And each time TM0C overflows, the content of bit 7 (TM9OUT)
is reversed.
TM9CON can be read from and written to by the program. However, write operations are
invalid for bits 4 to 6. If read, a value of "1" will always be obtained for bits 4 to 6.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), TM9CON becomes 70H.
Figure 8-25 shows the TM9CON configuration.
[Note]
Just before TM9C overflows, if an SB, RB, XORB or other read-modify-write instruction
is performed on TM9CON, then TM9OUT may not operate correctly.
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Chapter 8 General-Purpose 8/16 Bit Timers
7
TM9OUT
0
6
—
1
5
—
1
4
—
1
3
2
1
0
Address: 00CE [H]
R/W access: R/W
TM9RUN TM9C2 TM9C1 TM9C0
TM9CON
At reset
0
0
0
0
TM9C
Timer 9 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/32 TBCCLK
1/256 TBCCLK
Prohibited setting
Prohibited setting
0
1
Timer 9 halt counting
Timer 9 start counting
0
1
Low level output
High level output
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 8-25 TM9CON Configuration
[Note]
Do not select a timer 9 count clock setting that is prohibited. If a "prohibited setting" is
selected, timer 9 will not operate properly.
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Chapter 8 General-Purpose 8/16 Bit Timers
8.10.3 Example of Timer 9-related Register Settings
(1) General-purpose 8-bit timer 9 counter (TM9C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM9C,thesame
value will also be simultaneously and automatically written to the general-purpose 8-bit
timer 9 register (TM9R).
(2) General-purpose 8-bit timer 9 register (TM9R)
Thisregistersetsthevaluetobeloadedaftergeneral-purpose8-bittimer9counter(TM9C)
overflows. Ifthetimervalue(TM9C)andthereloadvalue(TM9R)areidentical, thisregister
will automatically be set just by setting TM9C. If the values are different or are to be
modified, this register must be set explicitly.
(3) General-purpose 8-bit timer 9 control register (TM9CON)
Bits 0 to 2 (TM9C0 to TM9C2) of this register specify the count clock for timer 9. If TM9OUT
(timer output) is to be used, specify the initial value with bit 7 (TM9OUT). If bit 3 (TM9RUN)
is set to "1", timer 9 will begin counting. If reset to "0", timer 9 will halt counting.
8
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Chapter 8 General-Purpose 8/16 Bit Timers
8.10.4 Timer 9 Operation
When the TM9RUN bit is set to "1", timer 9 will begin counting upward, running on the count
clock selected by TM9CON. When TM9C overflows, an interrupt request is generated, the
contents of TM9R are loaded into TM9C and the TM9OUT output is inverted. The initial
value of the TM9OUT pin is specified by bit 7 (TM9OUT) of TM9CON. This operation is
repeated until the TM9RUN bit is reset to "0". Overflow of TM9C can be used as the clock
output for PWM. Figure 8-26 shows an operation example (for settings of 1/n counter
frequency division ratio 1/1and 1/4 TBCCLK).
CPUCLK
TM count CLK
(1/4 TBCCLK)
TM9R
55H
TM9C
FEH
FFH
55H
56H
Overflow signal
(Clock output for PWM)
TM9OUT
Interrupt request generated
Figure 8-26 Timer 9 Operation Example
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Chapter 8 General-Purpose 8/16 Bit Timers
8.10.5 Timer 9 Interrupt
When a timer 9 interrupt factor occurs, the interrupt request flag (QTM9OV) is set to "1".
The interrupt request flag (QTM9OV) is located in interrupt request register 4 (IRQ4).
Interrupts can be enabled or disabled by the interrupt enable flag (ETM9OV). The interrupt
enable flag (ETM9OV) is located in interrupt enable register 4 (IE4).
Three levels of priority can be set with the interrupt priority setting flags (P0TM9OV and
P1TM9OV). The interrupt priority setting flags are located in interrupt priority control
register 9 (IP9).
Table8-10liststhevectoraddressofthetimer9interruptfactorandtheinterruptprocessing
flags.
Table 8-10 Timer 9 Vector Address and Interrupt Processing Flags
Vector
address [H]
0072
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
1
0
Overflow of timer 9
QTM9OV
ETM9OV
P1TM9OV
P0TM9OV
8
Symbols (byte) of registers that
contain interrupt processing flags
IRQ4
IE4
IP9
17-31
Reference page
17-16
17-21
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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Chapter 8 General-Purpose 8/16 Bit Timers
8-54
Chapter 9
Capture/Compare Timer
9
MSM66577 Family User's Manual
Chapter 9 Capture/Compare Timer
9. Capture/Compare Timer
9.1 Overview
The MSM66577 family has a built-in 2-channel capture/compare timer.
Timer functions consist of a capture mode used for pulse width and cycle measurements
and a compare out mode used for pulse output with real-time control. Functions can be
selected for use with each of the two channels.
9.2 Capture/Compare Timer Configuration
Figure 9-1 shows the capture/compare timer configuration. The counter unit consists of a
16-bit free running counter (FRC) and two capture/compare out modules.
Overflow
FRC
Interrupt request
Capture/compare out module
Comparator
Interrupt request
9
CPCMRn
Æ
CPCMBFRn
Æ
CPCMn
(P5_4, P5_5)
Edge detection
CPCMBFn
CPCMSBFn
CPCMOUTn
CAPCON
(n = 0, 1)
FRC: free running counter (16 bits)
CPCMRn: Capture/compare register (16 bits)
CAPCON: Capture control register
CPCMBFRn: Capture/compare buffer register (16 bits)
CPCMOUTn: Capture/compare out bit
CPCMn: Capture input/compare output pin (P5_4, P5_5)
CPCMBFn: Compare out buffer bit
CPCMSBFn: Compare out sub-buffer bit
Figure 9-1 Capture/Compare Timer Configuration
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Chapter 9 Capture/Compare Timer
9.3 Capture/Compare Timer Registers
Table 9-1 lists a summary of SFRs for control of the capture/compare timer.
Table 9-1 Summary of SFRs for Control of the Capture/Compare Timer
Address
[H]
Symbol
(byte)
Symbol
(word)
8/16
Initial
Reference
page
Name
R/W
R/W
Operation value [H]
0040
0041
004A
004B
004C
004D
Free running counter
—
—
—
FRC
16
16
16
8
0000
0000
0000
C0
9-3
9-6
9-6
9-4
Capture/compare
register 0
CPCMR0 R/W
CPCMR1 R/W
Capture/compare
register 1
Free running counter
control register
0050I
FRCON
—
R/W
0051I Capture control register
CAPCON
—
—
—
R/W
R/W
R/W
8
8
8
C0
F8
F8
9-7
9-6
9-6
0055I Compare control register 0 CPCMCON0
0056I Compare control register 1 CPCMCON1
00EA
00EB
00EC
00ED
Capture/compare
buffer register 0
Capture/compare
buffer register 1
—
—
CPCMBFR0 R/W
CPCMBFR1 R/W
16
16
0000
0000
9-8
9-8
[Notes]
1. Addresses are not consecutive in some places.
2. A star (P) in the address column indicates a missing bit.
3. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
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Chapter 9 Capture/Compare Timer
9.4 16-Bit Free Running Counter (FRC)
A 16-bit free running counter (FRC) is used as the counter unit of the compare/capture
timer.
9.4.1 16-Bit Free Running Counter Configuration
Figure 9-2 shows the 16-bit free running counter configuration.
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
0
15
OVF
1/8 TBCCLK
1/16 TBCCLK
1/32 TBCCLK
1/64 TBCCLK
1/128 TBCCLK
Interrupt request
FRC
16 bits
Capture/compare out module
FRCON
9
FRC: free running counter (16 bits)
FRCON: free running counter control register
Figure 9-2 16-Bit Free Running Counter Configuration
9.4.2 Description of 16-bit Free Running Counter Register
(1) 16-bit free running counter (FRC)
The 16-bit free running counter (FRC) is a 16-bit up-counter. Counter overflow causes an
interrupt request to be generated and the counter to be cleared to "0".
FRC can be read from and written to by the program.
Use the interrupt processing routine active when the interrupt request is generated to write
the next values to the free running counter (FRC).
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), FRC becomes 0000H.
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Chapter 9 Capture/Compare Timer
(2) Free running counter control register (FRCON)
The free running counter control register (FRCON) consists of 6 bits. FRCON selects the
count clock for the free running counter (FRC), starts/stops the counter, and specifies the
operating mode of the capture/compare out module. Bits 0 to 2 (FRCK0 to FRCK2) select
the FRC count clock and bit 3 (FRRUN) specifies whether to run or stop the counter. Bit
4 (CP0MD) specifies the CPCM0 operating mode and bit 5 (CP1MD) specifies the CPCM1
operating mode.
FRCON can be read from and written to by the program. However, write operations are
invalid for the upper 2 bits. If read, a value of "1" will always be obtained for the upper 2 bits.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), FRCON becomes C0H, TBCCLK is selected for the FRC count clock,
and counting is halted. Also, the capture/compare out module will specify the compare out
mode.
Figure 9-3 shows the FRCON configuration.
7
—
1
6
—
1
5
4
3
2
1
0
Address: 0050 [H]
R/W access: R/W
FRCON
At reset
CP1MD CP0MD FRRUN FRCK2 FRCK1 FRCK0
0
0
0
0
0
0
FRCK
FRC count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
TBCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/16 TBCCLK
1/32 TBCCLK
1/64 TBCCLK
1/128 TBCCLK
0
1
Halt FRC counting
Operate FRC counting
CP0MD
CPCM0 operating mode
Compare out mode
Capture mode
0
1
CP1MD
CPCM1 operating mode
Compare out mode
Capture mode
0
1
"—" indicates a nonexistent bit.
If read, its value will be "1."
Figure 9-3 FRCON Configuration
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Chapter 9 Capture/Compare Timer
9.5 Capture/Compare Out Modules
The MSM66577 family has two sets of capture/compare out modules. The configuration
of the two sets is identical with the only difference being the address of registers in the SFR
area.
[Note]
To switch the mode between the capture mode and the compare mode, first stop the free
running counter (set FRRUN of the FRCON register to "0"), then switch the mode. If the
modeisswitchedwithoutstoppingthefreerunningcounter,thecapture/compareregister
(CPCMR0 or CPCMR1) value may become different from the expected value.
9.5.1 Capture/Compare Out Module Configuration
Figure 9-4 shows the capture/compare out module configuration.
FRC
Comparator
Interrupt request
CPCMRn
Æ
9
CPCMBFRn
Æ
CPCMn
(P5_4, P5_5)
CAPCON
Edge detection
CPCMBFn
CPCMOUTn
CPCMSBFn
(n = 0, 1)
FRC: free running counter (16 bits)
CPCMRn: Capture/compare register (16 bits)
CAPCON: Capture control register
CPCMBFRn: Capture/compare buffer register (16 bits)
CPCMOUTn: Capture/compare out bit
CPCMn: Capture input/compare output pin (P5_4, P5_5)
CPCMBFn: Compare out buffer bit
CPCMSBFn: Compare out sub-buffer bit
Figure 9-4 Capture/Compare Out Module Configuration
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Chapter 9 Capture/Compare Timer
9.5.2 Description of Capture/Compare Out Module Registers
(1) Capture/compare registers (CPCMR0, CPCMR1)
Thecapture/compareregisters(CPCMR0andCPCMR1)consistof16bits. Inthecompare
out mode, CPCMR0 and CPCMR1 are always compared to the value of the free running
counter (FRC). In the capture mode, when the edge specified as valid is input to a CPCMn
pin, a capture event interrupt is generated, and at the same time, the contents of the free
running counter (FRC) are loaded into CPCMR0 and CPCMR1.
CPCMR0 and CPCMR1 can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), CPCMR0 and CPCMR1 become 0000H.
(2) Capture/compare control registers (CPCMCON0, CPCMCON1)
The capture/compare control registers (CPCMCON0 and CPCMCON1) consist of 3 bits.
In the compare out mode, if CPCMR0 and CPCMR1 match the value of the free running
counter (FRC), the contents of CPCMBFn (bit 1) are loaded into CPCMOUTn (bit 0). At the
sametime, thecontentsofCPCMSBFn(bit2)areloadedintoCPCMBFn(bit1). CPCMBFn
is set to the level (High or Low level) that is desired at the time of the next match.
CPCMCON0 and CPCMCON1 can be read from and written to by the program. However,
writeoperationsareinvalidfortheupper5bits. Ifread,thevalueoftheupper5bitsisalways
"1".
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), CPCMCON0 and CPCMCON1 become F8H.
Figure 9-5 shows the configuration of CPCMCON0 and CPCMCON1.
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
Address: 0055 [H] (CPCMCON0)
Address: 0056 [H] (CPCMCON1)
R/W access: R/W
CPCMSBFn CPCMBFn CPCMOUTn
CPCMCONn
At reset
0
0
0
The contents of this flag are output
to the CPCMn pin.
When the counter value matches
the CPCMRn value, the contents of
this flag are loaded into CPCMOUTn.
When the counter value matches
the CPCMRn value, the contents of
this flag are loaded into CPCMBFn.
"—" indicates a nonexistent bit.
If read, its value will be "1."
(n = 0, 1)
Figure 9-5 CPCMCON0 and CPCMCON1 Configuration
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Chapter 9 Capture/Compare Timer
[Note]
Just before the occurrence of an event caused by compare out, if an SB, RB, XORB or
other read-modify-write instruction is performed on CPCMCON0 or CPCMCON1, then
CPCMBFn and CPCMOUTn may not operate correctly.
(3) Capture control register (CAPCON)
The capture control register (CAPCON) consists of 4 bits. When the capture/compare out
module is in the capture mode, CAPCON specifies the valid edge for the signal input to
CPCM0 and CPCM1 pins. Bits 2 and 3 (CP0E0 and CP0E1) specify the valid edge of the
signal input to the CPCM0 pin, and bits 4 and 5 (CP1E0 and CP1E1) specify the valid edge
of the signal input to the CPCM1 pin.
CAPCON can be read from and written to by the program. However, write operations are
invalid for the upper 2 bits and lower 2 bits. If read, the upper 2 bits are always "1" and the
lower 2 bits are always "0".
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), CAPCON becomes C0H, and "capture input invalid" is specified for
CPCM0 and CPCM1.
Figure 9-6 shows the configuration of CAPCON.
7
—
1
6
—
1
5
4
3
2
1
—
0
0
—
0
9
Address: 0051 [H]
R/W access: R/W
CAPCON
At reset
CP1E1 CP1E0 CP0E1 CP0E0
0
0
0
0
CP0E
Valid edge during
CPCM0 capture mode
1
0
0
1
1
0
0
1
0
1
Input invalid
Falling edge
Rising edge
Both edges
CP1E
Valid edge during
CPCM1 capture mode
1
0
0
1
1
0
0
1
0
1
Input invalid
Falling edge
Rising edge
Both edges
"—" indicates a nonexistent bit.
If bits 6 and 7 are read, their value will be "1."
Bits 0 and 1 are read as "0."
Figure 9-6 CAPCON Configuration
[Note]
Set the minimum pulse width of the capture input longer than 1 CPU clock (CPUCLK).
The capture input signal is sampled at the falling edge of the CPUCLK and used as the
internal capture signal.
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Chapter 9 Capture/Compare Timer
(4) Capture/compare buffer registers (CPCMBFR0, CPCMBFR1)
The capture/compare buffer registers (CPCMBFR0, CPCMBFR1) consist of 16 bits.
During the compare out mode, if the value specified in CPCMR0 and CPCMR1 matches
the value of the free running counter (FRC), the value set in CPCMBFR0 and CPCMBFR1
is loaded into CPCMR0 and CPCMR1.
The program can read from and write to CPCMBFR0 and CPCMBFR1.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), CPCMBFR0 and CPCMBFR1 become 0000H.
9.6 Example of Capture/Compare Timer-related Register Settings
9.6.1 Capture Mode Settings
(1) Port 5 mode register (P5IO)
If CPCM0 is to be set to the capture mode, reset bit 4 (P5IO4) to "0" to configure the port
asaninput. IfCPCM1istobesettothecapturemode, resetbit5(P5IO5)to"0"toconfigure
the port as an input.
(2) Port 5 secondary function control register (P5SF)
Bit 4 (P5SF4) specifies whether the CPCM0 capture input is pulled up. Bit 5 (P5SF5)
specifies whether the CPCM1 capture input is pulled up.
(3) Capture control register (CAPCON)
Specify the valid edge for CPCM0 with bits 2 and 3 (CP0E0 and CP0E1). Specify the valid
edge for CPCM1 with bits 4 and 5 (CP1E0 and CP1E1).
(4) Free running counter (FRC)
The initial value at the start of counting can be set by writing an arbitrary 16-bit value. FRC
can be read from and written to during counting.
(5) Free running counter control register (FRCON)
Bits 0, 1, and 2 (FRCK0, FRCK1, and FRCK2) specify the count clock for the free running
counter. To set CPCM0 to the capture mode, set bit 4 (CP0MD) to "1". To set CPCM1 to
the capture mode, set bit 5 (CP1MD) to "1". If bit 3 (FRRUN) is set to "1", the free running
counter will begin counting. If reset to "0", the free running counter will halt counting.
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Chapter 9 Capture/Compare Timer
9.6.2 Compare Out Mode Settings
(1) Port 5 mode register (P5IO)
If CPCM0 is to be set to the compare out mode, set bit 4 (P5IO4) to "1" to configure the port
as an output. If CPCM1 is to be set to the compare out mode, set bit 5 (P5IO5) to "1" to
configure the port as an output.
(2) Port 5 secondary function control register (P5SF)
If CPCM0 is to be set to the compare out mode, set bit 4 (P5SF4) to "1" to configure the port
as a secondary function output. If CPCM1 is to be set to the compare out mode, set bit 5
(P5SF5) to "1" to configure the port as a secondary function output.
(3) Capture/compare control registers (CPCMCON0, CPCMCON1)
If CPCM0 is to be set to the compare out mode, specify with bit 0 (CPCMOUT0) the initial
value to be output to the CPCM0 pin, and specify with bit 1 (CPCMBF0) the value desired
to be output from the CPCM0 pin when the value of the free running counter matches the
contents of the CPCMR0. Specify with bit 2 (CPCMSBF0) the value desired to be output
from the CPCM0 pin when the next value of the free running counter matches the contents
of the CPCMR0. If CPCM1 is to be set to the compare out mode, specify with bit 0
(CPCMOUT1) the initial value to be output to the CPCM1 pin, and specify with bit 1
(CPCMBF1) the value desired to be output from the CPCM1 pin when the value of the free
runningcountermatchesthecontentsoftheCPCMR1. Specifywithbit2(CPCMSBF1)the
value desired to be output from the CPCM1 pin when the next value of the free running
counter matches the contents of the CPCMR1.
9
(4) Free running counter (FRC)
The initial value at the start of counting can be set by writing an arbitrary 16-bit value. FRC
can be read from and written to during counting.
(5) Capture/compare registers (CPCMR0, CPCMR1)
If CPCM0 has been set to the compare out mode, set a count value in CPCMR0 at which
to change the CPCM0 pin output. If CPCM1 has been set to the compare out mode, set
a count value in CPCMR1 at which to change the CPCM1 pin output.
(6) Capture/compare buffer registers (CPCMBFR0, CPCMBFR1)
If CPCM0 has been set to the compare out mode, CPCMBF0specifies the next count value
of CPCMR0 at which output of the CPCM0 pin will change. If CPCM1 has been set to the
compare out mode, CPCMBF1 specifies the next count value of CPCMR1 at which output
of the CPCM1 pin will change.
(7) Free running counter control register (FRCON)
Bits 0, 1, and 2 (FRCK0, FRCK1, and FRCK2) specify the count clock for the free running
counter. TosetCPCM0tothecompareoutmode,resetbit4(CP0MD)to"0".TosetCPCM1
to the compare out mode, reset bit 5 (CP1MD) to "0". If bit 3 (FRRUN) is set to "1", the free
runningcounterwillbegincounting. Ifresetto"0",thefreerunningcounterwillhaltcounting.
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Chapter 9 Capture/Compare Timer
9.7 Capture/Compare Timer Operation
9.7.1 Capture Mode Operation
When the free running counter (FRC) is in the RUN state, if the valid edge specified by
CAPCONisinputtotheCPCM0orCPCM1pins,thecaptureeventwillgenerateaninterrupt
request, and the contents of the free running counter (FRC) will be simultaneously loaded
into CPCMRn (where n = 0, 1).
Figure 9-7 shows an operation example of the capture mode.
CAP input
(falling edge)
ovf
Counter contents
(FRC)
d
b
e
c
a
0000H
CPCMRn contents
a
b
c
d
e
Interrupt
request
Interrupt
request
Interrupt
request
Interrupt
request
Interrupt
request
generated generated
generated generated
generated
Figure 9-7 Capture Module Operation Example
[Note]
Set the minimum pulse width of the capture input to at least 1 CPU clock (CPUCLK). The
capture inputsignalissampledatthefallingedgeoftheCPUCLKandusedastheinternal
capture signal.
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Chapter 9 Capture/Compare Timer
9.7.2 Compare Out Mode Operation
When the free running counter (FRC) is in the RUN state, CPCMR0 and CPCMR1 are
always compared to the value of the free running counter (FRC). If they match, an interrupt
request is generated by compare out and the contents of the CPCMBFn (bit 1) of
CPCMCON0 and CPCMCON1 are loaded into CPCMOUTn (bit 0) (where n = 0, 1).Also,
the contents of the CPCMSBFn (bit s) are loaded into CPCMBFn (bit 1) and the contents
of the CPCMBRn are loaded into CPCMRn. Therefore, set CPCMRn with the level desired
at the timing for the next match and set CPCMBFn with the level desired at the timing for
the match following the next match (where n = 0, 1). Use the interrupt processing routine
active when the interrupt request is generated to write the next values to CPCMRn and
CPCMBFn (where n = 0, 1).
Figure 9-8 shows an example of compare out mode operation.
ovf
CPCMRn = FRC
Free running counter
contents (FRC)
CPCMRn = FRC
b
a
d
9
c
0000H
a
b
c
d
CPCMRn contents
b
c
d
e
CPCMBFRn contents
CPCMOUTn
(CPCMn) contents
CPCMBFn contents
CPCMSBFn contents
Write to each
register
Interrupt request
generated
Interrupt request
generated
Write to CPCMRn,
CPCMBFn
Write to CPCMRn,
CPCMBFn
Interrupt request
generated
Interrupt request
generated
Write to CPCMRn,
CPCMBFn
Write to CPCMRn,
CPCMBFn
Figure 9-8 Compare Out Mode Operation Example
9-11
MSM66577 Family User's Manual
Chapter 9 Capture/Compare Timer
9.8 Example Timings for Changing the Output Level of Compare Out
Example timings in the compare out mode for changing the output level of the CMP output
are shown below.
Figure9-9showsanexamplewhen1/4CPUCLKisselectedastheclocksourceforthefree
running counter (FRC). When the contents of CPCMRn are 100H, the FRC and CPCMRn
matching signal will be HIGH 1 CLK after the interval where FRC is 100H. The CPCMn
output pin (CPCMOUTn) changes at the falling edge of the logical AND of this matching
signal with the FRC clock pulse. Further, the corresponding interrupt request flag is set at
the next M1S1 (signal that indicates the beginning of an instruction).
This example shows the timing of an output level change when 1/2 CPUCLK or larger
frequency division ratio is selected as the FRC clock source.
CPUCLK
FRC clock of 1/4 CPUCLK
FRC contents
100H
101H
100H
102H
CPCMRn contents
FRC and CPCMRn match
FRC and CPCMRn matching signal
CPCMOUTn
M1S1
IRQ
Interrupt transfer cycle
(when MIE, IE = "1")
Figure 9-9 Example Timing for Changing the Output Level of Compare Out
(FRC Clock = 1/4 CPUCLK)
9-12
MSM66577 Family User's Manual
Chapter 9 Capture/Compare Timer
Figure 9-10 shows an example when 1/1 CPUCLK is selected as the clock source for the
free running counter (FRC). When the contents of CPCMRn are 100H, the FRC and
CPCMRn matching signal will be HIGH 1 CLK after the interval where FRC is 100H. The
CPCMn output pin (CPCMOUTn) changes at the falling edge of the logical AND of this
matching signal with the FRC clock pulse. Therefore, when the FRC clock is set as 1/1
CPUCLK, the timing at which the CPCM output pin will change is FRC = CPCMRn + 01H
(when FRC is 101H in the figure below). The corresponding interrupt request flag is set at
the next M1S1 (signal that indicates the beginning of an instruction).
CPUCLK
FRC clock of 1/1 CPUCLK
FRC contents
0FCH 0FDH 0FEH 0FFH 100H 101H 102H 103H 104H 105H 106H 107H 108H
CPCMRn contents
100H
FRC and CPCMRn match
FRC and CPCMRn matching signal
CPCMOUTn
9
M1S1
IRQ
Interrupt transfer cycle
(when MIE, IE = "1")
Figure 9-10 Example Timing for Changing the Output Level of Compare Out
(FRC Clock = 1/1 CPUCLK)
[Note]
In the above, the free running counter (FRC) clock is described as the CPUCLK base.
However, the actual FRC clock source is the time base counter (TBC) output. Therefore,
the example of Figure 9-10 is limited to the case where TBCCLK is selected as the FRC
clock with TBCCLK = CPUCLK (when the 1/n counter at the TBC front stage is set with
the value 1/1).
For further details regarding TBC, refer to Chapter 7, "Time Base Counter (TBC)".
9-13
MSM66577 Family User's Manual
Chapter 9 Capture/Compare Timer
9.9 Capture/Compare Timer Interrupt
When each capture/compare timer interrupt factor occurs, the corresponding interrupt
request flag is set to "1". Interrupt request flags are located in interrupt request register 0
(IRQ0).
Interrupts can be enabled or disabled by interrupt enable flags that correspond to each
interrupt factor. The interrupt enable flags are located in interrupt enable register 0 (IE0).
Corresponding to each interrupt factor, interrupt priority setting flags can set three levels
of priority for each interrupt factor. The interrupt priority setting flags are located in interrupt
priority control registers 0 and 1 (IP0 and IP1).
Table 9-2 lists the vector address of each interrupt factor of the capture/compare timer and
the interrupt processing flags.
Table 9-2 Capture/Compare Timer Vector Addresses and Interrupt Processing Flags
Vector
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
address [H]
1
0
Overflow of free
000C
0016
0018
QFRCOV
QCPCM0
QCPCM1
EFRCOV
ECPCM0
ECPCM1
P1FRCOV
P1CPCM0
P1CPCM1
P0FRCOV
running counter
CPCM0 capture input
CPCM0 compare match
CPCM1 capture input
CPCM1 compare match
P0CPCM0
P0CPCM1
Symbols (BYTE) of registers that
contain interrupt processing flags
IRQ0
IE0
IP0/IP1
17-22/17-23
Reference page
17-12
17-17
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
9-14
Chapter 10
Real-Time Counter (RTC)
10
MSM66577 Family User's Manual
Chapter 10 Real-Time Counter (RTC)
10. Real-Time Counter (RTC)
10.1 Overview
The MSM66577 family contains one internal 15-bit real-time clock counter (RTC).
The real-time counter runs on the clock obtained from the oscillation circuit (32.768 kHz)
connected to the XT pins. Interrupt requests at 1, 0.5, 0.25, and 0.125 seconds can be
obtained from the output of the real-time counter.
Counting continues even when in a standby state (STOP, HALT and HOLD modes). The
STOP and HALT modes can be released by the real-time counter interrupt.
10.2 Real-Time Counter Configuration
Figure 10-1 shows the real-time counter configuration.
Bit 11 (0.125 s)
Bit 12 (0.25 s)
QRTC
Bit 13 (0.5 s)
Bit 14 (1 s)
10
0
14
XT
Oscillation
circuit
XTCLK
RTCC
R
XT0
RTCCON
XT1
To CPUCLK selector
XTCLK: Real-time counter clock (32.768 kHz)
RTCC: Real-time counter (15 bits)
RTCCON: Real-time counter control register
QRTC: Real-time counter interrupt
32.768 kHz
crystal
oscillator
XT0, XT1: 32.768 kHz oscillator connection pins for real-time counter
Figure 10-1 Real-Time Counter Configuration
10-1
MSM66577 Family User's Manual
Chapter 10 Real-Time Counter (RTC)
10.3 Real-Time Counter Control Register (RTCCON)
The real-time clock control register (RTCCON) consists of 4 bits. All real-time counter
settings are performed with RTCCON.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), RTCCON becomes F0H.
Figure 10-2 shows the RTCCON configuration.
[Description of each bit]
• RTCCL (bit 0)
This bit is used to reset the real-time counter. If RTCCL is set to "1", the real-time counter
will be reset to "0". When the real-time counter is reset, RTCCL is also simultaneously
reset to "0".
• RTCIE (bit 1)
This bit enables or disables the real-time counter interrupt.
• SELRTI0, SELRTI1 (bits 2 and 3)
These bits select the interrupt cycle for the real-time counter interrupt.
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
0
SELRTI1 SELRTI0 RTCIE RTCCL
Address: 0013 [H]
R/W access: R/W
RTCCON
At reset
0
0
0
0
0
1
Real-time counter operation in progress
Reset real-time counter
0
1
Disable real-time counter interrupt
Enable real-time counter interrupt
SELRTI
Real-time counter
interrupt cycle
1
0
0
1
1
0
0
1
0
1
1 s
0.5 s
0.25 s
0.125 s
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 10-2 RTCCON Configuration
10-2
MSM66577 Family User's Manual
Chapter 10 Real-Time Counter (RTC)
10.4 Example of Real-Time Counter Register Settings
(1) Peripheral Control Register (PRPHCON)
If the real-time counter related is to run on an external clock input to the XT0 pin (instead
of the clock from the XT oscillation circuit), set bit 4 (EXTXT) to "1". Thereafter, an external
clock can be input to the XT0 pin.
(2) Real-Time Counter Control Register (RTCCON)
To reset the real-time counter, set bit 0 (RTCCL) to "1". If the real-time interrupt is to be
used, specify the real-time counter interrupt request cycle with bits 2 and 3 (SELRTI0 and
SELRTI1) and set bit 1 (RTCIE) to "1" to enable the interrupt.
10.5 Real-Time Counter Operation
The real-time counter counts upward at the falling edge of XTCLK (XT clock). The output
of real-time counter bits 11 through 14, as selected by bits 2 and 3 (SELRTI0 and SELRTI1)
of the real-time counter control register (RTCCON), generate real-time counter interrupt
requests.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the real-time counter is reset to "0". The real-time counter can also be
reset to "0" by setting the RTCCL bit of RTCCON to "1".
10
10-3
MSM66577 Family User's Manual
Chapter 10 Real-Time Counter (RTC)
10.6 Real-Time Counter Interrupt
When the real-time counter interrupt factor occurs, the interrupt request flag (QRTC) is set
to "1". The interrupt request flag (QRTC) is located in interrupt request register 3 (IRQ3).
Interrupt can be enabled or disabled by the interrupt enable flag (ERTC). The interrupt
enable flag (ERTC) is located in interrupt enable register 3 (IE3).
Three levels of priority can be set with the interrupt priority setting flags (P0RTC and
P1RTC). The interrupt priority setting flags are located in interrupt priority control register
7 (IP7).
Table 10-1 lists the vector address of the real-time counter interrupt factor and the interrupt
processing flags.
Table 10-1 Real-Time Counter Vector Address and Interrupt Processing Flags
Vector
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
address [H]
1
0
Real-time counter output
(Cycle: 0.125 to 1 s)
0048
QRTC
ERTC
P1RTC
P0RTC
Symbols (BYTE) of registers that
contain interrupt processing flags
IRQ3
IE3
IP7
Reference page
17-15
17-20
17-29
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
10-4
Chapter 11
PWM Function
11
MSM66577 Family User's Manual
Chapter 11 PWM Function
11. PWM Function
11.1 Overview
The MSM66577 family contains 4 channels of PWM (Pulse Width Modulation) function that
can vary the duty with a fixed cycle. The resolution of each channel of PWM output is 8 bits.
Useofthisfunctionas2channelsofPWMwith16-bitresolutionisalsopossible. Whenused
as a 16-bit PWM, a high-speed mode is available that does not degrade the resolution of
PWM output.
11.2 PWM Configuration
TheMSM66577familyhastwosetsof2-channel8-bitPWMs(8-bitPWM0and8-bitPWM1)
that share a common counter. These can be cascaded and used as 16-bit PWM (16-bit
mode).
Figure 11-1 shows the PWM configuration.
PWCY0
High-speed mode circuit
PWM0OUT (P7_6)
Ø
1/1 CPUCLK
S
S
Q
Q
PWM2OUT (P8_6)
1/2 TBCCLK
1/4 TBCCLK
Timer 9 OVF
OVF
R
R
PWC0
Size
Size
comparator
comparator
PWINT2
11
PWR0
PWR2
PWINT0
PWCY1
High-speed mode circuit
PWM1OUT (P7_7)
Ø
1/1 CPUCLK
1/2 TBCCLK
1/4 TBCCLK
S
S
Q
PWM3OUT (P8_7)
Q
OVF
R
R
PWC1
Size
Size
comparator
comparator
PWINT3
PWR1
PWR3
PWINT1
PWCY0, PWCY1: PWM cycle register (8 bits)
PWC0, PWC1: PWM counter (8 bits)
PWR0 to PWR3: PWM register (8 bits)
PWM0OUT to PWM3OUT: PWM output pin
PWMINT0 to PWMINT3: Interrupt request
Figure 11-1 PWM Configuration
11-1
MSM66577 Family User's Manual
Chapter 11 PWM Function
11.3 PWM Register
Table 11-1 lists a summary of SFRs for PWM control.
Table 11-1 Summary of SFRs for PWM Control
Address
[H]
Symbol
(byte)
Symbol
(word)
8/16
Initial
Reference
page
Name
R/W
Operation value [H]
0090
0091
0092
0093
0094
0095
0096
0097
0098
PWM register 0
PWR0
00
PWR01 R/W
PWR23 R/W
PWCY R/W
8/16
00
11-4
11-4
11-3
11-3
PWM register 1
PWR1
PWM register 2
PWR2
00
8/16
00
PWM register 3
PWR3
PWM cycle register 0
PWM cycle register 1
PWM counter 0
PWCY0
PWCY1
PWC0
00
8/16
00
00
PWC
R/W
8/16
00
PWM counter 1
PWC1
PWM control register 0
PWCON0
PWCON1
—
—
R/W
R/W
8
8
00
FE
11-4
11-6
0099I PWM control register 1
[Notes]
1. A star (P) in the address column indicates a missing bit.
2. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
11-2
MSM66577 Family User's Manual
Chapter 11 PWM Function
11.3.1 Description of PWM Registers
(1) PWM counters (PWC0, PWC1)
ThePWMcounters(PWC0,PWC1)are8-bitup-counters. Whenoverflowoccurs,thevalue
in PWM cycle registers (PWCY0, PWCYC1) is loaded into PWC0 and PWC1.
PWC0 and PWC1 can be read from and written to by the program. PWC0 and PWC1 can
also be accessed as 16-bit PWC. During a 16-bit access, PWC1 is the upper 8 bits and
PWC0 is the lower 8 bits of PWC.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), PWC0 and PWC1 become 00H.
[Note]
Writing a count value to PWC0 causes the same value to also be written to PWM cycle
register 0 (PWCY0). Similarly, writing a count value to PWC1 causes the same value to
also be written to PWM cycle register 1 (PWCY1).
(2) PWM cycle registers (PWCY0, PWCY1)
The PWM cycle registers (PWCY0, PWCY1) are 8-bit registers that set the PWM cycle.
PWCY0andPWCY1canbereadfromandwrittentobytheprogram. PWCY0andPWCY1
can also be accessed as 16-bit PWCY. During a 16-bit access, PWCY1 is the upper 8 bits
and PWCY0 is the lower 8 bits of PWCY.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), PWCY0 and PWCY1 become 00H.
11
[Note]
The cycle set in PWCY0 must be longer than the duty value set by PWR0 and PWR2.
Also, thecyclesetinPWCY1mustbelongerthanthedutyvaluesetbyPWR1andPWR3.
During the 16-bit mode, the cycle set in PWCY must be longer than the duty value set in
PWR01 and PWR23.
11-3
MSM66577 Family User's Manual
Chapter 11 PWM Function
(3) PWM registers (PWR0 to PWR3)
The PWM registers (PWR0 to PWR3) are 8 bit registers that set the duty value. The duty
value setting for PWR0 and PWR2 is limited to within the cycle range set by PWCY0. Also,
the duty value setting for PWR1 and PWR3 is limited to within the cycle range set by
PWCY1.
PWR0 to PWR3 can be read from and written to by the program. PWR0 and PWR1 can
also be accessed as the 16-bit PWR01. PWR2 and PWR3 can also be accessed as the
16-bit PWR23. During a 16-bit access, PWR1 is the upper 8 bits and PWR0 is the lower
8 bits of PWR01, and PWR3 is the upper 8 bits and PWR2 is the lower 8 bits of PWR23.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), PWR0 to PWR3 become 00H.
[Note]
During the 16-bit mode, the duty valu set by PWR01 and PWR23 is limited to within the
cycle range set by PWCY.
(4) PWM control register 0 (PWCON0)
The PWM control register 0 (PWCON0) consists of 8 bits. PWCON0 starts and stops the
PWM counters (PWC0, PWC1), selects the counter clock, and specifies the interrupt factor
of PWINT0 and PWINT1.
PWCON0 can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), PWCON0 becomes 00H.
Figure 11-2 shows the PWCON0 configuration.
11-4
MSM66577 Family User's Manual
Chapter 11 PWM Function
7
6
5
4
3
2
1
0
Address: 0098 [H]
R/W access: R/W
PWC1OV PWCK11 PWCK10 PW1RUN PWC0OV PWCK01 PWCK00 PW0RUN
PWCON0
At reset
0
0
0
0
0
0
0
0
0
1
Stop PWC0
Operate PWC0
PWCK0
PWC0 input clock
1
0
0
1
1
0
0
1
0
1
1/1 CPUCLK
1/2 TBCCLK
1/4 TBCCLK
TM9 overflow
0
1
PWINT0 = PWC0 and PWR0 match
PWINT0 = PWC0 overflow
0
1
Stop PWC1
Operate PWC1
PWCK1
PWC1 input clock
1
0
0
1
1
0
0
1
0
1
1/1 CPUCLK
1/2 TBCCLK
1/4 TBCCLK
PWC0 overflow (16-bit mode)
0
1
PWINT1 = PWC1 and PWR1 match
PWINT1 = PWC1 overflow
11
Figure 11-2 PWCON0 Configuration
11-5
MSM66577 Family User's Manual
Chapter 11 PWM Function
(5) PWM control register 1 (PWCON1)
ThePWMcontrolregister1(PWCON1)consistsof1bit. PWCON1registerisusedtoselect
normalmodeorhigh-speedmodeofPWM. Ifbit0(PWHSM)issetto"1",themodechanges
to high-speed mode. High-speed mode can only be used during the 16-bit mode.
PWCON can be read from or written to by the program. However, write operations are
invalid for bits 1 through 7. If read, a value of "1" will always be obtained for bits 1 through
7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), PWCON1 becomes FEH.
Figure 11-3 shows the PWCON1 configuration.
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
PWHSM
0
Address: 0099 [H]
R/W access: R/W
PWCON1
At reset
0
Normal mode
1
High-speed mode
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 11-3 PWCON1 Configuration
[Note]
High-speed mode is only valid when 16-bit PWM is used.
11-6
MSM66577 Family User's Manual
Chapter 11 PWM Function
11.3.2 Example of PWM-related Register Settings
• 8-bit PWM settings
(1) Port 7 mode register (P7IO)
If PWM0OUT is to be used, set bit 6 (P7IO6) to "1" to configure the port as an output. If
PWM1OUT is to be used, set bit 7 (P7IO7) to "1" to configure the port as an output.
(2) Port 8 mode register (P8IO)
If PWM2OUT is to be used, set bit 6 (P8IO6) to "1" to configure the port as an output. If
PWM3OUT is to be used, set bit 7 (P8IO7) to "1" to configure the port as an output.
(3) Port 7 secondary function control register (P7SF)
If PWM0OUT is to be used, set bit 6 (P7SF6) to "1" to configure the port as a secondary
function output. If PWM1OUT is to be used, set bit 7 (P7SF7) to "1" to configure the port
as a secondary function output. In the PWM initial state or when PWM function is halted,
thePWMoutputportisfixedat"1". Tofixtheportat"0", returntheporttoaprimaryfunction.
(4) Port 8 secondary function control register (P8SF)
If PWM2OUT is to be used, set bit 6 (P8SF6) to "1" to configure the port as a secondary
function output. If PWM3OUT is to be used, set bit 7 (P8SF7) to "1" to configure the port
as a secondary function output. In the PWM initial state or when PWM function is halted,
thePWMoutputportisfixedat"1". Tofixtheportat"0", returntheporttoaprimaryfunction.
(5) PWM counters (PWC0, PWC1)
Set these counters with the value at which to start counting. Writing to PWC0 and PWC1
causes the same value to be simultaneously and automatically written to PWCY0 and
PWCY1.
11
(6) PWM cycle registers (PWCY0, PWCY1)
If PWM0OUT and PWM2OUT are to be used, set the PWM cycle in PWCY0. If PWM1OUT
and PWM3OUT are to be used, set the PWM cycle in PWCY1.
(7) PWM registers (PWR0 to PWR3)
If PWMnOUT are to be used, set the desired output duty value in PWRn (where n = 0 to 3).
Set a value for PWR0 and PWR2 that is larger than the value of PWCY0. Set a value for
PWR1 and PWR3 that is larger than the value of PWCY1.
11-7
MSM66577 Family User's Manual
Chapter 11 PWM Function
(8) PWM control register 0 (PWCON0)
If PWM0OUT and PWM2OUT are to be used, set the count clock for PWM counter 0
(PWC0) with bits 1 and 2 (PWCK00, PWCK01), and specify the interrupt factor that will
initiate a PWINT0 interrupt request with bit 3 (PWC0OV). If bit 0 (PW0RUN) is set to "1",
the PWM counter 0 (PWC0) begins counting. If reset to "0" the counting is halted.
If PWM1OUT and PWM3OUT are to be used, set the count clock for PWM counter 1
(PWC1) with bits 5 and 6 (PWCK10, PWCK11), and specify the interrupt factor that will
initiate a PWINT1 interrupt request with bit 7 (PWC1OV). If bit 4 (PW1RUN) is set to "1",
the PWM counter 1 (PWC1) begins counting. If reset to "0" the counting is halted.
[Equation to Calculate 8-Bit PWM Cycle]
f
= PWCLK / (256 – PWCYn)
f
: PWM cycle [Hz]
(PWM8)
(PWM8)
PWCLK : PWM input clock frequency [Hz]
PWCYn : Value of PWCY0 or PWCY1 (8 bits)
• 16-bit PWM settings
(1) Port 7 mode register (P7IO)
If PWM1OUT is to be used, set bit 7 (P7IO7) to "1" to configure the port as an output.
(2) Port 8 mode register (P8IO)
If PWM3OUT is to be used, set bit 7 (P8IO7) to "1" to configure the port as an output. When
the PWM function does not operate, this port is fixed at "1".
(3) Port 7 secondary function control register (P7SF)
If PWM1OUT is to be used, set bit 7 (P7SF7) to "1" to configure the port as a secondary
function output. In the PWM initial state or when PWM function is halted, the PWM output
port is fixed at "1". To fix the port at "0", return the port to a primary function.
(4) Port 8 secondary function control register (P8SF)
If PWM3OUT is to be used, set bit 7 (P8SF7) to "1" to configure the port as a secondary
function output. In the PWM initial state or when PWM function is halted, the PWM output
port is fixed at "1". To fix the port at "0", return the port to a primary function.
(5) PWM counters (PWC0, PWC1)
Set these counters with the value at which to start counting. Writing to PWC causes the
same value to be simultaneously and automatically written to PWCY.
(6) PWM cycle register (PWCY)
Set the PWM cycle in PWCY.
(7) PWM registers (PWR01, PWR23)
If PWM1OUT is to be used, set the desired output duty value in PWR01. If PWM3OUT is
tobeused,setthedesiredoutputdutyvalueinPWR23. SetavalueforPWR01andPWR23
that is larger than the value of PWCY.
11-8
MSM66577 Family User's Manual
Chapter 11 PWM Function
(8) PWM control register 0 (PWCON0)
Setting both bits 5 and 6 (PWCK10 and PWCK11) to "1" cascades the two counters (16-
bit mode) so that overflow of PWM counter 0 (PWC0) is the clock input to PWM counter 1
(PWC1), thereby forming 16-bit PWM counter (PWC). Bits 1 and 2 (PWCK00 and
PWCK01) specify the count clock. Bits 3 and 7 (PWC0OV and PWC1OV) specify the
interrupt factor for PWINT0 and PWINT1 interrupt requests. Leaving bit 4 (PW1RUN) set
to "1" allows starting and stopping during the 16-bit mode to be controlled with only bit 0
(PW0RUN).
(9) PWM control register 1 (PWCON1)
Bit 0 (PWHSM) specifies normal 16-bit mode or high-speed mode. During the high-speed
mode, starting and stopping can be controlled with only bit 4 (PW1RUN) of PWCON0.
[Equation to Calculate 16-Bit PWM Cycle]
f
= PWCLK / (65536 – PWCY)
f
: PWM cycle [Hz]
(PWM16)
(PWM16)
PWCLK : PWM input clock frequency [Hz]
PWCY : Value of PWCY (16 bits)
11.4 PWM Operation
11.4.1 PWM Operation During 8-bit Mode
During the 8-bit mode, PWM output can use the four output pins of PWM0OUT through
PWM3OUT.
PWM is started by setting the corresponding RUN bit (PW0RUN, PW1RUN) to "1". When
the corresponding RUN bit becomes 1, PWC0 and/or PWC1 begin counting, at the same
time the output flip-flop is set to "1", and a High level is output from the PWMnOUT pin
(where n = 0 to 3). PWC0 and PWC1 continue to count upward. When their value matches
the contents of the corresponding PWRn, an interrupt request is generated, the output flip-
flop is reset to "0", and a Low level is output from the PWMnOUT pin. If PWC0 and PWC1
overflow, the output flip-flop is set to "1", and the PWMnOUT pin outputs a High level. Also,
the value of PWCY0 and PWCY1 is loaded into PWC0 and PWC1. Thereafter, until the
RUN bit is reset to "0", this operation will repeat and the duty controlled waveform will be
output from the PWMnOUT pin. When the RUN bit is reset to "0", the PWMnOut pin is fixed
at "1".
11
[Note]
Depending upon the count clock selected for PWC0 and PWC1, immediately after PWM
is started, the PWM output duty may be shortened (for one cycle only).
IfthevalueofPWC0andPWC1is00H, andthevalueofthecorrespondingPWRnis00H,
the duty output is 1/256. Increasing the value of PWRn increases the output duty (High
level). If the value of PWRn is FFH, the output is 256/256 or 100% duty. To realize 0/
256 or 0% duty, use the port 1 primary function since 0% duty cannot be realized with the
PWM function.
Figure 11-4 shows an example of PWM output operation.
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MSM66577 Family User's Manual
Chapter 11 PWM Function
11.4.2 PWM Operation During 16-bit Mode
During the 16-bit mode, PWM output can use the two output pins of PWM1OUT and
PWM3OUT.
PWMisstartedbyfirstsettingPW1RUNto"1",andthenbysettingPWM0RUNto"1". When
the RUN bit becomes 1, PWC begins counting, the output flip-flop is simultaneously set to
"1", and a High level is output from the PWM1OUT pin (PWM3OUT pin). PWC continues
to count upward. When its value matches the contents of PWR01 (PWR23), a PWINT1
(PWINT3) interrupt request is generated, the output flip-flop is reset to "0", and a Low level
is output from the PWM1OUT pin (PWM3OUT pin). If PWC overflows, the output flip-flop
is set to "1", and the PWM1OUT pin (PWM3OUT pin) outputs a High level. Also, the value
of PWCY is loaded into PWC. Thereafter, until the RUN bit is reset to "0", this operation
will repeat and the duty controlled waveform will be output from the PWM1OUT pin
(PWM3OUT pin). When the RUN bit is reset to "0", the PWMnOut pin is fixed at "1".
However, even in the 16-bit mode, an interrupt request (PWINT2) is generated when the
value of PWC0 (lower 8 bits of PWC) matches that of PWR2 (lower 8 bits of PWR23). Also,
a PWINT0 interrupt is generated when the value of PWC0 (lower 8 bits of PWC) matches
that of PWR0 (lower 8 bits of PWR01), and an interrupt request (PWINT0) is generated
when PWC0 overflows.
[Note]
DependinguponthecountclockselectedforPWC, immediatelyafterPWMisstarted, the
PWM output duty may be shortened (for one cycle only).
IfthevalueofPWCis0000H, andthevalueofPWR01(PWR23)is0000H, thedutyoutput
is 1/65536. Increasing the value of PWR01 (PWR23) increases the output duty (High
level). If the value of PWR01 (PWR23) is FFFFH, the output is 65536/65536 or 100%
duty. Torealize0/65536or0%duty, usetheport1primaryfunctionsince0%dutycannot
be realized with the PWM function.
Figure 11-4 shows an example of PWM output operation. Figure 11-5 shows an example
of the timing at which PWM output changes.
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MSM66577 Family User's Manual
Chapter 11 PWM Function
OVF
PWC contents
PWCY contents
Value of (PWR-PWCY)
RUN bit
PWM output
waveform
RUN bit is set
PWC = PWR
PWC overflows
PWC = PWR
PWC overflows
PWC = PWR
Figure 11-4 Example of PWM Output Operation
11
CPUCLK
PWM clock 1/4 CPUCLK
PWC contents
100H
101H
100H
102H
PWRn contents
PWC and PWRn matching signal
Change in PWM output pin
Figure 11-5 Example of PWM Output Change Timing
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MSM66577 Family User's Manual
Chapter 11 PWM Function
11.4.3 PWM Operation During High-Speed Mode
During the 16-bit mode, setting bit 0 (PWHSM) of PWCON1 to "1" changes the mode to the
high-speed mode. In the high-speed mode, as shown in Figure 11-6, overflow of the upper
8 bits of PWC cause the lower 8 bits of PWC to be incremented. The contents of PWC and
PWR are compared, and a High level is output while PWC ≤ PWR.
1 cycle
FFH
Contents of PWC (upper 8 bits)
00H
Contents of PWC (lower 8 bits)
Contents of PWR
00H
01H
02H
FDH
FEH
FFH
0102H
PWM output
PWC value when PWM output
changes to a High level
0000H, 0001H, 0002H, 0003H 00FDH 00FEH 00FFH
0100H 0101H 0102H
Duty
2/65536 2/65536 2/65536 1/65536 1/65536 1/65536 1/65536
Figure 11-6 PWM Output Waveform During High-Speed Mode
The PWM output in the normal 16-bit mode is 1 pulse per cycle as specified by PWCY.
Therefore, when PWCY is 0000H (longest cycle), the PWM output is approximately 458 Hz
(for a main clock of 30 MHz). In the high-speed mode, a maximum of 256 pulses are output
in the cycle specified by PWCY. The PWM output can achieve the high-speed of 117.2
kHz (for a main clock of 30 MHz). With 256 pulses, because the sum of High and Low
intervals is the same as for the 16-bit mode, there is no change in PWM resolution.
Figure 11-7 shows an example of PWM output during the high-speed mode when PWCY
is 0000H (longest cycle).
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MSM66577 Family User's Manual
Chapter 11 PWM Function
PWM Register value
151413121110 9 8 7 6 5 4 3 2 1 0
1/65536
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1
1/65536 1/65536
1/65536 1/65536 1/65536
2/65536 1/65536 1/65536
3/65536 3/65536 2/65536
1/65536 1/65536 1/65536
–256 pulses total–
1/65536 1/65536 1/65536
2/65536 2/65536 2/65536
65279/65536
65535/65536
65536/65536
255/
65536
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11
Figure 11-7 Example of PWM Output During High-Speed Mode
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MSM66577 Family User's Manual
Chapter 11 PWM Function
11.5 PWM Interrupts
When each PWM interrupt factor occurs, the corresponding interrupt request flag is set to
"1". Interrupt request flags are located in interrupt request register 4 (IRQ4).
Interrupts can be enabled or disabled by the interrupt enable flag corresponding to each
interrupt factor. The interrupt enable flags are located in interrupt enable register 4 (IE4).
Three levels of priority can be set with the interrupt priority setting flag corresponding to
each interrupt factor. The interrupt priority setting flags are located in interrupt priority
control register 8 (IP8).
Table 11-2 lists the vector address of each PWM interrupt factor and the interrupt
processing flags.
Table 11-2 PWM Vector Addresses and Interrupt Processing Flags
Vector
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
address [H]
1
0
Overflow of PWC0
006A
006C
QPWM0
QPWM1
EPWM0
EPWM1
P1PWM0
P1PWM1
P0PWM0
Match of PWC0 and PWR0
Overflow of PWC1
P0PWM1
Match of PWC1 and PWR1
Match of PWC0 and PWR2
Match of PWC1 and PWR3
006E
0070
QPWM2
QPWM3
EPWM2
EPWM3
P1PWM2
P1PWM3
P0PWM2
P0PWM3
Symbols (BYTE) of registers that
contain interrupt processing flags
IRQ4
IE4
IP8
Reference page
17-16
17-21
17-30
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
11-14
Chapter 12
Serial Port Functions
12
MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12. Serial Port Functions
12.1 Overview
The MSM66577 family contains four built-in serial port channels: two UART/Synchronous
receiver transmitter serial port channels (SIO1 and SIO6), and two channels (SIO4 and
SIO5) of synchronous receiver transmitter serial ports with 32-byte FIFO.
12.2 Serial Port Configuration
Figure 12-1 shows the configuration of the serial ports.
TXD1 (P8_1)
TXC1 (P8_3)
RXD1 (P8_0)
RXC1 (P8_2)
BRG
(Timer 4)
SIO1 (UART/SYNC)
1/1 OSCCLK
1/2 OSCCLK
1/4 OSCCLK
1/8 OSCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/2 TM5OVF
SIOO4 (P10_4)
SIOI4 (P10_5)
SIO4 (SYNC with 32-byte FIFO)
SIOCK4 (P10_3)
1/1 OSCCLK
1/2 OSCCLK
1/4 OSCCLK
1/8 OSCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/2 TM5OVF
SIOO5 (P14_1)
SIOI5 (P14_2)
SIOCK5 (P14_0)
SIO5 (SYNC with 32-byte FIFO)
12
TXD6 (P15_1)
TXC6 (P15_3)
RXD6 (P15_0)
RXC6 (P15_2)
BRG
(Timer 3)
SIO6 (UART/SYNC)
Figure 12-1 Serial Port Configuration
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Chapter 12 Serial Port Functions
12.3 Serial Port Registers
Table 12-1 lists a summary of SFRs for control of the serial port functions.
Table 12-1 Summary of SFRs for Serial Port Function Control
Address
[H]
Symbol
(byte)
Symbol
(word)
—
8/16
Initial
Reference
page
Name
R/W
Operation value [H]
0084I SIO1 transmit control register ST1CON
R/W
R/W
8
8
04
00
12-4
0085
SIO1 receive control register
SIO1 transmit-receive
buffer register
SR1CON
—
12-6
0086
S1BUF
—
R/W
8
Undefined
12-10
0087I SIO1 status register
008CI SIO4 control register
S1STAT
SIO4CON
FIFOCON
—
—
—
R/W
R/W
R/W
8
8
8
00
80
11
12-8
12-41
12-43
008D
FIFO control register
SIO4 serial input FIFO
data register
008E
SIN4
—
—
R
8
8
Undefined
Undefined
12-45
12-45
SIO4 serial output FIFO
data register
008F
SOUT4
W
00CFI FIFO mode control register FIFOMOD
—
—
R/W
R/W
8
8
FC
80
12-54
12-52
00D5I SIO5 control register
SIO5CON
SIO5 serial input FIFO
00D6
SIN5
—
—
R
8
8
Undefined
Undefined
12-54
12-54
data register
SIO5 serial output FIFO
00D7
SOUT5
W
data register
00F4I SIO6 transmit control register ST6CON
—
—
R/W
R/W
8
8
04
00
12-16
12-18
00F5
SIO6 receive control register
SIO6 transmit-receive
buffer register
SR6CON
00F6
S6BUF
—
—
R/W
R/W
8
8
Undefined
00
12-22
12-20
00F7I SIO6 status register
S6STAT
[Notes]
1. Addresses are not consecutive in some places.
2. A star (P) in the address column indicates a missing bit.
3. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12.4 SIO1
The SIO1 has a UART mode and a synchronous mode. Timer 4 is used as a baud rate
generator exclusively for SIO1.
Table 12-2 lists specifications of SIO1.
Table 12-2 SIO1 Specifications
UART mode
Synchronous mode
Data length
Selectable as 7 or 8 bits
Odd, even, none
Selectable as 7 or 8 bits
Parity
Error service
Stop bit
Parity, overrun, framing
Selectable as 1 or 2 bits
Transmit buffer empty, transmit
complete, receive complete
Overrun
Factors that generate
interrupt requests
Full-duplex
Transmit buffer empty, transmit
complete, receive complete
Possible
Possible
communication
Both transmission and reception
data are double buffered
Both transmission and reception
data are double buffered
Transmit-receive buffer
Max. communication
speed (f = 30MHz)
1.875 Mbps
7.5 Mbps
LSB first
LSB first
An external clock can be used for
the UART baud rate
Master mode/ slave mode
Other
12.4.1 SIO1 Configuration
12
Figure 12-2 shows the SIO1 configuration.
Internal bus
BRG
S1BUF ST1CON S1STAT
Transmission control circuit
S1BUF SR1CON S1STAT
Reception control circuit
(Timer 4)
1/n
1/n
Transmit shift register
Receive shift register
TXD1 (P8_1)
TXC1 (P8_3)
RXD1 (P8_0)
RXC1 (P8_2)
BRG: Baud rate generator (timer 4)
S1BUF: Transmit-receive buffer register
ST1CON: SIO1 transmit control register
SR1CON: SIO1 receive control register
S1STAT: SIO1 status register
1/n: 1/n frequency dividing counter
TXD1: SIO1 transmit data output pin (P8_1)
TXC1: SIO1 transmit clock I/O pin (P8_3)
RXD1: SIO1 receive data input pin (P8_0)
RXC1: SIO1 receive clock I/O pin (P8_2)
Figure 12-2 SIO1 Configuration
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Chapter 12 Serial Port Functions
12.4.2 Description of SIO1 Registers
(1) SIO1 transmit control register (ST1CON)
The SIO1 transmit control register (ST1CON) is a 7-bit register that controls operation of
SIO1 transmission.
ST1CON can be read from and written to by the program. However, write operations are
invalid for bit 2. If read, a value of "1" will always be obtained for bit 2.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer,opcodetrap),ST1CONbecomes04H,thedatalengthforSIO1transmissionis8-bits,
2 stop bits are selected and the mode changes to UART mode with no parity.
The baud rate source is the same for transmission and reception. It is set by the receive
control register (SR1CON) to be described later.
[Note]
If ST1CON is to be modified, make those changes after transmission is complete. If
ST1CON is modified before transmission is completed, the current transmission and
future transmissions will not be executed correctly.
Figure 12-3 shows the ST1CON configuration.
[Description of each bit]
• ST1MOD (bit 0)
ST1MOD specifies the transmission mode (UART or synchronous).
• ST1LN (bit 1)
ST1LN specifies the SIO1 transmit data length.
• ST1STB/ST1SLV (bit 3)
During the UART mode, ST1STB specifies the SIO1 stop bit length.
During the synchronous mode, ST1SLV specifies master or slave operation.
• ST1PEN (bit 4)
ST1PEN specifies whether there is parity during SIO1 transmission. (Only valid during
the UART mode)
• ST1ODD (bit 5)
ST1ODD specifies the parity bit logic during SIO1 transmission. (Only valid during the
UART mode)
• TR1MIE (bit 6)
TR1MIE specifies whether to use the SIO1 transmit buffer empty signal as an interrupt
request signal.
• TR1NIE (bit 7)
TR1NIE specifies whether to use the SIO1 transmit complete signal as an interrupt
request signal.
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
7
6
5
4
3
2
1
0
ST1STB
ST1SLV
Address: 0084 [H]
R/W access: R/W
TR1NIE TR1MIE ST1ODD ST1PEN
—
1
ST1LN ST1MOD
ST1CON
At reset
0
0
0
0
0
0
0
UART mode
0
1
Synchronous mode
8-bit transmit data length
7-bit transmit data length
0
1
2 stop bits
1 stop bit
0
1
UART mode
(ST1STB)
Master mode transmission
Slave mode transmission
Synchronous mode
(ST1SLV)
0
1
No parity
Parity
UART mode
0
1
Even parity
Odd parity
0
1
UART mode
Transmit buffer empty interrupt request disabled
Transmit buffer empty interrupt request enabled
0
1
Transmit complete interrupt request disabled
Transmit complete interrupt request enabled
0
1
"—" indicates a nonexistent bit.
When read, its value will be "1."
12
Figure 12-3 ST1CON Configuration
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
(2) SIO1 receive control register (SR1CON)
The SIO1 receive control register (SR1CON) is an 8-bit register that controls operation of
SIO1 reception.
SR1CON can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), SR1CON becomes 00H and SIO1 reception is disabled.
[Note]
If SR1CON is to be modified, first reset SR1REN (bit 7) to "0" and then implement the
change. If SR1CON is modified before SR1REN (bit 7) is reset to "0", the current
reception and future receptions will not be executed correctly.
Figure 12-4 shows the SR1CON configuration.
[Description of each bit]
• SR1MOD (bit 0)
SR1MOD specifies the SIO1 reception mode (UART or synchronous).
• SR1LN (bit 1)
SR1LN specifies the SIO1 receive data length.
• S1EXC (bit 2)
S1EXC specifies the baud rate clock to be used by SIO1 during the UART mode. (This
clock is the same for both transmission and reception. The shift clock has a frequency
1/16th of the clock specified here.)
• SR1SLV (bit 3)
During the synchronous mode, ST1SLV specifies master or slave operation of SIO1.
(Only valid during the synchronous mode)
• SR1PEN (bit 4)
SR1PEN specifies whether there is parity during SIO1 reception. (Only valid during the
UART mode)
• SR1ODD (bit 5)
SR1ODD specifies the parity bit logic during SIO1 reception. (Only valid during the UART
mode)
• RC1IE (bit 6)
RC1IE specifies whether to use the SIO1 receive complete signal as an interrupt request
signal.
• SR1REN (bit 7)
SR1REN enables or disables SIO1 reception.
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Chapter 12 Serial Port Functions
7
6
5
4
3
2
1
0
Address: 0085 [H]
R/W access: R/W
SR1CON
At reset
SR1REN RC1IE SR1ODD SR1PEN SR1SLV S1EXC SR1LN SR1MOD
0
0
0
0
0
0
0
0
UART mode
0
1
Synchronous mode
8-bit receive data length
7-bit receive data length
0
1
Timer 4 overflow
External input
0
1
UART mode
Master mode reception
Slave mode reception
0
1
Synchronous mode
UART mode
No parity
Parity
0
1
Even parity
Odd parity
0
1
UART mode
Receive complete interrupt request disabled
Receive complete interrupt request enabled
0
1
SIO1 reception disabled
SIO1 reception enabled
0
1
Figure 12-4 SR1CON Configuration
12
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
(3) SIO1 status register (S1STAT)
The SIO1 status register (S1STAT) consists of 6 bits. Bits 0 through 2 save the SIO1 status
(normal or error) after reception is completed. Bits 3 through 5 save the status of SIO1 at
the start and completion of transmission and reception. However bits 0 through 2 are
updated after the reception is completed.
S1STAT can be read from and written to by the program. However, write operations are
invalid for bits 6 and 7. If read, a value of "0" will always be obtained for bits 6 and 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), S1STAT becomes 00H.
Figure 12-5 shows the S1STAT configuration.
[Description of each bit]
• FERR1 (bit 0)
If the stop bit in the data received by SIO1 is "0", FERR1 is set to "1" (framing error). This
bit is only valid during the UART mode.
• OERR1 (bit 1)
When the SIO1 reception is complete, if the previously received data has not been read
by the program, OERR1 is set to "1" (overrun error).
• PERR1 (bit 2)
If the parity bit in the data received by SIO1 does not match the parity of the data, PERR1
is set to "1" (parity error). This bit is only valid during the UART mode.
• TR1EMP (bit 3)
If the SIO1 transmit buffer empty signal is generated, TR1EMP is set to "1".
• TR1END (bit 4)
If the SIO1 transmit complete signal is generated, TR1EMP is set to "1".
• RC1END (bit 5)
If the SIO1 receive complete signal is generated, RC1END is set to "1".
[Note]
Once each bit of S1STAT is set to "1", the hardware does not reset the bits to "0".
Therefore, reset the bits to "0" with the program.
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
7
—
0
6
—
0
5
4
3
2
1
0
Address: 0087 [H]
R/W access: R/W
S1STAT
At reset
RC1END TR1END TR1EMP PERR1 OERR1 FERR1
0
0
0
0
0
0
No framing error
Framing error
0
1
UART mode
No overrun error
Overrun error
0
1
No parity error
Parity error
0
1
UART mode
0
1
Transmit buffer empty signal not generated
Transmit buffer empty signal generated
Transmit complete signal not generated
Transmit complete signal generated
0
1
Receive complete signal not generated
Receive complete signal generated
0
1
"—" indicates a nonexistent bit.
When read, its value will be "0."
Figure 12-5 S1STAT Configuration
12
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
(4) SIO1 transmit-receive buffer register (S1BUF)
The SIO1 transmit-receive buffer register (S1BUF) is an 8-bit register that stores the
transmit and receive data for serial port transmission and reception. Because S1BUF has
a duplex configuration for transmission and reception, it operates as a transmission buffer
when written to, and as a reception buffer when read from.
After the transmit data has been written to S1BUF, the transmit data is transferred to the
transmit shift register and the transmit buffer empty signal is generated. At that time, SIO1
will begin transmission.
After reception is complete, the contents of the receive shift register are transferred to
S1BUF and at that time, the receive complete signal is generated. The contents of S1BUF
are saved until the next reception is completed.
During a 7-bit data reception, bit 7 of S1BUF is "1", and the 7 bits from bit 0 through bit 6
are the reception data.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the value of S1BUF is undefined.
(5) SIO1 transmit shift register, receive shift register
The transmit shift register and receive shift register are 8-bit shift registers that perform the
actual shifting operation during transmission and reception.
The transmit shift register and receive shift register cannot be read from or written to by the
program.
Table 12-3 lists SIO1 transmit-receive frame lengths.
Table 12-3 SIO1 Transmit-Receive Frame Lengths
ST1CON/SR1CON
Transmit/Receive Frame Length
ST1PEN
ST1LN ST1MOD
[bit]
ST1STB
1
2
3
4
5
6
7
8
9
10 11 12
SR1PEN
SR1LN SR1MOD
START
STOP STOP
8-bit data
7-bit data
8-bit data
7-bit data
8-bit data
7-bit data
8-bit data
7-bit data
8-bit data
7-bit data
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
START
START
START
START
START
START
START
STOP STOP
STOP
0
0
0
1
1
1
1
0
1
1
0
0
1
1
STOP
PARITY STOP STOP
PARITY STOP STOP
PARITY STOP
PARITY STOP
– –
– –
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12.4.3 Example of SIO1-related Register Settings
12.4.3.1 UART Mode Settings
• Transmit settings
(1) Port 8 mode register (P8IO)
If TXD8 (transmit data output) is to be used, set bit 1 (P8IO1) to "1" to configure that port
as an output. If the baud rate clock is to be input externally, reset bit 2 (P8IO2) to "0" to
configure that port as an input.
(2) Port 8 secondary function control register (P8SF)
If TXD1 (transmit data output) is to be used, set bit 1 (P8SF1) to "1" to configure that port
as a secondary function output. If the baud rate clock is to be input externally, specify with
bit 2 (P8SF2) whether the input will be pulled-up.
(3) SIO1 transmit control register (ST1CON)
Reset bit 0 (ST1MOD) to "0" to change the mode to UART mode. Specify the transmit data
length with bit 1 (ST1LN). Specify the stop bit length with bit 3 (ST1STB). Specify whether
there is parity with bit 4 (ST1PEN). If parity is selected, specify the parity bit logic with bit
5 (ST1ODD). With bit 6 (TR1MIE), specify whether interrupt requests are enabled or
disabled when a transmit buffer empty signal occurs. With bit 7 (TR1NIE), specify whether
interrupt requests are enabled or disabled when a transmit complete signal occurs.
(4) SIO1 receive control register (SR1CON)
Specify with bit 2 (S1EXC) whether the baud rate clock is internal (overflow output of timer
4) or external (RXC1).
(5) SIO1 transmit-receive buffer register (S1BUF)
12
Transmission is started by writing the transmit data to S1BUF.
• Receive settings
(1) Port 8 mode register (P8IO)
If RXD1 (receive data input) is to be used, reset bit 0 (P8IO0) to "0" to configure that port
as an input. If the baud rate clock is to be input externally, reset bit 2 (P8IO2) to "0" to
configure that port as an input.
(2) Port 8 secondary function control register (P8SF)
Specify with bit 1 (P8SF0) whether the RXD1 pin will be pulled-up. If the baud rate clock
is to be input externally, specify with bit 2 (P8SF2) whether the input will be pulled-up.
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Chapter 12 Serial Port Functions
(3) SIO1 receive control register (SR1CON)
Reset bit 0 (SR1MOD) to "0" to change the mode to UART mode. Specify the receive data
lengthwithbit1(SR1LN). Specifywithbit2(S1EXC)whetherthebaudrateclockisinternal
(overflow output of timer 4) or external (RXC1). Specify whether there is parity with bit 4
(SR1PEN). If parity is selected, specify the parity bit logic with bit 5 (SR1ODD). With bit
7 (RC1IE), specify whether interrupt requests are enabled or disabled when a receive
complete signal occurs. If bit 7 (SR1REN) is set to "1", reception is enabled and the
reception operation is performed when data arrives.
12.4.3.2 Synchronous Mode Settings
• Transmit settings
(1) Port 8 mode register (P8IO)
If TXD1 (transmit data output) is to be used, set bit 1 (P8IO1) to "1" to configure that port
as an output. If the transmit clock is to be output externally (master mode), set bit 3 (P8IO3)
to"1"toconfigurethatportasanoutput. Ifthebaudrateclockistobeinputexternally(slave
mode), reset bit 3 (P8IO3) to "0" to configure that port as an input.
(2) Port 8 secondary function control register (P8SF)
If TXD1 (transmit data output) is to be used, set bit 1 (P8SF1) to "1" to configure that port
as a secondary function output. If the transmit clock is to be output externally (master
mode), set bit 3 (P8SF3) to "1" to configure that port as a secondary function output. If the
baud rate clock is to be input externally (slave mode), specify with bit 3 (P8SF3) whether
the input will be pulled-up.
(3) SIO1 transmit control register (ST1CON)
Set bit 0 (ST1MOD) to "1" to specify the mode to synchronous mode. Specify the transmit
data length with bit 1 (ST1LN). Specify master or slave mode transmission with bit 3
(ST1STB). Withbit6(TR1MIE), specifywhetherinterruptrequestsareenabledordisabled
when a transmit buffer empty signal occurs. With bit 7 (TR1NIE), specify whether interrupt
requests are enabled or disabled when a transmit complete signal occurs.
(4) SIO1 transmit-receive buffer register (S1BUF)
Transmission is started by writing the transmit data to S1BUF.
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• Receive settings
(1) Port 8 mode register (P8IO)
If RXD1 (receive data input) is to be used, reset bit 0 (P8IO0) to "0" to configure that port
as an input. If the transmit clock is to be output externally (master mode), set bit 2 (P8IO2)
to "1" to configure that port as an output. If the transmit clock is to be input externally (slave
mode), reset bit 2 (P8IO2) to "0" to configure that port as an input.
(2) Port 8 secondary function control register (P8SF)
Specify with bit 0 (P8SF0) whether the RXD1 pin will be pulled-up. If the transmit clock is
to be output externally (master mode), set bit 2 (P8SF2) to "1" to configure that port as a
secondary function output. If the transmit clock is to be input externally (slave mode),
specify with bit 2 (P8SF2) whether the input will be pulled-up.
(3) SIO1 receive control register (SR1CON)
Set bit 0 (SR1MOD) to "1" to specify the mode to synchronous mode. Specify the receive
datalengthwithbit1(SR1LN). Specifythemasterorslavemodewithbit3(SR1SLV). With
bit 6 (RC1IE), specify whether interrupt requests are enabled or disabled when a receive
complete signal occurs. If bit 7 (SR1REN) is set to "1", reception is enabled and the
reception operation is performed when data arrives.
12.4.3.3 Baud Rate Generator (Timer 4) Settings
If overflow of timer 4 is selected for use as the baud rate clock, implement the following
settings.
(1) General-purpose 8-bit timer 4 counter (TM4C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM4C,thesame
value will also be simultaneously and automatically written to the general-purpose 8-bit
timer 4 register (TM4R).
12
(2) General-purpose 8-bit timer 4 control register (TM4CON)
Bits 0 to 2 (TM4C0 to TM4C2) of this register specify the count clock for timer 4. If bit 3
(TM4RUN) is set to "1", timer 4 will begin counting. If reset to "0", timer 4 will halt counting.
[Equation to Calculate Baud Rate]
B = f
¥ 1/(256 – D) ¥ 1/n
B : baud rate [bps]
: timer 4 input clock frequency [Hz]
(TM4)
f
(TM4)
D : reload value (0 to 255)
n : 16 for the UART mode
4 for the synchronous mode
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12.4.4 SIO1 Interrupt
When any SIO1 interrupt factor occurs, the interrupt request flag (QSIO1) is set to "1". The
interrupt request flag (QSIO1) is located in interrupt request register 2 (IRQ2).
Interrupts can be enabled or disabled by the interrupt enable flag (ESIO1). The interrupt
enable flag (ESIO1) is located in interrupt enable register 2 (IE2).
Three levels of priority can be set with the interrupt priority setting flags (P0SIO1 and
P1SIO1). The interrupt priority setting flags (P0SIO1 and P1SIO1) are located in interrupt
priority control register 5 (IP5).
Table12-4liststhevectoraddressoftheSIO1interruptfactorsandtheinterruptprocessing
flags.
Table 12-4 SIO1 Vector Address and Interrupt Processing Flags
Vector
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
address [H]
1
0
SIO1 transmit buffer empty
signal is generated
SIO1 transmit complete
signal is generated
SIO1 receive complete
signal is generated
0038
QSIO1
ESIO1
P1SIO1
P0SIO1
Symbols (byte) of registers that
contain interrupt processing flags
IRQ2
IE2
IP5
Reference page
17-14
17-19
17-27
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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Chapter 12 Serial Port Functions
12.5 SIO6
The SIO6 has a UART mode and a synchronous mode. Timer 3 is used as a baud rate
generator exclusively for SIO6.
Table 12-5 lists specifications of SIO6.
Table 12-5 SIO6 Specifications
UART mode
Synchronous mode
Data length
Selectable as 7 or 8 bits
Odd, even, none
Selectable as 7 or 8 bits
Parity
Error service
Stop bit
Parity, overrun, framing
Selectable as 1 or 2 bits
Transmit buffer empty, transmit
complete, receive complete
Overrun
Factors that generate
interrupt requests
Full-duplex
Transmit buffer empty, transmit
complete, receive complete
Possible
Possible
communication
Both transmission and reception
data are double buffered
Both transmission and reception
data are double buffered
Transmit-receive buffer
Max. communication
speed (f = 30 MHz)
1.875 Mbps
7.5 Mbps
LSB first
LSB first
An external clock can be used for
the UART baud rate
Master mode/ slave mode
Other
12.5.1 SIO6 Configuration
12
Figure 12-6 shows the SIO6 configuration.
Internal bus
BRG
S6BUF ST6CON S6STAT
Transmission control circuit
S6BUF SR6CON S6STAT
Reception control circuit
(Timer 3)
1/n
1/n
Transmit shift register
Receive shift register
TXD6 (P15_1)
TXC6 (P15_3)
RXD6 (P15_0)
RXC6 (P15_2)
BRG: Baud rate generator (timer 3)
S6BUF: Transmit-receive buffer register
ST6CON: SIO6 transmit control register
SR6CON: SIO6 receive control register
S6STAT: SIO6 status register
1/n: 1/n frequency dividing counter
TXD6: SIO6 transmit data output pin (P15_1)
TXC6: SIO6 transmit clock I/O pin (P15_3)
RXD6: SIO6 receive data input pin (P15_0)
RXC6: SIO6 receive clock I/O pin (P15_2)
Figure 12-6 SIO6 Configuration
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12.5.2 Description of SIO6 Registers
(1) SIO6 transmit control register (ST6CON)
The SIO6 transmit control register (ST6CON) is a 7-bit register that controls operation of
SIO6 transmission.
ST6CON can be read from and written to by the program. However, write operations are
invalid for bit 2. If read, a value of "1" will always be obtained for bit 2.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer,opcodetrap),ST6CONbecomes04H,thedatalengthforSIO6transmissionis8-bits,
2 stop bits are selected and the mode changes to UART mode with no parity.
The baud rate source is the same for transmission and reception. It is set by the receive
control register (SR6CON) to be described later.
[Note]
If ST6CON is to be modified, make those changes after transmission is complete. If
ST6CON is modified before transmission is completed, the current transmission and
future transmissions will not be executed correctly.
Figure 12-7 shows the ST6CON configuration.
[Description of each bit]
• ST6MOD (bit 0)
ST6MOD specifies the transmission mode (UART or synchronous).
• ST6LN (bit 1)
ST6LN specifies the SIO6 transmit data length.
• ST6STB/ST6SLV (bit 3)
During the UART mode, ST6STB specifies the SIO6 stop bit length.
During the synchronous mode, ST6SLV specifies master or slave operation.
• ST6PEN (bit 4)
ST6PEN specifies whether there is parity during SIO6 transmission. (Only valid during
the UART mode)
• ST6ODD (bit 5)
ST6ODD specifies the parity bit logic during SIO6 transmission. (Only valid during the
UART mode)
• TR6MIE (bit 6)
TR6MIE specifies whether to use the SIO6 transmit buffer empty signal as an interrupt
request signal.
• TR6NIE (bit 7)
TR6NIE specifies whether to use the SIO6 transmit complete signal as an interrupt
request signal.
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7
6
5
4
3
2
1
0
ST6STB
ST6SLV
Address: 00F4 [H]
R/W access: R/W
TR6NIE TR6MIE ST6ODD ST6PEN
—
1
ST6LN ST6MOD
ST6CON
At reset
0
0
0
0
0
0
0
UART mode
0
1
Synchronous mode
8-bit transmit data length
7-bit transmit data length
0
1
2 stop bits
1 stop bit
0
1
UART mode
(ST6STB)
Master mode transmission
Slave mode transmission
Synchronous mode
(ST6SLV)
0
1
No parity
Parity
UART mode
0
1
Even parity
Odd parity
0
1
UART mode
Transmit buffer empty interrupt request disabled
Transmit buffer empty interrupt request enabled
0
1
Transmit complete interrupt request disabled
Transmit complete interrupt request enabled
0
1
"—" indicates a nonexistent bit.
When read, its value will be "1."
12
Figure 12-7 ST6CON Configuration
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Chapter 12 Serial Port Functions
(2) SIO6 receive control register (SR6CON)
The SIO6 receive control register (SR6CON) is an 8-bit register that controls operation of
SIO6 reception.
SR6CON can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), SR6CON becomes 00H and SIO6 reception is disabled.
[Note]
If SR6CON is to be modified, first reset SR6REN (bit 7) to "0" and then implement the
change. If SR6CON is modified before SR6REN (bit 7) is reset to "0", the current
reception and future receptions will not be executed correctly.
Figure 12-8 shows the SR6CON configuration.
[Description of each bit]
• SR6MOD (bit 0)
SR6MOD specifies the SIO6 reception mode (UART or synchronous).
• SR6LN (bit 1)
SR6LN specifies the SIO6 receive data length.
• S6EXC (bit 2)
S6EXC specifies the baud rate clock to be used by SIO6 during the UART mode. (This
clock is the same for both transmission and reception. The shift clock has a frequency
1/16th of the clock specified here.)
• SR6SLV (bit 3)
During the synchronous mode, ST6SLV specifies master or slave operation of SIO6.
(Only valid during the synchronous mode)
• SR6PEN (bit 4)
SR6PEN specifies whether there is parity during SIO6 reception. (Only valid during the
UART mode)
• SR6ODD (bit 5)
SR6ODD specifies the parity bit logic during SIO6 reception. (Only valid during the UART
mode)
• RC6IE (bit 6)
RC6IE specifies whether to use the SIO6 receive complete signal as an interrupt request
signal.
• SR6REN (bit 7)
SR6REN enables or disables SIO6 reception.
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Chapter 12 Serial Port Functions
7
6
5
4
3
2
1
0
Address: 00F5 [H]
R/W access: R/W
SR6CON
At reset
SR6 REN RC6IE SR6ODD SR6PEN SR6SLV S6EXC SR6LN SR6MOD
0
0
0
0
0
0
0
0
UART mode
0
1
Synchronous mode
8-bit receive data length
7-bit receive data length
0
1
Timer 3 overflow
External input
0
1
UART mode
Master mode reception
Slave mode reception
0
1
Synchronous mode
UART mode
No parity
Parity
0
1
Even parity
Odd parity
0
1
UART mode
Receive complete interrupt request disabled
Receive complete interrupt request enabled
0
1
SIO6 reception disabled
SIO6 reception enabled
0
1
Figure 12-8 SR6CON Configuration
12
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(3) SIO6 status register (S6STAT)
The SIO6 status register (S6STAT) consists of 6 bits. Bits 0 through 2 save the SIO6 status
(normal or error) after reception is completed. Bits 3 through 5 save the status of SIO6 at
the start and completion of transmission and reception. However bits 0 through 2 are
updated after the reception is completed.
S6STAT can be read from and written to by the program. However, write operations are
invalid for bits 6 and 7. If read, a value of "0" will always be obtained for bits 6 and 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), S6STAT becomes 00H.
Figure 12-9 shows the S6STAT configuration.
[Description of each bit]
• FERR6 (bit 0)
If the stop bit in the data received by SIO6 is "0", FERR6 is set to "1" (framing error). This
bit is only valid during the UART mode.
• OERR6 (bit 1)
When the SIO6 reception is complete, if the previously received data has not been read
by the program, OERR6 is set to "1" (overrun error).
• PERR6 (bit 2)
If the parity bit in the data received by SIO6 does not match the parity of the data, PERR6
is set to "1" (parity error). This bit is only valid during the UART mode.
• TR6EMP (bit 3)
If the SIO6 transmit buffer empty signal is generated, TR6EMP is set to "1".
• TR6END (bit 4)
If the SIO6 transmit complete signal is generated, TR6EMD is set to "1".
• RC6END (bit 5)
If the SIO6 receive complete signal is generated, RC6END is set to "1".
[Note]
Once each bit of S6STAT is set to "1", the hardware does not reset the bits to "0".
Therefore, reset the bits to "0" with the program.
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7
—
0
6
—
0
5
4
3
2
1
0
Address: 00F7 [H]
R/W access: R/W
S6STAT
At reset
RC6END TR6END TR6EMP PERR6 OERR6 FERR6
0
0
0
0
0
0
No framing error
Framing error
0
1
UART mode
No overrun error
Overrun error
0
1
No parity error
Parity error
0
1
UART mode
0
1
Transmit buffer empty signal not generated
Transmit buffer empty signal generated
Transmit complete signal not generated
Transmit complete signal generated
0
1
Receive complete signal not generated
Receive complete signal generated
0
1
"—" indicates a nonexistent bit.
When read, its value will be "0."
Figure 12-9 S6STAT Configuration
12
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Chapter 12 Serial Port Functions
(4) SIO6 transmit-receive buffer register (S6BUF)
The SIO6 transmit-receive buffer register (S6BUF) is an 8-bit register that stores the
transmit and receive data for serial port transmission and reception. Because S6BUF has
a duplex configuration for transmission and reception, it operates as a transmission buffer
when written to, and as a reception buffer when read from.
After the transmit data has been written to S6BUF, the transmit data is transferred to the
transmit shift register and the transmit buffer empty signal is generated. At that time, SIO6
will begin transmission.
After reception is complete, the contents of the receive shift register are transferred to
S6BUF and at that time, the receive complete signal is generated. The contents of S6BUF
are saved until the next reception is completed.
During a 7-bit data reception, bit 7 of S6BUF is "1", and the 7 bits from bit 0 through bit 6
are the reception data.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the value of S6BUF is undefined.
(5) SIO6 transmit shift register, receive shift register
The transmit shift register and receive shift register are 8-bit shift registers that perform the
actual shifting operation during transmission and reception.
The transmit shift register and receive shift register cannot be read from or written to by the
program.
Table 12-6 lists SIO6 transmit-receive frame lengths.
Table 12-6 SIO6 Transmit-Receive Frame Lengths
ST6CON/SR6CON
Transmit/Receive Frame Length
ST6PEN
ST6LN ST6MOD
[bit]
ST6STB
1
2
3
4
5
6
7
8
9
10 11 12
SR6PEN
SR6LN SR6MOD
START
STOP STOP
8-bit data
7-bit data
8-bit data
7-bit data
8-bit data
7-bit data
8-bit data
7-bit data
8-bit data
7-bit data
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
START
START
START
START
START
START
START
STOP STOP
STOP
0
0
0
1
1
1
1
0
1
1
0
0
1
1
STOP
PARITY STOP STOP
PARITY STOP STOP
PARITY STOP
PARITY STOP
– –
– –
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Chapter 12 Serial Port Functions
12.5.3 Example of SIO6-related Register Settings
12.5.3.1 UART Mode Settings
• Transmit settings
(1) Port 15 mode register (P15IO)
If TXD6 (transmit data output) is to be used, set bit 1 (P15IO1) to "1" to configure that port
as an output. If the baud rate clock is to be input externally, reset bit 2 (P15IO2) to "0" to
configure that port as an input.
(2) Port 15 secondary function control register (P15SF)
If TXD6 (transmit data output) is to be used, set bit 1 (P15SF1) to "1" to configure that port
as a secondary function output. If the baud rate clock is to be input externally, specify with
bit 2 (P15SF2) whether the input will be pulled-up.
(3) SIO6 transmit control register (ST6CON)
Reset bit 0 (ST6MOD) to "0" to change the mode to UART mode. Specify the transmit data
length with bit 1 (ST6LN). Specify the stop bit length with bit 3 (ST6STB). Specify whether
there is parity with bit 4 (ST6PEN). If parity is selected, specify the parity bit logic with bit
5 (ST6ODD). With bit 6 (TR6MIE), specify whether interrupt requests are enabled or
disabled when a transmit buffer empty signal occurs. With bit 7 (TR6NIE), specify whether
interrupt requests are enabled or disabled when a transmit complete signal occurs.
(4) SIO6 receive control register (SR6CON)
Specify with bit 2 (S6EXC) whether the baud rate clock is internal (overflow output of timer
3) or external (RXC6).
(5) SIO6 transmit-receive buffer register (S6BUF)
12
Transmission is started by writing the transmit data to S6BUF.
• Receive settings
(1) Port 15 mode register (P15IO)
If RXD6 (receive data input) is to be used, reset bit 0 (P15IO0) to "0" to configure that port
as an input. If the baud rate clock is to be input externally, reset bit 2 (P15IO2) to "0" to
configure that port as an input.
(2) Port 15 secondary function control register (P15SF)
Specify with bit 1 (P15SF0) whether the RXD6 pin will be pulled-up. If the baud rate clock
is to be input externally, specify with bit 2 (P15SF2) whether the input will be pulled-up.
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Chapter 12 Serial Port Functions
(3) SIO6 receive control register (SR6CON)
Reset bit 0 (SR6MOD) to "0" to change the mode to UART mode. Specify the receive data
lengthwithbit1(SR6LN). Specifywithbit2(S6EXC)whetherthebaudrateclockisinternal
(overflow output of timer 3) or external (RXC6). Specify whether there is parity with bit 4
(SR6PEN). If parity is selected, specify the parity bit logic with bit 5 (SR6ODD). With bit
6 (RC6IE), specify whether interrupt requests are enabled or disabled when a receive
complete signal occurs. If bit 7 (SR6REN) is set to "1", reception is enabled and the
reception operation is performed when data arrives.
12.5.3.2 Synchronous Mode Settings
• Transmit settings
(1) Port 15 mode register (P15IO)
If TXD6 (transmit data output) is to be used, set bit 1 (P15IO1) to "1" to configure that port
asanoutput. Ifthetransmitclockistobeoutputexternally(mastermode),setbit3(P15IO3)
to"1"toconfigurethatportasanoutput. Ifthebaudrateclockistobeinputexternally(slave
mode), reset bit 3 (P15IO3) to "0" to configure that port as an input.
(2) Port 15 secondary function control register (P15SF)
If TXD6 (transmit data output) is to be used, set bit 1 (P15SF1) to "1" to configure that port
as a secondary function output. If the transmit clock is to be output externally (master
mode), set bit 3 (P15SF3) to "1" to configure that port as a secondary function output. If the
baud rate clock is to be input externally (slave mode), specify with bit 3 (P15SF3) whether
the input will be pulled-up.
(3) SIO6 transmit control register (ST6CON)
Set bit 0 (ST6MOD) to "1" to specify the mode to synchronous mode. Specify the transmit
data length with bit 1 (ST6LN). Specify master or slave mode transmission with bit 3
(ST6STB). Withbit6(TR6MIE), specifywhetherinterruptrequestsareenabledordisabled
when a transmit buffer empty signal occurs. With bit 7 (TR6NIE), specify whether interrupt
requests are enabled or disabled when a transmit complete signal occurs.
(4) SIO6 transmit-receive buffer register (S6BUF)
Transmission is started by writing the transmit data to S6BUF.
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Chapter 12 Serial Port Functions
• Receive settings
(1) Port 15 mode register (P15IO)
If RXD6 (receive data input) is to be used, reset bit 0 (P15IO0) to "0" to configure that port
as an input. If the transmit clock is to be output externally (master mode), set bit 2 (P15IO2)
to "1" to configure that port as an output. If the transmit clock is to be input externally (slave
mode), reset bit 2 (P15IO2) to "0" to configure that port as an input.
(2) Port 15 secondary function control register (P15SF)
Specify with bit 0 (P15SF0) whether the RXD6 pin will be pulled-up. If the transmit clock
is to be output externally (master mode), set bit 2 (P15SF2) to "1" to configure that port as
a secondary function output. If the transmit clock is to be input externally (slave mode),
specify with bit 2 (P15SF2) whether the input will be pulled-up.
(3) SIO6 receive control register (SR6CON)
Set bit 0 (SR6MOD) to "1" to specify the mode to synchronous mode. Specify the receive
datalengthwithbit1(SR6LN). Specifythemasterorslavemodewithbit3(SR6SLV). With
bit 6 (RC6IE), specify whether interrupt requests are enabled or disabled when a receive
complete signal occurs. If bit 7 (SR6REN) is set to "1", reception is enabled and the
reception operation is performed when data arrives.
12.5.3.3 Baud Rate Generator (Timer 3) Settings
If overflow of timer 3 is selected for use as the baud rate clock, implement the following
settings.
(1) General-purpose 8-bit timer 3 counter (TM3C)
Setthetimervaluethatwillbevalidatthestartofcounting. WhenwritingtoTM3C,thesame
value will also be simultaneously and automatically written to the general-purpose 8-bit
timer 3 register (TM3R).
12
(2) General-purpose 8-bit timer 3 control register (TM3CON)
Bits 0 to 2 (TM3C0 to TM3C2) of this register specify the count clock for timer 3. If bit 3
(TM3RUN) is set to "1", timer 3 will begin counting. If reset to "0", timer 3 will halt counting.
[Equation to Calculate Baud Rate]
B = f
¥ 1/(256 – D) ¥ 1/n
B : baud rate [bps]
: timer 3 input clock frequency [Hz]
(TM3)
f
(TM3)
D : reload value (0 to 255)
n : 16 for the UART mode
4 for the synchronous mode
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Chapter 12 Serial Port Functions
12.5.4 SIO6 Interrupt
When any SIO6 interrupt factor occurs, the interrupt request flag (QSIO6) is set to "1". The
interrupt request flag (QSIO6) is located in interrupt request register 3 (IRQ3).
Interrupts can be enabled or disabled by the interrupt enable flag (ESIO6). The interrupt
enable flag (ESIO6) is located in interrupt enable register 3 (IE3).
Three levels of priority can be set with the interrupt priority setting flags (P0SIO6 and
P1SIO6). The interrupt priority setting flags (P0SIO6 and P1SIO6) are located in interrupt
priority control register 6 (IP6).
Table12-7liststhevectoraddressoftheSIO6interruptfactorsandtheinterruptprocessing
flags.
Table 12-7 SIO6 Vector Address and Interrupt Processing Flags
Vector
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
address [H]
1
0
SIO6 transmit buffer empty
signal is generated
SIO6 transmit complete
signal is generated
SIO6 receive complete
signal is generated
003E
QSIO6
ESIO6
P1SIO6
P0SIO6
Symbols (byte) of registers that
contain interrupt processing flags
IRQ3
IE3
IP6
Reference page
17-15
17-20
17-28
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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Chapter 12 Serial Port Functions
12.6 SIO1, SIO6 Operation
12.6.1 Transmit Operation
• UART mode
Figure 12-10 shows the timing diagram of operation during UART transmission.
The clock pulse from the baud rate generator (timer 3 or timer 4) or from an external input
is divided by 16 to generate the transmit shift clock.
If an external clock is to be used with the UART mode, input the clock to the receive clock
I/O pin (RXCn) for SIOn. The externally input clock is processed as shown in figure 12-11,
and is input to the 1/n dividing counter as the baud rate clock.
In synchronization with the transmit shift clock that has been generated, the transmission
circuit controls transmission of the transmit data.
The SnBUF write signal (a signal that is output when an instruction to write to SnBUF is
executed, for example "STB A, SnBUF") acts as a trigger to start transmission.
One CPU clock after the write signal is generated, transmit data in SnBUF is set in the
transmit shift register. At this time, synchronized to the signal indicating the beginning of
an instruction (M1S1), a transmit buffer empty signal is generated.
After the transmit data is set (after the fall of the data transfer signal to the transmit shift
register), synchronized to the falling edge of the next transmit shift clock, the start bit is
output from the transmit data output pin (TXDn). Thereafter, as specified by STnCON, the
transmit data (LSB first), parity bit, and finally the stop bit are output to complete the
transmission of one frame.
At this time, if the next transmit data has not been written to SnBUF, a transmit complete
signal is generated in synchronization with M1S1, and the transmission is completed.
12
Because generation of the transmit shift clock is always unrelated to writes to SnBUF, from
the time when transmit data is written to SnBUF until the start bit is output, there is a delay
of a maximum of 16 baud rate clocks.
Because each of SIO1 and SIO6 has SnBUF and the transmit shift register which are
designed in a duplex construction, during a transmission it is possible to write the next
transmit data to SnBUF. If SnBUF is written to during a transmission, after the current one
frame transmission is completed, the next transmit data will be automatically set in the
transmit shift register, and the data transmission will continue. After one frame of data is
transmit, if the next data to be transmit has been written to SnBUF, the transmit complete
signal will not be generated.
Figure 12-14 shows the timing diagram of operation during continuous transmission.
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
• Synchronous mode (SIO1, SIO6)
[Master mode]
Figure 12-12 shows the timing diagram of operation during master mode transmission.
The clock pulse from the baud rate generator (timer 4 for SIO1 timer 3 for SIO6) is divided
by 4 to generate the transmit shift clock.
In synchronization with the transmit shift clock that has been generated, the transmission
circuit controls transmission of the transmit data.
The SnBUF write signal (the signal that is output when an instruction to write to SnBUF is
executed, for example "STB A, SnBUF") acts as a trigger to start transmission.
One CPU clock after the write signal is generated, transmit data in SnBUF is set in the
transmit shift register. At this time, synchronized to the signal indicating the beginning of
an instruction (M1S1), a transmit buffer empty signal is generated.
After the transmit data is set (after the fall of the data transfer signal to the transmit shift
register), synchronizedtothefallingedgeofthenexttransmitshiftclock, theexternaloutput
clock begins to be output from the transmit clock I/O pin (TXCn). At the same time, transmit
data is output LSB first from the transmit data output pin (TXDn). Thereafter, as specified
bySTnCONandsynchronizedtothetransmitshiftclock,transmitdataisoutputtocomplete
the transmission of one frame.
At this time, if the next transmit data has not been written to SnBUF, a transmit complete
signal is generated in synchronization with M1S1, and the transmission is completed.
TXDn changes at the falling edge of TXCn. Therefore, at the receive side, TXDn is fetched
at the rising edge of TXCn.
Because generation of the transmit shift clock is always unrelated to writes to SnBUF, from
the time when transmit data is written to SnBUF until the first data is output, there is a delay
of a maximum of 4 baud rate clocks.
Because each of SIO1 and SIO6 has SnBUF and the transmit shift register which are
designed in a duplex construction, during a transmission it is possible to write the next
transmit data to SnBUF. If SnBUF is written to during a transmission, after the current one
frame transmission is completed, the next transmit data will be automatically set in the
transmit shift register, and the data transmission will continue. After one frame of data is
transmit, if the next data to be transmit has been written to SnBUF, the transmit complete
signal will not be generated.
Figure 12-14 shows the timing diagram of operation during continuous transmission.
[Note]
During continuous transmission, there is a time lag of 1 bit between the current data
transmission and the next data transmission, in which to set the next data. During this
interval, TXDn is forced to a High level.
12-28
MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
[Slave mode]
Figure 12-13 shows the timing diagram of operation during slave mode transmission.
In the slave mode, the transmit clock is input from the transmit clock I/O pin (TXCn). This
external input clock is detected with the edge of CPU clock to generate the transmit shift
clock.
In synchronization with the transmit shift clock that has been generated, the transmission
circuit controls transmission of the transmit data.
The SnBUF write signal (the signal that is output when an instruction to write to SnBUF is
executed, for example "STB A, SnBUF") acts as a trigger to start transmission.
One CPU clock after the write signal is generated, transmit data in SnBUF is set in the
transmit shift register. At this time, synchronized to the signal indicating the beginning of
an instruction (M1S1), a transmit buffer empty signal is generated.
After the transmit data is set (after the fall of the data transfer signal to the transmit shift
register), synchronized to the falling edge of the next transmit shift clock, the transmit data
is output LSB first from the transmit data output pin (TXDn). Thereafter, as specified by
STnCON and synchronized to the transmit shift clock, transmit data is output to complete
the transmission of one frame.
At this time, if the next transmit data has not been written to SnBUF, a transmit complete
signal is generated in synchronization with M1S1, and the transmission is completed.
TXDn changes at the falling edge of the transmit shift clock that has been generated from
the detected edge of the externally input TXCn. Therefore, at the receive side, TXDn is
fetched at the rising edge of TXCn.
Because each of SIO1 and SIO6 has SnBUF and the transmit shift register which are
designed in a duplex construction, during a transmission it is possible to write the next
transmit data to SnBUF. If SnBUF is written to during a transmission, after the current one
frame transmission is completed, the next transmit data will be automatically set in the
transmit shift register, and the data transmission will continue. After one frame of data is
transmit, if the next data to be transmit has been written to SnBUF, the transmit complete
signal will not be generated.
12
Figure 12-14 shows the timing diagram of operation during continuous transmission.
[Note]
During continuous transmission, there is a time lag of 2 CPU clocks between the current
data transmission and the data next transmission, in which to set the next data. During
thisinterval, TXDnisforcedtoaHighlevel. Ifanexternalclockissupplied, insertamargin
of 2 or more CPU clocks between the current data transmission and the next data
transmission.
12-29
Baud rate clock
Baud rate (1/16)
counter
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
Transmit
shift clock
Timing diagram of transmit shift clock generation (UART mode)
Write signal
to SnBUF
Data transfer
signal to transmit
shift register
Transmit
shift clock
Shift counter
0
1
2
3
9
A
B
0
1
2
9
A
B
C
START DATA
BIT (LSB)
DATA
(MSB)
STOP STOP START DATA
DATA
(MSB)
STOP STOP
Transmit data
(TXDn pin)
DATA
PARITY
PARITY
BIT
BIT
BIT
(LSB)
BIT
BIT
M1S1
Transmit buffer
empty signal
Transmit complete
signal
Figure 12-10 Transmission Timing Diagram (UART Mode)
MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12
12-31
Baud rate clock
Baud rate (1/4)
counter
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
Transmit shift clock
External output clock
Timing diagram of transmit shift clock generation (Synchronous master mode)
Write signal
to SnBUF
Data transfer
signal to transmit
shift register
Transmit
shift clock
Shift counter
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
DATA
(LSB)
DATA
(MSB)
DATA
(LSB)
DATA
(MSB)
Transmit data
(TXDn pin)
DATA DATA DATA DATA DATA
DATA DATA DATA DATA DATA
External output
clock (TXCn pin)
M1S1
Transmit buffer
empty signal
Transmit complete
signal
Figure 12-12 Transmission Timing Diagram (Synchronous Master Mode)
CPUCLK
External input clock
(TXCn pin)
Edge detection
Transmit shift clock
Timing diagram of transmit shift clock generation (Synchronous slave mode)
External input clock
(TXCn pin)
Write signal to SnBUF
Data transfer signal
to transmit shift register
Transmit shift clock
Shift counter
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
DATA
(LSB)
DATA
(MSB)
DATA
(LSB)
DATA
(MSB)
Transmit data
(TXDn pin)
DATA DATA DATA DATA DATA
DATA DATA DATA DATA DATA
M1S1
Transmit buffer
empty signal
Transmit complete
signal
Figure 12-13 Transmission Timing Diagram (Synchronous Slave Mode)
Write signal
to SnBUF
SnBUF
Data 1
Data 2
Data 3
Invalid
Data 4
Data 5
Transmit data
(TXDn pin)
Data 1
1 frame
Data 2
1 frame
Data 4
1 frame
Data 5
1 frame
Transmit buffer
empty signal
Transmit
complete signal
Figure 12-14 Transmission Timing Diagram (During Continuous Transmission)
MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12.6.2 Receive Operation
• UART mode
Figure 12-15 shows the timing diagram of operation during UART reception.
The clock pulse from the baud rate generator (timer 3 or timer 4) or from an external input
is divided by 16 to generate the shift clock.
If an external clock is to be used with the UART mode, input the clock to the receive clock
I/O pin (RXCn) for SIOn. The externally input clock is processed as shown in figure 12-11,
and is input to the 1/n dividing counter as the baud rate clock.
The 1/n dividing circuit remains halted in its reset state until reception begins. The 7th, 8th
and 9th pulses of the 1/16 divider (values 6, 7 and 8 of the baud rate (1/16) counter in figure
12-15) become the sampling clock for the receive data input pin (RXDn). The 10th pulse
(value 9 of the baud rate (1/n) counter in figure 12-15) becomes the receive shift clock.
In synchronization with the receive shift clock, the reception circuit controls reception of the
receive data.
Achangeinthereceivedatainputpin(RXDn)fromaHightoLowleveltriggersthereception
operation to start (at this time, SRnREN (bit 7) of SRnCON should be "1").
If the input signal to the receive data input pin (RXDn) is detected to have changed from a
HightoLowlevel,the1/16dividingcounterthathadbeenhaltedinitsresetstatenowbegins
to operate. The start bit (L level) is sampled at the three sampling clocks of the 7th, 8th,
and 9th pulses from the 1/16 dividing counter. If the start bit is at a Low level for two or more
samples, it is judged to be valid. If not, the start bit is judged invalid, reception operation
is initialized and then halted.
12
In a similar manner, receive data is sampled at the 7th, 8th, and 9th pulses from the 1/16
dividing counter. Data that is judged valid is shifted by the 10th clock, or in other words, by
the receive shift clock, into the receive shift register as receive data. Thereafter, data
reception continues as specified by SRnCON. The first stop bit (the 1st bit in the case of
2 stop bits) is received and the reception of one frame is completed.
At this time, if the received stop bit is "0", a framing error is issued. If the parity is incorrect,
a parity error is issued. And, if the previously received data has not been read, an overrun
error is issued (the previously received data will be overwritten).
However, at this time, the status register (SnSTAT) is not be updated of the detected error.
Later,thecontentsofthereceiveshiftregisteraretransferredtoSnBUF,areceivecomplete
signal is generated in synchronization with M1S1 that indicates the beginning of the next
instruction, and at the same timing, the status register (SnSTAT) is updated by the receive
complete signal and each error signal. The series of receptions is completed.
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
• Synchronous mode
[Master mode]
Figure 12-16 shows the timing diagram of operation during master mode reception.
The clock pulse from the baud rate generator (timer 4 for SIO1 and timer 3 for SIO6) is
divided by 4 to generate the external output clock. The 3rd pulse of the 1/4 divider (value
2 of the baud rate (1/4) counter in figure 12-16) becomes the sampling clock for the receive
data input pin (RXDn). The 4th pulse (value 3 of the baud rate (1/4) counter in figure 12-
16) becomes the receive shift clock.
In synchronization with the receive shift clock, the reception circuit controls reception of the
receive data.
The falling edge of the receive shift clock immediately after SRnREN (bit 7) of SRnCON is
setto"1"triggersthereceptionoperationtostartandtheexternaloutputclockisoutputfrom
the receive clock I/O pin (RXCn). At the next receive shift clock, receive data that was
sampled at the prior sampling clock is shifted into the receive shift register.
At the falling edge of the external output clock, the transmit side transmits data. That data
is shifted into the receive side at the falling edge of the transmit shift clock. Receive data
issampledonlyonce. Thereafter, datareceptioncontinuesasspecifiedbySRnCON. After
the last receive shift clock is output, the contents of the receive shift register are transferred
to SnBUF, and a receive complete signal is generated in synchronization with M1S1, the
signal that indicates the beginning of an instruction. At this time, an overrun error will be
generated if the previously received data has not been read (the previously received data
will be overwritten).
Finally, SRnREN of SRnCON is automatically cleared to "0" to complete the reception
series.
[Slave mode]
Figure 12-17 shows the timing diagram of operation during slave mode reception.
In the slave mode, the receive clock is input externally (from the receive clock I/O pin
(RXCn)). This external input clock is detected with the edge of CPU clock to generate the
receive shift clock.
Insynchronizationwiththereceiveshiftclockthathasbeengenerated, thereceptioncircuit
controls receiving the receive data.
ReceptionoperationistriggeredtobeginwhenSRnREN(bit7)ofSRnCONissetto"1"and
the external input clock is input to the receive clock I/O pin (RXCn).
WhiletheexternalinputclockisataLowlevel,thevalueofthereceivedatainputpin(RXDn)
is sampled. The sampled receive data is shifted into the receive shift register at the next
receive shift clock. Thereafter, data reception continues as specified by SRnCON. After
the last receive data is shifted in, the contents of the receive shift register are transferred
to SnBUF, and a receive complete signal is generated in synchronization with M1S1, the
signal that indicates the beginning of an instruction. At this time, an overrun error will be
generated if the previously received data has not been read (the previously received data
will be overwritten). This completes a one frame reception.
In the slave mode, SRnREN is not automatically cleared to "0" after completing the
reception. If the receive shift clock continues to be input, the receive operation will restart.
12-36
Baud rate clock
Baud rate (1/16)
counter
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
Sampling clock
Receive shift clock
Timing diagram of receive shift clock generation (UART mode)
Receive data
(RXDn pin)
START BIT DATA(LSB)
DATA
DATA
DATA(MSB)
PARITY
STOP BIT
Baud rate
counter
stops
Baud rate counter starts
Sampling clock
Receive shift clock
Shift counter
0
1
2
3
8
9
A
0
Transfer signal
from receive shift
register to SnBUF
SnBUF
M1S1
Receive complete
signal
Figure 12-15 Reception Timing Diagram (UART Mode)
Baud rate clock
Baud rate (1/4)
counter
Sampling clock
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
Receive shift clock
External output
clock
Timing diagram of receive shift clock generation (Synchronous master mode)
Receive enable
flag (SRnREN)
Receive data
(RXDn pin)
DATA(LSB)
DATA
DATA
DATA
DATA
DATA
DATA(MSB)
Sampling clock
Receive shift clock
Shift counter
0
1
2
3
4
5
6
7
0
External output
clock (RXCn pin)
Transfer signal from
receive shift register
to SnBUF
SnBUF
M1S1
Receive complete
signal
Figure 12-16 Reception Timing Diagram (Synchronous Master Mode)
CPUCLK
External input clock
(RXCn pin)
Edge detection
Receive shift clock
Sampling clock
Timing diagram of receive shift clock generation (Synchronous slave mode)
Receive data
(RXDn pin)
DATA(LSB)
DATA
DATA
DATA
DATA
DATA
DATA(MSB)
External input clock
(RXCn pin)
Sampling clock
Receive shift clock
Shift counter
0
1
2
3
4
5
6
0
Transfer signal
from receive shift
register to SnBUF
SnBUF
M1S1
Receive complete
signal
Figure 12-17 Reception Timing Diagram (Synchronous Slave Mode)
MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12.7 SIO4
SIO4 is an 8-bit auto transfer serial port used for clocked synchronous communication.
Synchronized to the clock specified by the SIO4 control register (SIO4CON), SIO4
continuously transmits and receives 8 bits of data LSB first. When transmission and
reception are complete, a transmit-receive interrupt is requested.
The maximum communication speed at f = 30 MHz is 5 Mbps.
12.7.1 SIO4 Configuration
Figure 12-18 shows the SIO4 configuration.
SIOI4 input
Data bus
Reception R
SOUT
Write pointer
R
RES
32 31 30
· · ·
11 10
9
8
7
6
5
4
3
2
1
[32 Byte FIFO]
Read pointer
R
RES
Data bus
SIN
SIOO4 output
Transmission R
Slave/Master
SIOCK4 (Slave)
SIOCK4
(Master)
1/1 OSCCLK
1/2 OSCCLK
1/4 OSCCLK
1/8 OSCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/2 Timer 5 OVF
Control circtuit
TEN FLAG
QSIO4 set
Transfer end
M1 • S1
SIO4CON: SIO4 control register
FIFOCON: FIFO control register
SIN4: SIO4 serial input FIFO data register
SOUT4: SIO4 serial output FIFO data register
SIOCK4: SIO4 transmit-receive clock input pin (P10_3)
SIOO4: SIO4 transmit data output pin (P10_4)
SIOI4: SIO4 receive data input pin (P10_5)
Figure 12-18 SIO4 Configuration
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12.7.2 Description of SIO4 Registers
(1) SIO4 control register (SIO4CON)
The SIO4 control register (SIO4CON) is an 8-bit register that controls SIO4 operation.
SIO4CON can be read from and written to by the program. However, write operations are
invalid for bit 7. If read, a value of "1" will always be obtained for bit 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), SIO4CON becomes 80H.
Figure 12-19 shows the SIO4CON configuration.
[Description of each bit]
• SIO4C0 to SIO4C2 (bits 0 to 2)
During the master mode, SIO4C0 to SIO4C2 select SIO4 clock. In the slave mode, these
bits are invalid.
• SIO4SL (bit 3)
SIO4SL specifies master or slave operation of SIO4.
• TEN4 (bit 4)
When TEN4 is set to "1", transmission and reception begin. When transmission and
reception are completed, it is automatically reset to "0".
• ICK4 (bit 5)
ICK4specifieswhetherthereisaSIO4intervalclock. (Onlyvalidduringthemastermode)
• BUSY4 (bit 6)
BUSY4 indicates a transfer operation status. This can be used to determine the waiting
time from setting TEN4 to "1" to transmission and reception start at multi-byte continuous
transfer in the B mode of FIFO mode selection using SIO4 and SIO5 alternatively.
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Chapter 12 Serial Port Functions
7
—
1
6
5
4
3
2
1
0
Address: 008C [H]
R/W access: R/W
SIO4SL SIO4C2 SIO4C1 SIO4C0
BUSY4 ICK4 TEN4
SIO4CON
At reset
0
0
0
0
0
0
0
SIO4C
SIO4 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1/1 OSCCLK
1/2 OSCCLK
1/4 OSCCLK
1/8 OSCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/2 TM5OVF
0
Master mode
Slave mode
1
0
1
Transfer end
Transfer start
0
1
No interval
1 frame interval
No transfer operation
0
1
(B mode of FIFO mode selection)
Transfer operation in progress
(B mode of FIFO mode selection)
"—" indicates a nonexistent bit.
When read, its value will be "1".
Figure 12-19 SIO4CON Configuration
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Chapter 12 Serial Port Functions
(2) FIFO control register (FIFOCON)
The FIFO control register (FIFOCON) controls operation of the FIFO registers that are
internal to SIO4 and SIO5.
FIFOCON can be read from and written to by the program. However, write operations to
bits 0, 1, 4 and 5 are invalid.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the value of FIFOCON becomes 11H.
Figure 12-20 shows the FIFOCON configuration.
[Description of each bit]
• EMP4 (bit 0)
EMP4indicatestheemptystatusoftheSIO4'sFIFOregister. DuetoSRESoperationand
at reset, the FIFO is cleared and enters the empty state. If all data in the FIFO register
is read, the empty state is entered.
• FUL4 (bit 1)
FUL4 indicates the full status of the SIO4's FIFO register. If 32 bytes of data are
completely stored in the FIFO register, the FIFO full state (FUL = 1) is entered.
• ORE4 (bit 2)
ORE4indicatestheoverflowstatusoftheSIO4'sFIFOregister(onlyvalidduringtheslave
mode). After completing reception of the number of bytes that were written to the FIFO
register before the transfer, if an external clock is input, ORE4 is set to "1". In this case,
because the FIFO register contents cannot be guaranteed, it is necessary to transfer the
data again. ORE4 can be reset to "0" by setting SRE4 (bit 3) to "1".
• SRE4 (bit 3)
SRE4 initializes SIO4. If SRE4 is set to "1", SIO4 will be initialized. After initialization,
SRE4 is automatically reset to "0".
• EMP5 (bit 4)
12
EMP5indicatestheemptystatusoftheSIO5'sFIFOregister. DuetoSRESoperationand
at reset, the FIFO is cleared and enters the empty state. If all data in the FIFO register
is read, the empty state is entered.
• FUL5 (bit 5)
FUL5 indicates the full status of the SIO5's FIFO register. If 32 bytes of data are
completely stored in the FIFO register, the FIFO full state (FUL = 1) is entered.
• ORE5 (bit 6)
ORE5indicatestheoverflowstatusoftheSIO5'sFIFOregister(onlyvalidduringtheslave
mode). After completing reception of the number of bytes that ware written to the FIFO
register before the transfer, if an external clock is input, ORE5 is set to "1". In this case,
because the FIFO register contents cannot be guaranteed, it is necessary to transfer the
data again. ORE5 can be reset to "0" by setting SRE5 (bit 7) to "1".
• SRE5 (bit 7)
SRE5 initializes SIO5. If SRE5 is set to "1", SIO5 will be initialized. After initialization,
SRE5 is automatically reset to "0".
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Chapter 12 Serial Port Functions
7
6
5
4
3
2
1
0
Address: 008D [H]
R/W access: R/W
FIFOCON
At reset
SRES5 ORE5 FUL5 EMP5 SRES4 ORE4 FUL4 EMP4
0
0
0
1
0
0
0
1
Normal
0
1
SIO4 FIFO empty state
Normal
0
1
SIO4 FIFO full state
Normal
0
1
SIO4 overflow error generated
Normal
0
1
Initialize SIO4
Normal
0
1
SIO5 empty state
Normal
0
1
SIO5 FIFO full state
Normal
0
1
SIO5 overflow error generated
Normal
0
1
Initialize SIO5
"—" indicates a nonexistent bit.
When read, its value will be "0."
Figure 12-20 FIFOCON Configuration
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Chapter 12 Serial Port Functions
(3) Serial input FIFO data register (SIN4)
The serial input FIFO data register (SIN4) is used to read 8-bit data received from the SIO
pin. Since SIN4 is read-only, do not attempt to write to this register.
When 1 byte of received data has been gathered in the shift register, it is automatically
loaded into the FIFO register. When transfer of the specified number of bytes is complete,
aninterruptisgenerated. Aftertheinterruptisgenerated,byreadingSIN4,datacanberead
in order from the earliest received data. Because incorrect transmission or reception will
occur if SIN4 is read during serial transmission or reception, do not attempt to read SIN4
while a transmission or reception is in progress.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of SIN4 are undefined.
(4) Serial output FIFO data register (SOUT4)
The serial output FIFO data register (SOUT4) is used to write the 8-bit serial data to be
output from the SIOO4 pin. Since SOUT4 is write-only, do not attempt to read this register.
After data written to the SOUT4 register has been stored in the FIFO register, the start of
transmission or reception causes that data to be sequentially loaded into a shift register.
Because incorrect transmission or reception will occur if SOUT4 is written to during serial
transmission or reception, do not attempt to write to SOUT4 while a transmission or
reception is in progress.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of SOUT 4 are undefined.
12
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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12.7.3 Example of SIO4-related Register Settings
• Master mode settings
(1) Port 10 mode register (P10IO)
If SIOCK4 (clock output) is to be used, set bit 3 (P10IO3) to "1" to configure the port as an
output. Also if SIOO4 (transmit data output) is to be used during transmission, set bit 4
(P10IO4) to "1" to configure the port as an output, and if SIOI4 (receive data input) is to be
used during reception, reset bit 5 (P10IO5) to "0" to configure the port as an input.
(2) Port 10 secondary function control register (P10SF)
If SIOCK4 (clock output) is to be used, set bit 3 (P10IO3) to "1" to configure the port as a
secondary function output. Also, if SIOO4 (transmit data output) is to be used during
transmission, set bit 4 (P10SF4) to "1" to configure the port as a secondary function output,
and if SIOI4 (receive data input) is to be used during reception, reset bit 5 (P10SF5) to "0"
to configure the port as a secondary function input.
(3) Serial output FIFO data register (SOUT4)
Write transmit data to SOUT4 (serial output FIFO data register).
[Note]
Writing to SOUT4 register and reading SIN4 are disabled during transmission or
reception. It is necessary to write dummy data of transmission bytes beforehand for only
reception,anditisnecessarytoreaddummydatafortransmissionbytesaftertransmission
only for transmission.
(4) SIO4 control register (SIO4CON)
SetSIO4clockwithbits0to2(SIO4C0toSIO4C2). Resetbit3(SIO4SL)to"0"tosetmaster
mode. Specify whether there is an interval clock with bit 5 (ICK4). Transmission and
reception are started by setting bit 4 (TEN4) to "1".
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Chapter 12 Serial Port Functions
• Slave mode settings
(1) Port 10 mode register (P10IO)
If SIOCK4 (clock output) is to be used, reset bit 3 (P10IO3) to "0" to configure the port as
an input. Also, if SIOO4 (transmit data output) is to be used during transmission, set bit 4
(P10IO4) to "1" to configure the port as an output, and if SIOI4 (receive data input) is to be
used during reception, reset bit 5 (P10IO5) to "0" to configure the port as an input.
(2) Port 10 secondary function control register (P10SF)
If SIOCK4 (clock output) is to be used, reset bit 3 (P10IO3) to "0" to configure the port as
a secondary function input. Also, if SIOO4 (transmit data output) is to be used during
transmission, set bit 4 (P10SF4) to "1" to configure the port as a secondary function output,
and if SIOI4 (receive data input) is to be used during reception, reset bit 5 (P10SF5) to "0"
to configure the port as a secondary function input.
(3) Serial output FIFO data register (SOUT4)
Write transmit data to SOUT4 (serial output FIFO data register).
[Note]
Writing to SOUT4 register is disabled during transmission or reception. It is necessary
to write dummy data of transmission bytes beforehand for only reception.
(4) SIO4 control register (SIO4CON)
SIO4 clock settings and specification of whether there is an interval clock with bit 5 (ICK4)
are invalid. Set bit 3 (SIO4SL) to "1" to set slave mode. Transmission and reception are
started by setting bit 4 (TEN4) to "1".
12
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Chapter 12 Serial Port Functions
12.7.4 SIO4 Interrupt
When the SIO4 interrupt factor occurs, the interrupt request flag (QSIO4) is set to "1". The
interrupt request flag (QSIO4) is located in interrupt request register 3 (IRQ3).
Interrupts can be enabled or disabled by the interrupt enable flag (ESIO4). The interrupt
enable flag (ESIO4) is located in interrupt enable register 3 (IE3).
Three levels of priority can be set with the interrupt priority setting flags (P0SIO4 and
P1SIO4). The interrupt priority setting flags (P0SIO4 and P1SIO4) are located in interrupt
priority control register 6 (IP6).
Table 12-8 lists the vector address of the SIO4 interrupt factor and the interrupt processing
flags.
Table 12-8 SIO4 Vector Address and Interrupt Processing Flags
Vector
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
address [H]
1
0
SIO4 transmit-receive
0040
QSIO4
ESIO4
P1SIO4
P0SIO4
complete signal is generated
Symbols (byte) of registers that
contain interrupt processing flags
IRQ3
IE3
IP6
Reference page
17-15
17-20
17-28
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
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Chapter 12 Serial Port Functions
12.7.5 SIO4 Operation
SIO4 can select the master mode or slave mode, and can transfer a maximum of 32-byte
transmit data continuyously.
In the master mode, the clock selected by bits 2 to 0 of SIO4CON is SIO4 clock. The SIO4
clock is output from the SIOCK4 pin.
In the slave mode, the clock input from the SIOCK4 pin is the SIO4 clock.
In both the master and slave modes, synchronized with the falling edge of the SIO4 clock,
SIO4 outputs serial-out data from the SIOO4 pin. Synchronized with the rising edge of the
SIO4 clock, serial-in data is input from the SIOI4 pin.
It is assumed that external devices change the serial-in data at the falling edge of the SIO4
clock and fetch the serial-out data at the rising edge of the SIO4 clock. Communication is
executed in an LSB first mode.
Transferoperationisstartedbysettingbit4(TEN4)ofSIO4CONto"1"afterwritingtransmit
data to FIFO. When transfer is completed, bit TEN4 is reset to "0" and interrupt request flag
(QSIO4) is set to "1" at the beginning of the next instruction (M1S1).
If bit TEN4 is reset to "0" during transfer, transmission and reception are immediately
interrupted and SIO4 is initialized. The contents previously transferred are not assured. In
the slave mode, set bit TEN4 to "1" when the SIOCK4 pin is at a high level to start transfer.
Figure 12-21 shows the timing of SIO4 operation during continuous transmission.
12
12-49
TEN4
T
INT
T
CLK
SIOCK4
SIOO4
D0
D0
D1
D2
D3
D4
D5
D6
D7
D7
D8
D8
D9
D9
D10 D11 D12 D13 D14
D15
D15
D119 D120 D121 D122 D123 D124 D125 D126 D127
Contents of transmit data written to FIFO last
Contents of transmit data written to FIFO first
D1
D2
D3
D4
D5
D6
D10 D11 D12 D13 D14
D119 D120 D121 D122 D123 D124 D125 D126 D127
Contents of receive data to be written to FIFO last
SIOI4
Contents of receive data to be written to FIFO first
MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12.8 SIO5
SIO5 is an 8-bit auto transfer serial port used for clocked synchronous communication.
Synchronized to the clock specified by the SIO5 control register (SIO5CON), SIO5
continuouslytransmitsandreceives8bitsofdatainanLSBfirstmode. When transmission
and reception are complete, a transmit-receive interrupt is requested.
The maximum communication speed at f = 30 MHz is 5 Mbps.
12.8.1 SIO5 Configuration
Figure 12-22 shows the SIO5 configuration.
SIOI5 input
Data bus
Reception R
SOUT
Write pointer
R
RES
32 31 30
· · ·
11 10
9
8
7
6
5
4
3
2
1
[32 Byte FIFO]
Read pointer
R
RES
Data bus
SIN
SIOO5 output
Transmission R
Slave/Master
SIOCK5 (Slave)
SIOCK5
(Master)
12
1/1 OSCCLK
1/2 OSCCLK
1/4 OSCCLK
1/8 OSCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/2 Timer 5 OVF
Control circtuit
TEN FLAG
QSIO5 set
Transfer end
M1 • S1
SIO5CON: SIO5 control register
FIFOCON: FIFO control register
SIN5: SIO5 serial input FIFO data register
SOUT5: SIO5 serial output FIFO data register
SIOCK5: SIO5 transmit-receive clock input pin (P14_0)
SIOO5: SIO5 transmit data output pin (P14_1)
SIOI5: SIO5 receive data input pin (P14_2)
Figure 12-22 SIO5 Configuration
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Chapter 12 Serial Port Functions
12.8.2 Description of SIO5 Registers
(1) SIO5 control register (SIO5CON)
The SIO5 control register (SIO5CON) is an 8-bit register that controls SIO5 operation.
SIO5CON can be read from and written to by the program. However, write operations are
invalid for bit 7. If read, a value of "1" will always be obtained for bit 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), SIO5CON becomes 80H.
Figure 12-23 shows the SIO5CON configuration.
[Description of each bit]
• SIO5C0 to SIO5C2 (bits0 to 2)
During the master mode, SIO5C0 to SIO5C2 select SIO5 clock. In the slave mode, these
bits are invalid.
• SIO5SL (bit 3)
SIO5SL specifies master or slave operation of SIO5.
• TEN5 (bit 4)
When TEN5 is set to "1", transmission and reception begin. When transmission and
reception are completed, it is automatically reset to "0".
• ICK5 (bit 5)
ICK5specifieswhetherthereisaSIO5intervalclock. (Onlyvalidduringthemastermode)
• BUSY5 (bit 6)
BUSY5 indicates a transfer operation status. This can be used to determine the waiting
time from setting TEN5 to "1" to transmission and reception start at multi-byte continuous
transfer using SIO4 and SIO5 alternatively.
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Chapter 12 Serial Port Functions
7
—
1
6
5
4
3
2
1
0
Address: 00D5 [H]
R/W access: R/W
SIO5SL SIO5C2 SIO5C1 SIO5C0
BUSY5 ICK5 TEN5
SIO5CON
At reset
0
0
0
0
0
0
0
SIO5C
SIO5 count clock
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1/1 OSCCLK
1/2 OSCCLK
1/4 OSCCLK
1/8 OSCCLK
1/2 TBCCLK
1/4 TBCCLK
1/8 TBCCLK
1/2 TM5OVF
0
Master mode
Slave mode
1
0
1
Transfer end
Transfer start
0
1
No interval
1 frame interval
No transfer operation
0
1
(B mode of FIFO mode selection)
Transfer operation in progress
(B mode of FIFO mode selection)
"—" indicates a nonexistent bit.
When read, its value will be "1".
12
Figure 12-23 SIO5CON Configuration
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Chapter 12 Serial Port Functions
(2) Serial input FIFO data register (SIN5)
The serial input FIFO data register (SIN5) is used to read 8-bit serial data received from the
SIO pin. Since SIN5 is read-only, do not attempt to write to this register.
When 1 byte of received data has been gathered in the shift register, it is automatically
loaded into the FIFO register. When transfer of the specified number of bytes is complete,
aninterruptisgenerated. Aftertheinterruptisgenerated,byreadingSIN5,datacanberead
in order from the earliest received data. Because incorrect transmission or reception will
occur if SIN5 is read during serial transmission or reception, do not attempt to read SIN5
while a transmission or reception is in progress.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of SIN5 are undefined.
(3) Serial output FIFO data register (SOUT5)
The serial output FIFO data register (SOUT5) is used to write the 8-bit serial data to be
output from the SIOO5 pin. Since SOUT5 is write-only, do not attempt to read this register.
After data written to the SOUT5 register has been stored in the FIFO register, the start of
transmission or reception causes that data to be sequentially loaded into a shift register.
Because incorrect transmission or reception will occur if SOUT5 is written to during serial
transmission or reception, do not attempt to write to SOUT5 while a transmission or
reception is in progress.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of SOUT5 are undefined.
(4) FIFO mode control register (FIFOMOD)
The FIFO mode control register (FIFOMOD) is a 2-bit register that specifies the mode of
combined SIO4 and SIO5 usage. However, write operations to bits 2 through 7 are invalid.
If bits 2 through 7 are read, a value of "1" will always be obtained.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), FIFOMOD becomes FCH.
Bits 0 and 1 (FMOD0, FMOD1) select the mode of combined SIO4 and SIO5 usage.
Change these flags when neither SIO4 nor SIO5 is transferring data.
1) A mode
This mode operates SIO4 and SIO5 independently.
2) B mode
This mode alternates usage of SIO4 and SIO5 through the SIO4 port interface to
consecutively transfer multiple bytes of data without limitation due to the number of FIFO
stages. Inthismode,operationofonlymastermodetransmissionandreceptionispossible.
In this mode, while a transfer is in progress for one SIO, even if the TEN flag of the other
SIO is set, that SIO's transfer will wait until the first SIO transfer is completed. After the first
SIO transfer is completed, the other SIO transfer will automatically start. This provides for
uninterrupted transfer.
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Chapter 12 Serial Port Functions
In this mode, be sure to alternate usage of SIO4 and SIO5. For example, if
SIO4ÆSIO5ÆSIO4 was used, then use SIO5ÆSIO4ÆSIO5 next. If B mode usage is
intermixed with other modes, for example, if SIO5ÆSIO4ÆSIO5 (B mode) is used, after
setting and using another mode, upon returning to the B mode, use SIO4ÆSIO5ÆSIO4 as
the next sequence.
Interval clock settings (ICK) are invalid in this mode.
3) C mode
Via the SIO5 port interface, this mode can monitor the SIO4 transfer operation performed
through the SIO4 interface.
SIO5 itself cannot be used with this mode.
4) D mode
Via the SIO4 port interface, this mode can monitor the SIO4 transfer operation performed
through the SIO5 interface.
SIO5 itself cannot be used with this mode.
Using the C or D modes, two systems of port interfaces can be connected to SIO4. Using
the A or D modes, two systems of SIOs (SIO4/SIO5) can be connected to the single SIO4
port interface.
Figure 12-24 shows the FIFOMOD configuration and Figure 12-25 shows the B, C, and D
mode configurations.
12
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
0
Address: 00CF [H]
R/W access: R/W
FMOD1 FMOD0
FIFOMOD
At reset
0
0
FMOD
FIFO mode selection
1
0
0
1
1
0
0
1
0
1
A mode
B mode
C mode
D mode
"—" indicates a nonexistent bit.
When read, its value will be "0."
Figure 12-24 FIFOMOD Configuration
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Chapter 12 Serial Port Functions
SIOO4 (P10_4)
SIOI4 (P10_5)
SIOCK4 (P10_3)
SIO4 (SYNC with 32-byte FIFO)
SIO5 (SYNC with 32-byte FIFO)
Transmit request
Auto switching control
(1) B Mode Configuration
SIOO4 (P10_4)
SIOI4 (P10_5)
SIOCK4 (P10_3)
SIO4 (SYNC with 32-byte FIFO)
SIOO5 (P14_1)
SIOI5 (P14_2)
SIOCK5 (P14_0)
(open)
(2) C Mode Configuration
SIOO5 (P14_1)
SIOI5 (P14_2)
SIOCK5 (P14_0)
SIO4 (SYNC with 32-byte FIFO)
SIOO4 (P10_4)
SIOI4 (P10_5)
SIOCK4 (P10_3)
(open)
(3) D Mode Configuration
Figure 12-25 Mode Configuration
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Chapter 12 Serial Port Functions
12.8.3 Example of SIO5-related Register Settings
• Master mode settings
(1) Port 14 mode register (P14IO)
If SIOCK5 (clock output) is to be used, set bit 0 (P14IO0) to "1" to configure the port as an
output. Also, if SIOO5 (transmit data output) is to be used during transmission, set bit 1
(P14IO1) to "1" to configure the port as an output, and if SIOI5 (receive data input) is to be
used during reception, reset bit 2 (P14IO2) to "0" to configure the port as an input.
(2) Port 14 secondary function control register (P14SF)
If SIOCK5 (clock output) is to be used, set bit 0 (P14IO0) to "1" to configure the port as a
secondary function output. Also, if SIOO5 (transmit data output) is to be used during
transmission, set bit 1 (P14SF1) to "1" to configure the port as a secondary function output,
and if SIOI5 (receive data input) is to be used during reception, reset bit 2 (P14SF2) to "0"
to configure the port as a secondary function input.
(3) Serial output FIFO data register (SOUT5)
Write transmit data to SOUT5 (serial output FIFO data register).
[Note]
Writing to SOUT5 register is disabled during transmission or reception. It is necessary
to write dummy data of transmission bytes beforehand for only reception.
(4) SIO5 control register (SIO5CON)
SetSIO5clockwithbits0to2(SIO5C0toSIO5C2). Resetbit3(SIO5SL)to"0"tosetmaster
mode. Specify whether there is an interval clock with bit 5 (ICK5). Transmission and
reception are started by setting bit 5 (TEN5) to "1".
12
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Chapter 12 Serial Port Functions
• Slave mode settings
(1) Port 14 mode register (P14IO)
If SIOCK5 (clock output) is to be used, reset bit 0 (P14IO0) to "0" to configure the port as
an input. Also, if SIOO5 (transmit data output) is to be used during transmission, set bit 1
(P14IO1) to "1" to configure the port as an output, and if SIOI5 (receive data input) is to be
used during reception, reset bit 2 (P14IO2) to "0" to configure the port as an input.
(2) Port 14 secondary function control register (P14SF)
If SIOCK5 (clock output) is to be used, reset bit 0 (P14IO0) to "0" to configure the port as
a secondary function input. Also, if SIOO5 (transmit data output) is to be used during
transmission, set bit 1 (P14SF1) to "1" to configure the port as a secondary function output,
and if SIOI5 (receive data input) is to be used during reception, reset bit 2 (P14SF2) to "0"
to configure the port as a secondary function input.
(3) Serial output FIFO data register (SOUT5)
Write transmit data to SOUT5 (serial output FIFO data register).
[Note]
Writing to SOUT5 register is disabled during transmission or reception. Reading SIN5
is also disabled. It is necessary to write dummy data of transmission bytes beforehand
for only reception, and it is necessary to read dummy data for transmission bytes after
transmission only for transmission.
(4) SIO5 control register (SIO5CON)
SIO5 clock settings and specification of whether there is an interval clock with bit 5 (ICK5)
are invalid. Set bit 3 (SIO5SL) to "1" to set slave mode. Transmission and reception are
started by setting bit 4 (TEN5) to "1".
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12.8.4 SIO5 Interrupt
When the SIO5 interrupt factor occurs, the interrupt request flag (QSIO5) is set to "1". The
interrupt request flag (QSIO5) is located in interrupt request register 3 (IRQ3).
Interrupts can be enabled or disabled by the interrupt enable flag (ESIO5). The interrupt
enable flag (ESIO5) is located in interrupt enable register 3 (IE3).
Three levels of priority can be set with the interrupt priority setting flags (P0SIO5 and
P1SIO5). The interrupt priority setting flags (P0SIO5 and P1SIO5) are located in interrupt
priority control register 6 (IP6).
Table 12-9 lists the vector address of the SIO5 interrupt factor and the interrupt processing
flags.
Table 12-9 SIO5 Vector Address and Interrupt Processing Flags
Vector
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
address [H]
1
0
SIO5 transmit-receive
003C
QSIO5
ESIO5
P1SIO5
P0SIO5
complete signal is generated
Symbols (byte) of registers that
contain interrupt processing flags
IRQ3
IE3
IP6
Reference page
17-15
17-20
17-28
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
12
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Chapter 12 Serial Port Functions
12.8.5 SIO5 Operation
SIO5 can select the master mode or slave mode, and can transfer a maximum of 32-byte
transmit data continuously.
In the master mode, the clock selected by bits 2 to 0 of SIO5CON is SIO5 clock. The SIO5
clock is output from the SIOCK5 pin.
In the slave mode, the clock input from the SIOCK5 pin is the SIO5 clock.
In both the master and slave modes, synchronized with the falling edge of the SIO5 clock,
SIO5 outputs serial-out data from the SIOO5 pin. Synchronized with the rising edge of the
SIO5 clock, serial-in data is input from the SIOI5 pin.
It is assumed that external devices change the serial-in data at the falling edge of the SIO5
clock and fetch the serial-out data at the rising edge of the SIO5 clock. Communication is
executed in an LSB first mode.
Transferoperationisstartedbysettingbit4(TEN5)ofSIO5CONto"1"afterwritingtransmit
data to FIFO. When transfer is completed, bit TEN5 is reset to "0" and interrupt request flag
(QSIO5) is set to "1" at the beginning of the next instruction (M1S1).
If bit TEN5 is reset to "0" during transfer, transmission and reception are immediately
interrupted and SIO5 is initialized. The contents previously transferred are not assured. In
the slave mode, set bit TEN5 to "1" when the SIOCK5 pin is at a high level to start transfer.
Figure 12-26 shows the timing of SIO5 operation during continuous transmission.
12-60
TEN5
T
INT
T
CLK
SIOCK5
SIOO5
D0
D0
D1
D2
D3
D4
D5
D6
D7
D7
D8
D8
D9
D9
D10 D11 D12 D13 D14
D15
D15
D119 D120 D121 D122 D123 D124 D125 D126 D127
Contents of transmit data written to FIFO last
Contents of transmit data written to FIFO first
D1
D2
D3
D4
D5
D6
D10 D11 D12 D13 D14
D119 D120 D121 D122 D123 D124 D125 D126 D127
Contents of receive data to be written to FIFO last
SIOI5
Contents of receive data to be written to FIFO first
MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
12-62
Chapter 13
A/D Converter Functions
13
MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
13. A/D Converter Functions
13.1 Overview
The MSM66577 family has an internal 8-channel A/D converter with 10-bit resolution.
The A/D converter can operate in a scan mode that sequentially converts several selected
channels, or in a select mode that converts one selected channel.
Asuccessivecomparisonmethodwithasampleandholdfunctionisusedtoconvertanalog
quantities to digital quantities.
13.2 A/D Converter Configuration
Figure 13-1 shows the A/D converter configuration.
VREF
AGND
AI0
AI1
AI2
AI3
AI4
AI5
AI6
AI7
ADR00
ADR01
ADR02
ADR03
ADR04
ADR05
ADR06
ADR07
Analog
selector
A/D converter
circuit
A/D control circuit
Interrupt
request
13
ADCON0L
ADINT0
ADCON0H
Internal bus
AI0 to AI7: analog input pins (P12_0 to P12_7)
ADR00 to ADR07: A/D result register (10 bits)
ADINT0: A/D interrupt control register 0
ADCON0H: A/D control register 0H
ADCON0L: A/D control register 0L
AGND: analog GND pin
VREF: analog reference voltage pin
Figure 13-1 A/D Converter Configuration
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MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
13.3 A/D Converter Registers
Table 13-1 lists a summary of SFRs for control of the A/D converter.
Table 13-1 Summary of SFRs for A/D Converter Control
Address
[H]
Symbol
(byte)
Symbol
(word)
—
8/16
Initial
Reference
page
Name
R/W
Operation value [H]
009CI A/D control register 0L
009DI A/D control register 0H
ADCON0L
ADCON0H
R/W
R/W
8
8
80
00
13-3
—
13-5
A/D interrupt control
009EI
ADINT0
—
R/W
R
8
F0
13-7
13-8
13-8
13-8
13-8
13-8
13-8
13-8
13-8
register 0
00A0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A/D result register 00
00A1
ADR00
ADR01
ADR02
ADR03
ADR04
ADR05
ADR06
ADR07
16
16
16
16
16
16
16
16
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
00A2
A/D result register 01
00A3
R
00A4
A/D result register 02
00A5
R
00A6
A/D result register 03
00A7
R
00A8
A/D result register 04
00A9
R
00AA
A/D result register 05
00AB
R
00AC
A/D result register 06
00AD
R
00AE
A/D result register 07
00AF
R
[Notes]
1. Addresses are not consecutive in some places.
2. A star (P) in the address column indicates a missing bit.
3. Do not write to ADR00 through ADR07. If written to, the contents of all the registers
from ADR00 through ADR07 may be overwritten.
4. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
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Chapter 13 A/D Converter Functions
13.3.1 Description of A/D Converter Registers
(1) A/D control register 0L (ADCON0L)
A/D control register 0L (ADCON0L) consists of 6 bits and specifies settings for the scan
mode.
ADCON0L can be read from and written to by the program. However, write operations are
invalid for bit 7. Also, if bit 3 is to be written to, a value of "0" must be written. If read, bit
3 is always "0" and bit 7 is always "1".
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), ADCON0L becomes 80H.
Figure 13-2 shows the ADCON0L configuration.
[Description of each bit]
• ADSNM00 to ADSNM02 (bits 0 to 2)
ADSNM00 to ADSNM02 specify the scan channels of the scan mode.
Change the scan channels while the A/D converter is halted.
Changes of the scan channels are valid only when ADRUN0 (bit 4) is "0".
• ADRUN0 (bit 4)
ADRUN0 starts and stops A/D conversion in the scan mode.
If set to "1", A/D conversion will begin. If reset to "0", conversion will be stopped. The
ADRUN0 bit specifies to operate or to halt A/D conversion and is not a status flag
indicating whether conversion is in progress or is halted.
• SNEX0 (bit 5)
SNEX0 specifies the factor that activates A/D conversion in the scan mode.
WhenSNEX0is"0",afterA/Dconversionofthepreviouschanneliscomplete,conversion
of the next channel begins. When SNEX0 is "1", after A/D conversion of the previous
channel is complete, 1 channel of A/D conversion is performed for each valid edge of the
signal at the external interrupt input pin (EXINT1).
• SCNC0 (bit 6)
SCNC0 specifies the operating mode after one cycle of scanning.
When SCNC0 is "0", after one cycle of the specified scanning channels, A/D conversion
starts again at the first channel.
13
When SCNC0 is "1", after one cycle of the specified scanning channels, A/D conversion
is stopped.
If used in the "SCNC0 = 1" mode, A/D conversion is reactivated by resetting to "0" the
INTSN0 flag that is located in ADINT0 and indicates when one cycle of scanning is
complete. (Control with the ADRUN0 bit is unnecessary. With ADRUN0 set to "1", A/D
conversion can be activated by resetting INTSN0 to "0".)
If the mode is to be switched to "SCNC0 = 0" (the "after one cycle, start the next
conversion" mode), reactivate the A/D conversion by resetting SCNC0 to "0". (Control
with the ADRUN0 bit is unnecessary.)
[Note]
Ifusedinthe"afteronecycleofscanning, stoptheconversion"mode, A/Dconversioncan
not be reactivated by resetting to "0" and then setting to "1" the ADRUN0 bit.
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MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
7
—
1
6
5
4
3
"0"
0
2
1
0
Address: 009C [H]
R/W access: R/W
ADSNM02 ADSNM01 ADSNM00
SCNC0 SNEX0 ADRUN0
ADCON0L
At reset
0
0
0
0
0
0
ADSNM0
A/D scan channels
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
ch0 to ch7
ch1 to ch7
ch2 to ch7
ch3 to ch7
ch4 to ch7
ch5 to ch7
ch6, ch7
ch7
0
1
Stop scan mode A/D conversion
Operate scan mode A/D conversion
0
1
After conversion is complete, start the next conversion
At the EXINT1 valid edge, start the next conversion
0
1
After one cycle, start the next conversion
After one cycle, stop the conversion
"—" indicates a nonexistent bit.
When read, its value will be "1."
"0" indicates that this bit must be written as "0."
When read, its value will be "0."
Figure 13-2 ADCON0L Configuration
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MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
(2) A/D control register 0H (ADCON0H)
ADCON0H is a 7-bit register that mainly controls the select mode of the A/D converter.
ADCON0H can be read from and written to by the program. However, if bit 3 is to be written
to, a value of "0" must be written. If read, bit 3 is always "0".
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), ADCON0H becomes 00H.
Figure 13-3 shows the ADCON0H configuration.
[Description of each bit]
• ADSTM00 to ADSTM02 (bits 0 to 2)
ADSTM00 to ADSTM02 specify the A/D conversion channel of the select mode.
Change the A/D conversion channel of the select mode while the A/D converter is halted.
Changes of the conversion channel of the select mode are valid only when STS0 (bit 4)
is "0".
• STS0 (bit 4)
STS0 starts and stops A/D conversion in the select mode.
If set to "1", A/D conversion will begin. If reset to "0", the conversion will be halted. When
A/D conversion in the select mode is completed, STS0 is automatically reset to "0" by the
hardware.
• ADTM00 to ADTM02 (bits 5 to 7)
ADTM00 and ADTM01 specify the number of clocks required for the A/D conversion of
1 channel.
Select an appropriate number of A/D conversion clocks based on the impedance of the
analog input signal source and the frequency of the source.
For further details, refer to Section 13.5, "Notes Regarding Usage of A/D Converter".
During A/D conversion, changes to the number of clocks will be ignored.
13
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MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
7
6
5
4
3
"0"
0
2
1
0
Address: 009D [H]
R/W access: R/W
ADSTM02 ADSTM01 ADSTM00
ADTM02 ADTM01 ADTM00 STS0
ADCON0H
At reset
0
0
0
0
0
0
0
ADSTM0
A/D select channel
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
0
1
Stop select mode A/D conversion
Operate select mode A/D conversion
ADTM0
Number of A/D conversion clocks
for 1 channel (when f = 30 MHz)
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1536 CPUCLK (51.2 ms)
1024 CPUCLK (34.1 ms)
768 CPUCLK (25.6 ms)
512 CPUCLK (17.1 ms)
384 CPUCLK (12.8 ms)
256 CPUCLK (8.5 ms)
192 CPUCLK (6.4 ms)
128 CPUCLK (4.3 ms)
"0" indicates that this bit must be written as "0."
When read, its value will be "0."
Figure 13-3 ADCON0H Configuration
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MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
(3) A/D interrupt control register (ADINT0)
ADINT0 is a 4-bit register that mainly controls the generation of interrupt requests by the
A/D converter.
ADINT0 can be read from and written to by the program. However, write operations are
invalid for bits 4 through 7. If read, a value of "1" will always be obtained for bits 4 through
7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), ADINT0 becomes F0H.
Figure 13-4 shows the ADINT0 configuration.
[Description of each bit]
• INTSN0 (bit 0)
INTSN0 indicates whether one cycle of the scan channels has been completed.
WhenINTSN0is"0", then"onecycleisnotcomplete". If"1", then"onecycleiscomplete".
Here, "one cycle is complete" signifies that in the scan mode, A/D conversion of channel
7 is complete. INTSN0 must be reset to "0” by the program.
• INTST0 (bit 1)
INTST0 indicates whether A/D conversion in the select mode is complete.
When INTST0 is "1", then A/D conversion is complete. INTST0 must be reset to "0" by
the program.
• ADSNIE0 (bit 2)
ADSNIE0 enables or disables interrupt requests when one cycle of scan channels is
complete. Here, "one cycle is complete" signifies that in the scan mode, A/D conversion
of channel 7 is complete.
• ADSTIE0 (bit 3)
ADSTIE0enablesordisablesinterruptrequestswhenA/Dconversioniscompletedinthe
select mode.
7
6
5
4
3
2
1
0
Address: 009E [H]
R/W access: R/W
13
ADSTIE0 ADSNIE0 INTST0 INTSN0
ADINT0
At reset
—
1
—
1
—
1
—
1
0
0
0
0
0
1
One cycle of scan channels is not complete
One cycle of scan channels is complete
0
1
A/D conversion in select mode is not complete
A/D conversion in select mode is complete
0
1
Disable interrupts from INTSN0
Enable interrupts from INTSN0
0
1
Disable interrupts from INTST0
Enable interrupts from INTST0
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 13-4 ADINT0 Configuration
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MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
(4) A/D result registers (ADR00 to ADR07)
A/D result registers (ADR00 to ADR07) consist of 10 bits and store the A/D conversion
results.
A/D result registers (ADR00 to ADR07) can only be read in word access operations by the
program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the value of ADR00 to ADR07 is undefined.
Figure 13-5 shows the configuration of the A/D result registers (ADR00 to ADR07).
R/W access: R (word access only)
Address [H]
00AF
00AE
00AD
00AC
00AB
00AA
00A9
00A8
00A7
00A6
00A5
00A4
00A3
00A2
00A1
00A0
7
6
5
4
3
2
1
0
—
—
—
—
—
—
bit9
bit1
bit9
bit1
bit9
bit1
bit9
bit1
bit9
bit1
bit9
bit1
bit9
bit1
bit9
bit1
bit8 bit9 : MSB
ADR07
ADR06
ADR05
ADR04
ADR03
ADR02
ADR01
ADR00
bit7
—
bit6
—
bit5
—
bit4
—
bit3
—
bit2
—
bit0 bit0 : LSB
bit8
bit0
bit8
bit0
bit8
bit0
bit8
bit0
bit8
bit0
bit8
bit0
bit8
bit0
bit7
—
bit6
—
bit5
—
bit4
—
bit3
—
bit2
—
bit7
—
bit6
—
bit5
—
bit4
—
bit3
—
bit2
—
bit7
—
bit6
—
bit5
—
bit4
—
bit3
—
bit2
—
bit7
—
bit6
—
bit5
—
bit4
—
bit3
—
bit2
—
bit7
—
bit6
—
bit5
—
bit4
—
bit3
—
bit2
—
bit7
—
bit6
—
bit5
—
bit4
—
bit3
—
bit2
—
bit7
bit6
bit5
bit4
bit3
bit2
"—" indicates a nonexistent bit. When read, its value will be "0."
Figure 13-5 A/D Result Registers (ADR00 to ADR07) Configuration
[Note]
Do not write to the A/D result registers (ADR00 to ADR07). If written to, all the registers
from ADR00 to ADR07 may be overwritten.
13-8
MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
13.3.2 Example of A/D Converter-related Register Settings
• Scan mode setting
(1) A/D control register 0H (ADCON0H)
With bits 5 to 7 (ADTM00 to ADTM02), specify the number of clocks required for the A/D
conversion per channel.
(2) A/D interrupt control register (ADINT0)
Specify that one cycle of the scan channels is not complete by resetting bit 0 (INTSN0) to
"0". With bit 2 (ADSNIE0), enable or disable the generation of interrupts when one cycle
of the scan channels is complete (INTSN0).
(3) A/D control register 0L (ADCON0L)
Specify the scan channels with bits 0 to 2 (ADSNM00 to ADSNM02). With bit 5 (SNEX0),
specify the factor that will start A/D conversion. With bit 6 (SCNC0), specify operation after
completion of one cycle of the scan channels. Set bit 4 (ADRUN0) to "1" to start the A/D
conversion. If reset to "0", the A/D conversion can be stopped before completion.
• Select mode setting
(1) A/D interrupt control register (ADINT0)
Specify that the AD conversion in the select mode is not complete by resetting bit 1
(INTST0) to "0". With bit 3 (ADSTIE0), enable or disable the generation of interrupts when
A/D conversion is completed in the select mode (INTST0).
(2) A/D control register 0H (ADCON0H)
Specify the A/D conversion channel with bits 0 to 2 (ADSTM00 to ADSTM02). With bits 5
to 7 (ADTM00 to ADTM02), specify the number of clocks required for the A/D conversion
per channel. Set bit 4 (STS0) to "1" to start the A/D conversion. If reset to "0", the A/D
conversion can be stopped before completion.
13
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MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
13.4 A/D Converter Operation
The A/D converter has two operating modes, the scan mode and the select mode.
The scan mode sequentially performs A/D conversion of channels from an arbitrary
channel to ch7. In the scan mode, when the A/D conversion of ch7 is complete, A/D
conversioncanbeselectedtoeitherstop,ortoautomaticallyrestartbeginningataspecified
channel.
Figure 13-6 shows an example of scan mode operation.
During scan mode operation, it is also possible to operate the select mode. In this case,
whentheselectmodeisactivated,A/Dconversionishaltedforthechannelbeingconverted
inscanmode, andA/Dconversionofthespecifiedchannelisperformedintheselectmode.
When the A/D conversion in the select mode is complete, scan mode A/D conversion is
restarted for the channel that was previously halted.
The timing diagram of Figure 13-7 shows the select mode being executed during the scan
mode.
While the A/D converter is stopped and also during the STOP mode, the circuitry is
controlled so that there is no current flow between V
and AGND. Therefore, it is not
REF
necessary to turn off the V
supply externally when it is not in use.
REF
(A/D stops)
(Repeats)
ch
0
1
2
3
4
5
6
7
ch
0
1
2
3
4
5
6
7
(a) Scan from ch2 to ch7
After one cycle, conversion stops (SCNC0 = 1)
(b) Scan from ch2 to ch7
After one cycle, next conversion starts (SCNC0 = 0)
Figure 13-6 Example Operation During Scan Mode
ch0
ch1
ch2
ch2
ch3
A/D conversion
in scan mode
ch4
A/D conversion
in select mode
(1)
(2)
(1) Terminate A/D conversion of ch2
Start A/D conversion of ch4 in select mode
(2) Complete A/D conversion of ch4
Restart A/D conversion in scan mode beginning with ch2
Figure 13-7 Timing Diagram of Select Mode Execution During Scan Mode
13-10
MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
13.5 Notes Regarding Usage of A/D Converter
13.5.1 Considerations When Setting the Conversion Time
Figure 13-8 shows an equivalent circuit of the analog input section of the A/D converter.
Because a successive comparison method with a sample and hold function is used in the
converter, the internal sampling capacitor must be charged or discharged within a fixed
sampling time to reach a voltage level that corresponds to the required precision.
The number of clocks required for the A/D conversion of 1 channel can be specified with
ADTM00 and ADTM01 of the A/D control register 0H (ADCON0H).
Table 13-2 lists the clock allocation for the A/D conversion processes of 1 channel.
Because the actual sampling time is determined by the operating frequency of the
microcomputer, actual sampling times can be computed from the numeric values in this
table.
Input resistor
R-IN
Analog input pins (AI0 to AI7)
To A/D conversion circuit
C
Sampling capacitor
R-IN
=
2 kW
C
= 64 pF
Figure 13-8 Equivalent Circuit of Analog Input Section
Table 13-2 Clock Allocation in A/D Conversion Processes
13
ADTM0
Number of clocks for A/D
Number of clocks required by each process
conversion of 1 channel
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
SamplingA/D
conversion
314
210
158
106
80
Other
1536
1024
768
512
384
256
192
128
935
623
467
311
233
155
116
77
287
191
143
95
71
54
47
41
35
28
23
Units: CPUCLK
13-11
MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
The following factors affect the conversion precision of the A/D converter.
1) Signal source impedance of the analog input ’ depends upon external circuit
2) Sampling time
’
depends upon ADTM00, ADTM01 settings
3) Actual precision of the A/D converter (comparator, CR precision, etc.)
The overall precision of the A/D converter is determined by the precision during sampling
(items 1 and 2 above) and the actual precision of the A/D converter.
In consideration of the precision during sampling (dependent upon the signal source
impedance), it is desirable to set a long sampling time. If the sampling time is short, it is
difficult to maintain precision. In practical applications, set the conversion clock (sampling
time)anddesignexternalcircuitrythatwillsatisfytheoptimumrequirementsfor"conversion
time" and "conversion precision".
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MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
13.5.2 Noise-Suppression Measures
Based on the voltage difference between the analog reference voltage (V
) pin and the
REF
analog ground (AGND), the A/D converter in the MSM66577 family converts an analog
voltage at the analog input pin into digital data. Because this type of A/D converter does
not have a reference voltage source inside the microcomputer, "stability" and "noise-
suppression measures" for V
and AGND are important.
REF
As noise-suppression measures, insert a bypass capacitor between the analog reference
voltage (V ) pin and the analog ground (AGND) pin. Also, connect the analog ground
REF
(AGND) to a stable GND on the circuit board.
If the digital and analog layouts can be separated on the circuit board, separate the circuit
into a digital system (V /GND) and an analog system (V
/AGND). Connect bypass
REF
DD
capacitors to each system to reduce the circulation of GND noise in the digital system.
Divide the circuit board into separate GND planes for the digital and analog systems, and
then connect each GND plane to a common location where there is a stable GND supply.
In addition to inserting a bypass capacitor of 10 mF to 47 mF or larger between V
and
REF
AGND, the stability of V
can be maintained by connecting a 0.01 mF to 0.1 mF high-pass
REF
capacitor in parallel. Because the V
voltage supply is used to avoid the effect of digital
REF
noise on the comparator used in A/D conversion, adding a high-pass capacitor is effective
in reducing V fluctuations.
REF
Figure 13-9 shows an example of noise-suppression measures.
TOP VIEW
Main clock
oscillator side
C0
VDD
+
C1
VDD
+
VREF
+
C1
C0
C1
C0
13
Analog
input
Oscillation
circuit
GND
VDD
AGND
GND
Analog system GND plane
C0
C0
Digital system GND plane
C0: 0.01 mF to 0.1 mF
1-PIN
C1: 10 mF to 47 mF or larger
Figure 13-9 Example of Noise-Suppression Measures
13-13
MSM66577 Family User's Manual
Chapter 13 A/D Converter Functions
13.6 A/D Converter Interrupt
When each of A/D converter interrupt factors occurs, the interrupt request flag (QAD) is set
to "1". The interrupt request flag (QAD) is located in interrupt request register 3 (IRQ3).
Interrupts can be enabled or disabled by the interrupt enable flag (EAD). The interrupt
enable flag (EAD) is located in interrupt enable register 3 (IE3).
Three levels of priority can be set with the interrupt priority setting flags (P0AD and P1AD).
The interrupt priority setting flags (P0AD and P1AD) are located in interrupt priority control
register 7 (IP7).
Table 13-3 lists the vector address of the A/D converter interrupt factors and the interrupt
processing flags.
Table 13-3 A/D Converter Vector Address and Interrupt Processing Flags
Vector
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
address [H]
1
0
A/D conversion of one cycle of
the scan channels is complete
A/D conversion of the
select mode is complete
0044
QAD
EAD
P1AD
P0AD
Symbols (byte) of registers that
contain interrupt processing flags
IRQ3
IE3
IP7
Reference page
17-15
17-20
17-29
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
13-14
Chapter 14
D/A Converter Functions
14
MSM66577 Family User's Manual
Chapter 14 D/A Converter Functions
14. D/A Converter Functions
14.1 Overview
The MSM66577 family has an internal 2-channel 8-bit D/A converter. The D/A conversion
method utilizes ladder resistors. If values desired to be output are written to 8-bit DA
registers(DAR0, DAR1), theconvertedanaloglevelswillbeoutputfromtheportsecondary
function output pins.
14.2 D/A Converter Configuration
Figure 14-1 shows the D/A converter configuration.
D/A
DAOUTn
converter circuit
DARn
(n = 0, 1)
Internal bus
DAR0: DA register 0
DAR1: DA register 1
DACON: DA control register
DAOUT0: D/A conversion output 0 (P14_6)
DAOUT1: D/A conversion output 1 (P14_7)
Figure 14-1 8-Bit D/A Converter Configuration
14
14-1
MSM66577 Family User's Manual
Chapter 14 D/A Converter Functions
14.3 D/A Converter Registers
Table 14-1 lists a summary of SFRs for control of the D/A converter.
Table 14-1 Summary of SFRs for D/A Converter Control
Address
[H]
Symbol
(byte)
Symbol
(word)
—
8/16
Initial value Reference
Name
R/W
operation
[H]
FE
00
00
page
14-2
14-2
14-2
00DD
00DE
00DF
D/A control register
DA register 0
DACON
DAR0
R/W
R/W
R/W
8
8
8
—
DA register 1
DAR1
—
14.3.1 Description of D/A Converter Registers
(1) DA registers (DAR0, DAR1)
DA registers (DAR0, DAR1) consist of 8 bits. After configuring the corresponding port as
a secondary function output and selecting AOn, if the desired output value is written to a
DA register, the converted analog level will be output from the corresponding port.
If a value other than 00H is written to a DA register, the DA section will consume power to
perform the conversion. Therefore, when not using D/A converters, write 00H to the DA
registers.
DA registers can be read from and written to by the program,.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), DAR0 and DAR1 become 00H.
(2) DA control register (DACON)
The DA control register (DACON) consists of 1 bit. Bit 0 (DAON) of DACON specifies
whether D/A conversion operates or is halted during standby.
If the STOP mode is transferred to while DAON is "0", even if the port secondary function
has been set and AOn selected, D/A conversion output will be discontinued while stopped,
andcurrentthatisconsumedattheD/Asectionwillbecut. Atthattime,DAregistercontents
will be preserved.
If DAON is set to "1" and the STOP mode transferred to, AOn will continue to be output.
DACON can be read from and written to by the program. However, write operations are
invalid for bits 1 to 7. If read, bits 1 to 7 are always "1".
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), DACON becomes FEH.
Figure 14-2 shows the DACON configuration.
14-2
MSM66577 Family User's Manual
Chapter 14 D/A Converter Functions
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
DAON
0
Address: 00DD [H]
R/W access: R/W
DACON
At reset
0
1
Halt during standby
Operate during standby
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 14-2 DACON Configuration
14.3.2 Example of D/A Converter-related Register Settings
(1) Port 14 mode register (P14IO)
If D/A conversion output is to be used, set bits 6 and 7 (P14IO6, P14IO7) to "1" to configure
the ports as outputs.
(2) Port 14 secondary function control register (P14SF)
IfD/Aconversionoutputistobeused, setbits6and7(P14SF6, P14SF7)to"1"toconfigure
the ports as secondary function outputs.
(3) DA registers (DAR0, DAR1)
Write a digital value to DAR0 that is equivalent to the analog level desired to be output from
pin AO0.
Write a digital value to DAR1 that is equivalent to the analog level desired to be output from
pin AO1.
(4) DA control register (DACON)
Withbit0(DAON), specifywhetherD/Aconversionwilloperateorbehaltedduringstandby.
14
14-3
MSM66577 Family User's Manual
Chapter 14 D/A Converter Functions
14.3.3 D/A Converter Operation
The 8-bit DA registers (DAR0, DAR1) are initialized to 00H. While in this state, if ports 14_6
and 14_7 (DAOUT0, DAOUT1) are configured as secondary function outputs, the output
will be at GND level (there is no current path in this state). At this time, if the port data
registers are read, a value of "1" will be obtained regardless of the D/A output level. If the
desired output value is written to DA registers (DAR0, DAR1), the converted analog level
will be output from the corresponding port. Since the analog output is not buffered inside
the chip, current cannot be drawn out. Therefore, connect a buffering amp if necessary.
Bit 0 (DAON) of the DA control register (DACON) is initialized to 0. At this time, if bit 2 (FLT)
of SBCON is set to "1" and the STOP mode entered, ports 14_6 and 14_7 (DAOUT0,
DAOUT1) will float, the D/A converter will halt, and the current path will be cut. DA register
(DAR0, DAR1) contents will be preserved.
With bit 0 (DAON) of the DA control register (DACON) set to "1", if the STOP mode is
entered, the D/A converter will not halt, and analog levels will continue to be output from
ports 14_6 and 14_7 (DAOUT0, DAOUT1).
If a value n is written to DA registers (DAR0, DAR1), the analog level obtained is expressed
as the following.
V
DD
¥ n/256 [V]
When V is 5 V, even if 0FFH is written to DA registers (DAR0, DAR1), the analog output
DD
will be approximately 4.98 V. A 5 V full-scale result cannot be obtained. Therefore, if a 5
V full-scale analog level is necessary, reconfigure the port as a primary function output.
14-4
Chapter 15
Peripheral Functions
15
MSM66577 Family User's Manual
Chapter 15 Peripheral Functions
15. Peripheral Functions
15.1 Overview
The MSM66577 family has the following functions to service peripheral ICs: a clock out
function, an external XTCLK input control function, a HOLD input control function, and a
WAIT input control function. These functions can be specified with the peripheral control
register (PRPHCON).
15.2 Description of Each Peripheral Function
15.2.1 Clock Out Function
The clock out function has following two functions :
• To output a frequency divided clock of the main clock (OSCCLK) via the CLKOUT pin.
• To output the subclock (XTCLK) via the XTOUT pin.
The main clock frequency division ratio is specified with bit 0 and bit 1 (CLKO0 and CLKO1)
of the peripheral control register (PRPHCON).
When the CLKOUT pin is to be used, P11_2 must be configured as a secondary function
output.
When the XTOUT pin is used to output the subclock (XTCLK), P11_3 must be configured
as a secondary function output.
15.2.2 External XTCLK Input Control Function
BecauseXToscillationoperatesonaninternallyregulatedvoltage, anexternalCLKcannot
normally be input to the oscillation pin. However, if bit 4 (EXTXT) of the peripheral control
register (PRPHCON) is set to "1", the internally regulated voltage is switched to V and
DD
the oscillation feedback resistor is turned off, enabling the input of an external XTCLK (V
level) to the XT pin.
DD
15.2.3 HOLD Input Control Function
If the HOLD mode, a standby function, is to be used, set bit 5 (HOLD) of the peripheral
control register (PRPHCON) to "1". Configuring P9_7 as a secondary function output
(HLDACK) enables the output of a signal that indicates availability of the bus (to transfer
to the HOLD mode).
15
15.2.4 WAIT Input Control Function
Settingbit6(WAIT)oftheperipheralcontrolregister(PRPHCON)to"1"enableswaitcycles
to be inserted by an external device when accessing an external data memory area.
15-1
MSM66577 Family User's Manual
Chapter 15 Peripheral Functions
15.3 Peripheral Control Register (PRPHCON)
The peripheral control register (PRPHCON) consists of 5 bits.
Bits 0 and 1 (CLKO0 and CLKO1) specify the frequency division ratio of OSCCLK that is
output from the CLKOUT pin. If bit 4 (EXTXT) is set to "1", an external clock can be input
to the XT oscillation circuit. Bit 5 (HOLD) enables or disables the HOLD pin input. Bit 6
(WAIT) enables or disables the WAIT pin input.
PRPHCON can be read from and written to by the program. However, write operations are
invalid for bits 2, 3 and 7. If read, a value of "1" will always be obtained for bits 2, 3 and 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), PRPHCON becomes 8CH.
Figure 15-1 shows the PRPHCON configuration.
7
—
1
6
5
4
3
—
1
2
—
1
1
0
Address: 0015 [H]
R/W access: R/W
WAIT HOLD EXTXT
CLKO1 CLKO0
PRPHCON
At reset
0
0
0
0
0
CLKO
CLKOUT pin output
1
0
0
1
1
0
0
1
0
1
1/1 OSCCLK
1/2 OSCCLK
1/4 OSCCLK
1/8 OSCCLK
0
1
XT self-oscillation (low voltage operation)
External XT (VDD level input)
0
1
Disable HOLD input
Enable HOLD input
0
1
Disable WAIT input
Enable WAIT input
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 15-1 PRPHCON Configuration
15-2
Chapter 16
External Interrupt Functions
16
MSM66577 Family User's Manual
Chapter 16 External Interrupt Functions
16. External Interrupt Functions
16.1 Overview
TheMSM66577familyisequippedwith9externalinterruptinputsthatcanbeclassifiedinto
2 categories. One category is maskable interrupts, of which there are 8 (EXINT0 to
EXINT7). The other category is non-maskable interrupts, and there is 1 (NMI).
EXINT0 to EXINT7 are assigned as secondary functions of ports P6_0 to P6_3 and P9_0
to P9_3. If EXINT are to be used, configure the corresponding ports as inputs.
NMI has its own dedicated pin.
16.2 External Interrupt Registers
Table 16-1 lists a summary of SFRs for the control of external interrupts.
Table 16-1 Summary of SFRs for External Interrupt Control
Address
[H]
Symbol
(byte)
Symbol
(word)
8/16
Initial
Reference
page
Name
R/W
R/W
R/W
R/W
Operation value [H]
External Interrupt Control
Register 0
0058
EXI0CON
EXI1CON
EXI2CON
—
—
—
8
8
8
00
00
16-2
16-3
16-4
External Interrupt Control
Register 1
0059I
005AI
External Interrupt Control
Register 2
0C/4C
[Notes]
1. A star (P) in the address column indicates a missing bit.
2. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
16
16-1
MSM66577 Family User's Manual
Chapter 16 External Interrupt Functions
16.2.1 Description of External Interrupt Registers
(1) External interrupt control register 0 (EXI0CON)
The external interrupt control register 0 (EXI0CON) consists of 8 bits and sets external
interrupts EXINT0 to EXINT3. For each external interrupt setting, EXI0CON specifies the
valid edge (falling edge, rising edge, or both edges) or the interrupt input invalid.
EXI0CON can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), EXI0CON becomes 00H.
Figure 16-1 shows the configuration of EXI0CON.
7
6
5
4
3
2
1
0
Address: 0058 [H]
R/W access: R/W
EX3M1 EX3M0 EX2M1 EX2M0 EX1M1 EX1M0 EX0M1 EX0M0
EXI0CON
At reset
0
0
0
0
0
0
0
0
EX0M
EXINT0 valid edge
1
0
0
1
1
0
0
1
0
1
Interrupt input invalid
Falling edge
Rising edge
Both edges
EX1M
EXINT1 valid edge
1
0
0
1
1
0
0
1
0
1
Interrupt input invalid
Falling edge
Rising edge
Both edges
EX2M
EXINT2 valid edge
1
0
0
1
1
0
0
1
0
1
Interrupt input invalid
Falling edge
Rising edge
Both edges
EX3M
EXINT3 valid edge
1
0
0
1
1
0
0
1
0
1
Interrupt input invalid
Falling edge
Rising edge
Both edges
Figure 16-1 EXI0CON Configuration
16-2
MSM66577 Family User's Manual
Chapter 16 External Interrupt Functions
(2) External interrupt control register 1 (EXI1CON)
The external interrupt control register 1 (EXI1CON) consists of 8 bits and sets external
interrupts EXINT4 to EXINT7. For each external interrupt setting, EXI1CON opecifies the
valid edge (falling edge, rising edge, or both edges) or the interrupt input invalid.
EXI1CON can be read from and written to by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), EXI1CON becomes 00H.
Figure 16-2 shows the configuration of EXI1CON.
7
6
5
4
3
2
1
0
Address: 0059 [H]
R/W access: R/W
EXI1CON
At reset
EX7M1 EX7M0 EX6M1 EX6M0 EX5M1 EX5M0 EX4M1 EX4M0
0
0
0
0
0
0
0
0
EX4M
EXINT4 valid edge
1
0
0
1
1
0
0
1
0
1
Interrupt input invalid
Falling edge
Rising edge
Both edges
EX5M
EXINT5 valid edge
1
0
0
1
1
0
0
1
0
1
Interrupt input invalid
Falling edge
Rising edge
Both edges
EX6M
EXINT6 valid edge
1
0
0
1
1
0
0
1
0
1
Interrupt input invalid
Falling edge
Rising edge
Both edges
EX7M
EXINT7 valid edge
1
0
0
1
1
0
0
1
0
1
Interrupt input invalid
Falling edge
Rising edge
16
Both edges
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 16-2 EXI1CON Configuration
16-3
MSM66577 Family User's Manual
Chapter 16 External Interrupt Functions
(3) External interrupt control register 2 (EXI2CON)
The external interrupt control register 2 (EXI2CON) consists of 4 bits. Bits 4 and 5 (NMIM0
and NMIM1) specify the valid edge for NMI. Bit 7 (MIPF) enables or disables priority control
for all maskable interrupts. Bit 6 (NMIRD) monitors the NMI pin.
EXI2CON can be read from and written to by the program. However, write operations to
the lower 4 bits and bit 6 are invalid. If read, bits 0 and 1 will always be "0", and bits 2 and
3 will be "1". The NMI pin level is read from bit 6 (NMIRD). This bit can be conveniently
used by the program to read the pin level during a NMI routine.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), EXI2CON becomes 0CH if the NMI pin is at a low level, or 4CH if the
NMI pin is at a high level.
Figure 16-3 shows the configuration of EXI2CON.
7
6
5
4
3
2
1
0
Address: 005A [H]
R/W access: R/W
EXI2CON
At reset
MIPF NMIRD NMIM1 NMIM0
0/1
—
—
—
—
0
0
0
1
1
0
0
NMIM
NMI valid edge
1
0
1
1
0
*
Falling edge
Rising edge
Both edges
0
1
0
1
NMI pin at LOW level
NMI pin at HIGH level
0
1
Disable IP priority
Enable IP priority
"—" indicates a nonexistent bit.
If bits 0 and 1 are read, their value will be "0."
If bits 2 and 3 are read, their value will be "1."
"*" indicates a "0" or "1"
Figure 16-3 EXI2CON Configuration
16-4
MSM66577 Family User's Manual
Chapter 16 External Interrupt Functions
16.2.2 Example of External Interrupt-related Register Settings
(1) Port 6 mode register (P6IO)
If EXINT0 to EXINT3 are to be used, reset the corresponding bits 0 to 3 (P6IO0 to P6IO3)
to "0” to configure those ports as inputs.
(2) Port 9 mode register (P9IO)
If EXINT4 and/or EXINT5 are to be used, reset the corresponding bits 0 to 3 (P9IO0 to
P9IO3) to "0” to configure those ports as inputs.
(3) Port 6 secondary function control register (P6SF)
If EXINT0 to EXINT3 are to be used, enable or disable pull-up resistors with the
corresponding bits 0 to 3 (P6SF0 to P6SF3).
(4) Port 9 secondary function control register (P9SF)
If EXINT4 and/or EXINT5 are to be used, enable or disable pull-up resistors with the
corresponding bits 0 to 3 (P9SF0 to P9SF3).
(5) External interrupt control register 0 (EXI0CON)
IfEXINT0istobeused,specifythevalidedgewithbits0and1(EX0M0,EX0M1). IfEXINT1,
EXINT2 and/or EXINT3 are to be used, specify a valid edge for each with bits 2 and 3
(EX1M0, EX1M1), bits 4 and 5 (EX2M0, EX2M1), and bits 6 and 7 (EX3M0, EX3M1).
(6) External interrupt control register 1 (EXI1CON)
IfEXINT4istobeused,specifythevalidedgewithbits0and1(EX4M0,EX4M1).IfEXINT5,
EXINT6 and EXINT7 are to be used, specify the valid edge with bits 2 and 3 (EX5M0,
EX5M1), bits 4 and 5 (EX6M0, EX6M1), and bits 6 and 7 (EX7M0, EX7M1).
(7) External interrupt control register 2 (EXI2CON)
Specify the NMI valid edge with bits 4 and 5 (NMIM0, NMIM1). If interrupt priority is to be
used, set bit 7 (MIPF) to "1".
16
16-5
MSM66577 Family User's Manual
Chapter 16 External Interrupt Functions
16.3 EXINT0 to EXINT7 Interrupts
When a valid edge is input to each external interrupt input pin, the corresponding interrupt
requestflagissetto"1". Theinterruptrequestflagsarelocatedininterruptrequestregisters
0 to 2 (IRQ0 to IRQ2).
Interrupts can be enabled or disabled by the interrupt enable flag that corresponds to each
pin input. The interrupt enable flags are located in interrupt enable registers 0 to 2 (IE0 to
IE2).
Three levels of priority can be set with the interrupt priority setting flags that correspond to
each pin input. The interrupt priority setting flags are located in interrupt priority control
registers 0, 2 and 4 (IP0, IP2 and IP4).
Table 16-2 lists the vector addresses for each pin input of EXINT0 to EXINT7 and the
interrupt processing flags.
*n (n = 1 to 9) in the above table indicates the register in which each flag is allocated.
Table 16-2 EXINT0 to EXINT7 Vector Addresses and Interrupt Processing Flags
Vector
Interrupt
request
Interrupt
enable
Priority level
Interrupt factor
address [H]
1
0
EXINT0 pin input
(external interrupt 0)
EXINT1 pin input
(external interrupt 1)
EXINT2 pin input
(external interrupt 2)
EXINT3 pin input
(external interrupt 3)
EXINT4 pin input
(external interrupt 4)
EXINT5 pin input
(external interrupt 5)
EXINT6 pin input
(external interrupt 6)
EXINT7 pin input
(external interrupt 7)
*1
*2
*4
*5
*7
*8
000A
001C
001E
0020
002A
002C
002E
0030
QINT0
QINT1
QINT2
QINT3
QINT4
QINT5
QINT6
QINT7
EINT0
EINT1
EINT2
EINT3
EINT4
EINT5
EINT6
EINT7
P1INT0
P1INT1
P1INT2
P1INT3
P1INT4
P1INT5
P1INT6
P1INT7
P0INT0
P0INT1
P0INT2
P0INT3
P0INT4
P0INT5
P0INT6
P0INT7
*3
*6
*9
*1
*2
*3
*4
*5
*6
*7
*8
*9
IRQ0
IRQ1
IRQ2
IE0
IE1
IE2
IP0
IP2
IP4
Symbols (byte) of registers that
contain interrupt processing flags
*1
*2
*3
*4
*5
*6
*7
*8
*9
17-12
17-13
17-14
17-17
17-18
17-19
17-22
17-24
17-26
Reference page
Forfurtherdetailsregardinginterruptprocessing, refertoChapter17, "InterruptProcessing
Functions".
16-6
Chapter 17
Interrupt Processing Functions
17
MSM66577 Family User's Manual
Chapter 17 Interrupt Processing Functions
17. Interrupt Processing Functions
17.1 Overview
The MSM66577 family has 39 types of interrupts (9 external and 30 internal). These are
assigned to 30 vectors. One of the external interrupts is a non-maskable interrupt. Three
levels of priority can be set for maskable interrupts.
Table 17-1 lists interrupts and their corresponding vector addresses.
Table 17-1 Interrupts and Their Corresponding Vector Addresses
Interrupt
NMI pin input (non-maskable interrupt)
EXINT0 pin input (external interrupt 0)
Free running counter overflow
CPCM0 event input, compare match
CPCM1 event input, compare match
Timer 0 overflow
Vector address [H]
0008
000A
000C
0016
0018
001A
EXINT1 pin input (external interrupt 1)
EXINT2 pin input (external interrupt 2)
EXINT3 pin input (external interrupt 3)
Timer 1 overflow
001C
001E
0020
0022
Timer 2 overflow
0024
Timer 3 overflow
0026
EXINT4 pin input (external interrupt 4)
EXINT5 pin input (external interrupt 5)
EXINT6 pin input (external interrupt 6)
EXINT7 pin input (external interrupt 7)
Timer 4 overflow
002A
002C
002E
0030
0036
SIO1 transmit buffer empty, transmit complete,
receive complete
0038
Timer 5 overflow
003A
003C
Interrupt by SIO5 transfer completion
Interrupt by SIO6 transmit buffer empty,
transmit completion, receive completion
Interrupt by SIO4 transfer completion
Timer 6 overflow
003E
0040
0042
17
One cycle of A/D conversion scan channels complete,
A/D conversion select mode complete
Real-time counter output (interval: 0.125 to 1 s)
PWC0 overflow, match of PWC0 and PWR0
PWC1 overflow, match of PWC1 and PWR1
Match of PWC0 and PWR2
0044
0048
006A
006C
006E
0070
0072
Match of PWC1 and PWR3
Timer 9 overflow
17-1
MSM66577 Family User's Manual
Chapter 17 Interrupt Processing Functions
17.2 Interrupt Function Registers
Table 17-2 lists a summary of SFRs for interrupt processing
Table 17-2 Summary of SFRs for Interrupt Processing
Address
[H]
Symbol
(byte)
Symbol
(word)
8/16
Initial
Reference
page
Name
R/W
R/W
R/W
Operation value [H]
0004
0005
PSWL
PSWH
00
Program status word
PSW
—
8/16
00
2-18
16-4
External interrupt control
register 2
005AI
EXI2CON
8
0C/4C
0030I Interrupt request register 0
0031I Interrupt request register 1
0032I Interrupt request register 2
0033I Interrupt request register 3
005CI Interrupt request register 4
0034I Interrupt enable register 0
0035I Interrupt enable register 1
0036I Interrupt enable register 2
0037I Interrupt enable register 3
005DI Interrupt enable register 4
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IE0
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
00
00
00
00
E0
00
00
00
00
E0
17-12
17-13
17-14
17-15
17-16
17-17
17-18
17-19
17-20
17-21
IE1
IE2
IE3
IE4
Interrupt priority control
0038I
IP0
IP1
IP2
IP3
IP4
IP5
IP6
IP7
IP8
IP9
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
00
00
00
00
00
00
00
00
00
FC
17-22
17-23
17-24
17-25
17-26
17-27
17-28
17-29
17-30
17-31
register 0
Interrupt priority control
0039I
register 1
Interrupt priority control
003A
register 2
Interrupt priority control
003BI
register 3
Interrupt priority control
003CI
register 4
Interrupt priority control
003DI
register 5
Interrupt priority control
003EI
register 6
Interrupt priority control
003FI
register 7
Interrupt priority control
005EI
register 8
Interrupt priority control
005FI
register 9
[Notes]
1. Addresses may not be consecutive in some places.
2. A star (P) in the address column indicates a missing bit.
3. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
17-2
MSM66577 Family User's Manual
Chapter 17 Interrupt Processing Functions
17.3 Description of Interrupt Processing
17.3.1 Non-Maskable Interrupt (NMI)
The non-maskable interrupt (NMI) is an external interrupt that cannot be masked.
When the valid edge specified by bits 4 and 5 (NMIM0, NMIM1) of EXI2CON is detected,
the CPU immediately transfers processing to the non-maskable interrupt.
However, the one exception occurs after reset (RES signal input, execution of a BRK
instruction,overflowofthewatchdogtimer,opcodetrap),wherethenon-maskableinterrupt
is masked until execution of the first instruction is complete. This function is intended to
prevent loss of program control after reset in the case where the non-maskable interrupt
occurs before the system stack pointer (SSP) is set with a value (when the SSP is
undefined). Therefore,operatedaspartoftheaboveNMIfunction,setanappropriatevalue
in SSP with the "first instruction after reset".
[Related information reference guide]
NMI settings … page 16-4
When the non-maskable interrupt (NMI) occurs, a sequence such as listed below is
automatically processed by the hardware and the first instruction of the NMI routine is
executed. 14 cycles are used to transfer to the NMI routine.
• Save the program counter (PC)
• Save the accumulator (ACC)
• Save the local register base (LRB)
• Save the program status word (PSW)
• Reset the non-maskable interrupt request flag
• Disable maskable interrupts
• Disable multiple interrupts by the non-maskable interrupt
• Load the program counter with the value that has been written to the NMI routine vector
table (0008H, 0009H)
Use a RTI instruction at the end of the NMI routine.
When a RTI instruction is executed, the hardware automatically processes a sequence
such as listed below to complete the NMI routine. 12 cycles are used to return from the NMI
routine.
• Restore the program status word (PSW)
• Restore the local register base (LRB)
• Restore the accumulator (ACC)
• Restore the program counter (PC)
• Enable maskable interrupts
17
• Enable multiple interrupts by the non-maskable interrupt
Figure 17-1 shows examples of saving and restoring the PC, ACC, LRB and PSW.
17-3
MSM66577 Family User's Manual
Chapter 17 Interrupt Processing Functions
[Note]
If the program memory space has been expanded to 1MB, in addition to the above
processing, the code segment register (CSR) will be saved and restored. In this case,
17 cycles will be used to transfer to the NMI routine, and 14 cycles to return from the NMI
routine.
• Interrupt processing example (for a 64KB program memory space)
07F7H
07F8H
SSP Æ 07F7H
07F8H
07F7H
07F8H
PSWL
PSWH
LRBL
LRBH
ACCL
ACCH
PCL
PSWL
PSWH
LRBL
LRBH
ACCL
ACCH
PCL
07F9H
07F9H
07F9H
07FAH
07FAH
07FAH
07FBH
07FBH
07FBH
07FCH
07FCH
07FDH
07FEH
07FCH
07FDH
07FDH
07FEH
07FEH
SSP Æ 07FFH
07FFH
PCH
SSP Æ 07FFH
PCH
(before saving)
(after saving)
(before execution of
RTI instruction)
(after execution of
RTI instruction)
• Interrupt processing example (for a greater than 64KB program memory space)
07F4H
07F5H
07F4H
SSP Æ 07F5H
07F6H
07F4H
07F5H
07F6H
PSWL
PSWH
LRBL
07F6H
PSWL
PSWH
LRBL
07F7H
07F7H
07F7H
07F8H
07F8H
07F8H
07F9H
07F9H
LRBH
ACCL
ACCH
CSR
07F9H
LRBH
ACCL
ACCH
CSR
07FAH
07FAH
07FAH
07FBH
07FBH
07FBH
07FCH
07FCH
07FCH
07FDH
07FDH
Undefined
PCL
07FDH
Undefined
PCL
07FEH
07FEH
07FEH
SSP Æ 07FFH
07FFH
PCH
SSP Æ 07FFH
PCH
(before saving)
(after saving)
(before execution of
RTI instruction)
(after execution of
RTI instruction)
SSP: System Stack Pointer
Figure 17-1 Examples of Saving and Restoring the PC, ACC, LRB and PSW
17-4
MSM66577 Family User's Manual
Chapter 17 Interrupt Processing Functions
17.3.2 Maskable Interrupts
Maskable interrupts are generated by various interrupt factors such as built-in internal
peripheral hardware, external interrupt inputs, etc.
The control of maskable interrupts is performed by the following.
• Interrupt request registers (IRQ0 to IRQ4)
• Interrupt enable registers (IE0 to IE4)
• Master interrupt enable flag (MIE)
• Master interrupt priority flag (MIPF)
• Interrupt priority control registers (IP0 to IP9)
(1) Interrupt request registers (IRQ0 to IRQ4)
Interrupt request registers (IRQs) are set to "1" when each interrupt source generates an
interrupt signal. If an interrupt is received, the registers are automatically reset to "0" while
transferring to the interrupt processing routine. IRQ bits can also be set to "1" or "0" by the
program.
(2) Interrupt enable registers (IE0 to IE4)
Interrupt enable registers (IEs) individually enable or disable the generation of interrupts.
When an IE bit is "0", generation of the corresponding interrupt is disabled. When an IE bit
is "1", generation of the corresponding interrupt is enabled.
(3) Master interrupt enable flag (MIE)
The master interrupt enable flag (MIE) is a 1-bit flag located in the program status word
(PSW). MIE enables or disables generation of all the maskable interrupts.
MIE = "0" All maskable interrupts are disabled (regardless of IE)
MIE = "1" Maskable interrupts are enabled (only those interrupt factors enabled by IE)
[Related information reference guide]
Program status word (PSW) … Page 2-18
(4) Master interrupt priority flag (MIPF)
Themasterinterruptpriorityflag(MIPF)isa1-bitflaglocatedintheexternalinterruptcontrol
register 2 (EXI2CON). MIPF enables or disables priority for all the maskable interrupts.
MIPF = "0" Priority control disabled (regardless of IP, interrupts controlled by MIE and IE
only)
MIPF = "1" Priority control enabled (3 levels of priority control according to IP setting)
[Related information reference guide]
External interrupt control register 2 (EXI2CON) … Page 16-4
17
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Chapter 17 Interrupt Processing Functions
(5) Interrupt priority control registers (IP0 to IP9)
Interrupt priority control registers (IPs) specify the priority of maskable interrupts. The 2-
bit specification (P1xxx, P0xxx) for each interrupt indicates 3 levels of priority (where xxx
is an abbreviation for each interrupt factor). For further details regarding priority control,
refer to Section 17.3.3, "Priority Control of Maskable Interrupts".
Priority is specified as shown below.
P1xxx
P0xxx
Priority
Level 0
0
0
1
0
1
*
(low)
Level 1
Level 2
(high)
( * indicates either "0" or "1")
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Chapter 17 Interrupt Processing Functions
Figure 17-2 shows a block diagram of the control for maskable interrupts. IRQ bits are
indicated as Qxxx, IE bits as Exxx, and IP bits as P0xxx, P1xxx for each interrupt factor.
In some cases, several maskable interrupts correspond to the same interrupt vector. For
those interrupts, within each function block there is a flag to enable or disable multiple
interrupts and an interrupt request flag to verify (by polling) which interrupt was generated.
[1 interrupt vector for each interrupt]
Interrupt
controller
Exxx
MIE
MIPF
P1xxx P0xxx
LV2
LV1
LV0
NP
Interrupt
source
Qxxx
[1 interrupt vector for 2 interrupts]
Y Interrupt
Interrupt
controller
Enable Y
source
Exxx
MIE
MIPF
P1xxx P0xxx
LV2
LV1
LV0
NP
Y interrupt request
Qxxx
Z interrupt
Enable Z
source
Z interrupt request
The control in the above enclosed area exists in each function block.
Figure 17-2 Maskable Interrupt Control Block Diagram
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Chapter 17 Interrupt Processing Functions
Table 17-3 lists the vector address and bit symbol for each maskable interrupt.
If multiple maskable interrupts are generated simultaneously, the lower vector address (in
the order of Table 17-3) is given priority and processed. Similarly, for interrupts that have
been enabled, if the priority level is set and priority control enabled (MIPF = "1"), when
multiplemaskableinterruptswiththesamepriorityaregeneratedsimultaneously, thelower
vector address is given priority and processed.
Table 17-3 Vector Addresses and Bit Symbols for Maskable Interrupts
Vector
address [H] request
QINT0
Interrupt
Interrupt
enable
EINT0
Priority level
No.
Interrupt factor
1
0
1
2
3
4
5
6
7
8
9
EXINT0 pin input (external interrupt 0)
Free running counter overflow
CPCM0 event input, compare match
CPCM1 event input, compare match
Timer 0 overflow
000A
000C
0016
0018
001A
001C
001E
0020
0022
0024
0026
002A
002C
002E
0030
0036
P1INT0
P0INT0
QFRCOV EFRCOV P1FRCOV P0FRCOV
QCPCM0 ECPCM0 P1CPCM0 P0CPCM0
QCPCM1 ECPCM1 P1CPCM1 P0CPCM1
QTM0OV ETM0OV P1TM0OV P0TM0OV
EXINT1 pin input (external interrupt 1)
EXINT2 pin input (external interrupt 2)
EXINT3 pin input (external interrupt 3)
Timer 1 overflow
QINT1
QINT2
QINT3
EINT1
EINT2
EINT3
P1INT1
P1INT2
P1INT3
P0INT1
P0INT2
P0INT3
QTM1OV ETM1OV P1TM1OV P0TM1OV
QTM2OV ETM2OV P1TM2OV P0TM2OV
QTM3OV ETM3OV P1TM3OV P0TM3OV
10 Timer 2 overflow
11 Timer 3 overflow
12 EXINT4 pin input (external interrupt 4)
13 EXINT5 pin input (external interrupt 5)
14 EXINT6 pin input (external interrupt 6)
15 EXINT7 pin input (external interrupt 7)
16 Timer 4 overflow
QINT4
QINT5
QINT6
QINT7
EINT4
EINT5
EINT6
EINT7
P1INT4
P1INT5
P1INT6
P1INT7
P0INT4
P0INT5
P0INT6
P0INT7
QTM4OV ETM4OV P1TM4OV P0TM4OV
QSIO1 ESIO1 P1SIO1 P0SIO1
QTM5OV ETM5OV P1TM5OV P0TM5OV
SIO1 transmit buffer empty, transmit
17
0038
complete, receive complete
18 Timer 5 overflow
003A
003C
19 Interrupt by SIO5 transfer completion
QSIO5
QSIO6
QSIO4
ESIO5
ESIO6
ESIO4
P1SIO5
P1SIO6
P1SIO4
P0SIO5
P0SIO6
P0SIO4
Interrupt by SIO6 transmit buffer empty,
20
003E
transmit completion, receive completion
21 Interrupt by SIO4 transfer completion
22 Timer 6 overflow
0040
0042
QTM6OV ETM6OV P1TM6OV P0TM6OV
One cycle of A/D conversion scan channels
23
0044
QAD
EAD
P1AD
P0AD
complete, A/D conversion select mode complete
24 Real-time counter output (interval: 0.125 to 1 s)
25 PWC0 overflow, match of PWC0 and PWR0
26 PWC1 overflow, match of PWC1 and PWR1
27 Match of PWC0 and PWR2
0048
006A
006C
006E
0070
0072
QRTC
ERTC
P1RTC
P0RTC
QPWM0
QPWM1
QPWM2
QPWM3
EPWM0 P1PWM0 P0PWM0
EPWM1 P1PWM1 P0PWM1
EPWM2 P1PWM2 P0PWM2
EPWM3 P1PWM3 P0PWM3
28 Match of PWC1 and PWR3
29 Timer 9 overflow
QTM9OV ETM9OV P1TM9OV P0TM9OV
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Chapter 17 Interrupt Processing Functions
When a maskable interrupt occurs, a sequence such as listed below is automatically
processed by the hardware and the first instruction of the maskable interrupt routine is
executed. 14 cycles are used to transfer to the maskable interrupt routine.
• Save the program counter (PC)
• Save the accumulator (ACC)
• Save the local register base (LRB)
• Save the program status word (PSW)
• Reset the IRQ that initiated the maskable interrupt process
• Reset MIE in PSW (resetting MIE to "0" disables reception of all maskable interrupts)
• Disable reception of interrupts with the same or lower interrupt priority level (if MIPF = 1)
• Load the program counter with the value that has been written to the vector table
Use a RTI instruction at the end of the maskable interrupt routine.
When a RTI instruction is executed, the hardware automatically processes a sequence
such as listed below to complete the maskable interrupt routine. 12 cycles are used to
return from the maskable interrupt routine.
• Enable reception of interrupts with the same or lower interrupt priority level (if MIPF = 1)
• Restore the program status word (PSW) (set MIE to "1")
• Restore the local register base (LRB)
• Restore the accumulator (ACC)
• Restore the program counter (PC)
Figure 17-1 shows examples of saving and storing the PC, ACC, LRB and PSW.
[Note]
If the program memory space has been expanded to 1MB, in addition to the above
processing, the code segment register (CSR) will be saved and restored. In this case,
17 cycles will be used to transfer to the maskable interrupt routine, and 14 cycles to return
from the maskable interrupt routine.
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17.3.3 Priority Control of Maskable Interrupts
The MSM66577 family can set 3 levels of priority for each maskable interrupt factor,
resulting in easy to realize control of multiple interrupts. Priority control in actual programs
is described below.
(1) Basic interrupt control
When a maskable interrupt occurs, since the reception of other maskable interrupts is
automatically disabled (MIE = "0"), other interrupts (except for nonmaskable interrupts and
reset processing) will not occur within the interrupt processing routine. If another maskable
interrupt is generated during execution of the interrupt routine, that interrupt will wait for
processing. In such a case, immediately after processing of the first interrupt is completed,
processing of the interrupt that has been waiting will begin. (See Figure 17-3.) If several
interrupts are awaiting processing, the interrupt vector with the lowest address will be
processed first. (See Table 17-3.)
(2) Multiple interrupt control
During execution of an interrupt routine, other maskable interrupts may be enabled. This
is known as "multiple interrupt control". If multiple interrupt control is required, make a
setting so that multiple interrupts will be enabled (MIE = "1") within the maskable interrupt
routine when a maskable interrupt occurs.
The following two methods exist for multiple interrupt control.
(i) Control by IE flags
(ii) Control by MIPF (Master Interrupt Priority Flag)
(i) Control by IE flags
In the interrupt processing routine, only those IE flags that correspond to the multiple
interrupt factors to be enabled are set to "1". Multiple interrupts from other factors are
disabled by setting their IE flags to "0".
Next, by setting the MIE flag to "1" within the interrupt processing routine, the reception of
multiple interrupts for the enabled interrupt factors enabled by setting the IE flags to "1" will
begin. (See Figure 17-4.)
If an interrupt occurs for which the corresponding IE flag is "0" while another interrupt is
being processed, the interrupt will wait until the interrupt process being executed is
completed and the program changes its IE flag to "1".
(ii) Control by MIPF (Master Interrupt Priority Flag)
In addition to the control of (i) above, by setting MIPF to "1", the priority of maskable
interruptscanbecontrolledbythehardware. Oftheenabledinterruptfactorsspecifiedwith
IE = "1", multiple interrupts are enabled only for those interrupt factors whose priority is
higher than that of the interrupt currently being processed. (If MIPF = "0", then all interrupt
factors with IE specified as "1" will be enabled for multiple interrupts.)
Ifinterruptsaregeneratedhavingthesameorlowerprioritythanthatoftheinterruptprocess
currently being executed, those interrupts will wait until completion of the interrupt process
currently being executed. After completion of the interrupt process, if several interrupts are
waiting, they will be executed in order of highest priority. However, if there are several
interrupts with the same priority level, the interrupt with the lowest vector address will be
processed first. (See Table 17-3.)
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Main program flow
Interrupt request A occurs (IRQ = 1, IE = 1)
MIEÆ"0"
Interrupt processing routine A
Interrupt request B occurs (IRQ = 1, IE = 1)
Interrupt wait
MIEÆ"1"
MIEÆ"0"
Interrupt processing routine B
MIEÆ"1"
Figure 17-3 Fundamental Interrupt Control
Main program flow
Interrupt request A occurs (IRQ = 1, IE = 1)
Interrupt request B occurs (IRQ = 1, IE = 1)
MIEÆ"0"
MIEÆ"1"
Interrupt processing routine A
MIEÆ"0"
Interrupt processing routine B
MIEÆ"1"
17
MIEÆ"1"
Figure 17-4 Multiple Interrupt Control
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17.4 IRQ, IE and IP Register Configurations for Each Interrupt
Each interrupt factor has its own interrupt request register (IRQ0 to IRQ4), interrupt enable
register (IE0 to IE4) and interrupt priority control register (IP0 to IP9).
These registers are allocated as a group of interrupt processing registers, independent
from the group of operation and control registers for each internal peripheral module.
The configurations of each interrupt processing register are presented below, showing
which bits of which registers are allocated as the IRQ, IE and IP flags for each interrupt
factor. At the end of chapters describing internal peripheral modules, a reference page is
listed for the interrupt processing registers of that module.
17.4.1 Interrupt Request Registers (IRQ0 to IRQ4)
(1) Interrupt request register 0 (IRQ0)
Interrupt request register 0 (IRQ0) consists of 4 bits. Bits are set to "1" corresponding to
external interrupt 0 (bit 0), overflow of free running counter (bit 1), CPCM0 event input /
compare match (bit 6), and CPCM1 event input/compare match (bit 7).
IRQ0 can be read or written by the program. However, if writing to bits 2 through 5, always
write those bits as "0". If read, a value of "0" will always be obtained for bits 2 through 5.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IRQ0 becomes 00H.
Figure 17-5 shows the configuration of IRQ0.
7
6
5
4
"0"
0
3
"0"
0
2
1
0
Address: 0030 [H]
R/W access: R/W
QCPCM1 QCPCM0 "0"
"0" QFRCOV QINT0
IRQ0
At reset
0
0
0
0
0
0
0
No interrupt request from external interrupt 0
Interrupt request from external interrupt 0
1
0
1
No free running counter overflow interrupt request
Free running counter overflow interrupt request
No CPCM0 capture input/compare
match interrupt request
0
1
Interrupt request from CPCM0 capture
input/compare match
No CPCM1 capture input/compare
match interrupt request
0
1
Interrupt request from CPCM1 capture
input/compare match
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
Figure 17-5 IRQ0 Configuration
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Chapter 17 Interrupt Processing Functions
(2) Interrupt request register 1 (IRQ1)
Interrupt request register 1 (IRQ1) consists of 7 bits. Bits are set to "1" corresponding to
overflow of timer 0 (bit 0), external interrupts 1 to 3 (bits 1 to 3) and overflow of timers 1 to
3 (bits 4 to 6).
IRQ1 can be read or written by the program. However, if writing to bit 7, always write the
bit as "0". If read, a value of "0" will always be obtained for bit 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IRQ1 becomes 00H.
Figure 17-6 shows the configuration of IRQ1.
7
"0"
0
6
5
4
3
2
1
0
Address: 0031 [H]
R/W access: R/W
QTM3OV QTM2OV QTM1OV QINT3 QINT2 QINT1 QTM0OV
IRQ1
At reset
0
0
0
0
0
0
0
0
No request from timer 0 overflow interrupt
Request from timer 0 overflow interrupt
1
0
1
No interrupt request from external interrupt 1
Interrupt request from external interrupt 1
0
1
No interrupt request from external interrupt 2
Interrupt request from external interrupt 2
0
1
No interrupt request from external interrupt 3
Interrupt request from external interrupt 3
0
1
No request from timer 1 overflow interrupt
Request from timer 1 overflow interrupt
0
1
No request from timer 2 overflow interrupt
Request from timer 2 overflow interrupt
0
1
No request from timer 3 overflow interrupt
Request from timer 3 overflow interrupt
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
Figure 17-6 IRQ1 Configuration
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Chapter 17 Interrupt Processing Functions
(3) Interrupt request register 2 (IRQ2)
Interrupt request register 2 (IRQ2) consists of 6 bits. Bits are set to "1" corresponding to
external interrupts 4 to 7 (bits 0 to 3), overflow of timer 4 (bit 6), and SIO1 transmit buffer
empty/transmit complete/receive complete (bit 7).
IRQ2 can be read or written by the program. However, if writing to bits 4 and 5, always write
those bits as "0". If read, a value of "0" will always be obtained for bits 4 and 5.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IRQ2 becomes 00H.
Figure 17-7 shows the configuration of IRQ2.
7
6
5
"0"
0
4
"0"
0
3
2
1
0
Address: 0032 [H]
R/W access: R/W
QSIO1 QTM4OV
QINT7 QINT6 QINT5 QINT4
IRQ2
At reset
0
0
0
0
0
0
0
No interrupt request from external interrupt 4
Interrupt request from external interrupt 4
1
0
1
No interrupt request from external interrupt 5
Interrupt request from external interrupt 5
0
1
No interrupt request from external interrupt 6
Interrupt request from external interrupt 6
0
1
No interrupt request from external interrupt 7
Interrupt request from external interrupt 7
0
1
No request from timer 4 overflow interrupt
Request from timer 4 overflow interrupt
No request from SIO1 transmit buffer empty/
transmit complete, receive complete interrupt
0
1
Request from SIO1 transmit buffer empty/
transmit complete, receive complete interrupt
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
Figure 17-7 IRQ2 Configuration
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(4) Interrupt request register 3 (IRQ3)
Interrupt request register 3 (IRQ3) consists of 7 bits. Bits are set to "1" corresponding to
overflow of timer 5 (bit 0), SIO5 and SIO4 transmit-receive completion (bits 1 and 3),
overflow of timer 6 (bit 4), A/D conversion scan channel cycle complete/select mode
complete (bit 5), and real-time counter output (bit 7).
IRQ3 can be read or written by the program. However, if writing to bit 6, always write the
bit as "0". If read, a value of "0" will always be obtained for bit 6.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IRQ3 becomes 00H.
Figure 17-8 shows the configuration of IRQ3.
7
QRTC
0
6
"0"
0
5
4
3
2
1
0
Address: 0033 [H]
R/W access: R/W
QAD QTM6OV QSIO4 QSIO6 QSIO5 QTM5OV
IRQ3
At reset
0
0
0
0
0
0
0
No request from timer 5 overflow interrupt
Request from timer 5 overflow interrupt
1
0
1
Disable interrupt by SIO5 transfer completion
Enable interrupt by SIO5 transfer completion
No request from interrupt by SIO6 transmit buffer empty,
transmit completion, receive completion
0
1
Request from interrupt by SIO6 transmit buffer empty,
transmit completion, receive completion
0
1
No request from interrupt by SIO4 transfer completion
Request from interrupt by SIO4 transfer completion
0
1
No request from timer 6 overflow interrupt
Request from timer 6 overflow interrupt
No request from A/D conversion scan channel
cycle complete/select mode complete interrupt
0
1
Request from A/D conversion scan channel
cycle complete/select mode complete interrupt
0
1
No request from real-time counter output interrupt
Request from real-time counter output interrupt
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
17
Figure 17-8 IRQ3 Configuration
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(5) Interrupt request register 4 (IRQ4)
Interrupt request register 4 (IRQ4) consists of 5 bits. Bits are set to "1" corresponding to
overflow of PWC0/matching of PWC0 and PWR0 (bit 0), overflow of PWC1/matching of
PWC1 and PWR1 (bit 1), matching of PWC0 and PWR2 (bit 2), matching of PWC1 and
PWR3 (bit 3), and overflow of timer 9 (bit 4).
IRQ4 can be read or written by the program. However, writes to bits 5 through 7 are invalid.
If read, a value of "1" will always be obtained for bits 5 through 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IRQ4 becomes E0H.
Figure 17-9 shows the configuration of IRQ4.
7
—
1
6
—
1
5
—
1
4
3
2
1
0
Address: 005C [H]
R/W access: R/W
QTM9OV QPWM3QPWM2QPWM1QPWM0
IRQ4
At reset
0
0
0
0
0
No request from PWC0 overflow/PWC0
0
and PWR0 matching interrupt
Request from PWC0 overflow/PWC0
and PWR0 matching interrupt
1
No request from PWC1 overflow/PWC1
and PWR1 matching interrupt
0
1
Request from PWC1 overflow/PWC1
and PWR1 matching interrupt
0
1
No request from PWC0 and PWR2 matching interrupt
Request from PWC0 and PWR2 matching interrupt
0
1
No request from PWC1 and PWR3 matching interrupt
Request from PWC1 and PWR3 matching interrupt
0
1
No request from timer 9 overflow interrupt
Request from timer 9 overflow interrupt
"—" indicates a non-existent bit.
When read, its value will be "1".
Figure 17-9 IRQ4 Configuration
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17.4.2 Interrupt Enable Registers (IE0 to IE4)
(1) Interrupt enable register 0 (IE0)
Interrupt enable register 0 (IE0) consists of 4 bits. The generation of interrupts is enabled
by setting bits to "1" corresponding to external interrupt 0 (bit 0), overflow of free running
counter (bit 1), CPCM0 event input /compare match (bit 6), and CPCM1 event input/
compare match (bit 7).
IE0 can be read or written by the program. However, if writing to bits 2 through 5, always
write those bits as "0". If read, a value of "0" will always be obtained for bits 2 through 5.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IE0 becomes 00H.
Figure 17-10 shows the configuration of IE0.
7
6
5
4
"0"
0
3
"0"
0
2
1
0
Address: 0034 [H]
R/W access: R/W
ECPCM1ECPCM0 "0"
"0" EFRCOV EINT0
IE0
At reset
0
0
0
0
0
0
0
Disable external interrupt 0
Enable external interrupt 0
1
0
1
Disable free running counter overflow interrupt
Enable free running counter overflow interrupt
Disable CPCM0 capture input/compare
match interrupt
0
1
Enable CPCM0 capture input/compare
match interrupt
Disable CPCM1 capture input/compare
match interrupt
0
1
Enable CPCM1 capture input/compare
match interrupt
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
Figure 17-10 IE0 Configuration
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(2) Interrupt enable register 1 (IE1)
Interrupt enable register 1 (IE1) consists of 7 bits. The generation of interrupts is enabled
by setting bits to "1" corresponding to overflow of timer 0 (bit 0), external interrupts 1 to 3
(bits 1 to 3), and overflow of timers 1 to 3 (bits 4 to 6).
IE1 can be read or written by the program. However, if writing to bit 7, always write the bit
as "0". If read, a value of "0" will always be obtained for bit 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IE1 becomes 00H.
Figure 17-11 shows the configuration of IE1.
7
"0"
0
6
ETM3OV
0
5
4
3
2
1
0
Address: 0035 [H]
R/W access: R/W
ETM2OV ETM1OV EINT3 EINT2 EINT1 ETM0OV
IE1
At reset
0
0
0
0
0
0
0
Disable timer 0 overflow interrupt
Enable timer 0 overflow interrupt
1
0
1
Disable external interrupt 1
Enable external interrupt 1
0
1
Disable external interrupt 2
Enable external interrupt 2
0
1
Disable external interrupt 3
Enable external interrupt 3
0
1
Disable timer 1 overflow interrupt
Enable timer 1 overflow interrupt
0
1
Disable timer 2 overflow interrupt
Enable timer 2 overflow interrupt
0
1
Disable timer 3 overflow interrupt
Enable timer 3 overflow interrupt
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
Figure 17-11 IE1 Configuration
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(3) Interrupt enable register 2 (IE2)
Interrupt enable register 2 (IE2) consists of 6 bits. The generation of interrupts is enabled
by setting bits to "1" corresponding to external interrupts 4 to 7 (bits 0 to 3), overflow of timer
4 (bit 6), and SIO1 transmit buffer empty/transmit complete/receive complete (bit 7).
IE2 can be read or written by the program. However, if writing to bits 4 and 5, always write
those bits as "0". If read, a value of "0" will always be obtained for bits 4 and 5.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IE2 becomes 00H.
Figure 17-12 shows the configuration of IE2.
7
6
5
4
"0"
0
3
2
1
0
Address: 0036 [H]
R/W access: R/W
ESIO1 ETM4OV "0"
EINT7 EINT6 EINT5 EINT4
IE2
At reset
0
0
0
0
0
0
0
0
Disable external interrupt 4
Enable external interrupt 4
1
0
1
Disable external interrupt 5
Enable external interrupt 5
0
1
Disable external interrupt 6
Enable external interrupt 6
0
1
Disable external interrupt 7
Enable external interrupt 7
0
1
Disable timer 4 overflow interrupt
Enable timer 4 overflow interrupt
Disable SIO1 transmit buffer empty/transmit
complete, receive complete interrupt
0
1
Enable SIO1 transmit buffer empty/transmit
complete, receive complete interrupt
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
Figure 17-12 IE2 Configuration
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(4) Interrupt enable register 3 (IE3)
Interrupt enable register 3 (IE3) consists of 7 bits. The generation of interrupts is enabled
by setting bits to "1" corresponding to overflow of timer 5 (bit 0), SIO5 and SIO4 transmit-
receive completion (bits 1 and 3), SIO6 transmit buffer empty/transmit complete/receive
complete (bit 2) overflow of timer 6 (bit 4), A/D conversion scan channel cycle complete/
select mode complete (bit 5), and real-time counter output (bit 7).
IE3 can be read or written by the program. However, if writing to bit 6, always write the bit
as "0". If read, a value of "0" will always be obtained for bit 6.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IE3 becomes 00H.
Figure 17-13 shows the configuration of IE3.
7
ERTC
0
6
"0"
0
5
4
3
2
1
0
Address: 0037 [H]
R/W access: R/W
EAD ETM6OV ESIO4 ESIO6 ESIO5 ETM5OV
IE3
At reset
0
0
0
0
0
0
0
Disable timer 5 overflow interrupt
Enable timer 5 overflow interrupt
1
0
1
Disable interrupt by SIO5 transfer completion
Enable interrupt by SIO5 transfer completion
No request from interrupt by SIO6 transmit buffer empty,
transmit completion, receive completion
0
1
Request from interrupt by SIO6 transmit buffer empty,
transmit completion, receive completion
0
1
No request from interrupt by SIO4 transfer completion
Request from interrupt by SIO4 transfer completion
0
1
Disable timer 6 overflow interrupt
Enable timer 6 overflow interrupt
Disable A/D conversion scan channel cycle
complete/select mode complete interrupt
0
1
Enable A/D conversion scan channel cycle
complete/select mode complete interrupt
0
1
Disable real-time counter output interrupt
Enable real-time counter output interrupt
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
Figure 17-13 IE3 Configuration
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Chapter 17 Interrupt Processing Functions
(5) Interrupt enable register 4 (IE4)
Interrupt enable register 4 (IE4) consists of 5 bits. The generation of interrupts is enabled
by setting bits to "1" corresponding to overflow of PWC0/matching of PWC0 and PWR0 (bit
0), overflow of PWC1/matching of PWC1 and PWR1 (bit 1), matching of PWC0 and PWR2
(bit 2), matching of PWC1 and PWR3 (bit 3), and overflow of timer 9 (bit 4).
IE4 can be read or written by the program. However, writes to bits 5 through 7 are invalid.
If read, a value of "1" will always be obtained for bits 5 through 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IE4 becomes E0H.
Figure 17-14 shows the configuration of IE4.
7
—
1
6
—
1
5
—
1
4
3
2
1
0
Address: 005D [H]
R/W access: R/W
ETM9OV EPWM3 EPWM2 EPWM1 EPWM0
IE4
At reset
0
0
0
0
0
Disable PWC0 overflow/PWC0
and PWR0 matching interrupt
0
1
Enable PWC0 overflow/PWC0
and PWR0 matching interrupt
Disable PWC1 overflow/PWC1
and PWR1 matching interrupt
0
1
Enable PWC1 overflow/PWC1
and PWR1 matching interrupt
0
1
Disable PWC0 and PWR2 matching interrupt
Enable PWC0 and PWR2 matching interrupt
0
1
Disable PWC1 and PWR3 matching interrupt
Enable PWC1 and PWR3 matching interrupt
0
1
Disable timer 9 overflow interrupt
Enable timer 9 overflow interrupt
"—" indicates a non-existent bit.
When read, its value will be "1".
Figure 17-14 IE4 Configuration
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17.4.3 Interrupt Priority Control Registers (IP0 to IP9)
(1) Interrupt priority control register 0 (IP0)
Interrupt priority control register 0 (IP0) consists of 4 bits and specifies the interrupt priority
for external interrupt 0 (bits 0 and 1) and overflow of the free running counter (bits 2 and 3).
IP0 can be read or written by the program. However, if writing to bits 4 through 7, always
write those bits as "0". If read, a value of "0" will always be obtained for bits 4 through 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP0 becomes 00H.
Figure 17-15 shows the configuration of IP0.
7
6
5
4
3
2
1
0
Address: 0038 [H]
R/W access: R/W
IP0
"0"
"0"
"0"
"0" P1FRCOV P0FRCOV P1INT0 P0INT0
At reset
0
0
0
0
0
0
0
0
INT0
External interrupt 0 priority
P1 P0
0
0
1
0
1
*
Level 0
Level 1
Level 2
FRCOV
P1 P0
Free running counter
interrupt priority
0
0
1
0
1
*
Level 0
Level 1
Level 2
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
"*" indicates a "0" or "1".
Figure 17-15 IP0 Configuration
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(2) Interrupt priority control register 1 (IP1)
Interrupt priority control register 1 (IP1) consists of 4 bits and specifies interrupt priority for
CPCM0eventinput/comparematch(bits4and5)andCPCM1eventinput/comparematch
(bits 6 and 7).
IP1 can be read or written by the program. However, if writing to bits 0 through 3, always
write those bits as "0". If read, a value of "0" will always be obtained for bits 0 through 3.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP1 becomes 00H.
Figure 17-16 shows the configuration of IP1.
7
6
5
4
3
"0"
0
2
"0"
0
1
"0"
0
0
"0"
0
Address: 0039 [H]
R/W access: R/W
IP1
At reset
P1CPCM1P0CPCM1P1CPCM0 P0CPCM0
0
0
0
0
CPCM0
CPCM0 capture input /compare
match interrupt priority
P1 P0
Level 0
0
0
1
0
1
*
Level 1
Level 2
CPCM1
P1 P0
CPCM1 capture input /compare
match interrupt priority
Level 0
Level 1
Level 2
0
0
1
0
1
*
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
"*" indicates a "0" or "1".
Figure 17-16 IP1 Configuration
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(3) Interrupt priority control register 2 (IP2)
Interrupt priority control register 2 (IP2) consists of 8 bits and specifies interrupt priority for
overflowoftimer0(bits0and1), externalinterrupts1(bits2and3), externalinterrupt2(bits
4 and 5) and external interrupt 3 (bits 6 and 7).
IP2 can be read or written by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP2 becomes 00H.
Figure 17-17 shows the configuration of IP2.
7
6
5
4
3
2
1
0
Address: 003A [H]
R/W access: R/W
P1INT3 P0INT3 P1INT2 P0INT2 P1INT1 P0INT1 P1TM0OV P0TM0OV
IP2
At reset
0
0
0
0
0
0
0
0
TM0OV
Timer 0 overflow interrupt priority
P1 P0
0
0
1
0
1
*
Level 0
Level 1
Level 2
INT1
External interrupt 1 priority
P1 P0
0
0
1
0
1
*
Level 0
Level 1
Level 2
INT2
External interrupt 2 priority
P1 P0
0
0
1
0
1
*
Level 0
Level 1
Level 2
INT3
External interrupt 3 priority
P1 P0
0
0
1
0
1
*
Level 0
Level 1
Level 2
"*" indicates a "0" or "1".
Figure 17-17 IP2 Configuration
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Chapter 17 Interrupt Processing Functions
(4) Interrupt priority control register 3 (IP3)
Interrupt priority control register 3 (IP3) consists of 6 bits and specifies interrupt priority for
overflow of timers 1 to 3 (bits 0 to 5).
IP3 can be read or written by the program. However, if writing to bits 6 and 7, always write
those bits as "0". If read, a value of "0" will always be obtained for bits 6 and 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP3 becomes 00H.
Figure 17-18 shows the configuration of IP3.
7
"0"
0
6
5
4
3
2
1
0
Address: 003B [H]
R/W access: R/W
IP3
At reset
"0" P1TM3OV P0TM3OV P1TM2OV P0TM2OV P1TM1OV P0TM1OV
0
0
0
0
0
0
0
TM1OV
Timer 1 overflow interrupt priority
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
TM2OV
P1 P0
Timer 2 overflow interrupt priority
Level 0
Level 1
Level 2
0
0
1
0
1
*
TM3OV
P1 P0
Timer 3 overflow interrupt priority
Level 0
Level 1
Level 2
0
0
1
0
1
*
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
"*" indicates a "0" or "1".
Figure 17-18 IP3 Configuration
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(5) Interrupt priority control register 4 (IP4)
Interrupt priority control register 4 (IP4) consists of 8 bits and specifies interrupt priority for
external interrupt 4 (bits 0 and 1), external interrupt 5 (bits 2 and 3), external interrupt 6 (bits
4 and 5) and external interrupt 7 (bits 6 and 7).
IP4 can be read or written by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP4 becomes 00H.
Figure 17-19 shows the configuration of IP4.
7
6
5
4
3
2
1
0
Address: 003C [H]
R/W access: R/W
IP4
At reset
P1INT7 P0INT7 P1INT6 P0INT6 P1INT5 P0INT5 P1INT4 P0INT4
0
0
0
0
0
0
0
0
INT4
External interrupt 4 priority
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
INT5
External interrupt 5 priority
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
INT6
External interrupt 6 priority
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
INT7
External interrupt 7 priority
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
"*" indicates a "0" or "1".
Figure 17-19 IP4 Configuration
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(6) Interrupt priority control register 5 (IP5)
Interrupt priority control register 5 (IP5) consists of 4 bits and specifies interrupt priority for
overflow of timer 4 (bits 4 and 5) and SIO1 transmit buffer empty/transmit complete/receive
complete (bits 6 and 7).
IP5 can be read or written by the program. However, if writing to bits 0 through 3, always
write those bits as "0". If read, a value of "0" will always be obtained for bits 0 through 3.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP5 becomes 00H.
Figure 17-20 shows the configuration of IP5.
7
6
5
4
3
"0"
0
2
"0"
0
1
"0"
0
0
"0"
0
Address: 003D [H]
R/W access: R/W
IP5
At reset
P1SIO1 P0SIO1 P1TM4OV P0TM4OV
0
0
0
0
TM4OV
Timer 4 overflow interrupt priority
P1 P0
0
0
1
0
1
*
Level 0
Level 1
Level 2
SIO1 transmit buffer
empty/transmit complete, receive
complete interrupt priority
SIO1
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
"*" indicates a "0" or "1."
Figure 17-20 IP5 Configuration
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(7) Interrupt priority control register 6 (IP6)
Interrupt priority control register 6 (IP6) consists of 8 bits and specifies interrupt priority for
overflow of timer 5 (bits 0 and 1), SIO6 transmit buffer empty/transmit coplete/receive
complete (bits 4 and 5) and SIO5 and SIO4 transmit-receive completion (bits 2, 3, 6 and 7).
IP6 can be read or written by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP6 becomes 00H.
Figure 17-21 shows the configuration of IP6.
7
6
5
4
3
2
1
0
Address: 003E [H]
R/W access: R/W
IP6
At reset
P1SIO4 P0SIO4 P1SIO6 P0SIO6 P1SIO5 P0SIO5 P1TM5OV P0TM5OV
0
0
0
0
0
0
0
0
TM5OV
Timer 5 overflow interrupt priority
P1 P0
Level 0
0
0
1
0
1
*
Level 1
Level 2
SIO5
SIO5 transmit-receive
complete interrupt priority
P1 P0
Level 0
0
0
1
0
1
*
Level 1
Level 2
SIO6
SIO6 transmit-receive
complete interrupt priority
P1 P0
Level 0
0
0
1
0
1
*
Level 1
Level 2
SIO4
SIO4 transmit-receive
complete interrupt priority
P1 P0
Level 0
0
0
1
0
1
*
Level 1
Level 2
"*" indicates a "0" or "1."
Figure 17-21 IP6 Configuration
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Chapter 17 Interrupt Processing Functions
(8) Interrupt priority control register 7 (IP7)
Interrupt priority control register 7 (IP7) consists of 6 bits and specifies interrupt priority for
overflow of timer 6 (bits 0 and 1), A/D conversion scan channel cycle complete/select mode
complete (bits 2 and 3), and real-time counter output (bits 6 and 7).
IP7 can be read or written by the program. However, if writing to bits 4 and 5, always write
those bits as "0". If read, a value of "0" will always be obtained for bits 4 and 5.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP7 becomes 00H.
Figure 17-22 shows the configuration of IP7.
7
6
5
"0"
0
4
"0"
0
3
2
1
0
Address: 003F [H]
R/W access: R/W
IP7
At reset
P1RTC P0RTC
P1AD P0AD P1TM6OV P0TM6OV
0
0
0
0
0
0
TM6OV
Timer 6 overflow interrupt priority
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
A/D conversion scan channel
cycle complete /select mode
complete interrupt priority
AD
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
RTC
Real-time counter
output interrupt priority
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
"*" indicates a "0" or "1."
Figure 17-22 IP7 Configuration
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Chapter 17 Interrupt Processing Functions
(9) Interrupt priority control register 8 (IP8)
Interrupt priority control register 8 (IP8) consists of 8 bits and specifies interrupt priority for
overflow of PWC0/matching of PWC0 and PWR0 (bits 0 and 1), overflow of PWC1/
matching of PWC1 and PWR1 (bits 2 and 3), matching of PWC0 and PWR2 (bits 4 and 5)
and matching of PWC1 and PWR3 (bits 6 and 7).
IP8 can be read or written by the program.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP8 becomes 00H.
Figure 17-23 shows the configuration of IP8.
7
6
5
4
3
2
1
0
Address: 005E [H]
R/W access: R/W
IP8
At reset
P1PWM3 P0PWM3 P1PWM2 P0PWM2 P1PWM1 P0PWM1 P1PWM0 P0PWM0
0
0
0
0
0
0
0
0
PWM0
PWC0 overflow/PWC0 and PWR0
matching interrupt priority
P1 P0
Level 0
0
0
1
0
1
*
Level 1
Level 2
PWM1
P1 P0
PWC1 overflow/PWC1 and PWR1
matching interrupt priority
Level 0
Level 1
Level 2
0
0
1
0
1
*
PWM2
P1 P0
PWC0 and PWR2 matching
interrupt priority
Level 0
Level 1
Level 2
0
0
1
0
1
*
PWM3
P1 P0
PWC1 and PWR3 matching
interrupt priority
0
0
1
0
1
*
Level 0
Level 1
Level 2
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
"*" indicates a "0" or "1".
Figure 17-23 IP8 Configuration
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Chapter 17 Interrupt Processing Functions
(10) Interrupt priority control register 9 (IP9)
Interrupt priority control register 9 (IP9) consists of 2 bits and specifies interrupt priority for
the overflow of timer 9 (bits 0 and 1).
IP9 can be read or written by the program. However, writes to bits 2 through 7 are invalid.
If read, a value of "1" will always be obtained for bits 2 through 7.
When reset (RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), IP9 becomes FCH.
Figure 17-24 shows the configuration of IP9.
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
0
Address: 005F [H]
R/W access: R/W
IP9
At reset
P1TM9OV P0TM9OV
0
0
TM9OV
Timer 9 overflow interrupt priority
P1 P0
Level 0
Level 1
Level 2
0
0
1
0
1
*
"—" indicates a nonexistent bit.
When read, its value will be "1".
"*" indicates a "0" or "1".
Figure 17-24 IP9 Configuration
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Chapter 17 Interrupt Processing Functions
17-32
Chapter 18
Bus Port Functions
18
MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
18 Bus Port Functions
18.1 Overview
The MSM66577 family can externally expand program memory (usually ROM) up to a
maximum of 1MB and data memory (usually RAM) up to a maximum of 1MB. With the
SELMBUS pin setting, a multiplexed bus type (address/data time division) or a separate
bustype(independentaddress/databuses)canbeselectedforthebusportinterfaceofthe
MSM66577 family.
Bus ports (A0 to A19, D0 to D7) and control signals (SELMBUS, ALE, PSEN, RD, WR) are
used to access the external program memory and external data memory.
WhentheSELMBUSpinisatahighlevel, busportsareconfiguredastheseparatebuswith
20 address (A0 to A19) lines and 8 data (D0 and D7) lines and assigned as the secondary
functions of port 0 (P0), port 1 (P1), port 2 (P2) and port 4 (P4). Unnecessary upper
addresses can be reset as normal I/O ports.
PSEN (P3_1) is used as a strobe signal to read the external program memory. RD (P3_2)
and WR (P3_3) are used as read and write strobes for external data memory.
When the SELMBUS pin is at a low level, bus ports are configured as the multiplexed bus
with 12 address (A8 to A19) lines and 8 address/data combined lines (D0 to D7) and
assigned as the secondary functions of port 0 (P0), port 1 (P1), and port 2 (P2).
Unnecessary upper addresses can be reset as normal I/O ports.
18.2 Port Operation
18.2.1 Port Operation When Accessing Program Memory
• Separate bus type (the SELMBUS pin at a high level)
When accessing internal program memory (addresses 0H to 1FFFFH with the EA pin at a
high level), P0, P1, P2, P3_1 and P4 operate as I/O ports.
When accessing external program memory (the EA pin at a low level or addresses 20000H
to FFFFFH with the EA pin at a high level), P0 operates as the program data input port, P1,
P2, and P4 operate as address output ports, and P3_1 operates as the PSEN output port.
If the EA pin is at a low level, P0, P1, P2, P3_1 and P4 are automatically switched
(secondary function control registers and mode registers are set) to bus port and control
signal functions (hereafter referred to as bus port functions) when reset (RES signal input,
execution of a BRK instruction, overflow of the watchdog timer, opcode trap). If the EA pin
is at a high level, bus port functions are not automatically switched. It is necessary to switch
to bus port functions before external program memory is accessed by setting secondary
function control registers and mode registers on software.
18
Of theportsthat areautomaticallyset asbusport functionswhenthe EA pinisat alowlevel,
if upper address or other output is unnecessary, then after reset, those ports can be
operated as I/O ports by resetting their secondary function control register.
Table 18-1 lists the operation of P0, P1, P2, P3_1 and P4 in the separate bus type during
a program memory access.
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Table 18-1 P0, P1, P2, P3_1 and P4 Operation During Program Memory Access
(Separate Bus Type)
Memory to be
accessed
P1, P2, P4
operation
Address
P0 operation
P3_1 operation
When EA = H,
Internal program
I/O port
0H to 1FFFFH
After set as
secondary
After set as
secondary
After set as
secondary
When EA = H,
function output,
program data input
function output,
address output
function output,
PSEN output
20000H to FFFFFH
External program
When EA = L,
Program data input Address output
PSEN output
0H to FFFFFH
• Multiplexed bus type (the SELMBUS pin at a low level)
When accessing internal program memory (addresses 0H to 1FFFFH with the EA pin at a
high level), P0, P1, P2, P3_1 and P4 operate as I/O ports.
When accessing external program memory (the EA pin at a low level or addresses 20000H
to FFFFFH with the EA pin at a high level), P0 operates as the address output and program
data input port, P1 and P2 operate as addresses output ports, P3_0 operates as the ALE
output port, and P3_1 operates as the PSEN output port.
If the EA pin is at a low level, P0, P1, P2, P3_0 and P3_1 are automatically switched
(secondary function control registers and mode registers are set) to bus port and control
signal functions (hereafter referred to as bus port functions) when reset (RES signal input,
execution of a BRK instruction, overflow of the watchdog timer, opcode trap). If the EA pin
is at a high level, bus port functions are not automatically switched. It is necessary to switch
to bus port functions before external program memory is accessed by setting secondary
function control registers and mode registers on software.
Of theportsthat areautomaticallyset asbusport functionswhenthe EA pinisat alowlevel,
if upper address or other output is unnecessary, then after reset, those ports can be
operated as normal I/O ports by resetting their secondary function control register.
Table 18-2 lists the operation of P0, P1, P2, P3_0 and P3_1 in the multiplexed bus type
during a program memory access.
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Chapter 18 Bus Port Functions
Table 18-2 P0, P1, P2, P3_0 and P3_1 Operation During Program Memory Access
(Multiplexed Bus Type)
Memory to be
accessed
P1, P2, P4
operation
P3_1
P3_0
Address
P0 operation
operation
operation
When EA = H,
Internal program
I/O port
0H to 1FFFFH
After set as
secondary
function
After set as
secondary
function,
address
After set as
secondary
function
After set as
secondary
function
output,
output, PSEN output, ALE
output output
When EA = H,
address
output
20000H to FFFFFH
External program
output/pro-
gram data
input
Address
output/pro-
gram data
input
Address
output
PSEN output ALE output
When EA = L,
0H to FFFFFH
18
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Chapter 18 Bus Port Functions
18.2.2 Port Operation When Accessing Data Memory
• Separate bus type (the SELMBUS pin at a high level)
When accessing internal data memory (addresses 0H to 11FFH), P0, P1, P2, P3_2, P3_3
and P4 operate as I/O ports.
When accessing external data memory (addresses 1200H to FFFFFH), set ports P0, P1,
P2, P3_2, P3_3 and P4 to their secondary functions so that P0 operates as a data I/O pin,
P1, P2, and P4 operate as address output pins, and P3_2 and P3_3 operate as RD andWR
output pins.
IftheEApinisatalowlevel,P0,P1,P2andP4areautomaticallysetasbusports(secondary
function control registers and mode registers are set) when reset (RES signal input,
execution of a BRK instruction, overflow of the watchdog timer, opcode trap). Because
P3_2 and P3_3 are automatically set as input ports instead of RD and WR output pins,
before external data memory is accessed, they must be set as secondary function outputs.
Of theportsthat areautomaticallyset asbusport functionswhenthe EA pinisat alowlevel,
if upper address or other output is unnecessary, then after reset, those ports can be
operated as I/O ports by resetting their secondary function control register.
Table 18-3 lists the operation of P0, P1, P2, P3_2, P3_3 and P4 in the separate bus type
during a data memory access.
Table 18-3 P0, P1, P2, P3_2, P3_3 and P4 Operation During Data Memory Access
(Separate Bus Type)
Data to be
accessed
P1, P2, P4
operation
P3_2, P3_3
operation
Address
P0 operation
Internal data
0H to 11FFH
I/O port
After set as
secondary
After set as
secondary
function output
After set as
secondary
External data
1200H to FFFFFH
*1
*1
function output
data I/O
,
,
function output,
RD and WR output
address output
*1 If the EA pin is at a low level, P0, P1, P2 and P4 are automatically set as secondary
function outputs when reset.
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Chapter 18 Bus Port Functions
• Multipexed bus type (the SELMBUS pin at a low level)
When accessing internal data memory (addresses 0H to 11FFH), P0, P1, P2, P3_0, P3_2
and P3_3 operate as I/O ports.
When accessing external data memory (addresses 1200H to FFFFFH), set ports P0, P1,
P2, P3_0, P3_2 and P3_3 to their secondary functions so that P0 operates as an address
output and data I/O pin, P1 and P2 operate as address output pins, P3_0, P3_2 and P3_3
operate as ALE, RD and WR output pins.
If the EA pin is at a low level, P0, P1 and P2 are automatically set as bus ports (secondary
function control registers and mode registers are set) when reset (RES signal input,
execution of a BRK instruction, overflow of the watchdog timer, opcode trap). Because
P3_2 and P3_3 are automatically set as input ports instead of RD and WR output pins,
before external data memory is accessed, they must be set as secondary function outputs.
Of theportsthat areautomaticallyset asbusport functionswhenthe EA pinisat alowlevel,
if upper address or other output is unnecessary, then after reset, those ports can be
operated as I/O ports by resetting their secondary function control register.
Table 18-4 lists the operation of P0, P1, P2, P3_0, P3_2 and P3_3 in the multiplexed bus
type during a data memory access.
Table 18-4 P0, P1, P2, P3_0, P3_2 and P3_3 Operation During Data Memory Access
(Multiplexed Bus Type)
Data to be
accessed
P1, P2
operation
P3_0, P3_2, P3_3
operation
Address
P0 operation
Internal data
0H to 11FFH
I/O port
After set as
secondary
After set as
secondary
function output
After set as
secondary
External data
1200H to FFFFFH
*1
*1
function output
data I/O
,
,
function output,
ALE, RD and WR
output
address output
*1 If the EA pin is at a low level, P0, P1 and P2 are automatically set as secondary function
outputs when reset.
18
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
18.3 External Memory Access
18.3.1 External Program Memory Access
• Separate bus type (the SELMBUS pin at a high level)
A program memory space of 1MB maximum (00000H to FFFFFH) can be accessed with
the 16-bit program counter (PC) and 4-bit code segment register (CSR). When the EA pin
issettoahighlevel, programaddressesfrom10000HtoFFFFFHaccessexternalprogram
memory. WhentheEA pinissettoalowlevel, programaddressesfrom00000HtoFFFFFH
access external program memory.
If the EA pin is set to a high level and external program memory is to be used from 10000H
to FFFFFH, then P0, P1, P2 and P4 must be set as secondary function outputs. In addition,
P3_1 (PSEN output) must also be set as a secondary function output.
Figure 18-1 shows an example connection of external program memory (ROM) in the
separate bus type.
External ROM
(1MB max.)
Microcontroller
D0 to D7 (P0_0 to P0_7)
O0 to O7
A0 to A19
A0 to A19 (P4_0 to P4_7,
P1_0 to P1_7,
P2_0 to P2_3)
OE
CE
(P3_1) PSEN
Figure 18-1 External ROM Connection Example (Separate Bus Type)
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Chapter 18 Bus Port Functions
• Multiplexed bus type (the SELMBUS pin at a low level)
A program memory space of 1MB maximum (00000H to FFFFFH) can be accessed with
the 16-bit program counter (PC) and 4-bit code segment register (CSR). When the EA pin
issettoahighlevel, programaddressesfrom10000HtoFFFFFHaccessexternalprogram
memory. WhentheEA pinissettoalowlevel, programaddressesfrom00000HtoFFFFFH
access external program memory.
If the EA pin is set to a high level and external program memory is to be used from 10000H
to FFFFFH, then P0, P1 and P2 must be set as secondary function outputs. In addition,
P3_0 and P3_1 (PSEN output) must also be set as a secondary function output.
Figure 18-2 shows an example connection of external program memory (ROM) in the
multiplexed bus type.
External ROM
(1MB max.)
Microcontroller
O0 to O7
Latch
circuit
AD0 to AD7 (P0_0 to P0_7)
(P3_0) ALE
A0 to A7
A8 to A19 (P1_0 to P1_7,
P2_0 to P2_3)
A8 to A19
OE
CE
(P3_1) PSEN
Figure 18-2 External ROM Connection Example (Multiplexed Bus Type)
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
18.3.2 External Data Memory Access
• Separate bus type (the SELMBUS pin at a high level)
A data memory space of 1MB maximum (0000H to FFFFFH) can be accessed with the 16-
bit RAM address pointer (RAP) and 4-bit data segment register (DSR). Data addresses
from 0000H to 11FFH access internal data memory. Data addresses from 1200H to
FFFFFH access external data memory. External data memory is accessed in 8-bit (byte)
units.
If external data memory is to be used, P0 must be set as a secondary function output
(memory data I/O). Also, corresponding to the memory address, P1, P2 and P4 must be
set as secondary function outputs (address outputs). In addition, P3_2 and P3_3 must be
set as secondary function outputs (WR and RD outputs).
If the EA pin is at a low level, P0, P1, P2 and P4 automatically become secondary function
outputs.
If necessary, insert external pull-up resistors at the WR and RD pins.
Figure 18-3 shows an example connection of external data memory (RAM) in the separate
bus type.
External RAM
(1MB max.)
Microcontroller
D0 to D7 (P0_0 to P0_7)
IO0 to IO7
A0 to A19 (P4_0 to P4_7,
P1_0 to P1_7,
A0 to A19
P2_0 to P2_3)
(P3_2) RD
(P3_3) WR
OE
WE
CE
VDD
Figure 18-3 External RAM Connection Example (Separate Bus Type)
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
• Multiplexed bus type (the SELMBUS pin at a low level)
A data memory space of 1MB maximum (0000H to FFFFFH) can be accessed with the 16-
bit RAM address pointer (RAP) and 4-bit data segment register (DSR). Data addresses
from 0000H to 11FFH access internal data memory. Data addresses from 1200H to
FFFFFH access external data memory. External data memory is accessed in 8-bit (byte)
units.
If external data memory is to be used, P0 must be set as a secondary function output
(memory data I/O). Also, corresponding to the memory address, P1 and P2 must be set
as secondary function outputs (address outputs). In addition, P3_0, P3_2 and P3_3 must
be set as secondary function outputs (WR and RD outputs).
If the EA pin is at a low level, P0, P1, P2 and P4 automatically become secondary function
outputs.
If necessary, insert external pull-up resistors at the WR and RD pins.
Figure 18-4 shows an example connection of external data memory (RAM) in the
multiplexed bus type.
External RAM
(1MB max.)
Microcontroller
IO0 to IO7
Latch
circuit
AD0 to AD7
(P0_0 to P0_7)
A0 to A7
(P3_0) ALE
A8 to A19 (P1_0 to P1_7,
P2_0 to P2_3)
A8 to A19
(P3_2)RD
(P3_3)WR
OE
WE
CE
VDD
Figure 18-4 External RAM Connection Example (Multiplexed Bus Type)
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
18.4 External Memory Access Timing
18.4.1 External Program Memory Access Timing
Figures 18-5 and 18-6 show the timing for accessing external program memory in the
separate bus type.
Figure 18-7 and 18-8 show the timing for accessing external program memory in the
multiplexed bus type.
Forexternalmemorywithslowaccesstimes,afunctionisavailabletoinsertwaitcycles(see
Section 4.4, "READY Function"). Use this function to match the access time of the external
memory to be used. The ROMRDY register specifies the number of wait cycles to insert.
For actual AC characteristics, refer to Chapter 20, "Electrical Characteristics".
CPUCLK
P3_1/PSEN
A0 to A19
(P4_0 to P4_7,
P1_0 to P1_7,
P2_0 to P2_3)
PC0 to 19
PC0 to 19
PC0 to 19
PC0 to 19
D0 to D7
(P0_0 to P0_7)
INST0 to 7
INST0 to 7
INST0 to 7
Figure 18-5 External Program Memory Access Timing (No Wait Cycles)
(Separate Bus Type)
CPUCLK
P3_1/PSEN
A0 to A19
(P4_0 to P4_7,
P1_0 to P1_7,
P2_0 to P2_3)
PC0 to 19
PC0 to 19
D0 to D7
(P0_0 to P0_7)
INST0 to 7
INST0 to 7
Wait cycles inserted as
specified by ROMRDY
Two wait cycles are inserted
in this example.
Figure 18-6 External Program Memory Access Timing (2 Wait Cycles)
(Separate Bus Type)
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Chapter 18 Bus Port Functions
CPUCLK
P3_0/ALE
P3_1/PSEN
A8 to A19
(P1_0 to P1_7,
P2_0 to P2_3)
PC8 to 19
PC8 to 19
AD0 to AD7
(P0_0 to P0_7)
PC0 to 7
INST0 to 7
PC0 to 7
INST0 to 7
Figure 18-7 External Program Memory Access Timing (No Wait Cycles)
(Multiplexed Bus Type)
CPUCLK
P3_0/ALE
P3_1/PSEN
A8 to A19
(P1_0 to P1_7,
P2_0 to P2_3)
PC8 to 19
PC8 to 19
PC0 to 7
D0 to D7
(P0_0 to P0_7)
PC0 to 7
INST0 to 7
Wait cycles inserted as
specified by ROMRDY
Two wait cycles are inserted
in this example.
Figure 18-8 External Program Memory Access Timing (2 Wait Cycles)
(Multiplexed Bus Type)
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
18.4.2 External Data Memory Access Timing
Figures 18-9 and 18-10 show the timing for accessing data program memory in the
separate bus type.
Forexternalmemorywithslowaccesstimes,afunctionisavailabletoinsertwaitcycles(see
section 4.4, "Ready Function"). Use this function to match the access time of the external
memory to be used. Compared to internal data memory accesses, when accessing
external data memory, 2 or 3 wait cycles are automatically inserted for each 1 byte access.
The RAMRDY register specifies the number of wait cycles to insert in addition to the 3 to
4 cycles that are automatically inserted.
For actual AC characteristics, refer to Chapter 20, "Electrical Characteristics".
CPUCLK
P3_2/RD
A0 to A19
(P4_0 to P4_7,
RAP0 to 19
Din 0 to 7
RAP0 to 19
Din 0 to 7
P1_0 to P1_7,
P2_0 to P2_3)
D0 to D7
(P0_0 to P0_7)
P3_3/WR
A0 to A19
(P4_0 to P4_7,
P1_0 to P1_7,
P2_0 to P2_3)
RAP0 to 19
Dout 0 to 7
RAP0 to 19
D0 to D7
(P0_0 to P0_7)
Dout 0 to 7
Figure 18-9 External Data Memory Access Timing (Word Access: No Wait Cycles)
(Separate Bus Type)
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
CPUCLK
P3_2/RD
A0 to A19
(P4_0 to P4_7,
P1_0 to P1_7,
P2_0 to P2_3)
RAP0 to 19
D0 to D7
(P0_0 to P0_7)
Din 0 to 7
P3_3/WR
A0 to A19
(P4_0 to P4_7,
P1_0 to P1_7,
P2_0 to P2_3)
RAP0 to 19
D0 to D7
(P0_0 to P0_7)
Dout 0 to 7
Wait cycles inserted as
specified by RAMRDY
Two wait cycles are inserted
in this example.
Figure 18-10 External Data Memory Access Timing (Byte Access: 2 Wait Cycles)
(Separate Bus Type)
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
CPUCLK
P3_0/ALE
P3_2/RD
A8 to A19
(P1_0 to P1_7,
P2_0 to P2_3)
RAP8 to 19
RAP8 to 19
AD0 to AD7
RAP0 to 7
RAP0 to 7
Din 0 to 7
Din 0 to 7
(P0_0 to P0_7)
P3_3/WR
A8 to A19
(P1_0 to P1_7,
P2_0 to P2_3)
RAP8 to 19
RAP8 to 19
AD0 to AD7
(P0_0 to P0_7)
Dout 0 to 7
RAP0 to 7
RAP0 to 7
Dout 0 to 7
Figure 18-11 External Data Memory Access Timing (Word Access: No Wait Cycles)
(Multiplexed Bus Type)
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
CPUCLK
P3_0/ALE
P3_2/RD
A8 to A19
(P1_0 to P1_7,
P2_0 to P2_3)
RAP8 to 19
AD0 to AD7
(P0_0 to P0_7)
RAP0 to 7
Din 0 to 7
P3_3/WR
A8 to A19
(P1_0 to P1_7,
P2_0 to P2_3)
RAP8 to 19
D0 to D7
(P0_0 to P0_7)
RAP0 to 7
Dout 0 to 7
Wait cycles inserted as
specified by RAMRDY
Two wait cycles are inserted
in this example.
Figure 18-12 External Data Memory Access Timing (Byte Access: 2 Wait Cycles)
(Multiplexed Bus Type)
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
18.5 Notes Regarding Usage of Bus Port Function
18.5.1 Dummy Read Strobe Output
The MSM66577 family of microcontrollers utilize the nX-8/500S, Oki’s proprietary 16-bit
CPU core.
The instruction code of the nX-8/500S uses 8 bits as its basic unit and consists of 1 to 6
bytes. Instructions are classified as NATIVE instructions for commonly performed
operations or as COMPOSIT instructions to realize a wide range of addressing. NATIVE
instructions consist of 1 to 4 bytes and are used to achieve high coding and processing
efficiency.
COMPOSIT instructions consist of a 1 to 3 byte address field (PREFIX) and a 1 to 3 byte
operation field (SUFFIX). The PREFIX and SUFFIX are combined to realize a wide range
of addressing.
If instructions accompanying a write to external data memory are to be executed, an
unnecessary RD signal (dummy RD) will be output before the actual access (WR signal) if
some of those instructions are COMPOSIT instructions, (This is limited to cases where the
PREFIX specifies an external data memory area.) For byte and bit accesses, a dummy RD
signal is output once. For word accesses, a dummy RD signal is output twice.
Some considerations must be exercised in cases where the above mentioned read strobe
affects the internal operation of peripheral devices.
Using the bus port function, the specific example of connecting and accessing the 8251
serial interface LSI chip as a peripheral device will be described.
[Example]
Whenthemicrocomputerwritestothetransmitbufferofthe8251,ifCOMPOSITinstructions
are used with the above conditions, output of the dummy read strobe will cause data in the
receive buffer to be read. If receive data exists in the receive buffer, the 8251 will determine
that the CPU has finished reading data, and the receive ready output signal will be reset.
Some considerations must be exercised in cases where peripheral devices operate
differently when read and write operations are performed at the same address.
These types of problems can be avoided by using NATIVE instructions.
For example, a dummy strobe is not output if load and store instructions (L, LB, ST, STB)
are used to read from and write to the accumulator (ACC). (If programming in C language,
these sections can be written as assembler functions.)
If general-purpose memory (RAM or ROM) is connected to a bus port, the problems
described above should not occur. Problems only occur if a connected peripheral device
(functional device) is accessed using COMPOSIT instructions as described above and the
read strobe affects the internal operation of the peripheral device.
Connect peripheral devices to bus ports based on an understanding of the operation
described herein and the function and operation of peripheral devices.
Tables 18-5 and 18-6 list PREFIX and SUFFIX combinations (instructions) that output a
dummy RD when an external data memory area is accessed.
In the tables, PREFIX addressing is inserted at the "*" in the SUFFIX column.
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
Table 18-5 Instructions (Byte/Bit Manipulations) in Which a Dummy RD Occurs Once
(PREFIX and SUFFIX Combinations)
SUFFIX
PREFIX
*
Instruction symbol Instruction code
Instruction code
SB
*
*
08+bit
00+bit
B8
Rn
68+n
B0
B2
B1
B3
B5
B7
B8
B9
9B
9B
BA
BB
RB
[X1]
SBR
RBR
TBR
*
*
*
[DP]
B9
[DP–]
[DP+]
off
CA
MB *.bit, C
MBR *.bit, C
MBR C, *.bit
MOVB *,A
18+bit
BB
dir
BA
N16[X1]
N16[X2]
n7[DP]
n7[USP]
[X1+A]
[X1+R0]
AA
MOVB *,#N8
AB
CLRB
FILLB
*
*
C7
D7
Table 18-6 Instructions (Word Manipulations) in Which a Dummy RD Occurs Twice
(PREFIX and SUFFIX Combinations)
SUFFIX
PREFIX
*
Instruction symbol Instruction code
Instruction code
MOV *,A
AA
AB
C7
D7
ERn
64+n
A0
A2
A1
A3
A5
A7
A8
A9
8B
8B
AA
AB
MOV *,#N16
[X1]
CLR
FILL
*
*
[DP]
[DP–]
[DP+]
off
dir
N16[X1]
N16[X2]
n7[DP]
n7[USP]
[X1+A]
[X1+R0]
18
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MSM66577 Family User's Manual
Chapter 18 Bus Port Functions
18.5.2 External Bus Access Timing
The MSM66577 family employs a high-speed separate address and data bus type for
external bussing.
IftheMSM66577familyrunsathighspeed, thereadandwritestrobesignalsmaybeintheir
logically active states before the address outputs are changed and then set up. Care must
betakenforACcharacteristicswhenperipheraldevices, suchasgeneral-purposeSRAMs,
whose address outputs have to be set up on the rising edge of the WR signal are connected
using the bus port function.
Refer to the AC characteristics (Chapter 20, "Electrical Characteristics") for operating
frequencies to be used.
The AC characteristic values are given under the conditions listed below:
• Load capacitor C = 50 pF
L
• Measurement point for AC timing
V
V
/V = 0.8 V/2.0 V for V = 4.5 to 5.5 V
OL OH
DD
/V = 0.16V /0.44V for V = 2.4 to 3.6 V
OL OH
DD
DD
DD
• Ambient temperature Ta = –30 to +70˚C
• Power supply voltage V = 2.4 to 3.6 V/4.5 to 5.5 V
DD
In order to set up the address value before the WR signal is made to its logically active state
under the above conditions, either of the following operating frequencies should be
provided:
• f = 11 MHz or less for V = 2.4 to 3.6 V
DD
• f = 20 MHz or less for V = 4.5 to 5.5 V
DD
The upper limits of operating frequencies will actually be varied according to conditions
(load capacitance and supply voltages on the printed circuit boards) of products to which
the MSM66577 family is to be applied.
The contents described above should be considered to connect the peripheral devices,
such as general-purpose SRAMs.
18-18
Chapter 19
Flash Memory
19
MSM66577 Family User's Manual
Chapter 19 Flash Memory
19. Flash Memory
19.1 Overview
TheMSM66577familyprovidesaflashROMversion, whichisequippedwithanelectrically
programmable non-volatile memory (flash memory) as the internal program memory. With
three types of flash memory programming modes, the flash ROM version can be
programmed even after being installed in a system.
There are two types of flash ROM version: the MSM66Q577 operates in the range of 4.5
to 5.5 V and the MSM66Q577LY operates in the range of 3.0 to 3.6 V. Select the device
that matches the voltage range to be used.
19.2 Features
l
Power supply voltage
MSM66Q577 (4.5 to 5.5 V operation)
…
…
Can be programmed with a single 4.5 to
5.5 V power supply
MSM66Q577LY (3.0 to 3.6 V operation)
Can be programmed with a single 3.0 to
3.6 V power supply
l
Programming modes
Flash memory has the following three programming modes.
· Parallel mode
…
Can be programmed with a PROM writer of MINATO
ELECTRONICS make
· Serial mode
· User mode
…
…
Can be programmed with a flash memory writer
Can be programmed by program execution.
l
l
Programming blocks
Flash memory is programmed in blocks of 128-byte units.
Auto-erase function
Since an auto-erase function is provided to automatically erase the block to be written to
prior to programming, it is unnecessary to erase flash memory before programming.
l
l
Programming Time
Programming time for the flash memory is listed below.
· Programming (128 byte unit) … Approx. 40 ms (at 4.5 to 5.5 V)
Approx. 50 ms (at 3.0 to 3.6 V)
Write protect function
Flash memory has a built-in power-on write protect function that automatically disables
programming for approximately 20 ms after power is turned on.
Inaddition, thereisanacceptorfunctiontopreventincorrectprogrammingintheusermode
due to a running of out-of-control program.
19
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
l
Security function
Flash memory has a built-in security function that disables reading of contents of memory
externally and / or programming externally. The security function is set in the serial mode,
but once the security function is set, contents of memory cannot be externally read from or
programming cannot be performed externally, in any programming mode.
The security function cannot be set in the parallel mode or in the user mode.
19.3 Programming Modes
Flash memory has the following three programming modes. Since an auto-erase function
is provided for all the programming modes, it is not necessary to erase the flash memory
prior to programming.
Figure 19-1 shows a block diagram of the flash memory programming modes.
(1) Parallel mode
Programming in this mode is performed with a PROM writer of MINATO ELECTRONICS
make. A special program to write to flash memory is unnecessary.
In the parallel mode, connect Oki Electrics’ flash memory program conversion adapter
(modelno. MTP66573)toaROMwriterwithmodelno. 1893(version1.20dorlater)or1931
(version 1.20d or later) manufactured by MINATO ELECTRONICS, Inc. and then perform
the programming.
(2) Serial mode
Programming in this mode is performed with a flash memory writer. A special program to
write to flash memory is unnecessary. Flash memory can be programmed by a single
microcontroller or after it is mounted on a printed circuit board.
In the serial mode, connect a flash memory writer (model no. PW66K) or a flash
microcontroller programmer (model no. AF200) manufactured by YDC Corporation to the
twomicrocontrollerpins(P9_2,P9_3),theEApin,andV andGNDpins,andthenperform
DD
the programming. Programming is performed while the microcontroller is in the reset or
STOP modes.
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
(3) User mode
In this mode, instead of using a programming writer, programming is performed by
executing a program that writes to flash memory. Programming can be performed after the
device is mounted on the circuit board.
In the user mode, programming is performed by executing a write program already stored
(using either the serial mode or parallel mode) in flash memory of the microcontroller.
Flash memory
PROM writer
Parallel
interface
(1) Parallel
mode
program conversion
adapter
of MINATO*1
make
MTP66573
PW66K or flash
microcontroller
programmer
AF200*2 of
Memory
control
circuit
Flash
memory
(2) Serial
mode
Serial
interface
YDC*3 make
Writer is
unnecessary.
(Memory is
programmed
by execution of
write program.)
(3) User
mode
CPU
interface
Peripherals
CPU
Flash ROM version
*1: MINATO is MINATO ELECTRONICS, Inc.
*2: AF200 is a trademark of YDC Corporation
*3: YDC is YDC Corporation
Figure 19-1 Block Diagram of Programming Modes
19
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
19.4 Parallel Mode
19.4.1 Overview of the Parallel Mode
Programming in the parallel mode is performed with a PROM writer with model no. 1893
(version 1.20d or later) or 1931 (version 1.20d or later) manufactured by MINATO
ELECTRONICS, Inc. The writing and reading of programs is performed by connecting Oki
Electric’s flash memory program conversion adapter (MTP66573) to a PROM writer.
Figure 19-2 shows a connection diagram. Since an auto-erase function is provided, flash
memory does not have to be erased prior to programming.
[Note] The security function cannot be set in the parallel mode.
19.4.2 PROM Writer Setting
For the details of PROM writer settings, refer to the manual of the PROM writer used.
When writing data, be sure to use the device code "MSM66Q577," which has been
registeredexclusivelyfortheMSM66Q577, or"MSM66Q577L,"whichhasbeenregistered
exclusivelyfortheMSM66Q577L. Inaddition, neverusetheSiliconSignaturemode, which
automaticallysetsadevicecodewhenanLSIisinserted. RefertothePROMwritermanual
for details.
19.4.3 Flash Memory Programming Conversion Adapter
Use Oki Electric’s flash memory program conversion adapter (MTP66573).
Flash ROM version
PROM writer of MINATO ELECTRONICS make
pin 1
MTP66573
Figure 19-2 Parallel Mode Connection Diagram
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
19.5 Serial Mode
19.5.1 Overview of the Serial Mode
Programming in the serial mode is performed with a flash memory writer. Programs can
be written or read by a single microcontroller or after it is mounted on a printed circuit board.
Intheserialmode, thewritingandreadingofprogramsisperformedbyconnectingtheflash
memory writer PW66K or YDC Corporation's flash microcontroller programmer AF200 to
thetwomicrocontrollerpins(P9_2,P9_3),theEApin,andV andGNDpins. Programming
DD
and reading are performed while the microcontroller is in the reset or STOP mode. Since
an auto-erase function is provided, flash memory does not have to be erased prior to
programming.
19.5.2 Serial Mode Settings
The serial mode is set automatically by connecting the flash microcontroller programmer
to the specific pins and then executing a programming or read operation. When writing or
reading is complete, the serial mode setting is released.
(1) Pins used in serial mode
Table 19-1 lists the pins used in the serial mode.
The serial mode can only be set while the microcontroller is in reset or STOP mode. Be
careful of the high voltage (approx. 9 V) that the flash microcontroller programmer applies
to the EA pin to set the serial mode. V is connected to monitor V of the user system.
DD
DD
Table 19-1 List of Pins Used in Serial Mode
Pin name
Flash memory function
FLACK (serial clock input)
FLADAT (serial data I/O)
P9_2
P9_3
EA
FLAMOD (high voltage input to set serial mode)
User system VDD monitor
Ground
VDD
GND
[Note]
During the serial mode, the voltage higher than the power supply (approx. 9 V) is
applied to the EA pin by the flash microcontroller programmer.
19
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
(2) Serial mode connection circuit
Intheserialmode,theflashmemorywriter(PW66K)ortheflashmicrocontrollerprogrammer
(AF200) must be connected to the P9_2, P9_3, EA, V and GND pins of the flash ROM
DD
version in the user system. In addition, install a switch in the user system to cut off the user
system during programming and reading in the serial mode.
Figure 19-3 shows serial mode connection circuit example 1.
Switch
Flash ROM version
(FLACLK) P9_2
(FLADAT) P9_3
(FLAMOD) EA
*RES
To user system
VDD
GND
* Connect in the case of resetting
and programming/reading on the
flash microcontroller programmer.
To flash microcontroller programmer
Figure 19-3 Serial Mode Connection Circuit Example 1
19-6
MSM66577 Family User's Manual
Chapter 19 Flash Memory
If not possible to install a switch in the user system, do not use pins P9_2 and P9_3 with
the user system and connect them only to the flash microcontroller programmer. Also,
connect each of the P9_2, P9_3 and EA pins through a resistor of approximately 100 kW
to V
.
DD
Figure 19-4 shows serial mode connection circuit example 2.
[Note]
The programming and reading in the serial mode are performed while the microcontroller
is in the reset or STOP mode. To execute the programming/reading during reset, apply
"L" level to the RES pin. In the case where the flash microcontroller programmer does not
apply "L" level to the RES pin, the "L" level should be applied by the user application
system.
Flash ROM version
Approx. 100 kW
(FLACLK) P9_2
(FLADAT) P9_3
(FLAMOD) EA
RES
VDD
To user application
system
GND
To flash microcontroller programmer
Figure 19-4 Serial Mode Connection Circuit Example 2
19
19-7
MSM66577 Family User's Manual
Chapter 19 Flash Memory
(3) Serial mode programming method
Programmingintheserialmodeisperformedwiththeuseofaflashmemorywriter(PW66K)
or a flash microcontroller programmer (AF200).
The procedure for programming with the flash microcontroller programmer is listed below.
Refer to the PW66K and AF200 User’s Manuals for details of the flash microcontroller
programmer.
1)ConnecttheflashmicrocontrollerprogrammertotheP9_2, P9_3, EA, V andGNDpins
DD
of the flash ROM version.
2) Set the microcontroller to the reset or STOP mode.
· The flash microcontroller will generate a protocol error if other than reset or STOP mode
is set.
3) Perform the programming or read operation with the flash microcontroller programmer.
· The serial mode is set automatically.
4) Verify that operation of the flash microcontroller programmer has been completed
correctly.
· The serial mode is released automatically.
5) Release reset or the STOP mode.
· The microcontroller runs the program that has been written.
(4) Setting of security function
The security function can be set or reset in the serial mode. For the setting method, refer
to the User's Manual for the flash microcontroller programmer.
When the security function is set, the flash memory outputs 0s, for external reading,
throughout its entire area and programming are disabled, in all programming modes.
(5) Notes on use of serial mode
If programming is performed during the STOP mode, while programming is in progress, do
not generate an interrupt or a reset via the RES pin input. If generated, the CPU may run
out of control after the serial mode is released. During the STOP mode, execution of BRK
instructions, overflow of the watchdog timer, and opcode traps will not generate reset. If
an interrupt or reset is generated, reprogram the entire flash memory area.
In addition, when programming in the serial mode is performed during the STOP mode, do
not allow external interrupts 6 and 7 to be generated (set EXINT 6 and 7 valid edges of
EXI1CON to interrupt input invalid).
19-8
MSM66577 Family User's Manual
Chapter 19 Flash Memory
19.6 User Mode
19.6.1 Overview of the User Mode
Instead of using a programming writer, programming in the user mode is performed by
executing a program on the user's system to write to flash memory. Programming can be
performed even after the microcontroller is mounted on a circuit board in the user’s system.
Since an auto-erase function is provided, flash memory does not have to be erased prior
to programming.
The user mode executes a program to write to flash memory. The program is prepared to
contain commands to execute the write operation and the I/O method of data to be written.
Theprogrammustbewritten(usingeithertheserialmodeorparallelmode)toflashmemory
in advance.
Figure 19-5 shows a block diagram of the user mode.
[Note]
The security function cannot be set in the user mode.
CPU
CPU
128KB
flash
memory
interface
control
circuit
4KB RAM
Peripheral
Data I/O
(can be set
by program)
300H to 37FH
Flash ROM version
Figure 19-5 User Mode Block Diagram
19
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
19.6.2 User Mode Programming Registers
The MSM66577 family has internal special function registers (SRFs) for programming with
the user mode. Programming in the user mode is performed by controlling the following
registers: the flash memory control register (FLACON), the flash memory address register
(FLAADRS) and the flash memory acceptor (FLAACP).
Table 19-2 lists a summary of the SFRs for the user mode.
Table 19-2 Summary of SFRs for User Mode
Address
[H]
Symbol
(byte)
Symbol
(word)
—
8/16
Initial
Reference
page
Name
R/W
W
Operation value [H]
00F0I Flash memory acceptor
FLAACP
8
8
"0"
C6
19-11
Flash memory control
00F1I
FLACON
—
R/W
19-12
19-11
register
00F2I Flash memory address
—
—
FLAADRS R/W
16
Undefined
register
00F3
Notes:
1. A star (I) in the address column indicates a missing bit.
2. For details, refer to Chapter 21, "Special Function Registers (SFRs)".
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
19.6.3 Description of User Mode Registers
(1) Flash memory address register (FLAADRS)
Bits 3 to 12 (FA7 to FA16) of the FLAADRS register set the flash memory address to be
programmed.
Figure 19-6 shows the configuration of FLAADRS.
15
—
1
14
—
1
13
—
1
12
11
10
9
8
7
6
5
4
3
2
—
1
1
—
1
0
—
1
FLAADRS
At reset
FA16 FA15 FA14 FA13 FA12 FA11 FA10 FA9
FA8
FA7
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Address: 00F2 [H]
R/W access: R/W
FA16 to 7
Programming address
15 14 13 12 11 10 9
8
0
0
1
7
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000H to 007FH
0080H to 00FFH
0100H to 017FH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1FE80H to 1FEFFH
1FF00H to 1FF7FH
1FF80H to 1FFFFH
"—" indicates a nonexistent bit.
When read, its value will be "1".
Figure 19-6 FLAADRS Configuration
(2) Flash memory acceptor (FLAACP)
FLAACP is an acceptor used when data is to be set in the flash memory control register.
FLAACP is set to "1" when the program writes n5H, nAH (n = 0 to F) consecutively.
Programming the flash memory resets FLAACP to "0".
Figure 19-7 shows the FLAACP configuration.
7
6
5
4
3
2
1
0
Address: 00F0 [H]
R/W access: W
FLAACP
Consecutive writing of n5H, nAH
enables writing to FLACON.
Figure 19-7 FLAACP Configuration
19
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
(3) Flash memory control register (FLACON)
FLACON is a 4-bit register that controls programming and operation of the flash memory.
Figure 19-8 shows the FLACON configuration.
7
6
5
4
3
2
1
0
Address: 00F1 [H]
R/W access: R/W
FLACON
At reset
—
—
AMPOFF FCLK1 FCLK0
—
—
PRG
1
1
0
0
0
1
1
0
0
1
Programming completed
Programming request
FCLK
Flash memory transfer clock
1/16 OSCCLK
0
0
1
*
1
0
0
1
1/8 OSCCLK
1/4 OSCCLK
"—" indicates a nonexistent bit.
When read, its value will be "1".
"*" indicates a "0" or "1".
Figure 19-8 FLACON Configuration
Writes to bits 0, 3, and 4 of FLACON are valid after consecutively writing n5H, nAH (n = 0
toF)toFLAACPsothattheflashmemoryacceptorissetto"1". FLAACPisresetto"0"after
the flash memory is programmed. To reprogram the flash memory, it is necessary to once
again set the flash memory acceptor to "1". Also, while the security is being set, it is not able
to write to bits 0, 3, and 4 of the FLACON.
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
[Description of each bit]
· PRG (bit 0)
If PRG (bit 0) of FLACON is set to "1", after the execution of one instruction, the CPU will
enter the hold state and data at internal RAM addresses 300H through 37FH will be
transferred to flash memory. Then, a flash memory block will be cleared by the auto-erase
function and the write operation performed.
After programming is completed, the hold state is released and this bit is reset to "0". Prior
to programming, set the address to be written in FLAADRS and the data to be written in
internal RAM addresses 300H to 37FH.
Notes:
· Ifaninterruptoccursduringprogrammingoftheflashmemory, processingoftheinterrupt
is suspended. The interrupt is processed after programming is completed.
· If reset is initiated by input to the RES pin during programming of the flash memory, the
reset is processed after programming is normally completed in the flash memory.
Figure 19-9 shows the relationship between internal RAM and flash memory.
Internal RAM
Flash memory
200H
0000H
300H
37FH
128 bytes
4KB RAM
128KB
flash memory
Data from internal RAM
addresses 300H to 37FH
is programmed to the address
specified by FLAADRS.
11FFH
128 bytes
0FFFFH
Figure 19-9 Relation between Internal RAM and Flash Memory
19
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
· FCLK0, FCLK1 (bits 3,4)
FCLK0 (bit 3) and FCLK1 (bit 4) of the FLACON register are bits that set the clock that
transfers data from internal RAM addresses 300H through 37FH to flash memory. At
reset, sincebothFCLK0andFCLK1become"0", 1/16CLKwillbeselectedasthetransfer
clock.
Set FCLK0 and FCKL1 such that the transfer clock frequency is 10 MHz or less for the
MSM66Q577 (4.5 to 5.5 V programming voltage) and 6.6 MHz or less for the
MSM66Q577LY (3.0 to 3.6 V programming voltage).
· AMPOFF (bit 5)
AMPOFF (bit 5) of FLACON is a bit that is provided to control the sense amplifiers of the
flash memory. However, the sense amplifiers constantly have intermittent access to the
flash memory regardless of the state of this bit, in which case the flash memory enters
the low power mode.
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
19.6.4 User Mode Programming Example
(1) User mode programming flowchart example
Figure 19-10 shows a flowchart for user mode programming of flash memory.
Since an auto-erase function is prepared, flash memory does not have to be erased prior
to programming.
Start
Set FLAADRS (FA7 to FA16) with the upper ten bits of the address
desired to write to in 128 byte units.
Set the programming address
in FLAADRS
1)
2)
3)
4)
5)
6)
7)
8)
9)
1)
2)
Using serial I/O or external memory access, set the programming
data in internal RAM addresses 300H through 37FH.
Set programming data in internal
RAM addresses 300H to 37FH
Write the consecutive values of n5H, nAH (n = 0 to F) to FLAACP to
set the flash memory acceptor to "1." Programming the flash
memory causes the flash memory acceptor to be reset to "0."
3)
4)
5)
6)
7)
8)
9)
Set the flash memory acceptor
Set the PRG flag
Set the program (PRG) flag of FLACON. Programming causes the
PRG flag to be reset to "0."
After the PRG flag is set, the CPU executes one instruction.
(Example: NOP instruction)
Execute one instruction
After the execution of one instruction, the CPU automatically enters
the hold state.
Automatically enter hold state
Programming execution
Automatically release hold state
Verify the programmed data
Programming complete
When the CPU enters the hold state, data in internal RAM addresses
300H through 37FH is transferred to the flash memory, and
programming (with the auto-erase function) is performed.
After completion of flash memory programming, the hold state is
automatically released and the CPU executes the next instruction.
Verify that data has been written to the flash memory. ROM table
reference instructions may be used to verify the data.
Note: If programming has been performed by an external program,
the programmed data cannot be verified.
Figure 19-10 Programming Flowchart Example
19
19-15
MSM66577 Family User's Manual
Chapter 19 Flash Memory
(2) User mode programming program example
Listed below is an example program that programs data to flash memory addresses 5500H
through 557FH (128 bytes) and then verifies the data of those 128 bytes.
It is assumed that the data to be programed has already been stored in internal RAM
addresses 300H through 37FH.
MOV
FLAADRS,#0550H
FLAACP,#05H
FLAACP,#0AH
FLACON,#11H
Set the start address (5500H) for programming.
MOVB
MOVB
MOVB
NOP
Set the flash memory acceptor.
Set the PRG flag.
After execution of one instruction, the hold state
is entered and programming begins. When
programming is complete, the hold state is
released.
MOV
MOV
SDD
DP,#300H
ER0,#5500H
Set the internal RAM address in DP.
Set the flash memory address in ER0.
Set the data descriptor.
LOOP:
LC
CMP
A, [ER0]
A, [DP+]
Load flash memory data into the accumulator.
Compare accumulator and internal RAM data,
then increment the internal RAM address by +2.
If they are not equal, jump to the error routine.
Increment the flash memory address by +2.
If verification of the 128 bytes is not complete,
jump to LOOP.
JC
ADDB
JBR
NE,ERR
R0,#02H
R0.7,LOOP
ERR:
Perform error processing.
Note: If programming has been performed by an external program, the programmed data
cannot be verified.
19.6.5 Notes on Use of User Mode
Note the following items when generating a program to be used with the user mode.
· Ifaninterruptoccursduringprogrammingoftheflashmemory, processingoftheinterrupt
is put on hold. The interrupt is processed after programming is completed.
· If reset is initiated by input to the RES pin during programming of the flash memory, the
reset is processed. However, the flash memory area that was in the process of being
programmed will have been incorrectly programmed. If reset is initiated during
programming, reprogram the flash memory area that was in the process of being
programmed.
· Do not program to the flash memory area that contains the programming program being
executing. (After programming is completed, the CPU program control will run out of
control.)
· Development tools (emulator) cannot evaluate programming or erasing.
19-16
MSM66577 Family User's Manual
Chapter 19 Flash Memory
19.7 Notes on Program
(1) Programming of flash memory immediately after power-on
Programming to flash memory is automatically disabled for approximately 20 ms (for both
4.5 to 5.5 V and 3.0 to 3.6 V devices) after power is turned on. Therefore, if flash memory
is to be programmed immediately after power is turned on, wait for the above time by
guaranteeing a power-on reset time.
(2) Note on STOP mode release
Flash memory requires a standby time of at least 50 ms when the STOP mode is released.
Therefore, set the standby control register (SBYCON) to guarantee the stabilization time
for main clock (OSCCLK) oscillation when the STOP is released.
(3) Supply voltage sense reset function
If the internal ROM (high level input to the EA pin) of the MSM66Q577LY/MSM66Q577 is
operative, the reset function is implemented at a supply voltage of 3 V or less for the
MSM66Q577 (the version operating in the range of 4.5 to 5.5 V) and at a supply voltage of
1.5 V or less for the MSM66Q577LY (the version operating in the range of 3.0 to 3.6 V).
Programming is automatically disabled for approximately 20 ms after the reset function is
implemented. Also, the reset function is not implemented during the STOP mode (only
when oscillation of the main clock is terminated).
19
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MSM66577 Family User's Manual
Chapter 19 Flash Memory
19-18
Chapter 20
Electrical Characteristics
20
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
20. Electrical Characteristics
20.1 Absolute Maximum Ratings
Parameter
Symbol
Condition
MSM66577/Q577
Rated value
–0.3 to +7.0
Unit
V
Digital power supply voltage
VDD
MSM66577L/Q577LY
–0.3 to +4.6
V
GND = AGND
= 0 V
—
—
—
—
Input voltage
VI
VO
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to VREF
V
Output voltage
V
Ta = 25˚C
Analog reference voltage
Analog input voltage
VREF
VAI
V
V
Ta = 70˚C
per package
mW
˚C
100-pin TQFP
Power dissipation
650
PD
Storage temperature
TSTG
—
–50 to +150
20.2 Recommended Operating Conditions
Parameter
Symbol
Condition
Range
Unit
MSM66577
MSM66577L
MSM66Q577
fOSC £ 30 MHz
fOSC £ 14 MHz
fOSC £ 30 MHz
4.5 to 5.5
2.4 to 3.6
4.5 to 5.5
3.0 to 3.6
Digital power supply
voltage
VDD
V
MSM66Q577LY fOSC £ 14 MHz
Analog reference voltage
Analog input voltage
VREF
VAI
—
—
VDD – 0.3 to VDD
AGND to VREF
2.0 to 5.5
2.0 to 3.6
2 to 30
V
V
MSM66577/Q577
Memory hold voltage
VDDH
V
f
OSC = 0 Hz
MSM66577L/Q577LY
MSM66577
VDD = 4.5 to 5.5 V
VDD = 2.4 to 3.6 V
VDD = 4.5 to 5.5 V
VDD = 3.0 to 3.6 V
MSM66577L
MSM66Q577
MSM66Q577LY
2 to 14
fOSC
MHz
2 to 30
Operating frequency
2 to 14
fXT
Ta
32.768
kHz
˚C
—
Ambient temperature
Fan out
—
–30 to +70
MOS load
P0, P3, P11
—
—
20
6
N
P1, P2, P4, P5, P6, P7,
P8, P9, P10, P14, P15
TTL load
—
1
20
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MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
20.3 Allowable Output Current Values
MSM66577L/577 (VDD = 2.4 to 3.6 V/4.5 to 5.5 V, Ta = –30 to +70˚C)
MSM66Q577LY/Q577 (VDD = 3.0 to 3.6 V/4.5 to 5.5 V, Ta = –30 to +70˚C)
Unit
Parameter
"H" output pin (1 pin)
"H" output pins
(sum total)
Pin
All output pins
Sum total of all
output pins
Symbol
Min.
Typ.
Max.
IOH
—
—
–2
—
—
—
—
–40
S IOH
10
5
P0, P3, P11
Other ports
"L" output pin (1 pin)
IOL
Sum total of
P0, P3, P11
Sum total of
P1, P2, P4
80
mA
"L" output pins
(sum total)
Sum total of
P5, P6, P9
S IOL
—
—
50
Sum total of
P7, P8, P10, P14, P15
Sum total of
all output pins
140
[Note]
Each of the family devices has unique pattern routes for the internal power and ground.
ConnectthepowersupplyvoltagetoallV pinsandthegroundpotentialtoallGNDpins.
DD
If a device may have one or more V or GND pins to which the power supply voltage
DD
or the ground potential is not connected, it cannot be guaranteed for normal operation.
20.4 Internal Flash ROM Programming Conditions
Unit
V
Parameter
Symbol
Condition
Rating
4.5 to 5.5
3.0 to 3.6
–30 to +70
0 to +50
100
MSM66Q577
VDD
Supply voltage
V
MSM66Q577LY
During Read
∞C
∞C
Ambient temperature
Ta
During Programming
—
—
Endurance
Blocks size
CEP
—
Cycles
bytes
128
20-2
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
20.5 DC Characteristics
20.5.1 DC Characteristics (VDD = 4.5 to 5.5 V)
MSM66577/Q577 (VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Parameter
Symbol
Condition
Min.
0.44VDD
0.80VDD
–0.3
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
Max.
VDD + 0.3
VDD + 0.3
0.16VDD
0.20VDD
—
Unit
"H" input voltage
*1
—
VIH
"H" input voltage
"L" input voltage
"L" input voltage
*2,*3,*4,*5,*6
*1
—
VIL
–0.3
*2,*3,*4,*5,*6
I
O = –400 mA
IO = –2.0 mA
VDD – 0.4
"H" output voltage *1, *4
V
DD – 0.6
—
V
VOH
—
VDD – 0.4
IO = –200 mA
O = –1.0 mA
"H" output voltage
"L" output voltage
"L" output voltage
*2
—
V
DD – 0.6
—
I
0.4
0.8
IO = 3.2 mA
*1, *4
—
I
O = 10.0 mA
IO = 1.6 mA
VOL
—
0.4
*2
*3
—
0.8
I
O = 5.0 mA
Input leakage current
Input current
—
1/–1
1/–250
15/–15
±10
mA
*5 IIH/IIL
*6
—
VI = VDD/0 V
Input current
—
VO = VDD/0 V
VI = 0 V
mA
kW
*1,*2,*4
ILO
—
Output leakage current
Pull-up resistance
Rpull
25
—
100
fOSC = 1 MHz,
Ta = 25˚C
CI
5
7
—
—
4
Input capacitance
Output capacitance
Analog reference
supply current
pF
CO
—
During A/D operation
When A/D is stopped
—
—
—
mA
IREF
—
10
mA
*1: Applicable to P0
*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15
*3: Applicable to P12, SELMBUS, EA, NMI
*4: Applicable to P3, P11
*5: Applicable to RES
*6: Applicable to OSC0
20
20-3
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
Supply current (VDD = 4.5 to 5.5 V)
MSM66577/Q577 (VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Mode
Symbol
IDD
Condition
Min.
—
Typ.
60
80
500
40
5
Max.
80
Unit
fOSC = 30 MHz
mA
mA
CPU operation
—
MSM66577
180
800
60
fXT = 32.768 kHz
OSC is stopped
mode
*1
—
MSM66Q577
mA
*2
fOSC = 30 MHz
—
HALT mode
IDDH
mA
XT is used
—
110
100
XT is not used
—
1
mA
*3
STOP mode
IDDS
OSC is stopped, XT is not used
—
0.2
10
VDD = 2 V, Ta = 25°C
[Note]
Ports used as inputs are at V or 0 V. Other ports are unloaded.
DD
*1: CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2: CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3: CPU and all the peripheral functions are deactivated (The clock timer is being activated when
the XT is used).
20-4
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
20.5.2 DC Characteristics (VDD = 2.4 to 3.6 V)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Symbol
Condition
Min.
0.55VDD
0.80VDD
–0.3
Typ.
—
Max.
VDD + 0.3
VDD + 0.3
0.16VDD
0.20VDD
—
Unit
"H" input voltage
*1
VIH
—
"H" input voltage
"L" input voltage
"L" input voltage
*2,*3,*4,*5,*6
*1
—
—
—
VIL
–0.3
*2,*3,*4,*5,*6
—
IO = –400 mA
IO = –2.0 mA
IO = –200 mA
IO = –1.0 mA
IO = 3.2 mA
VDD – 0.4
—
"H" output voltage *1, *4
V
V
DD – 0.8
—
—
VOH
VDD – 0.4
VDD – 0.8
—
—
—
—
—
—
"H" output voltage
"L" output voltage
"L" output voltage
*2
*1, *4
*2
—
0.5
0.9
I
O = 5.0 mA
IO = 1.6 mA
O = 2.5 mA
—
VOL
—
—
—
—
—
—
40
—
—
—
—
—
—
—
—
—
—
100
5
0.5
I
0.9
Input leakage current *3,*6
1/–1
1/–250
15/–15
±10
200
—
IIH/IIL
VI = VDD/0 V
mA
Input current
Input current
*5
*6
ILO
VO = VDD/0 V
VI = 0 V
mA
kW
*1,*2,*4
Output leakage current
Pull-up resistance
Rpull
CI
Input capacitance
Output capacitance
Analog reference
supply current
fOSC = 1 MHz,
Ta = 25˚C
pF
7
—
CO
During A/D operation
When A/D is stopped
—
—
2
mA
IREF
mA
5
*1: Applicable to P0
*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15
*3: Applicable to P12, SELMBUS, EA, NMI
*4: Applicable to P3, P11
*5: Applicable to RES
*6: Applicable to OSC0
20
20-5
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
Supply current (VDD = 2.4 to 3.6 V)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Mode
Symbol
Condition
Min.
—
Typ.
15
Max.
25
Unit
fOSC = 14 MHz
mA
mA
mA
IDD
—
50
150
CPU operation
MSM66577L
fXT = 32.768 kHz
OSC is stopped
*1
mode
MSM66Q577LY
—
—
—
—
300
10
3
600
17
*2
fOSC = 14 MHz
HALT mode
IDDH
mA
XT is used
110
100
XT is not used
1
mA
*3
STOP mode
IDDS
OSC is stopped, XT is not used
—
0.2
10
VDD = 2 V, Ta = 25°C
[Note]
Ports used as inputs are at V or 0 V. Other ports are unloaded.
DD
*1: CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2: CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3: CPU and all the peripheral functions are deactivated (The clock timer is being activated when
the XT is used).
20-6
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
20.6 AC Characteristics
20.6.1 AC Characteristics (VDD = 4.5 to 5.5 V)
(1) Separate Bus Type
1. External program memory control
(VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
13
Max.
—
Unit
fOSC = 30 MHz
tfWH
tfWL
tPW
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
—
13
—
2 tf – 15
—
—
PSEN pulse width
tPD
45
PSEN pulse delay time
Address setup time
ns
tAS
CL = 50 pF
tf – 25
0
—
—
tAH
tIS
Address hold time
Instruction setup time
Instruction hold time
Read data access time
25
—
—
tIH
0
—
3 tf – 65*1
tACC
Note: tf = tcyc/2
t
cyc
CPUCLK
t
fWH
t
fWL
PSEN
t
PD
t
PW
PC0 to 19
A0 to A19
D0 to D7
t
AH
t
AS
INST0 to 7
t
ACC
t
IS
t
IH
Bus timing during no wait cycle time
*1 The read data access time (t
) is (3 + 2n) tf – 65 when n wait cycles are inserted.
ACC
For more details, refer to Section 18.4, "External Memory Access Timing".
20
20-7
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
2. External data memory control
(VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Parameter
Symbol
tcyc
Condition
Min.
33.3
13
Max.
—
Unit
Cycle time
f
OSC = 30 MHz
tfWH
tfWL
tRW
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
RD pulse width
—
13
—
—
2 tf – 15
2 tf – 15
—
tWW
—
WR pulse width
tRD
tWD
tAS
45
45
RD pulse delay time
—
WR pulse delay time
Address setup time
Address hold time
ns
CL = 50 pF
tf – 25
tf – 3
25
—
—
—
tAH
Read data setup time
Read data hold time
Read data access time
Write data setup time
Write data hold time
tRS
tRH
tACC
tWS
tWH
0
—
3 tf – 65*1
—
—
2 tf – 30
tf – 3
—
Note: tf = tcyc/2
t
cyc
CPUCLK
t
fWH
t
fWL
RD
t
RD
t
RW
RAP0 to 19
A0 to A19
t
AS
t
AH
D0 to D7
DIN0 to 7
t
RS
t
RH
t
ACC
WR
t
WD
t
WW
RAP0 to 19
A0 to A19
D0 to D7
t
AH
t
AS
DOUT0 to 7
t
WS
t
WH
Bus timing during no wait cycle time
*1 The read data access time (t ) is (3 + 2n) tf – 65 when n wait cycles are inserted.
ACC
For more details, refer to Section 18.4, "External Memory Access Timing".
20-8
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
(2) Multiplexed Bus Type
1. External program memory control
(VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
Max.
Unit
fOSC = 30 MHz
—
tfWH
tfWL
tAW
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
13
—
13
—
2 tf – 10
2 tf – 15
tf – 3
2 tf – 15
tf – 3
3 tf – 25
0
—
tPW
—
PSEN pulse width
tPAD
tALS
tALH
tAHS
tAHH
tIS
—
PSEN pulse delay time
Low address setup time
CL = 50 pF
—
ns
Low address hold time
High address setup time
—
—
High address hold time
Instruction setup time
Instruction hold time
—
—
25
tIH
0
tf – 3
Note: tf = tcyc/2
tcyc
CPUCLK
tfWH
tfWL
ALE
tAW
PSEN
tPAD
tPW
AD0 to AD7
A8 to A19
PC0 to 7
INST0 to 7
t
ALS
t
ALH
tIS
tIH
PC8 to 19
tAHH
tAHS
Bus timing during no wait cycle time
20
20-9
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
2. External data memory control
(VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Parameter
Symbol
tcyc
Condition
Min.
33.3
Max.
—
Unit
Cycle time
fOSC = 30 MHz
tfWH
tfWL
tAW
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
13
—
13
—
2 tf – 10
—
tRW
—
RD pulse width
2 tf – 15
2 tf – 15
tf – 3
tWW
—
WR pulse width
tRAD
tWAD
tALS
tALH
tAHS
tAHH
tRS
—
RD pulse delay time
tf – 3
—
WR pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Read data setup time
Read data hold time
Write data setup time
Write data hold time
ns
CL = 50 pF
2 tf – 15
tf – 3
3 tf – 25
tf – 3
25
—
—
—
—
—
tRH
0
tf – 3
—
tWS
2 tf – 30
tf – 3
tWH
—
tcyc
Note: tf = tcyc/2
CPUCLK
tfWH
tfWL
ALE
tAW
RD
tRAD
tRW
RAP0 to 7
AD0 to AD7
DIN0 to 7
tRS
tRH
tALS
tALH
RAP8 to 19
A8 to A19
tAHS
tAHH
WR
tWAD
tWW
AD0 to AD7
A8 to A19
RAP0 to 7
DOUT0 to 7
tWS
tWH
tALS
tALH
RAP8 to 19
tAHS
tAHH
Bus timing during no wait cycle time
20-10
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
(3) Serial port control
• Serial ports 1 and 6 (SIO1 and 6)
Master mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
Max.
—
Unit
fOSC = 30 MHz
4 tcyc
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
2 tf – 5
5 tf – 10
13
ns
CL = 50 pF
—
—
0
—
Note: tf = tcyc/2
t
cyc
CPUCLK
TXC/RXC
tSCKC
SDOUT
(TXD)
t
STMXH
t
STMXS
SDIN
(RXD)
t
SRMXH
t
SRMXS
20
20-11
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
Slave mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
Condition
Min.
33.3
Max.
—
Unit
tcyc
fOSC = 30 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
tSTMXS
tSTMXH
tSRMXS
tSRMXH
4 tcyc
—
—
2 tf – 15
4 tf – 10
13
ns
CL = 50 pF
—
—
3
—
Note: tf = tcyc/2
tcyc
CPUCLK
TXC/RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXH
tSRMXS
20-12
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
• Serial ports 4 and 5 (SIO4 and 5)
Master mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
200
Max.
—
Unit
fOSC = 30 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
6 tf – 5
ns
CL = 50 pF
—
4.5 tf – 10
13
—
0
—
Note: tf = tcyc/2
tcyc
CPUCLK
SIOCK
tSCKC
SDOUT
(SIOO)
tSTMXH
tSTMXS
SDIN
(SIOI)
tSRMXH
tSRMXS
20
20-13
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
Slave mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
Condition
Min.
33.3
200
Max.
—
Unit
tcyc
fOSC = 30 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
—
3 tf – 15
6 tf – 10
13
ns
CL = 50 pF
—
—
3
—
Note: tf = tcyc/2
t
cyc
CPUCLK
SIOCK
t
SCKC
SDOUT
(SIOO)
t
STMXH
t
STMXS
SDIN
(SIOI)
t
SRMXS
t
SRMXH
Measurement points for AC timing (except the serial port)
VDD
2.0 V
0.8 V
2.0 V
0.8 V
0 V
Measurement points for AC timing (the serial port)
VDD
0.8 VDD 0.8 VDD
0.2 VDD 0.2 VDD
0 V
20-14
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
20.6.2 AC Characteristics (VDD = 2.4 to 3.6 V)
(1) Separate Bus Type
1. External program memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Symbol
tcyc
Condition
Min.
71.4
28
Max.
—
Unit
Cycle time
f
OSC = 14 MHz
tfWH
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
—
tfWL
tPW
tPD
tAS
tAH
tIS
28
—
2 tf – 40
—
—
PSEN pulse width
95
PSEN pulse delay time
Address setup time
ns
CL = 50 pF
tf – 45
0
—
Address hold time
—
Instruction setup time
Instruction hold time
Read data access time
75
—
tIH
0
—
3 tf – 120*1
tACC
—
Note: tf = tcyc/2
t
cyc
CPUCLK
t
fWH
t
fWL
PSEN
t
PD
t
PW
PC0 to 19
A0 to A19
D0 to D7
t
AH
t
AS
INST0 to 7
t
ACC
t
IS
t
IH
Bus timing during no wait cycle time
*1 The read data access time (t ) is (3 + 2n) tf – 120 when n wait cycles are inserted.
ACC
For more details, refer to Section 18.4, "External Memory Access Timing".
20
20-15
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
2. External data memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
Condition
Min.
71.4
28
Max.
—
Unit
tcyc
f
OSC = 14 MHz
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
RD pulse width
tfWH
tfWL
tRW
—
28
—
2 tf – 40
2 tf – 40
—
—
tWW
—
WR pulse width
95
95
—
RD pulse delay time
tRD
tWD
tAS
—
WR pulse delay time
Address setup time
Address hold time
ns
CL = 50 pF
tf – 45
tf – 6
75
tAH
—
tRS
Read data setup time
Read data hold time
Read data access time
Write data setup time
Write data hold time
—
tRH
tACC
tWS
tWH
0
—
—
3 tf – 120*1
2 tf – 55
tf – 6
—
—
Note: tf = tcyc/2
t
cyc
CPUCLK
t
fWH
t
fWL
RD
t
RD
t
RW
RAP0 to 19
A0 to A19
t
AS
t
AH
D0 to D7
DIN0 to 7
t
RS
t
RH
t
ACC
WR
t
WD
t
WW
RAP0 to 19
A0 to A19
D0 to D7
t
AH
t
AS
DOUT0 to 7
t
WS
t
WH
Bus timing during no wait cycle time
) is (3 + 2n) tf – 120 when n wait cycles are inserted.
*1 The read data access time (t
ACC
For more details, refer to Section 18.4, "External Memory Access Timing".
20-16
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
(2) Multiplexed Bus Type
1. External program memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
Max.
Unit
f
OSC = 14 MHz
—
tfWH
tfWL
tAW
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
28
—
28
—
2 tf – 15
2 tf – 40
tf – 6
2 tf – 25
tf – 6
3 tf – 45
0
—
tPW
—
PSEN pulse width
tPAD
tALS
tALH
tAHS
tAHH
tIS
—
PSEN pulse delay time
Low address setup time
CL = 50 pF
—
ns
Low address hold time
High address setup time
—
—
High address hold time
Instruction setup time
Instruction hold time
—
—
75
tIH
0
tf – 6
Note: tf = tcyc/2
t
cyc
CPUCLK
t
fWH
t
fWL
ALE
t
AW
PSEN
t
PAD
t
PW
AD0 to AD7
A8 to A19
PC0 to 7
INST0 to 7
t
ALS
t
ALH
t
IS
t
IH
PC8 to 19
t
AHH
t
AHS
Bus timing during no wait cycle time
20
20-17
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
2. External data memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Symbol
tcyc
Condition
Min.
71.4
Max.
—
Unit
Cycle time
fOSC = 14 MHz
tfWH
tfWL
tAW
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
28
—
28
—
2 tf – 15
—
tRW
—
RD pulse width
2 tf – 40
2 tf – 40
tf – 6
tWW
—
WR pulse width
tRAD
tWAD
tALS
tALH
tAHS
tAHH
tRS
—
RD pulse delay time
tf – 6
—
WR pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Read data setup time
Read data hold time
Write data setup time
Write data hold time
ns
CL = 50 pF
2 tf – 25
tf – 6
3 tf – 45
tf – 6
75
—
—
—
—
—
tRH
0
tf – 6
—
tWS
2 tf – 55
tf – 6
tWH
—
Note: tf = tcyc/2
tcyc
CPUCLK
tfWH
tfWL
ALE
tAW
RD
tRAD
tRW
RAP0 to 7
AD0 to AD7
DIN0 to 7
tRS
tRH
tALS
tALH
RAP8 to 19
A8 to A19
tAHS
tAHH
WR
tWAD
tWW
AD0 to AD7
A8 to A19
RAP0 to 7
DOUT0 to 7
tWS
tWH
tALS
tALH
RAP8 to 19
tAHS
tAHH
Bus timing during no wait cycle time
20-18
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
(3) Serial port control
• Serial ports 1 and 6 (SIO1 and 6)
Master mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
Max.
—
Unit
fOSC = 14 MHz
tSCKC
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
4 tcyc
—
tSTMXS
tSTMXH
tSRMXS
—
2 tf – 10
5 tf – 20
21
ns
CL = 50 pF
—
—
tSRMXH
0
—
Note: tf = tcyc/2
tcyc
CPUCLK
TXC/RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXH
tSRMXS
20
20-19
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
Slave mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
Max.
—
Unit
fOSC = 14 MHz
tSCKC
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
4 tcyc
2 tf – 30
4 tf – 20
21
—
tSTMXS
tSTMXH
tSRMXS
—
ns
CL = 50 pF
—
—
tSRMXH
7
—
Note: tf = tcyc/2
tcyc
CPUCLK
TXC/RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
20-20
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
• Serial ports 4 and 5 (SIO4 and 5)
Master mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
400
Max.
—
Unit
fOSC = 14 MHz
tSCKC
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
—
tSTMXS
tSTMXH
tSRMXS
—
5.6 tf – 10
ns
CL = 50 pF
—
4.2 tf – 20
21
—
tSRMXH
0
—
Note: tf = tcyc/2
t
cyc
CPUCLK
SIOCK
t
SCKC
SDOUT
(SIOO)
t
STMXH
t
STMXS
SDIN
(SIOI)
t
SRMXH
t
SRMXS
20
20-21
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
Slave mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
Max.
—
Unit
fOSC = 14 MHz
tSCKC
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
400
—
tSTMXS
tSTMXH
tSRMXS
2.8 tf – 30
5.6 tf – 20
21
—
ns
CL = 50 pF
—
—
tSRMXH
7
—
Note: tf = tcyc/2
tcyc
CPUCLK
SIOCK
tSCKC
SDOUT
(SIOO)
tSTMXH
tSTMXS
SDIN
(SIOI)
tSRMXS
tSRMXH
Measurement points for AC timing (except the serial port)
VDD
0.44 VDD 0.44 VDD
0.16 VDD 0.16 VDD
0 V
Measurement points for AC timing (the serial port)
VDD
0.8 VDD 0.8 VDD
0.2 VDD 0.2 VDD
0 V
20-22
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
20.7 A/D Converter Characteristics
20.7.1 A/D Converter Characteristics (VDD = 4.5 to 5.5 V)
(Ta = –30 to +70˚C, VDD = VREF = 4.5 V to 5.5 V, AGND = GND = 0 V)
Parameter
Resolution
Symbol
n
Condition
Min.
—
Typ.
10
—
Max.
—
Unit
Refer to measurement
circuit of Fig. 20-1
Bit
—
Linearity error
EL
±3
Analog input source
impedance
ED
—
Differential linearity error
Zero scale error
Full-scale error
—
±2
EZS
EFS
—
—
+3
RI £ 5 kW
LSB
tconv = 8.5 ms
—
—
–3
Refer to measurement
ECT
—
Cross talk
—
—
±1
circuit of Fig. 20-2
Set according to
tCONV
ms/ch
Conversion time
8.5
3906.3
ADTM set data
20.7.2 A/D Converter Characteristics (VDD = 2.4 to 3.6 V)
MSM66577L (Ta = –30 to +70˚C, VDD = VREF = 2.4 to 3.6 V, AGND = GND = 0 V)
MSM66Q577LY (Ta = –30 to +70˚C, VDD = VREF = 3.0 to 3.6 V, AGND = GND = 0 V)
Parameter
Resolution
Symbol
n
Condition
Min.
—
Typ.
10
—
Max.
—
Unit
Refer to measurement
circuit of Fig. 20-1
Bit
—
Linearity error
EL
±4
Analog input source
impedance
ED
—
Differential linearity error
Zero scale error
Full-scale error
—
±3
EZS
EFS
—
—
+4
RI £ 5 kW
LSB
tconv = 27.4 ms
—
—
–4
Refer to measurement
circuit of Fig. 20-2
Set according to
ADTM set data
ECT
—
Cross talk
—
—
±2
tCONV
ms/ch
Conversion time
27.4
3906.3
Reference
voltage
VDD
+5 V/+3 V
VREF
0.1
mF
47
mF
+
+
0.1
47
RI
mF
mF
–
AI0 to AI7
AGND GND
+
0 V
Analog input
CI
RI (impedance of analog input source) £ 5 kW
CI 0.1 mF
20
=
Figure 20-1 Measurement Circuit
20-23
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
Cross talk is the difference
between the A/D conversion
results when the same
analog input is applied to AI0
through AI7 and the A/D
conversion results of the
circuit to the left.
5 kW
–
+
AI0
AI1
Analog input
0.1 mF
to
AI7
VREF or AGND
Figure 20-2 Cross Talk Measurement Circuit
Definition of Terminology
1.
Resolution
Resolution is the value of minimum discernible analog input.
10
With 10 bits, since 2 = 1024, resolution of (VREF – AGND) ÷ 1024 is possible.
2.
Linearity error
Linearity error is the difference between ideal conversion characteristics and actual
conversion characteristics of a 10-bit A/D converter (not including quantization error).
Ideal conversion characteristics can be obtained by dividing the voltage between V
AGND into 1024 equal steps.
and
REF
3.
Differential linearity error
Differential linearity error indicates the smoothness of conversion characteristics. Ideally,
therangeofanaloginputvoltagethatcorrespondsto1convertedbitofdigitaloutputis1LSB
= (V
– AGND) ÷ 1024. Differential error is the difference between this ideal bit size and
REF
bit size of an arbitrary point in the conversion range.
4.
5.
Zero scale error
Zero scale error is the difference between ideal conversion characteristics and actual
conversioncharacteristicsatthepointwherethedigitaloutputchangesfrom000Hto001H.
Full-scale error
Full-scale error is the difference between ideal conversion characteristics and actual
conversion characteristics at the point where the digital output changes from 3FEH to
3FFH.
20-24
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
20.8 D/A Converter Characteristics
MSM66577/MSM66Q577 (VDD = 2.4 to 3.6 V/4.5 to 5.5 V, Ta = –30 to +70˚C)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70˚C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70˚C)
Parameter
Resolution
Symbol
Condition
Min.
—
Typ.
—
Max.
8
Unit
n
Bit
EL
—
Linearity error
—
—
±1
±2
50
40
LSB
Absolute precision
Conversion time
—
tCONV
—
—
—
CL = 50 pF
—
—
20
10
ms
kW
Analog output impedance
—
Definition of Terminology
1.
Resolution
Resolution is the value of minimum discernible analog output.
8
With 8 bits, since 2 = 256, resolution of (V – GND) ÷ 256 is possible.
DD
2.
Linearity error
Linearity error is the difference between ideal conversion characteristics and actual
conversion characteristics of a 8-bit D/A converter.
Ideal conversion characteristics can be obtained by dividing the voltage between V and
DD
GND into 256 equal steps.
3.
Absolute precision
Absolute precision is a gross error including a linearity error and the effect of noise.
20
20-25
MSM66577 Family User's Manual
Chapter 20 Electrical Characteristics
20-26
Chapter 21
Special Function Registers (SFRs)
21
MSM66577 Family User's Manual
Chapter 21 Special Function Registers (SFRs)
21. Special Function Registers (SFRs)
21.1 Overview
The 256-byte area of addresses 0000H to 00FFH in data memory is the special function
register (SFR) area.
The SFR area is a register group that includes special function registers such as the
following.
Peripheral hardware mode registers
Arithmetic register (ACC)
Control registers (PSW, LRBL, LRBH, SSP)
21.2 List of SFRs
Table 21-1 lists the SFRs. Terms in the table are defined as follows:
• Address [H]:
• Function:
Addresses are expressed in hexadecimal format.
The register is named after the SFR function.
• Byte, Word:
Symbol
This symbol indicates an I/O function register.
Each symbol indicates whether access is by byte or
word.
—
A dash indicates that the function cannot be accessed
by that unit.
• Bit Symbol:
Symbol
This symbol indicates an I/O function register.
Insomecasestherearetwobitsymbols,howeverthere
is no difference in function.
Blank
0
The I/O register is also assigned to this bit.
However, since individual access of this bit is either
unnecessary or not possible, no bit symbol is needed.
If writing to this bit, always write a value of "0".
Even when writing a byte or word that includes this bit,
write this bit as "0".
This bit always reads as "0".
21
21-1
MSM66577 Family User's Manual
Chapter 21 Special Function Registers (SFRs)
1
If writing to this bit, always write a value of "1".
Even when writing a byte or word that includes this bit,
write this bit as "1".
This bit always reads as "1".
(1)
All writes to this bit are ignored.
This bit always reads as "1".
(0)
All writes to this bit are ignored.
This bit always reads as "0".
Undefined
This indicates a bit that does not support the I/O
function.
Programming should be done on the assumption that
the value of this bit is always undefined.
Operation of this bit when an in-circuit emulator is used
may differ from operation when an actual chip (such as
MASK or OTP versions) is used.
• R/W:
This indicates whether the specified SFR can be read
(R) or written (W).
Both read and write are possible
Read-only
R/W:
R:
W:
Write-only
• 8/16:
This indicates the unit of bit access for the specified
SFR.
8/16:
8:
Both 8-bit and 16-bit access are possible
Only 8-bit access is possible
16:
Only 16-bit access is possible
• Initial value [H]:
This indicates the contents of each SFR at reset (RES
signal input, execution of a BRK instruction, overflow of
the watchdog timer, or an opcode trap is generated).
Values are expressed in hexadecimal format.
• Reference page:
[Note]
This indicates the page on which the configuration of
each SFR is described.
Do not perform the following operation on SFRs.
1. Write operations on read-only SFRs
2. Read operations on write-only SFRs
3. 16-bit operations on 8-bit SFRs
4. 8-bit operations on 16-bit SFRs
5. Operation on addresses that are not allocated as registers
6. Operations in the area for emulator use
21-2
Table 21-1 SFR List (1/7)
Address
[H]
Initial value Reference
Bit Symbol
Function
System stack pointer
Local register base
Program status word
Accumulator
Byte Word
R/W 8/16
16
[H]
page
7
6
5
4
3
2
1
0
0000
0001
0002
0003
0004
0005
0006
0007
–
–
FF
FF
SSP
2-23
LRBL
LRB
Undefined
Undefined
00
2-22
2-18
2-17
8/16
LRBH
PSWL
PSWH
MAB
CY
F1
ZF
BCB1 BCB0
F0
S
SCB2 SCB1 SCB0
F2 OV MIE
PSW
8/16
HC
DD
00
00
00
ACCL
ACCH
R/W
8/16
ACC
0008 Table segment register
0009 Data segment register
000B ROM window register
000C ROM ready control register
000D RAM ready control register
000E Stop code acceptor
000F Standby control register
0010 Memory size acceptor
0011 Memory size control register
0013 Real-time counter control register
0015 Peripheral control register
0018 Port 0 data register
0019 Port 1 data register
001A Port 2 data register
001B Port 3 data register
001C Port 4 data register
001D Port 5 data register
001E Port 6 data register
001F Port 7 data register
0020 Port 0 mode register
0021 Port 1 mode register
TSR
DSR
0
0
0
0
0
0
1
0
0
0
1
0
00
00
Undefined
8B
2-26
2-27
4-2
4-4
4-5
3-3
3-4
2-2
2-1
10-2
15-2
5-12
5-14
5-16
5-18
5-20
5-22
5-24
5-26
5-12
5-14
8/16
DSTSR
ROMWIN
ROMRDY
RAMRDY
STPACP
SBYCON
MEMSACP
MEMSCON
RTCCON
PRPHCON
P0
P1
P2
P3
P4
P5
P6
P7
P0IO
P1IO
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
8
8
8
(1)
(1)
0
(1) IRORDY ORDY1 ORDY0
(1)
ARDY12 ARDY11 ARDY10
ARDY02 ARDY01 ARDY00
FF
"0"
08
"0"
FC
F0
8C
00
00
00
00
00
00
00
00
00/FF
00/FF
W
STP R/W
W
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
CLK1 CLK0 OST1 OST0 OSCS FLT
HLT
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
LROM LRAM
SELRTI1 SELRTI0 RTCIE RTCCL
WAIT HOLD EXTXT
(1)
(1) CLKO1 CLKO0
P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0
P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0
(0)
(0)
P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0
P5_7 P5_6 P5_5 P5_4 (0) (0) (0) (0)
P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0
P7_7 P7_6 (0) (0) (0) (0) (0) (0)
P0IO7 P0IO6 P0IO5 P0IO4 P0IO3 P0IO2 P0IO1 P0IO0
P1IO7 P1IO6 P1IO5 P1IO4 P1IO3 P1IO2 P1IO1 P1IO0
(0)
(0)
(0)
(0)
(0)
(0)
P2_3 P2_2 P2_1 P2_0
P3_3 P3_2 P3_1 P3_0
R/W
Table 21-1 SFR List (2/7)
Bit Symbol
Address
[H]
Initial value Reference
Function
Byte Word
R/W 8/16
[H]
00/0F
00/02
00/FF
00
page
5-16
5-18
5-20
5-22
5-24
5-26
7
6
5
4
3
2
1
0
0022 Port 2 mode register
0023 Port 3 mode register
0024 Port 4 mode register
0025 Port 5 mode register
0026 Port 6 mode register
0027 Port 7 mode register
P2IO
P3IO
P4IO
P5IO
P6IO
P7IO
–
–
–
–
–
–
(0)
(0)
(0)
(0)
P2IO3 P2IO2 P2IO1 P2IO0
8
8
8
8
8
8
(0)
(0)
(0)
(0)
P3IO3 P3IO2 P3IO1 P3IO0
P4IO7 P4IO6 P4IO5 P4IO4 P4IO3 P4IO2 P4IO1 P4IO0
P5IO7 P5IO6 P5IO5 P5IO4 (0) (0) (0) (0)
P6IO7 P6IO6 P6IO5 P6IO4 P6IO3 P6IO2 P6IO1 P6IO0
P7IO7 P7IO6 (0) (0) (0) (0) (0) (0)
00
00
XAD7 XAD6 XAD5 XAD4 XAD3 XAD2 XAD1 XAD0
P0SF7 P0SF6 P0SF5 P0SF4 P0SF3 P0SF2 P0SF1 P0SF0
XDM15 XDM14 XDM13 XDM12 XDM11 XDM10 XDM9 XDM8
P1SF7 P1SF6 P1SF5 P1SF4 P1SF3 P1SF2 P1SF1 P1SF0
XDM19 XDM18 XDM17 XDM16
8
8
8
8
00/FF
00/FF
00/0F
00/03
00/FF
00
5-12
5-14
5-16
5-18
5-20
5-22
5-24
5-26
0028 Port 0 secondary function control register P0SF
0029 Port 1 secondary function control register P1SF
002A Port 2 secondary function control register P2SF
002B Port 3 secondary function control register P3SF
002C Port 4 secondary function control register P4SF
002D Port 5 secondary function control register P5SF
002E Port 6 secondary function control register P6SF
002F Port 7 secondary function control register P7SF
–
–
–
–
–
–
–
–
(0)
(0)
(0)
(0)
P2SF3 P2SF2 P2SF1 P2SF0
WR RD PSEN ALE
P3SF3 P3SF2 P3SF1 P3SF0
(0)
(0)
(0)
(0)
XDM7 XDM6 XDM5 XDM4 XDM3 XDM2 XDM1 XDM0
P4SF7 P4SF6 P4SF5 P4SF4 P4SF3 P4SF2 P4SF1 P4SF0
PTM0OUT CPCM1 CPCM0
R/W
8
8
8
8
P5SF7
(0)
(0)
(0)
(0)
P5SF6 P5SF5 P5SF4
PTM2OUT
PTM1OUT
P6SF6
P6SF4 P6SF3 P6SF2 P6SF1 P6SF0
00
P6SF7
P6SF5
PWM1OUT PWM0OUT
P7SF7 P7SF6
QCPCM1 QCPCM0
(0)
(0)
0
(0)
0
(0)
0
(0)
(0)
00
0030 Interrupt request register 0
0031 Interrupt request register 1
0032 Interrupt request register 2
0033 Interrupt request register 3
0034 Interrupt enable register 0
0035 Interrupt enable register 1
0036 Interrupt enable register 2
0037 Interrupt enable register 3
IRQ0
IRQ1
IRQ2
IRQ3
IE0
IE1
IE2
IE3
–
–
–
–
–
–
–
–
0
QFRCOV QINT0
8
8
8
8
8
8
8
8
00
00
00
00
00
00
00
00
17-12
17-13
17-14
17-15
17-17
17-18
17-19
17-20
0
QTM3OV QTM2OV QTM1OV QINT3 QINT2 QINT1 QTM0OV
QSIO1 QTM4OV
QRTC
0
0
QINT7 QINT6 QINT5 QINT4
QAD QTM6OV QSIO4 QSIO6 QSIO5 QTM5OV
EFRCOV EINT0
ETM3OV ETM2OV ETM1OV EINT3 EINT2 EINT1 ETM0OV
ESIO1 ETM4OV
ERTC
0
ECPCM1 ECPCM0
0
0
0
0
0
0
0
EINT7 EINT6 EINT5 EINT4
0
EAD ETM6OV ESIO4 ESIO6 ESIO5 ETM5OV
Table 21-1 SFR List (3/7)
Address
[H]
Initial value Reference
Bit Symbol
Function
Byte Word
R/W 8/16
[H]
page
17-22
17-23
17-24
17-25
17-26
17-27
17-28
17-29
7
0
6
0
5
0
4
0
3
2
1
0
0038 Interrupt priority control register 0
0039 Interrupt priority control register 1
003A Interrupt priority control register 2
003B Interrupt priority control register 3
003C Interrupt priority control register 4
003D Interrupt priority control register 5
003E Interrupt priority control register 6
003F Interrupt priority control register 7
IP0
IP1
IP2
IP3
IP4
IP5
IP6
IP7
–
–
–
–
–
–
–
–
–
P1FRCOV P0FRCOV P1INT0 P0INT0
8
8
8
8
8
8
8
8
00
00
00
00
00
00
00
00
P1CPCM1 P0CPCM1 P1CPCM0 P0CPCM0
0
0
0
0
P1INT3 P0INT3 P1INT2 P0INT2 P0INT1 P0INT1 P1TM0OV P0TM0OV
P1SIO0 P0SIO0 P1TM3OV P0TM3OV P1TM2OV P0TM2OV P1TM1OV P0TM1OV
P1INT7 P0INT7 P1INT6 P0INT6 P1INT5 P0INT5 P1INT4 P0INT4
P1SIO1P0SIO1 P1TM4OV P0TM4OV
P1SIO4P0SIO4P1SIO6 P0SIO6P1SIO5P0SIO5 P1TM5OV P0TM5OV
P1RTC P0RTC P1AD P0AD P1TM6OV P0TM6OV
0
0
0
0
0
0
0040
00
00
00
00
00
00
Free running counter
0041
FRC
16
16
9-3
9-6
9-6
–
004A
–
–
Capture compare register 0
004B
CPCMR0
004C
–
–
Capture compare register 1
004D
CPCMR1
R/W
16
0050 Free running counter control register FRCON
–
–
–
–
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1) CP1MD CP0MD FRRUN FRCK2 FRCK1 FRCK0
(1) CP1E1 CP1E0 CP0E1 CP0E0 (0) (0)
8
8
8
8
8
8
8
8
8
8
8
8/16
16
C0
C0
FC
FC
00
00
0C/4C
E0
E0
00
9-4
9-7
9-6
0051 Capture control register
CAPCON
CPCMCON0
CPCMCON1
EXI0CON
EXI1CON
EXI2CON
IRQ4
IE4
0055 Compare control register 0
0056 Compare control register 1
0058 External interrupt control register 0
0059 External interrupt control register 1
005A External interrupt control register 2
005C Interrupt request register 4
005D Interrupt enable register 4
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
CPCMSBF0 CPCMBF0 CPCMOUT0
CPCMSBF1 CPCMBF1 CPCMOUT1
9-6
EX3M1 EX3M0 EX2M1 EX2M0 EX1M1 EX1M0 EX0M1 EX0M0
EX7M1 EX7M0 EX6M1 EX6M0 EX5M1 EX5M0 EX4M1 EX4M0
MIPF NMIRD NMIM1 NMIM0 (1)
(1)
(1)
16-2
16-3
16-4
17-16
17-21
17-30
17-31
7-3
(1)
(0)
(0)
(1)
(1)
(1)
(1)
QTM9OV QPWM3 QPWM2 QPWM1 QPWM0
ETM9OV EPWM3 EPWM2 EPWM1 EPWM0
005E Interrupt priority control register 8
005F Interrupt priority control register 9
0060 TBC clock dividing register
0061 TBC clock dividing counter
IP8
IP9
TBCKDVR
P1PWM3 P0PWM3 P1PWM2 P0PWM2 P1PWM1 P0PWM1 P1PWM0 P0PWM0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
P1TM9OV P0TM9OV
FC
F0
F0
TBCKDV
–
7-2
R
0062
–
–
Undefined
Undefined
General-purpose 16-bit timer 0 counter
0063
TM0C
16
8-4
R/W
Table 21-1 SFR List (4/7)
Bit Symbol
Address
[H]
Initial value Reference
Function
Byte Word
R/W 8/16
[H]
page
7
6
5
4
3
2
1
0
0064
0065
–
–
Undefined
Undefined
70
General-purpose 16-bit timer 0 register
TM0R
16
8
8-4
0066 General-purpose 16-bit timer 0 control register TM0CON
–
TM0OUT
(1)
(1)
(1) TM0RUN TM0C2 TM0C1 TM0C0
8-4
8-10
8-10
8-10
8-10
8-10
8-11
8-22
8-22
8-22
8-28
8-28
8-28
8-34
8-34
8-34
8-43
8-43
8-41
0068
0069
006A
006B
TM1C
TM2C
TM1R
TM2R
Undefined
Undefined
Undefined
Undefined
70
General-purpose 8-bit timer 12 counter
General-purpose 8-bit timer 12 register
TM12C
8/16
TM12R
8/16
006C General-purpose 8-bit timer 1 control register TM1CON
006D General-purpose 8-bit timer 2 control register TM2CON
0070 General-purpose 8-bit timer 3 counter TM3C
0071 General-purpose 8-bit timer 3 register TM3R
0072 General-purpose 8-bit timer 3 control register TM3CON
0074 General-purpose 8-bit timer 4 counter TM4C
0075 General-purpose 8-bit timer 4 register TM4R
0076 General-purpose 8-bit timer 4 control register TM4CON
0078 General-purpose 8-bit timer 5 counter TM5C
0079 General-purpose 8-bit timer 5 register TM5R
007A General-purpose 8-bit timer 5 control register TM5CON
007C General-purpose 8-bit timer 6 counter TM6C
007D General-purpose 8-bit timer 6 register TM6R
007E General-purpose 8-bit timer 6 control register TM6CON
–
–
–
–
–
–
–
–
–
–
–
–
–
–
TM1OUT
TM2OUT
(1)
(1)
(1) TM1RUN TM1C2 TM1C1 TM1C0
8
8
8
8
8
8
8
8
8
8
8
8
8
8
(1) MODPWM MOD16 TM2RUN TM2C2 TM2C1 TM2C0
40
Undefined
Undefined
70
Undefined
Undefined
70
Undefined
Undefined
70
Undefined
Undefined
10
TM3OUT
TM4OUT
TM5OUT
(1)
(1)
(1)
(1)
(1)
(1)
(1) TM3RUN TM3C2 TM3C1 TM3C0
(1) TM4RUN TM4C2 TM4C1 TM4C0 R/W
(1) TM5RUN TM5C2 TM5C1 TM5C0
MODWDT WDTLDE WDTRUN
(1) ATMRUN WDTC2 WDTC1 WDTC0
ST1STB
0084 SIO1 transmit control register
ST1CON
–
TR1NIE TR1MIE ST1ODD ST1PEN
(1)
ST1LN ST1MOD
8
04
00
12-4
ST1SLV
SR1REN RC1IE SR1ODD SR1PEN SR1SLV S1EXC SR1LN SR1MOD
0085 SIO1 receive control register
0086 SIO1 transmit-receive buffer register S1BUF
SR1CON
–
–
–
–
–
–
–
8
8
8
8
8
8
8
12-6
Undefined 12-10
0087 SIO1 status register
008C SIO4 control register
008D FIOF control register
008E SIO4 input FIFO data register
008F SIO4 output FIFO data register
0090 PWM register 0
0091 PWM register 1
0092 PWM register 2
0093 PWM register 3
S1STAT
SIO4CON
FIFOCON
SIN4
SOUT4
PWR0
PWR1
PWR2
PWR3
(0)
(0) RC1END TR1END TR1EMP PERR1 OERR1 FERR1
00
80
11
12-8
12-41
12-43
(1) BUSY4 ICK4 TEN4 SIO4SL SIO4C2 SIO4C1 SIO4C1
SRES5 ORE5 FUL5 EMP5 SRES4 ORE4 FUL4 EMP4
R
W
Undefined 12-45
Undefined 12-45
00
PWR01
8/16
11-4
00
R/W
00
PWR23
8/16
11-4
00
Table 21-1 SFR List (5/7)
Address
[H]
Initial value Reference
Bit Symbol
Function
Byte Word
R/W 8/16
8/16
[H]
page
7
6
5
4
3
2
1
0
0094 PWM cycle register 0
0095 PWM cycle register 1
0096 PWM counter 0
PWCY0
PWCY
PWCY1
00
00
11-3
PWC0
PWC1
00
00
8/16
11-3
PWC
0097 PWM counter 1
0098 PWM control register 0
0099 PWM control register 1
009C A/D control register 0L
009D A/D control register 0H
009E A/D interrupt control register 0
PWCON0
–
–
–
–
–
PWC1OV PWCK11 PWCK10 PW1RUN PWC0OV PWCK01 PWCK00 PW0RUN
8
8
8
8
8
00
FE
80
80
11-4
11-6
13-3
13-5
13-7
R/W
PWCON1
(1)
(1)
(1)
(1)
(1)
(1)
0
0
(1)
(1) PWHSM
ADCON0L
SCNC0 SNEX0 ADRUN0
ADSNM02 ADSNM01 ADSNM00
ADSTM02 ADSTM01 ADSTM00
ADCON0H
ADINT0
–
ADTM02 ADTM01 ADTM00 STS0
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
ADSTIE0 ADSNIE0 INTST0 INTSN0
F0
00A0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
00
A/D result register 00
00A1
ADR00
ADR01
ADR02
ADR03
ADR04
ADR05
ADR06
ADR07
16
16
16
16
16
16
16
16
13-8
13-8
13-8
13-8
13-8
13-8
13-8
13-8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
00A2
A/D result register 01
00A3
00A4
A/D result register 02
00A5
00A6
A/D result register 03
00A7
R
00A8
A/D result register 04
00A9
00AA
A/D result register 05
00AB
00AC
A/D result register 06
00AD
00AE
A/D result register 07
00AF
(0)
(0)
(0)
00B8 Port 8 data register
00B9 Port 9 data register
00BA Port 10 data register
00BB Port 11 data register
P8
P9
P10
P11
–
–
–
–
P8_7 P8_6
P9_7
(0)
P8_4 P8_3 P8_2 P8_1 P8_0
(0) P9_3 P9_2 P9_1 P9_0
8
8
8
8
5-28
5-30
5-32
5-34
(0)
(0)
(0)
00
00
00
R/W
P10_5 P10_4 P10_3
(0) (0) P11_3 P11_2 P11_1 P11_0
(0)
(0)
(0)
(0)
Table 21-1 SFR List (6/7)
Address
[H]
Initial value Reference
Bit Symbol
Function
Byte Word
R/W 8/16
[H]
Undefined
00
page
5-36
5-37
7
6
5
4
3
2
1
0
00BC Port 12 data register
00BE Port 14 mode register
00BF Port 15 mode register
00C0 Port 8 mode register
00C1 Port 9 mode register
00C2 Port 10 mode register
00C3 Port 11 mode register
00C4 Port 14 mode register
00C5 Port 15 mode register
P12
P14
P15
P8IO
P9IO
P10IO
P11IO
P14IO
P15IO
–
–
–
–
–
–
–
–
–
P12_7 P12_6 P12_5 P12_4 P12_3 P12_2 P12_1 P12_0
R
8
8
P14_7 P14_6
(0) (0)
P8IO7 P8IO6
P9IO7
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
P14_2 P14_1 P14_0
P15_3P15_2 P15_1 P15_0
8
00
5-93
P8IO4 P8IO3 P8IO2 P8IO1 P8IO0
(0) P9IO3 P9IO2 P9IO1 P9IO0
(0) (0)
(0) P11IO3 P11IO2 P11IO1 P11IO0
(0) (0) P14IO2 P14IO1 P14IO0
8
8
8
8
8
8
00
00
00
00
00
00
5-28
5-30
5-32
5-34
5-37
5-39
(0)
(0) P10IO5 P10IO4 P10IO3 (0)
(0) (0)
(0)
P14IO7 P14IO6 (0)
(0)
AO1
(0)
AO0
(0)
(0) P15IO3 P15IO2 P15IO1 P15IO0
SIOO5 SIOCK5
00C6 Port 14 secondary function control register P14SF
00C7 Port 15 secondary function control register P15SF
00C8 Port 8 secondary function control register P8SF
00C9 Port 9 secondary function control register P9SF
00CA Port 10 secondary function control register P10SF
–
–
–
–
–
–
(0)
(0)
(0) P14SF2
8
8
8
8
8
8
00
00
00
00
00
00
5-37
5-39
5-28
5-30
5-32
5-34
P14SF7 P14SF6
P14SF1 P14SF0
TXC6 RXC6 TXD6
P15SF3P15SF2 P15SF1
(0) (0)
(0)
(0)
(0)
(0)
P15SF0
P8SF0
R/W
PWM3OUT PWM2OUT
PTM4OUT TXC1 RXC1 TXD1
P8SF4 P8SF3 P8SF2 P8SF1
P8SF7 P8SF6
HLDACK
P9SF7
(0)
(0)
P9SF3 P9SF2 P9SF1 P9SF0
SIOO4 SIOCK4
P10SF4P10SF3
(0)
(0)
(0) P10SF5
(0)
(0)
(0)
XTOUT CLKOUT
P11SF3 P11SF2
00CB Port 11 secondary function control register P11SF
00CC General-purpose 8-bit timer 9 counter TM9C
(0)
(0)
(0)
P11SF1 P11SF0
–
–
–
–
8
8
8
8
Undefined
Undefined
70
8-49
8-49
8-49
00CD General-purpose 8-bit timer 9 register
TM9R
00CE General-purpose 8-bit timer 9 control register TM9CON
FIFOMOD
TM9OUT
(1)
(1)
(1)
(1)
(1)
(1) TM9RUN TM9C2 TM9C1 TM9C0
(1) (1) (1) FMOD1 FMOD0
00CF FIFO mode register
FC
12-54
Table 21-1 SFR List (7/7)
Address
[H]
Initial value Reference
Bit Symbol
Function
Byte Word
R/W 8/16
[H]
page
7
6
5
4
3
2
1
0
00D5 SIO5 control register
00D6 SIO5 input FIFO data register
00D7 SIO5 output FIFO data register
00DD DA control register
00DE DA register 0
SIO5CON
SIN5
SOUT5
DACON
DAR0
DAR1
–
–
–
–
–
(1) BUSY5 ICK5 TEN5 SIO5SLSIO5C2 SIO5C1 SIO5C0 R/W
8
8
8
8
8
8
80
12-52
R
W
Undefined 12-54
Undefined 12-54
(1)
(1)
(1)
(1)
(1)
(1)
(1)
DAON
FE
00
00
14-2
14-2
14-2
00DF DA register 1
00EA
00EB
R/W
Capture compare buffer register 0
CPCMBFR0
16
16
00
00
9-8
9-8
–
–
–
00EC
Capture compare buffer register 1
00ED
CPCMBFR1
00F0 Flash memory acceptor
00F1 Flash memory control register
FLAACP
FLACON
–
–
–
8
8
"0"
C6
19-11
19-12
W
(1)
FA11 FA10 FA9
(1) (1) (1)
(1) AMPOFF FCLK1 FCLK0 (1)
(1)
(1)
PRG
(1)
00F2
FA8 FA7 (1)
FLAADRS
16 Undefined 19-11
Flash memory address register
00F3
–
FA16 FA15 FA14 FA13 FA12
ST6STB
00F4 SIO6 transmit control register
ST6CON
8
04
00
12-16
12-18
TR6NIE TR6MIE ST6ODD ST6PEN
(1)
ST6LN ST6MOD
R/W
–
ST6SLV
00F5 SIO6 receive control register
00F6 SIO6 transmit-receive buffer register S6BUF
00F7 SIO6 status register
SR6CON
8
8
8
SR6REN RC6IE SR6ODD SR6PEN SR6SLV S6EXC SR6LN SR6MOD
(0) RC6END TR6END TR6EMP PERR6 OERR6 FERR6
–
–
Undefined 12-22
S6STAT
00
12-20
(0)
[Note]
A star (P) in the address column indicates a SFR existing only in the Flash ROM version.
For details, refer to Chapter 19, "Flash Memory".
MSM66577 Family User's Manual
Chapter 21 Special Function Registers (SFRs)
21-10
Chapter 22
Package Dimensions
22
MSM66577 Family User's Manual
Chapter 22 Package Dimensions
22. Package Dimensions
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
42 alloy
Solder plating (≥5 mm)
0.55 TYP.
Oki Electric Industry Co., Ltd.
4/Oct. 28, 1996
Notes for Mounting the Surface Mounting Type Package
The TQFP is a surface mount type package and is very susceptible to heat in reflow
mounting and to humidity absorbed in storage. Therefore, before you do reflow mounting,
contact Oki's responsible sales person on the product name, package name, pin number,
package code and desired mounting conditions (reflow method, temperature and times).
22-1
22
MSM66577 Family User's Manual
Chapter 22 Package Dimensions
22-2
Note on Programming
MSM66577 Family User's Manual
Note on Programming
Note on Programming
When the compare output function is used, if a compare match takes place while CPCMR0
or CPCMR1 is being read, the value of the CPCMR0 or CPCMR1 register being read will
be changed. However, in the case of ICE, such a change does not occur.
In cases where a compare match takes place while CPCMR0 or CPCMR1 is read, make
the free running counter (FRC) stop (FRRUN = 0), then read CPCMR0 or CPCMR1.
A-1
MSM66577 Family User's Manual
Note on Programming
A-2
Revision History
MSM66577 Family User's Manual
Revision History
Revision History
Page
Document
Date
Description
Previous Current
Edition Edition
No.
—
—
PEUL66577-01
FEUL66577-01
Dec. 2000
Jun. 2002
Preliminary edition 1
Cover Cover
Deleted "Preliminary"
1-4
1-8
1-4
1-8
Partly changed the contents of Table 1-1.
Partly changed the contents of Table 1-2.
Added an explanation of STOP mode to
Sec. 3.2.4 (3).
3-9
3-9
3-10
6-3
6-3
6-4
6-5
9-5
3-10
6-3
6-3
6-4
6-5
9-5
Added two items to [Note].
Added Table 6-2.
Modified Figure 6-4.
Modified Figure 6-6.
Modified Figure 6-7.
Addede [Note] to Sec. 9.5.
Added an explanation of SIO4 to Sec. 12.7.
12-40 12-40
Added an explanation of SIO5 to Sec. 12.8.
Partly changed the contents of Sec. 17.3.3 (2).
Deleted "Preliminary" from the chapter title.
12-51 12-51
17-10 17-10
19-1
19-1
19-1 to 19-1 to
Partly changed the contents of Sections 19.1
through 19.9.
19-9
20-1
19-9
20-1
Deleted "Preliminary" from the chapter title.
Partly changed the contents of the table of
supply current.
20-4
20-6
20-4
20-6
Partly changed the contents of the table of
supply current.
Changed the Min. value of tSCKC in the table.
Changed the Min. value of tSCKC in the table.
Changed the Min. value of tSCKC in the table.
Changed the Min. value of tSCKC in the table.
20-13 20-13
20-14 20-14
20-21 20-21
20-22 20-22
—
—
A-1
R-1
Added "Note on Programming".
Added "Revision History".
R-1
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