MSM66Q577LY-NTB [OKI]
16-Bit Microcontroller; 16位微控制器
| 型号： | MSM66Q577LY-NTB |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 16-Bit Microcontroller |
| 文件： | 总34页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PEDL66577-01
This version: Apr. 2000
Semiconductor
1
Preliminary
MSM66577 Family
16-Bit Microcontroller
GENERAL DESCRIPTION
The MSM66577 family of highly functional CMOS 16-bit single chip microcontrollers utilizes the nX-8/500S,
Oki’s proprietary CPU core.
Four channels of serial ports, consisting of two channels of synchronous serial ports with 32-byte FIFO registers
and two channels of UART/synchronous serial ports, enable easy interfacing with external peripheral LSI devices
such as an encoder/decoder or servocontroller.
A switching function permits selection of separate address and data lines or multiplexed lines for the external bus
interface to correspond to various peripheral LSI devices.
With features such as a clock gear function, dual clock function, STOP/HALT mode, programmable pull-up ports
in which individual bits can be programmed, and a small, thin package, the MSM66577 family of microprocessors
is optimally suited for the system control of small-sized low power devices.
The flash ROM version (MSM66Q577LY) programmable with a single 3V power supply (3.0 to 3.6V) and flash
ROM version (MSM66Q577) programmable with a single 5V power supply (4.5 to 5.5V) are also included in the
family. These versions are easily adaptable to sudden specification changes and to new product versions.
APPLICATIONS
Digital Audio Control Systems
PC peripheral Control Systems
Office Electronics Control Systems
ORDERING INFORMATION
Order Code or Product Name
MSM66577L-xxTB *1
MSM66577-xxTB *1
Package
Remark
Low voltage mask ROM version (2.4 to 3.6 V)
5 V mask ROM version (4.5 to 5.5 V)
MSM66577L flash ROM version (3.0 to 3.6V)
MSM66577 flash ROM version (4.5 to 5.5 V)
100-pin plastic TQFP
(TQFP 100-P-1414-0.50-K)
MSM66Q577LY-NTB *2
MSM66Q577-NTB *2
*1 : The “xx” of “-xx” stands for the code number.
*2 : The “N” of “-N” stands for the flash ROM and the OTP ROM, blank version.
When OKI programs and ship the flash ROM and OTP, the part number is changed from ”–N” to ”–XX” (code
number ) , for example, MSM66Q577-999TB.
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MSM66577 Family
FEATURES
Name
MSM66577L
MSM66577
Operating temperature
–30°C to +70°C
Power supply voltage/
maximum frequency
VDD = 2.4 to 3.6 V/f = 14 MHz
VDD = 4.5 to 5.5 V/f = 30 MHz
143 ns at 14 MHz
67 ns at 30 MHz
Minimum instruction
execution time
61 µs at 32.768 kHz
Internal ROM size (max. external)
Internal RAM size (max. external)
I/O ports
128 KB (1 MB)
4 KB (1 MB)
74 I/O pins (with programmable pull-up resistors) 8 input-only pins
16-bit free running timer × 1ch
Compare output/capture input × 2ch
16-bit timer (auto reload/timer out) × 1ch
8-bit auto reload timer × 2ch (can also be used as 16-bit timer × 1ch)
8-bit auto reload timer × 1ch
Timers
8-bit auto reload timer × 3ch
(also functions as serial communication baud rate generator)
8-bit auto reload timer × 1ch (also functions as watchdog timer)
Watch timer (Real-timer counter) × 1ch
8-bit PWM × 4ch (can also be used as 16-bit PWM × 2ch)
Synchronous, with 32-byte FIFO × 2ch
UART/Synchronous × 2ch
Serial port
A/D converter
D/A converter
10-bit A/D converter × 8ch
8-bit D/A converter × 2ch
Non-maskable × 1ch
Maskable × 8ch
External interrupt
Interrupt priority
3 levels
External bus interface
(Separate address and data busses / multiplexed address and data
busses)
Others
Bus release function
Dual clocks function
Clock gear function
MSM66Q577LY
MSM66Q577
Flash ROM version
(VDD=3.0 to 3.6V)
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MSM66577 Family
SPECIAL FEATURES
1. High-performance CPU
The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical
addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support.
2. A variety of power saving modes
Attaching a 32.768-kHz crystal produces a real-time clock signal from the internal clock timer. Use of a single
clock in place of dual clocks is possible.
The clock gear function allows a 1/2 × or 1/4 × main clock to be selected for the CPU operating clock.
Switching the CPU clock to 32.768-kHz signal, 1/2 × main clock, or 1/4 × main clock, then produces operation in
a low power consumption mode.
The family provides a wide range of standby control functions. In addition to the usual STOP mode that stops the
oscillator, there are the quick restart STOP mode that shuts down the CPU and peripherals but leaves the oscillator
running, and the HALT mode that shuts down the CPU but leaves the peripherals running.
3. Variety of multifunctional serial ports
The family includes two channels of built-in synchronous serial ports with 32-byte FIFO implementing an auto
transfer function.
The family allows multi-byte 1-frame information which consists of address, command, and data to be easily and
efficiently transmitted to or received from a serial interface type peripheral LSI device. The family also allows
multi-byte character information to be easily and efficiently transmitted to or received from an LCD module.
In addition, the family has two channels of combined UART/synchronous serial ports, and provides four channels
of serial interfaces.
UART/synchronous SIO
UART/synchronous SIO
Synchronous SIO with 32-byte FIFO
Synchronous SIO with 32-byte FIFO
4. MSM66Q577LY and MSM66Q577 with flash memory programmable with single power supply
In addition to the regular mask ROM version, the family includes these versions with 128KB of flash memory that
can be programmed using a single power supply.
For the MSM66Q577LY, an internal booster circuit derives the necessary program voltage from the device's low
(3.0 to 3.6V) power supply, and the program voltage for the MSM66Q577 is provided with a single 5 V power
supply (4.5 to 5.5 V).
5. High-precision A/D and D/A converters
The family includes a high-precision 10-bit analog-to-digital converter with eight channels and 8-bit digital-to-
analog converter with two channels.
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MSM66577 Family
6. Multifunction PWM
The family supports both 8- and 16-bit PWM operation.
Choosing between the time-base counter output or overflow from an 8-bit auto-reload timer as the PWM counter
clock source provides a wide number of possibilities over a broad frequency range. The 16-bit PWM configuration
supports a high-speed synchronization mode that generates a high-precision output signal with less ripple suitable
for digital-to-analog control applications.
7. Programmable pull-up resistors
Building the pull-up resistors into the chip contributes to overall design compactness.
Making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system
design. These programmable pull-up resistors are available for all I/O pins not already assigned specific functions
(such as the oscillator connection pins).
8. Wide support for external interrupts
There are a total of nine interrupt channels for use in communicating with external devices: eight for maskable
interrupts and one for non-maskable interrupts.
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MSM66577 Family
BLOCK DIAGRAM
TM0OUT
16 bit Timer0
TM0EVT
TM1OUT
TM1EVT
TM2OUT
TM2EVT
XT0
CPU Core
XT1
8 bit Timer1
8 bit Timer2
OSC0
OSC1
HOLD
HLDACK
RES
System
Control
CLKOUT
XTOUT
ALU
Peripheral
Control
RXD1
TXD1
RXC1
TXC1
Registers
SIO1
SSP
LRB
PSW
PC
(UART/SYNC)
ALU Control
ACC
DSR TSR CSR
TM4OUT
8 bit Time4/BRG
RXD6
TXD6
RXC6
TXC6
SIO6
(UART/SYNC)
Memory Control
Pointing Registers
Local Registers
8 bit Timer3/BRG
Instruction
Decoder
SIOI4
SIOO4
SIOCK4
SIO4
(32 byte FIFO SYNC)
EA
ROM
128K
SELMBUS
PSEN
RD
RAM
4K
8 bit Timer5/BRG
SIOI5
SIOO5
SIOCK5
SIO5
WR
WAIT
(32 byte FIFO SYNC)
8 bit Timer6/WDT
D0 to D7
(AD0 to AD7*)
PWMOUT0
PWMOUT2
8 bit PWM0
8 bit PWM1
A0 to A19
PWMOUT1
PWMOUT3
P0
P1
P2
P3
P4
P5
P6
P7
TBC
RTC
8 bit Timer9
CAP/CMP
CPCM0
CPCM1
16 bit FRC
VREF
AGND
AI0 to AI7
P8
P9
10 bit A/D
Converter
P10
P11
P12
P14
P15
AO0
AO1
NMI
8 bit D/A Converter
Interrupt
EXINT0
to
EXINT7
*: Address output/data I/O when
selecting multiplexed bus type.
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MSM66577 Family
PIN CONFIGURATION (TOP VIEW)
SIOCK4/P10-3
SIOO4/P10-4
SIOI4/P10-5
RXD1/P8-0
P1-7/A15
P1-6/A14
P1-5/A13
P1-4/A12
P1-3/A11
P1-2/A10
P1-1/A9
P1-0/A8
P4-7/A7
P4-6/A6
P4-5/A5
P4-4/A4
P4-3/A3
P4-2/A2
P4-1/A1
P4-0/A0
1
5
75
70
65
60
55
TXD1/P8-1
RXC1/P8-2
TXC1/P8-3
TM4OUT/P8-4
PWM2OUT/P8-6
PWM3OUT/P8-7
PWM0OUT/P7-6
PWM1OUT/P7-7
VDD
10
15
20
25
GND
HLDACK/P9-7
EXINT4/P9-0
EXINT5/P9-1
EXINT6/P9-2
EXINT7/P9-3
EXINT0/P6-0
EXINT1/P6-1
EXINT2/P6-2
EXINT3/P6-3
TM1EVT/P6-4
TM1OUT/P6-5
GND
P0-7/D7(AD7*)
P0-6/D6(AD6*)
P0-5/D5(AD5*)
P0-4/D4(AD4*)
P0-3/D3(AD3*)
P0-2/D2(AD2*)
P0-1/D1(AD1*)
P0-0/D0(AD0*)
100-pin Plastic TQFP
*: Address output/data I/O when selecting multiplexed bus type.
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MSM66577 Family
PIN DESCRIPTIONS
In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin.
Description
Function
Symbol
Primary function
8-bit I/O port
Secondary function
Type
I/O
Type
I/O
Port
P0_0/D0 (AD0)
to
P0_7/D7 (AD7)
External memory access
Data I/O port
10 mA sink capability
Pull-up resistors can be
specified for each individual bit
(Address output/data I/O port when
selecting a multiplexed bus)
P1_0/A8
External memory access
Address output port
8-bit I/O port
I/O
I/O
Pull-up resistors can be
specified for each individual bit
O
O
O
O
to
P1_7/A15
P2_0/A16
to
P2_3/A19
4-bit I/O port
External memory access
Address output port
Pull-up resistors can be
specified for each individual bit
P3_0/ALE
4-bit I/O port
External memory access
Address latch enable signal
output pin
10 mA sink capability
Pull-up resistors can be
specified for each individual bit
P3_1/PSEN
External program memory
access
I/O
Read strobe output pin
P3_2/RD
P3_3/WR
External memory access
Read strobe output pin
O
O
External memory access
Write strobe output pin
P4_0/A0
to
8-bit I/O port
External memory access
Address output port
(When selecting a separate bus
type)
Pull-up resistors can be
specified for each individual bit
I/O
I/O
O
P4_7/A7
P5_4/CPCM0
P5_5/CPCM1
4-bit I/O port
Capture 0 input / Compare
0 output pin
I/O
I/O
Pull-up resistors can be
specified for each individual bit
Capture 1 input / Compare
1 output pin
P5_6/TM0OUT
P5_7/TM0EVT
P6_0/EXINT0
P6_1/EXINT1
P6_2/EXINT2
P6_3/EXINT3
P6_4/TM1EVT
P6_5/TM1OUT
P6_6/TM2EVT
P6_7/TM2OUT
O
I
Timer 0 timer output pin
Timer 0 external event input pin
External interrupt 0 input pin
External interrupt 1 input pin
External interrupt 2 input pin
External interrupt 3 input pin
Timer1 external event input pin
Timer 1 timer output pin
8-bit I/O port
I
Pull-up resistors can be
specified for each individual bit
I
I
I
I/O
I
O
I
Timer 2 external event pin
Timer 2 timer output pin
O
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MSM66577 Family
Description
Function
Symbol
Primary function
Secondary function
Type
I/O
Type
O
Port
P7_6/PWM0OUT
P7_7/PWM1OUT
2-bit I/O port
Pull-up resistors can be
PWM0 output pin
PWM1 output pin
O
specified for each individual bit
P8_0/RXD1
7-bit I/O port
I
O
I/O
I/O
O
O
O
I
SIO1 receive data input pin
SIO1 transmit data output pin
SIO1 receive clock I/O pin
SIO1 transmit clock I/O pin
Timer 4 timer output pin
PWM2 output pin
Pull-up resistors can be
specified for each individual bit
P8_1/TXD1
P8_2/RXC1
P8_3/TXC1
I/O
I/O
P8_4/TM4OUT
P8_6/PWM2OUT
P8_7/PWM3OUT
P9_0/EXINT4
P9_1/EXINT5
P9_2/EXINT6
P9_3/EXINT7
P9_7/HLDACK
P10_3/SIOCK4
P10_4/SIOO4
P10_5/SIOI4
P11_0/WAIT
PWM3 output pin
5-bit I/O port
External Interrupt 4 input pin
External Interrupt 5 input pin
External Interrupt 6 input pin
External Interrupt 7 input pin
HOLD mode output pin
Pull-up resistors can be
specified for each individual bit
I
I
I
O
I/O
I
3-bit I/O port
SIO4 transmit-receive clock I/O pin
SIO4 receive data input pin
SIO4 transmit data output pin
Pull-up resistors can be
specified for each individual bit
I/O
I/O
I
O
4-bit I/O port
External data memory access
wait input pin
I
10 mA sink capability
Pull-up resistors can be
P11_1/HOLD
P11_2/CLKOUT
P11_3/XTOUT
P12_0/AI0
I
HOLD mode request input pin
Main clock pulse output pin
Sub clock pulse output pin
A/D converter analog input port
specified for each individual bit
O
O
8-bit input port
to
I
P12_7/AI7
P14_0/SIOCK5
5-bit I/O port
SIO5 transmit-receive clock I/O
pin
I/O
Pull-up resistors can be
specified for each individual bit
P14_1/SIOO5
P14_2/SIOI5
P14_6/AO0
P14_7/AO1
P15_0/RXD6
P15_1/TXD6
P15_2/RXC6
P15_3/TXC6
O
I
SIO5 transmit data output pin
SIO5 receive data input pin
D/A converter analog output port
D/A converter analog output port
SIO6 receive data input pin
SIO6 transmit data output pin
SIO6 receive clock I/O pin
I/O
I/O
O
O
I
4-bit I/O port
Pull-up resistors can be
specified for each individual bit
O
I/O
I/O
SIO6 transmit clock I/O pin
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MSM66577 Family
Function
Symbol
VDD
Type
I
Description
Power
supply
Power supply pin
Connect all VDD pins to the power supply.*
GND
I
GND pin
Connect all GND pins to GND.*
VREF
AGND
XT0
I
I
I
Analog reference voltage pin
Analog GND pin
Oscillation
Sub clock oscillation input pin
Connect to a crystal oscillator of f = 32.768 kHz.
XT1
O
I
Sub clock oscillation output pin
Connect to a crystal oscillator of f = 32.768 kHz.
The clock output is opposite in phase to XT0.
OSC0
OSC1
Main clock oscillation input pin
Connect to a crystal or ceramic oscillator. Or, input an external
clock.
O
Main clock oscillation output pin
Connect to a crystal or ceramic oscillator.
The clock output is opposite in phase to OSC0.
Leave this pin unconnected when an external clock is used.
Reset
Other
RES
NMI
EA
I
I
I
Reset input pin
Non-maskable interrupt input pin
External program memory access input pin
If the EA pin is enabled (low level), the internal program memory is
masked and the CPU executes the program code in external
program memory through all address space.
SELMBUS
I
SELMBUS = H: Address/data separate bus type
SELMBUS = L: Multiplexed bus type
* Each of the family devices has unique pattern routes for the internal power and ground. Connect the
power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one
or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it
can not be guaranteed for normal operation.
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MSM66577 Family
ABSOLUTE MAXIMUM RATINGS
Parameter
Digital power supply
voltage
Symbol
VDD
Condition
MSM66577/Q577
Rating
Unit
V
–0.3 to +7.0
MSM66577L/Q577LY
–0.3 to +4.6
V
Input voltage
VI
VO
—
—
—
—
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to VREF
V
GND = AGND = 0 V
Ta = 25°C
Output voltage
V
Analog reference voltage
Analog input voltage
VREF
VAI
V
V
Ta = 70°C
per package
Power dissipation
PD
100-pin TQFP
650
mW
°C
Storage Temperature
TSTG
—
–50 to +150
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Range
Unit
V
MSM66577
f
f
f
f
OSC ≤ 30 MHz
4.5 to 5.5
4.5 to 5.5
2.4 to 3.6
MSM66Q577
MSM66577L
OSC ≤ 30 MHz
OSC ≤ 14 MHz
OSC ≤ 14 MHz
Digital power supply voltage
VDD
MSM66Q577LY
3.0 to 3.6
VDD –0.3 to VDD
AGND to VREF
2.0 to 5.5
Analog reference voltage
Analog input voltage
Memory hold voltage
VREF
VAI
—
—
V
V
V
VDDH
fOSC = 0 Hz
MSM66577 VDD = 4.5 to 5.5 V
2 to 30
MSM66Q577
MSM66577L
V
DD = 4.5 to 5.5 V
DD = 2.4 to 3.6 V
2 to 30
2 to 14
fOSC
MHz
Operating frequency
V
MSM66Q577LY
V
DD = 3.0 to 3.6V
2 to 14
32.768
–30 to +70
20
fXT
Ta
—
kHz
°C
—
Ambient temperature
Fan out
—
MOS load
P0, P3, P11
6
—
N
P1, P2, P4, P5, P6,
P7, P8, P9, P10,
P14, P15
TTL load
1
—
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MSM66577 Family
ALLOWABLE OUTPUT CURRENT VALUES
MSM66577/Q577 (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Pin
Symbol
IOH
Min.
—
Typ.
—
Max.
–2
Unit
“H” output pin (1 pin)
“H” output pins (sum total)
All output pins
Sum total of all output pins
P0, P3, P11
∑IOH
—
—
–40
10
“L” output pin (1 pin)
IOL
—
—
Other ports
5
Sum total of P0, P3, P11
Sum total of P1, P2, P4
Sum total of P5, P6, P9
Sum total of P7, P8, P10, P14, P15
Sum total of all output pins
80
mA
“L” output pins (sum total)
[Note]
∑IOL
—
—
50
140
Each of the family devices has unique pattern routes for the internal power and ground. Connect the
power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one
or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it
can not be guaranteed for normal operation.
INTERNAL FLASH ROM PROGRAMMING CONDITIONS
Parameter
Supply Voltage
Symbol
VDD
Condition
MSM66Q577
MSM66Q577LY
During Read
During Programming
—
Rating
4.5 to 5.5
3.0 to 3.6
-30 to +70
+0 to +50
100
Unit
V
°C
Ambient Temperature
Ta
Endurance
Blocks size
CEP
—
Cycles
bytes
—
128
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MSM66577 Family
ELELCTRICAL CHARACTERISTICS
DC Characteristics 1 (VDD = 4.5 to 5.5 V)
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
“H” input voltage
“H” input voltage *2,*3,*4,*5,*6
“L” input voltage *1
“L” input voltage *2,*3,*4,*5,*6
Symbol
VIH
Condition
—
Min.
0.44VDD
0.80VDD
–0.3
–0.3
VDD–0.4
VDD–0.6
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
VDD+0.3
VDD+0.3
0.16VDD
0.2VDD
—
Unit
*1
VIL
—
IO = –400 µA
IO = –2.0 mA
IO = 3.2 mA
IO = 10.0 mA
IO = 1.6 mA
IO = 5.0 mA
“H” output voltage
“L” output voltage
“L” output voltage
*1, *2, *4
VOH
V
—
0.4
*1, *4
*2
—
0.8
VOL
—
0.4
—
0.8
Input leakage current *3
—
1/–1
Input current
Input current
*5
*6
IIH/IIL
VI = VDD/0 V
—
1/–250
15/–15
µA
—
Output leakage current
*1, *2, *4
ILO
VO = VDD/0 V
VI = 0 V
—
—
±10
µA
kΩ
pF
pull
R
Pull-up resistance
Input capacitance
Output capacitance
25
—
—
—
—
50
5
100
—
—
4
CI
f = 1 MHz, Ta = 25°C
CO
7
During A/D operation
When A/D is stopped
—
—
mA
µA
Analog reference supply
current
IREF
10
*1: Applicable to P0
*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15
*3: Applicable to P12, SELMBUS, EA, NMI
*4: Applicable to P3, P11
*5: Applicable to RES
*6: Applicable to OSC0
Supply current (VDD=4.5 to 5.5 V)
(VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Mode
Symbol
IDD
Condition
f=30 MHz
f=32.768 kHz
f=30 MHz
Min.
—
—
—
—
—
Typ.
60
80
40
5
Max.
90
180
60
110
100
Unit
mA
µA
CPU operation mode *1
HALT mode *2
IDDH
mA
XT is used
XT is not used
OSC is stopped, XT is not used
VDD=2 V, Ta=25°C
OSC is
stopped
1
STOP mode *3
IDDS
µA
—
0.2
10
[Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
*1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used).
12/34
PEDL66577-01
1Semiconductor
MSM66577 Family
DC Characteristics 2 (VDD = 2.4 to 3.6 V)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
“H” input voltage
Symbol
VIH
Condition
MSM66577L
MSM66Q577LY
—
Min.
0.44VDD
0.55VDD
0.80VDD
–0.3
–0.3
VDD–0.4
VDD–0.8
VDD–0.4
VDD–0.8
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
5
Max.
VDD+0.3
VDD+0.3
VDD+0.3
0.16VDD
0.2VDD
—
Unit
*1
“H” input voltage *2,*3,*4,*5,*6
“L” input voltage *1
“L” input voltage *2,*3,*4,*5,*6
VIL
—
IO = –400 µA
IO = –2.0 mA
IO = –200 µA
IO = –1.0 mA
IO = 3.2 mA
IO = 5.0 mA
IO = 1.6 mA
IO = 2.5 mA
“H” output voltage
“H” output voltage
“L” output voltage
“L” output voltage
*1, *4
*2
—
V
VOH
—
—
0.5
*1, *4
*2
—
0.9
VOL
—
0.5
—
0.9
Input leakage current *3
—
1/–1
1/–250
15/–15
±10
Input current
Input current
*5
*6
IIH/IIL
VI = VDD/0 V
—
µA
—
Output leakage current *1, *2, *4
Pull-up resistance
ILO
VO = VDD/0 V
VI = 0 V
—
µA
pull
R
40
200
kΩ
Input capacitance
CI
—
—
f = 1 MHz, Ta = 25°C
pF
Output capacitance
CO
—
7
—
During A/D operation
When A/D is stopped
—
—
—
2
mA
µA
Analog reference supply current
*1: Applicable to P0
IREF
—
5
*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15
*3: Applicable to P12
*4: Applicable to P3, P11, SELMBUS, EA, NMI
*5: Applicable to RES
*6: Applicable to OSC0
Supply current (VDD=2.4 to 3.6 V)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Mode
Symbol
IDD
Condition
f=14 MHz
f=32.768 kHz
f=14 MHz
Min.
—
—
—
—
Typ.
15
50
10
3
Max.
30
150
20
110
100
Unit
mA
µA
CPU operation mode *1
HALT mode *2
IDDH
mA
XT is used*
XT is not used*
OSC is stopped, XT is not used
VDD=2 V, Ta=25°C*
OSC is
stopped
—
1
STOP mode *3
IDDS
µA
—
0.2
10
[Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
*1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used).
13/34
PEDL66577-01
1Semiconductor
MSM66577 Family
AC Characteristics 1 (VDD = 4.5 to 5.5 V)
(1) Separate Bus Type
External program memory control
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
13
Max.
Unit
fOSC = 30 MHz
—
—
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
PSEN pulse width
PSEN pulse delay time
Address setup time
tφWH
tφWL
tPW
13
—
2 tφ – 15
—
—
tPD
45
ns
tAS
CL = 50 pF
tφ – 25
0
—
Address hold time
tAH
—
Instruction setup time
Instruction hold time
tIS
25
—
tIH
0
—
Read data access time
tACC
—
3 tφ – 65
Note: tφ = tcyc/2
tcyc
CPUCLK
tφ
tφ
WL
WH
PSEN
tPD
tPW
A0 to A19
D0 to D7
PC0 to 19
tAH
tAS
INST0 to 7
tIS
tIH
tACC
Bus timing during no wait cycle time
14/34
PEDL66577-01
1Semiconductor
MSM66577 Family
External data memory control
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
13
Max.
—
Unit
fOSC = 30 MHz
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
RD pulse width
tφWH
tφWL
tRW
—
13
—
2 tφ – 15
2 tφ – 15
—
—
WR pulse width
tWW
tRD
tWD
tAS
—
RD pulse delay time
WR pulse delay time
Address setup time
Address hold time
45
—
45
ns
CL = 50 pF
tφ – 25
tφ – 3
25
—
tAH
—
Read data setup time
Read data hold time
Read data access time
Write data setup time
Write data hold time
tRS
—
tRH
0
—
tACC
tWS
—
3tφ –65
—
2tφ – 30
tφ – 3
tWH
—
tcyc
Note: tφ = tcyc/2
CPUCLK
tφWH
tφWL
RD
tRD
tRW
A0 to A19
RAP0 to 19
tAS
tAH
DIN0 to 7
tRS
D0 to D7
tRH
tACC
WR
tWD
tWW
RAP0 to 19
A0 to A19
D0 to D7
tAS
tAH
DOUT0 to 7
tWS
tWH
Bus timing during no wait cycle time
15/34
PEDL66577-01
1Semiconductor
MSM66577 Family
(2) Multiplexed bus type
External program memory control
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
Condition
Min.
33.3
Max.
—
Unit
tcyc
tφWH
tφWL
TAW
tPW
fOSC = 30 MHz
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
13
—
13
—
2 tφ – 10
2 tφ – 15
tφ – 3
2tφ – 15
tφ – 3
3tφ – 25
0
—
PSEN pulse width
—
PSEN pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Instruction setup time
Instruction hold time
tPAD
tALS
tALH
tAHS
tAHH
tIS
—
ns
CL = 50 pF
—
—
—
—
25
—
tIH
0
tφ – 3
Note: tφ = tcyc/2
tcyc
CPUCLK
tφWH
tφWL
tAW
ALE
PSEN
tPAD
tPW
AD0 to AD7
A8 to A19
PC0 to 7
INST0 to 7
tIS
tIH
tALS
tALH
PC8 to 19
tAHH
tAHS
Bus timing during no wait cycle time
16/34
PEDL66577-01
1Semiconductor
MSM66577 Family
External data memory control
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
Max.
—
Unit
fOSC = 30 MHz
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
tφWH
tφWL
tAW
13
—
13
—
2 tφ – 10
2 tφ – 15
2 tφ – 15
tφ – 3
tφ – 3
2 tφ – 15
tφ – 3
3 tφ – 25
tφ – 3
25
—
RD pulse width
WR pulse width
tRW
—
tWW
tRAD
tWAD
tALS
tALH
tAHS
tAHH
tRS
—
RD pulse delay time
WR pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Read data setup time
Read data hold time
Write data setup time
Write data hold time
—
—
ns
CL = 50 pF
—
—
—
—
—
tRH
0
tφ – 3
—
tWS
2tφ – 30
tφ – 3
tWH
—
tcyc
Note: tφ = tcyc/2
CPUCLK
tφWH
tφWL
tAW
ALE
RD
tRW
tRAD
A
DIN0 to 7
RAP0 to 7
AD0 to AD7
A8 to A19
WR
tRH
tALS
tALH
tRS
RAP8 to 19
tAHH
tAHS
tWAD
tWW
DOUT0 to 7
RAP0 to 7
AD0 to AD7
A8 to A19
tWH
tALS
tALH
tWS
RAP8 to 19
tAHH
tAHS
Bus timing during no wait cycle time
17/34
PEDL66577-01
1Semiconductor
MSM66577 Family
(3) Serial port control
Serial ports 1 and 6 (SIO1 and 6)
Master mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
Max.
—
Unit
fOSC = 30 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
4 tcyc
2 tφ – 5
5 tφ – 10
13
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
ns
CL = 50 pF
—
—
0
—
Note: tφ = tcyc/2
tcyc
CPUCLK
TXC/RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
18/34
PEDL66577-01
1Semiconductor
MSM66577 Family
Slave mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
Max.
—
Unit
fOSC = 30 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
4 tcyc
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
2 tφ – 15
4 tφ – 10
13
—
ns
CL = 50 pF
—
—
3
—
Note: tφ = tcyc/2
tcyc
CPUCLK
TXC/RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXH
tSRMXS
19/34
PEDL66577-01
1Semiconductor
MSM66577 Family
Serial ports 4 and 5 (SIO4 and 5)
Master mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
Max.
—
Unit
fOSC = 30 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
6 tcyc
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
6 tφ – 5
4.5 tφ – 10
13
—
ns
CL = 50 pF
—
—
0
—
Note: tφ = tcyc/2
tcyc
CPUCLK
SIOCK
tSCKC
SDOUT
(SIOO)
tSTMXH
tSTMXS
SDIN
(SIOI)
tSRMXS
tSRMXH
20/34
PEDL66577-01
1Semiconductor
MSM66577 Family
Slave mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3
Max.
—
Unit
fOSC = 30 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
6 tcyc
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
3 tφ – 15
6 tφ – 10
13
—
ns
CL = 50 pF
—
—
3
—
Note: tφ = tcyc/2
tcyc
CPUCLK
SIOCK
tSCKC
SDOUT
(SIOO)
tSTMXH
tSTMXS
SDIN
(SIOI)
tSRMXS
tSRMXH
Measurement points for AC timing (except the serial port)
VDD
2.0 V
2.0 V
0.8 V
0.8 V
0 V
Measurement points for AC timing (the serial port)
VDD
0.8VDD
0.8VDD
0.2VDD
0.2VDD
0V
21/34
PEDL66577-01
1Semiconductor
MSM66577 Family
AC Characteristics 2 (VDD = 2.4 to 3.6 V)
(1) Separate Bus Type
External program memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
28
Max.
Unit
fOSC = 14 MHz
—
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
PSEN pulse width
PSEN pulse delay time
Address setup time
tφWH
tφWL
tPW
—
28
—
2 tφ – 40
—
—
tPD
95
ns
tAS
CL = 50 pF
tφ – 45
0
—
Address hold time
tAH
—
—
Instruction setup time
Instruction hold time
tIS
75
tIH
0
—
Read data access time
tACC
—
3 tφ – 120
Note: tφ = tcyc/2
tcyc
CPUCLK
tφ
tφ
WL
WH
PSEN
tPD
tPW
A0 to A19
D0 to D7
PC0 to 19
tAH
tAS
INST0 to 7
tIS
tIH
tACC
Bus timing during no wait cycle time
22/34
PEDL66577-01
1Semiconductor
MSM66577 Family
External data memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
28
Max.
—
Unit
fOSC = 14 MHz
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
RD pulse width
tφWH
tφWL
tRW
—
28
—
2 tφ – 40
2 tφ – 40
—
—
WR pulse width
tWW
tRD
tWD
tAS
—
RD pulse delay time
WR pulse delay time
Address setup time
Address hold time
95
—
95
ns
CL = 50 pF
tφ – 45
tφ – 6
75
—
tAH
—
Read data setup time
Read data hold time
Read data access time
Write data setup time
Write data hold time
tRS
—
tRH
0
—
tACC
tWS
—
3tφ –120
—
2tφ – 55
tφ – 6
tWH
—
tcyc
Note: tφ = tcyc/2
CPUCLK
tφWH
tφWL
RD
tRD
tRW
RAP0 to 19
A0 to A19
tAS
tAH
D0 to D7
DIN0 to 7
tRS
tRH
tACC
WR
tWD
tWW
RAP0 to 19
A0 to A19
D0 to D7
tAS
tAH
DOUT0 to 7
tWS
tWH
Bus timing during no wait cycle time
23/34
PEDL66577-01
1Semiconductor
MSM66577 Family
(2) Multiplexed bus type
External program memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
Condition
Min.
71.4
Max.
—
Unit
tcyc
tφWH
tφWL
tAW
tPW
tPAD
tALS
tALH
tAHS
tAHH
tIS
fOSC = 14 MHz
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
28
—
28
—
2 tφ – 15
2 tφ – 40
tφ – 6
2tφ – 25
tφ – 6
3tφ – 45
0
—
PSEN pulse width
—
PSEN pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Instruction setup time
Instruction hold time
—
ns
CL = 50 pF
—
—
—
—
75
—
tIH
0
tφ – 6
Note: tφ = tcyc/2
tcyc
CPUCLK
tφWH
tφWL
tAW
ALE
PSEN
tPAD
tPW
AD0 to AD7
A8 to A19
PC0 to 7
INST0 to 7
tIS
tALS
tIH
tALH
PC8 to 19
tAHH
tAHS
Bus timing during no wait cycle time
24/34
PEDL66577-01
1Semiconductor
MSM66577 Family
External data memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
Max.
—
Unit
fOSC = 14 MHz
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
tφWH
tφWL
tAW
28
—
28
—
2 tφ – 15
2 tφ – 40
2 tφ – 40
tφ – 6
tφ – 6
2 tφ – 25
tφ – 6
3 tφ – 45
tφ – 6
75
—
RD pulse width
WR pulse width
tRW
—
tWW
tRAD
tWAD
tALS
tALH
tAHS
tAHH
tRS
—
RD pulse delay time
WR pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Read data setup time
Read data hold time
Write data setup time
Write data hold time
—
—
ns
CL = 50 pF
—
—
—
—
—
tRH
0
tφ – 6
—
tWS
2tφ – 55
tφ – 6
tWH
—
Note: tφ = tcyc/2
tcyc
CPUCLK
tφWH
tφWL
tAW
ALE
RD
tRAD
tRW
A
DIN0 to 7
RAP0 to 7
AD0 to AD7
t
tALS
tALH
tRS
A8 to A19
RAP8 to 19
tAHH
tAHS
WR
tWAD
tWW
DOUT0 to 7
AD0 to AD7
A8 to A19
RAP0 to 7
tWH
tALS
tALH
tWS
RAP8 to 19
tAHS
tAHH
Bus timing during no wait cycle time
25/34
PEDL66577-01
1Semiconductor
MSM66577 Family
(3) Serial port control
Serial ports 1 and 6 (SIO1 and 6)
Master mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
Max.
—
Unit
fOSC = 14 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
4 tcyc
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
2 tφ – 10
5 tφ – 20
21
—
ns
CL = 50 pF
—
—
0
—
Note: tφ = tcyc/2
tcyc
CPUCLK
TXC/RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXH
tSRMXS
26/34
PEDL66577-01
1Semiconductor
MSM66577 Family
Slave mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
Max.
—
Unit
fOSC = 14 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
tSTMXS
tSTMXH
tSRMXS
tSRMXH
4 tcyc
2 tφ – 30
4 tφ – 20
21
—
—
—
—
—
ns
CL = 50 pF
7
Note: tφ = tcyc/2
tcyc
CPUCLK
TXC/RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
27/34
PEDL66577-01
1Semiconductor
MSM66577 Family
Serial ports 4 and 5 (SIO4 and 5)
Master mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
Max.
—
Unit
fOSC = 14 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
5.6 tcyc
5.6 tφ – 10
4.2 tφ – 20
21
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
ns
CL = 50 pF
—
—
0
—
Note: tφ = tcyc/2
tcyc
CPUCLK
SIOCK
tSCKC
SDOUT
(SIOO)
tSTMXH
tSTMXS
SDIN
(SIOI)
tSRMXS
tSRMXH
28/34
PEDL66577-01
1Semiconductor
MSM66577 Family
Slave mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
Max.
—
Unit
fOSC = 14 MHz
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSCKC
5.6 tcyc
2.8 tφ – 30
5.6 tφ – 20
21
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
ns
CL = 50 pF
—
—
7
—
Note: tφ = tcyc/2
tcyc
CPUCLK
SIOCK
tSCKC
SDOUT
(SIOO)
tSTMXH
tSTMXS
SDIN
(SIOI)
tSRMXH
tSRMXS
Measurement points for AC timing (except the serial port)
VDD
0.44VDD 0.44VDD
0.16VDD 0.16VDD
0V
Measurement points for AC timing (the serial port)
VDD
0.8VDD
0.8VDD
0.2VDD
0.2VDD
0V
29/34
PEDL66577-01
1Semiconductor
MSM66577 Family
A/D Converter Characteristics 1 (VDD = 4.5 to 5.5 V)
(Ta = –30 to 70°C, VDD = VREF = 4.5 to 5.5 V, AGND = GND = 0 V)
Parameter
Symbol
n
Condition
Min.
—
Typ.
10
—
Max.
—
Unit
Bit
Resolution
Refer to measurement
circuit 1
Linearity error
EL
—
±3
Analog input source
impedance
Differential linearity error
Zero scale error
ED
—
—
±2
EZS
—
—
+3
RI ≤ 5 kΩ
LSB
Full-scale error
Cross talk
EFS
ECT
—
—
—
—
–3
±1
t
conv = 10.7 µs
Refer to measurement
circuit 2
Set according to
ADTM set data
Conversion time
tCONV
10.7
—
—
µs/ch
A/D Converter Characteristics 2 (VDD = 2.4 to 3.6 V)
MSM66577L (Ta = –30 to 70°C, VDD = VREF = 2.4 to 3.6 V, AGND = GND = 0 V)
MSM66Q577LY (Ta = –30 to 70°C, VDD = VREF = 3.0 to 3.6 V, AGND = GND = 0 V)
Parameter
Symbol
n
Condition
Min.
—
Typ.
10
—
Max.
—
Unit
Bit
Resolution
Refer to measurement
circuit 1
Linearity error
EL
—
±4
Analog input source
impedance
Differential linearity error
Zero scale error
ED
—
—
±3
EZS
—
—
+4
RI ≤ 5 kΩ
LSB
Full-scale error
Cross talk
EFS
ECT
—
—
—
—
–4
±2
t
conv = 10.7 µs
Refer to measurement
circuit 2
Set according to
ADTM set data
Conversion time
tCONV
27.4
—
—
µs/ch
Reference
voltage
VREF
VDD
+5 V / +3V
+
+
0.1
47
µF
µF
0.1
µF
47
µF
RI
–
AI0 to AI7
+
AGND
GND
0 V
Analog input
CI
RI (impedance of analog input source) ≤5 kΩ
CI 0.1 µF
Measurement Circuit 1
30/34
PEDL66577-01
1Semiconductor
MSM66577 Family
5 kΩ
Cross talk is the difference
–
+
AI0
between the A/D conversion
results when the same
analog input is applied to AI0
through AI7 and the A/D
conversion results of the
circuit to the left.
AI1
to
Analog input
0.1 µF
AI7
VREF or AGND
Measurement Circuit 2
Definition of Terminology
1. Resolution
Resolution is the value of minimum discernible analog input.
With 10 bits, since 210 = 1024, resolution of (VREF – AGND) ÷ 1024 is possible.
2. Linearity error
Linearity error is the difference between ideal conversion characteristics and actual conversion
characteristics of a 10-bit A/D converter (not including quantization error).
Ideal conversion characteristics can be obtained by dividing the voltage between VREF and AGND into 1024
equal steps.
3. Differential linearity error
Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog
input voltage that corresponds to 1 converted bit of digital output is 1LSB = (VREF – AGND) ÷ 1024.
Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion
range.
4. Zero scale error
Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics
at the point where the digital output changes from 000H to 001H.
5. Full-scale error
Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics
at the point where the digital output changes from 3FEH to 3FFH.
31/34
PEDL66577-01
1Semiconductor
MSM66577 Family
D/A Converter Characteristics
MSM66577/Q577 (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C)
MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = –30 to +70°C)
Parameter
Resolution
Symbol
n
Condition
Min.
—
Typ.
—
Max.
8
Unit
Bit
Linearity error
EL
—
—
—
±1
±2
50
—
LSB
Absolute precision
Conversion time
Analog output impedance
—
—
—
tCONV
—
CL = 50 pF
—
—
20
20
µs
—
kΩ
Definition of Terminology
1. Resolution
Resolution is the value of minimum discernible analog output.
With 8 bits, since 28 = 256, resolution of (VDD – GND) ÷ 256 is possible.
2. Linearity error
Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of
an 8-bit D/A converter.
Ideal conversion characteristics can be obtained by dividing the voltage between VDD and GND into 256 equal
steps.
3. Differential linearity error
Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog
input voltage that corresponds to 1 converted bit of digital input is 1LSB = (VDD – GND) ÷ 256. Differential error
is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range.
4. Absolute precision
Absolute precision is a gross error including a linearity error and the effect of noise.
32/34
PEDL66577-01
1Semiconductor
MSM66577 Family
PACKAGE DIMENSIONS
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.55 TYP.
4/Oct. 28, 1996
5
Notes for Mounting the Surface Mount Type Packages
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
33/34
PEDL66577-01
1Semiconductor
MSM66577 Family
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2000 Oki Electric Industry Co., Ltd.
34/34
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