MSM7533HRS [OKI]
PCM Codec, MU-Law, 1-Func, CMOS, PDIP20, 0.300 INCH, 2.54 PITCH, SKINNY, PLASTIC, DIP-20;
| 型号： | MSM7533HRS |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | PCM Codec, MU-Law, 1-Func, CMOS, PDIP20, 0.300 INCH, 2.54 PITCH, SKINNY, PLASTIC, DIP-20 PC 电信 光电二极管 电信集成电路 |
| 文件： | 总18页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0020-28-81
This version: Aug. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7533H/7533V/7534
2ch Single Rail CODEC
GENERAL DESCRIPTION
The MSM7533 and MSM7534 are two-channel CODEC CMOS ICs for voice signals ranging from
300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices
contain two-channel AD/DA converters in a single chip and achieve a reduced footprint and a
reduced number of external components.
TheMSM7533andMSM7534arebestsuitedforananaloginterfacetoanechocancellerDSPused
in digital telephone terminals, digital PABXs, and hands free terminals.
FEATURES
• Single power supply: +5 V
• Power consumption
Operating mode:
Power save mode:
Power down mode:
35 mW Typ.
7 mW Typ.
0.05 mW Typ.
74 mW Max.
16 mW Max.
0.3 mW Max.
V
DD
V
DD
V
DD
= 5 V
= 5 V
= 5 V
• ITU-T Companding law
MSM7533H:
MSM7534:
MSM7533V:
m-law
A-law
m/A-law pin selectable
• Built-in PLL eliminates a master clock
• The PCM interface can be switched between 2 channel serial/parallel
• Transmission clock: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
(During 2 channel serial mode, the 64 and 96 kHz clocks are disabled)
• Adjustable transmit gain
• Built-in reference voltage supply
• Analog output can directly drive a 600 W line transformer
• Package options:
20-pin plastic skinny DIP (DIP20-P-300-2.54-S1) (Product name : MSM7533HRS)
(Product name : MSM7533VRS)
(Product name : MSM7534RS)
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name : MSM7533HGS-K)
(Product name : MSM7533VGS-K)
(Product name : MSM7534GS-K)
1/18
¡ Semiconductor
MSM7533H/7533V/7534
BLOCK DIAGRAM
DOUT1
AIN1
–
+
RC
LPF
8th
BPF
AD
CONV.
DOUT2
TCONT
GSX1
AIN2
–
+
RC
LPF
8th
BPF
XSYNC
PLL
GSX2
AUTO
ZERO
BCLK
RTIM
5th
LPF
RSYNC
S&H
–
+
AOUT1
AOUT2
(ALAW)
DA
CONV.
5th
LPF
S&H
–
+
CHPS
DIN1
DIN2
RCONT
PDN
PWD
Logic
SG
GEN
VR
GEN
VDD
AG
DG
SGC
2/18
¡ Semiconductor
MSM7533H/7533V/7534
PIN CONFIGURATION (TOP VIEW)
SGC 1
AOUT2 2
AOUT1 3
PDN 4
20 AIN2
SGC 1
AOUT2 2
NC 3
24 AIN2
23 GSX2
22 GSX1
21 AIN1
20 NC
19 GSX2
18 GSX1
17 AIN1
AOUT1 4
PDN 5
CHPS 6
NC 7
19 (ALAW) *
18 AG
CHPS 5
16 (ALAW) *
15 AG
VDD
8
17 NC
V
6
DD
DG 9
RSYNC 10
DIN2 11
16 BCLK
15 XSYNC
14 DOUT2
13 DOUT1
DG 7
14 BCLK
13 XSYNC
12 DOUT2
11 DOUT1
RSYNC 8
DIN2 9
DIN1 12
NC : No connect pin
24-Pin Plastic SOP
DIN1 10
20-Pin Plastic Skinny DIP
* The ALAW pin is only applied to the MSM7533VRS/MSM7533VGS-K.
3/18
¡ Semiconductor
MSM7533H/7533V/7534
PIN AND FUNCTIONAL DESCRIPTIONS
AIN1, AIN2, GSX1, GSX2
AIN1 and AIN2 are the transmit analog inputs for channels 1 and 2.
GSX1 and GSX2 are the transmit level adjustments for channels 1 and 2.
AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output
of the op-amp and are used to adjust the level, as shown below.
WhennotusingAIN1andAIN2,connectAIN1toGSX1andAIN2toGSX2.Duringpowersaving
and power down mode, the GSX1 and GSX2 outputs are at AG voltage.
R2
R4
GSX1
AIN1
CH1 Gain
Gain = R2/R1 £ 10
R1: Variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)
C1
C2
R1
R3
CH1
Analog Input
–
+
GSX2
AIN2
CH2 Gain
Gain = R4/R3 £ 10
R3: Variable
R4 > 20 kW
C2 > 1/(2 ¥ 3.14 ¥ 30 ¥ R3)
CH2
Analog Input
–
+
AOUT1, AOUT2
AOUT1 is the receive analog output for channel 1 and AOUT2 is used for channel 2.
The output signal has an amplitude of 3.4 V above and below the signal ground voltage (SG).
PP
When the digital signal of +3 dBmO is input to DIN1 and DIN2, it can drive a load of 600 W or
more.
During power saving or power down mode, these outputs are at the voltage level of SG with a
high impedance.
4/18
¡ Semiconductor
MSM7533H/7533V/7534
V
DD
Power supply for +5 V.
A power supply for an analog circuit of the system which the device is applied should be used.
A bypass capacitor of 0.1 mF to 1 mF with excellent high frequency characteristics and a capacitor
of 10 mF to 20 mF should be connected between this pin and the AG pin if needed.
DIN1
DIN1 is the PCM signal input for channel 1, when the parallel mode is selected.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The analog signal is output from the AOUT1 pin.
The data rate of the PCM signal is equal to the frequency of BCLK signal.
ThePCMsignalisshiftedatafallingedgeoftheBCLKsignalandlatchedintotheinternalregister
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is not used and should be connected to GND (0 V).
DIN2
DIN2 is the PCM signal input for channel 2, when the parallel mode is selected.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The analog signal is output from the AOUT2 pin.
The data rate of the PCM signal is equal to the frequency of BCLK signal.
ThePCMsignalisshiftedatafallingedgeoftheBCLKsignalandlatchedintotheinternalregister
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is used for the 2ch multiplexed PCM signal input.
BCLK
Shift clock signal input for the DIN1, DIN2, DOUT1, and DOUT2 signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.
5/18
¡ Semiconductor
MSM7533H/7533V/7534
RSYNC
Receive synchronizing signal input.
The eight bits PCM data required are selected from serial PCM signals on the DIN1 and DIN2
pins by the receive synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK (generated from the same clock source as BCLK). The
frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the
frequency characteristic of the receive section.
However, if the frequency characteristic of the system used is not strictly specified, this device
can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics in this specifications
are not guaranteed.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the DOUT1 and DOUT2 pins is output in synchronization with this
transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all
timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
the frequency characteristic of the transmit section.
However, if the frequency characteristic of the system used is not strictly specified, this device
can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics in this specification
are not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving
state.
6/18
¡ Semiconductor
MSM7533H/7533V/7534
DOUT1
PCM signal output of channel 1 when the parallel mode is selected.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance sate during power saving or power down mode.
When the serial mode is selected, this pin is for the output of serial multiplexed 2ch PCM signal.
A pull-up resistor must be connected to this pin because it is an open drain output.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7534(A-law) outputs the character signal, inverting the even bits.
PCMIN/PCMOUT
Input/Output Level
MSM7533H (m-law)
MSM7534 (A-law)
MSD
MSD
+Full scale
+0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
–0
–Full scale
DOUT2
PCM signal outputs for channel 2 when the parallel mode is selected.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down modes.
When the serial mode is selected, this pin is left open.
A pull-up resistor must be connected to this pin because it is an open drain output.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7534(A-law) outputs the character signal, inverting the even bits.
7/18
¡ Semiconductor
MSM7533H/7533V/7534
CHPS
Control signal input for the mode selection of PCM input and output.
When this signal is at a logic "1" level, the PCM input and output are in the parallel mode. The
PCM data of CH1 and CH2 is input to DIN1 and DIN2, and output from DOUT1 and DOUT2
with the same timing.
When this signal is at a logic "0" level, the PCM input and output is in the serial mode. The PCM
data of CH1 and CH2 is input to DIN2 and output from DOUT1 as time division multiplexed
data.
Theparallelmodeisconvenientlyappliedtothedigitalinterfacetotheechocanceller(MSM7520),
and the serial mode is applied to the digital interface to PCM multiplexer's for PABXs.
PDN
Power down control signal.
When PDN is at a logic "0" level, both transmit and receive circuits are in a power down state.
AG
Analog signal ground.
DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.
SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
ALAW
Control signal input of the companding law selection.
Provides only for the MSM7533VRS/MSM7533VGS-K. The CODEC will operate in the m-law
when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at
alogic"1"level. TheCODECoperatesinthem-lawifthepinisleftopen, sincethispinisinternally
pulled down.
8/18
¡ Semiconductor
MSM7533H/7533V/7534
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
Rating
0 to 7
Unit
V
—
—
—
—
VAIN
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–55 to +150
V
VDIN
TSTG
V
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Analog Input Voltage
Symbol
Condition
Min.
Typ.
5.0
Max.
Unit
V
VDD Voltage must be fixed
4.75
–30
—
5.25
+85
3.4
Ta
—
+25
—
°C
VAIN Gain = 1
VPP
Digital Input High Voltage
Digital Input Low Voltage
VIH
2.2
0
—
—
VDD
0.8
V
V
XSYNC, RSYNC, BCLK,
DIN1, DIN2, PDN, CHPS
VIL
FC
64, 128, 256, 512, 1024,
2048, 96, 192, 384, 768,
1536, 1544, 200
BCLK = (eliminates 64, 96 kHz,
when 2ch serial mode)
Clock Frequency
kHz
Sync Pulse Frequency
Clock Duty Ratio
FS
DC
tIr
XSYNC, RSYNC
6.0
40
8.0
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9.0
60
kHz
%
BCLK
Digital Input Rise Time
Digital Input Fall Time
XSYNC, RSYNC, BCLK, DIN1,
DIN2, PDN, CHPS
—
50
ns
ns
ns
ns
ns
ns
ms
ns
ns
kW
pF
tIf
—
50
tXS
tSX
tRS
tSR
BCLKÆXSYNC, See Timing Diagram
XSYNCÆBCLK, See Timing Diagram
BCLKÆRSYNC, See Timing Diagram
RSYNCÆBCLK, See Timing Diagram
100
100
100
100
1 BCLK
100
100
0.5
—
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
—
—
—
Sync Pulse Width
DIN Set-up Time
DIN Hold Time
tWS XSYNC, RSYNC
tDS DIN1, DIN2
100
—
tDH DIN1, DIN2
—
RDL Pull-up resistor, DOUT1, DOUT2
CDL DOUT1, DOUT2
—
Digital Output Load
—
100
Transmit gain stage, Gain = 1 VDD/2–100
Transmit gain stage, Gain = 10 VDD/2–10
VDD/2+100 mV
VDD/2+10 mV
Analog Input Allowable DC Offset
Allowable Jitter Width
Voff
—
XSYNC, RSYNC
—
500
ns
9/18
¡ Semiconductor
MSM7533H/7533V/7534
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = +5 V 5%, Ta = –30°C to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
IDD1 Operating mode, No signal
—
7.0
14.0
mA
Power-save mode, PDN = 1,
Power Supply Current
IDD2
—
1.3
3.0
mA
XSYNC or BCLK OFF
IDD3 Power-down mode, PDN = 0
—
2.2
0.0
—
0.01
—
—
—
—
0.2
—
5
0.05
VDD
0.8
2.0
0.5
0.4
10
mA
V
Input High Voltage
VIH
VIL
IIH
IIL
—
—
—
—
Input Low Voltage
V
High Level Input Leakage Current
Low Level Input Leakage Current
Digital Output Low Voltage
Digital Output Leakage Current
Input Capacitance
mA
mA
V
—
VOL Pull-up resistance > 500 W
0.0
—
IO
—
—
mA
pF
CIN
—
—
Transmit Analog Interface Characteristics
(VDD = +5 V 5%, Ta = –30°C to +85°C)
Parameter
Input Resistance
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
MW
kW
pF
RINX AIN1, AIN2
RLGX GSX1, GSX2
CLGX with respect to SG
VOGX
Output Load Resistance
Output Load Capacitance
Output Amplitude
20
—
—
—
—
30
–1.7
–20
—
+1.7
+20
V
Offset Voltage
VOSGX
Gain = 1
—
mV
Receive Analog Interface Characteristics
(VDD = +5 V 5%, Ta = –30°C to +85°C)
Parameter
Symbol
Condition
AOUT1, AOUT2 (each) with
respect to SG
Min.
Typ.
Max.
Unit
kW
pF
Output Load Resistance
RLAO
0.6
—
—
CLAO AOUT1, AOUT2
—
—
50
Output Load Capacitance
Output Amplitude
AOUT1, AOUT2, RL = 0.6 kW,
VOAO
–1.7
—
+1.7
V
with respect to SG
AOUT1, AOUT2
Offset Voltage
VOSAO
–100
—
+100
mV
with respect to SG
10/18
¡ Semiconductor
AC Characteristics
Parameter
MSM7533H/7533V/7534
(VDD = +5 V 5%, Ta = –30°C to +85°C)
Freq.
(Hz)
Level
(dBm0)
Symbol
Condition Min.
Typ.
Max.
Unit
Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
LossR1
LossR2
LossR3
LossR4
LossR5
SD T1
SD T2
60
300
20
26
+0.07
Reference
–0.04
+0.06
0.4
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
–0.15
+0.20
1020
2020
3000
3400
300
Transmit Frequency Response
Receive Frequency Response
0
0
–0.15
–0.15
0
+0.20
+0.20
0.80
–0.15
–0.03
Reference
–0.02
+0.15
0.45
+0.20
1020
2020
3000
3400
–0.15
–0.15
0.0
+0.20
+0.20
0.80
—
3
35
43
0
35
41
—
Transmit Signal to Distortion Ratio SD T3
1020
–30
–40
–45
3
35
38
—
dB
dB
dB
dB
SD T4
SD T5
SD R1
SD R2
29
31.5
—
*1
24
36
36
36
27
—
43
—
0
41
—
Receive Signal to Distortion Ratio SD R3 1020
–30
–40
–45
3
40
—
SD R4
SD R5
GT T1
GT T2
30
*1
33.5
—
25
30
—
–0.3
+0.01
Reference
–0.09
–0.09
–0.1
+0.3
–10
–40
–50
–55
3
Transmit Gain Tracking
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
1020
1020
–0.3
–0.5
–1.2
–0.3
+0.3
+0.5
+1.2
+0.3
0
–10
–40
–50
–55
Reference
+0.09
+0.2
Receive Gain Tracking
–0.3
–0.5
–1.2
+0.3
+0.5
+1.2
+0.23
*1 Psophometric filter is used
11/18
¡ Semiconductor
MSM7533H/7533V/7534
AC Characteristics (Continued)
(VDD = +5 V 5%, Ta = –30°C to +85°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
Unit
AIN = SG
—
–73.5
–71.5
–78
–70
–68
–75
Nidle T
—
—
—
—
Idle Channel Noise
*1*2
dBmOp
Nidle R
AV T
*1 *3
—
VDD = 5.0 V
0.821
0.850
0.850
0.880
0.880
Absolute Level (Initial Difference)
Ta = 25°C
Vrms
AV R
AV Tt
0.821
–0.2
*4
1020
1020
0
VDD = 5 V
5%
—
—
+0.2
+0.2
dB
dB
Absolute Level
(Deviation of Temperature and Power)
Ta = –30
to 85°C *4
A to A
BCLK
AV Rt
Td
–0.2
—
Absolute Delay
0
0
—
0.6
ms
ms
= 64 kHz
*5
tgd T1
tgd T2
tgd T3
tgd T4
tgd T5
tgd R1
500
600
—
—
—
—
—
—
—
—
—
—
75
70
73
0.19
0.11
0.02
0.05
0.07
0.00
0.00
0.00
0.09
0.12
80
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
—
Transmit Group Delay
1000
2600
2800
500
*5
t
gd R2
gd R3
600
Receive Group Delay
t
1000
2600
2800
0
0
ms
dB
tgd R4
gd R5
t
CR T
CR R
TRANS Æ RECV
RECV Æ TRANS
CH to CH
1020
76
—
Crosstalk Attenuation
CR CH
78
—
*1 Psophometric filter is used
*2 Upper is specified for the m-law, lower for the A-law
*3 Input "0" code to PCMIN
*4 AVT is defined between GSX and DOUT and AVR between DIN and AOUT
*5 Minimum value of the group delay distortion
12/18
¡ Semiconductor
MSM7533H/7533V/7534
AC Characteristics (Continued)
(VDD = +5 V 5%, Ta = –30°C to +85°C)
Freq.
(Hz)
4.6 kHz to
72 kHz
300 to
3400
Level
(dBm0)
Parameter
Discrimination
Symbol
Condition Min.
Typ.
32
Max.
—
Unit
dB
0 to
DIS
S
0
0
30
4000 Hz
4.6 kHz to
—
Out-of-band Spurious
–37.5
–52
30
–35
–35
—
dBmO
dBmO
dB
100 kHz
fa = 470
fd = 320
0 to
Intermodulation Distortion
Power Supply Noise Rejection Ratio
IMD
–4
2fa – fd
*6
—
—
PSR T
50 mVPP
PSR R 50 kHz
tSD
20
20
20
20
—
—
—
—
200
200
200
200
tXD1
Digital Output Delay Time
CL = 100 pF + 1 LSTTL
ns
tXD2
tXD3
*6 The measurement under idle channel noise
13/18
¡ Semiconductor
MSM7533H/7533V/7534
TIMING DIAGRAM
Transmit Timing
BCLK
1
2
3
4
5
6
7
8
9
10
11
tXS
tSX
tWS
XSYNC
tXD1
tSD
MSD
tXD2
D3
tXD3
D8
DOUT1
DOUT2
D2
D4
D5
D6
D7
Transmit Side
Receive Timing
BCLK
1
2
3
4
5
6
7
8
9
10
11
tRS
tSR
tWS
RSYNC
tDS
tDH
DIN1
DIN2
MSD
D2
D3
D4
D5
D6
D7
D8
Receive Side
Figure. 1 Timing Diagram in the Parallel Mode (CHPS = 1)
BCLK
XSYNC
MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8
DOUT1
CH1 PCM Data
CH2 PCM Data
Transmit Side
BCLK
RSYNC
MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8
DIN2
CH1 PCM Data
CH2 PCM Data
Receive Side
Figure. 2 Timing Diagram in the Serial Mode (CHPS = 0)
14/18
¡ Semiconductor
MSM7533H/7533V/7534
APPLICATION CIRCUIT
Example of Basic Connection (PCM Serial Mode Operation)
+5 V
1 kW
MSM7533
2CH Multiplex PCM
Signal Output
AIN1
GSX1
DOUT1
DOUT2
CH1
Analog Input
(Open)
2CH Multiplex PCM
Signal Intput
AOUT1
DIN2
DIN1
CH1
Analog Output
0 V
Bit Clock Input
Sync Pulse Input
AIN2
GSX2
BCLK
CH2
Analog Input
XSYNC
RSYNC
Power Down Control Input
1: Operation
AOUT2
PDN
CH2
Analog Output
SGC
AG
DG
0.1 mF
1 mF
0: Power Down
CHPS
VDD
0 V
0 V
10 mF
+
+5 V
0 to 20 W
Example of Interface to the Echo Canceller MSM7520
MSM7533
AIN1
GSX1
AOUT1
AOUT2
GSX2
AIN2
SOUT
SIN
RIN
ROUT
+5 V
PDN
VDD
0.1 mF
+10 W
10 mF
CHPS
XSYNC
RSYNC
BCLK
SGC
AG
+5 V
1 mF
10 kW
0 V
DG
10 kW
DIN1
DOUT2
DIN2
+5 V
+5 V
DOUT1
MSM7520-001
SIN
SOUT
RIN
ROUT
SCK
NLP
GC
+5 V
SYNC
INT
IRLD
HCL
ADP
ATT
VSS
SYNCO
SCKO
RESET
RST
POWER DOWN
PWDWN
CKSEL
VDD
36 MHz CLK Input
X1
X2
+5 V
0 V
+5 V
0 V
15/18
¡ Semiconductor
MSM7533H/7533V/7534
RECOMMENDATIONS FOR ACTUAL DESIGN
• Toassureproperelectricalcharacteristics,usebypasscapacitorswithexcellenthighfrequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.
• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-
DD
up phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
powersupplytoavoiderroneousoperationandthedegradationofthecharacteristicsofthese
devices.
16/18
¡ Semiconductor
PACKAGE DIMENSIONS
DIP20-P-300-2.54-S1
MSM7533H/7533V/7534
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.49 TYP.
17/18
¡ Semiconductor
MSM7533H/7533V/7534
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/18
相关型号：
MSM7533VGS-K
PCM Codec, A/MU-Law, 2-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24
OKI
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