MSM7540GS-K [OKI]
ADPCM Codec, A-Law, 1-Func, PDSO28, PLASTIC, SOP-28;
| 型号： | MSM7540GS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | ADPCM Codec, A-Law, 1-Func, PDSO28, PLASTIC, SOP-28 PC 光电二极管 |
| 文件： | 总16页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7540-03
This version: Nov. 1999
Previous version: Aug. 1998
¡ Semiconductor
MSM7540/7560
Single Rail ADPCM CODEC
GENERAL DESCRIPTION
TheMSM7540/7560aresinglechannelADPCMCODECICswhichperformmutualtranscoding
between an analog voice band signal 300 to 3400 Hz and 32 kbps ADPCM serial data.
Using advanced circuit technology, these devices operate using a single 5 V power supply and
have low power consumption.
The MSM7540/7560 are optimized for advanced digital cordless telephone system applications.
FEATURES
• Single 5 V Power Supply Operation
• ADPCM Algorithm :
Complies completely with 1988's version ITU-T
G.721 (32 kbps)
• Transmit/Receive Full-Duplex Operation
• Transmit/Receive Synchronous Mode Only
• Serial ADPCM Transmission Data Rate :
• Serial PCM Transmission Data Rate :
• PCM Interface Coding Format
MSM7540 :
32 kbps to 2048 kbps
64 kbps to 2048 kbps
A-laworLinear(14-bit,2'scompliment)Selectable
m-laworLinear(14-bit,2'scompliment)Selectable
MSM7560 :
• Low Power Consumption
Operating Mode :
Power-Down Mode :
60 mW Typ.
1.0 mW Typ.
• Two Analog Input Amplifier Stages :
• Analog Output Stage :
Externally Adjustable Gain
Push-pull Drive (direct drive of 350 W + 120 nF)
• Built-in Crystal Oscillator (10.368 MHz)
• Built-in Reference Voltage Supply
• Option Reset Specified by ITU-T G. 721/ADPCM
• Package:
28-pin plastic SOP
(SOP28-P-430-1.27-K) (Product name: MSM7540GS-K)
(Product name: MSM7560GS-K)
1/16
VDD AG DG
X1
X2
–
+
AIN1
GSX1
AIN2
XSYNC
IS
BCLKA
0
1
1
0
P
/
–
+
A/D
Conv.
COM-
PANDER
RC-
LPF
ADPCM
CODER
BPF
S
GSX2
SG
0
1
P
/
VREF
PCMSO
S
PDN
S
/
CLOCK/
TIMING
PCMSI
BCLKB
PCMRI
MCK
P
RES
LPS
S
/
AOUT+
–1
P
1
0
P
/
–
PCMRO
AOUT–
PWI
+
S
1
0
0
1
S
/
D/A
Conv.
EX-
PANDER
RC-
LPF
ADPCM
DECODER
LPF
IR
RSYNC
VFRO
P
FEDL7540-03
MSM7540/7560
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
RES 1
PCMRI 2
PCMRO 3
28 BCLKB
27 BCLKA
26 XSYNC
25 RSYNC
24 MCK
23 X2
4
5
IR
IS
6
PCMSI
PCMSO
LPS
7
22 X1
8
21 PDN
9
20
19
18
17
16
15
DG
VDD
10
11
12
13
14
AG
AOUT+
AOUT–
PWI
SG
AIN1
GSX1
AIN2
VFRO
GSX2
28-Pin Plastic SOP
3/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
PIN AND FUNCTIONAL DESCRIPTIONS
AIN1, AIN2, GSX1, GSX2
Transmit analog inputs and the output for transmit gain adjustment.
AIN1 (AIN2) connects to the inverting input of the internal transmit amplifier. GSX1 (GSX2)
connects to the internal transmit amplifier output. Refer to Fig. 1 for gain adjustment.
VFRO, AOUT+, AOUT–, PWI
Receive analog output and the output for receive gain adjustment.
VFRO is the receive filter output. AOUT+ and AOUT– are differential analog signal outputs
which can directly drive Z = 350 W + 120 nF. Refer to Fig. 1 for gain adjustment.
L
Analog Input
C1
C2
R1
R3
AIN1
–
+
R2
R4
GSX1
AIN2
–
+
to ENCODER
GSX2
Transmit Gain:
= (R2/R1) ¥ (R4/R3)
VFRO
PWI
from DECODER
RS*
Receive Gain:
= (R6/R5)
R5
R6
AOUT–
–
+
ZL=120 nF
V0
Analog Output
+ 350 W
–1
AOUT+
* : Side Tone Pass (Gain = R6/RS)
Figure 1 Analog Input/Output Interface
4/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
SG
Analog signal ground voltage output.
The output voltage of this pin is approximately 2.4 V. Put bypass capacitors between this pin
and the AG pin. During power-down this output voltage is 0 V. The external SG voltage, if
necessary, should be used via a buffer.
AG
Analog ground.
DG
Digital ground.
This ground is separated internally from the analog signal ground pin (AG). The DG pin must
be kept as close as possible to AG on the PCB.
VDD
+5 V power supply.
LPS
PCM coding law selection.
MSM7540 only ; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
A-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).
MSM7560 only ; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
m-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).
PDN
Power down control input.
If this pin is "0", this device is in the power-down state.
Normally, this pin is set to "1".
RES
Optional reset input specified by ITU-T Recommendation G. 721.
If this pin is "0", the device is in the reset state. The reset width (during "L") should be 125ms or
more.
MCK
Master clock input.
The frequency must be 10.368 MHz. The master clock signal may be asynchronous to BCLKA,
BCLKB, XSYNC, and RSYNC.
PCMSO
Transmit PCM data output.
PCM is output from MSB in synchronization with the rising edge of BCLKB and XSYNC.
5/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
PCMSI
Transmit PCM data input.
This signal is converted to the transmit ADPCM data. PCM is shifted in synchronization with
the falling edge of BCLKB. Normally, this pin is connected to PCMSO.
PCMRO
Receive PCM data output.
PCM is the output signal after ADPCM decoder processing. This signal is output serially from
MSB in synchronization with the rising edge of BCLKB and RSYNC.
PCMRI
Receive PCM data input.
PCM is shifted on the falling edge of the BCLKB and input from MSB. Normally, this pin is
connected to PCMRO.
IS
Transmit ADPCM signal output.
After having encoded PCM with ADPCM, this signal is output from MSB in synchronization
with the rising edge of BCLKA and XSYNC . This pin is an open drain output and remains in a
high impedance state during power-down. IS requires a pull-up resistor.
IR
Receive ADPCM signal input.
The ADPCM signal is shifted in series and synchronization with the falling edge of BCLKA and
RSYNC, starting with MSB.
BCLKB
Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI).
The frequency is set in the 64 kHz to 2048 kHz range.
XSYNC
8 kHz synchronous signal input for transmit PCM and ADPCM data.
Synchronize this signal with BCLKA and BCLKB signal. XSYNC is used to indicate the MSB of
the serial PCM and ADPCM data stream.
Be sure to input the XSYNC signal because it is also used as the input of the timing generator.
RSYNC
8 kHz synchronous signal input for receive PCM and ADPCM data.
Synchronize this signal with BCLKA and BCLKB signal. RSYNC is used to indicate the MSB of
the serial PCM and ADPCM data stream.
BCLKA
Shift clock input for the ADPCM data (IS, IR).
The frequency is set in the range of 32 kHz to 2048 kHz.
6/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
X1, X2
Crystal oscillator (10.368 MHz) connection.
Connect X2, the clock output pin, directly to the MCK pin.
When using a conventional external clock of 10.368 MHz, X1 should be connected to the ground,
leave X2 open, and provide the external clock through the MCK pin.
<Using a self-oscilation circuit>
MSM7540/60
<Using an external clock>
MSM7540/60
X1
X2 MCK
X1
X2 MCK
10.368 MHz
10.368 MHz
7/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
Rating
Unit
—
—
—
—
–0.3 to +7
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–55 to +150
V
V
VAIN
VDIN
V
TSTG
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Symbol
VDD
Condition
Voltage must be fixed
—
Min.
Typ.
—
Max.
Unit
V
4.5
5.5
Ta
–25
+25
+70
°C
MCK, XSYNC, RSYNC, PCMRI,
PCMSI, BCLKA, BCLKB, IR,
LPS, PDN, RES
VIH
Input High Voltage
Input Low Voltage
2.2
0
—
—
VDD
0.6
V
V
MCK, XSYNC, RSYNC, PCMRI,
PCMSI, BCLKA, BCLKB, IR,
LPS, PDN, RES
VIL
fMCK
fBCKA
fBCKB
fSYMC
DC
Master Clock Frequency
Bit Clock Freqency
MCK
–
0.01% 10.368
+0.01% MHz
BCLKA
32
64
—
30
—
—
8.0
50
2048
kHz
kHz
kHz
%
BCLKB
2048
—
Synchronous Signal Frequency
Clock Duty Ratio
XSYNC, RSYNC
MCK, BCLKA, BCLKB
MCK, XSYNC, RSYNC, PCMRI,
PCMSI, BCLKA, BCLKB, IR,
LPS, PDN, RES
70
tIr
Digital Input Rise Time
Digital Input Fall Time
—
—
—
—
50
50
ns
ns
MCK, XSYNC, RSYNC, PCMRI,
PCMSI, BCLKA, BCLKB, IR,
LPS, PDN, RES
tIf
tXS
tXS
BCLKA, BCLKB to XSYNC
XSYNC to BCLKA, BCLKB
BCLKA, BCLKB to RSYNC
RSYNC to BCLKA, BCLKB
XSYNC, RSYNC
100
100
100
100
—
—
—
—
ns
ns
ns
ns
ms
ns
ns
W
Transmit Sync Signal Setting Time
Receive Sync Signal Setting Time
tRS
tSR
tWS
tDS
tDH
RDL
CDL
CSG
—
—
—
—
Synchronous Signal Width
PCM, ADPCM Set-up Time
PCM, ADPCM Hold Time
1 BCLK
100
100
500
—
—
100
—
—
—
—
—
—
IS (Pull-up Resistor)
IS, PCMSO, PCMRO
SG´GND
—
—
Digital Output Load
—
100
—
pF
mF
Bypass Capacitor for SG
—
10 + 0.1
8/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C)
Parameter
Symbol
Condition
Operating Mode,
Min.
Typ.
Max.
Unit
IDD1
—
12
24
mA
(When no signal, and
Power Down Mode
= 5.0 V)
VDD
Power Supply Current
IDD2
—
0.2
0.5
mA
(When
= 5.0 V)
VDD
Input High Voltage
Input Low Voltage
VIH
VIL
IIH
IIL
—
—
2.2
0.0
—
—
—
—
—
0.2
—
5
VDD
0.6
2.0
0.5
0.4
10
V
V
VI = VDD
VI = 0 V
mA
mA
V
Input Leakage Current
—
Output Low Voltage
Output Leakage Current
Input Capacitance
VOL 1 LSTTL, Pull-up: 500 W
0.0
—
IO
IS
mA
pF
CIN
—
—
—
Transmit Analog Interface Characteristics
Parameter
Input Resistance
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
MW
kW
pF
RINX AIN1, AIN2
Output Load Resistance
Output Load Capacitance
Output Amplitude
RLGX GSX1, GSX2
50
—
—
CLGX GSX1, GSX2
—
—
100
*2.226
+20
—
VOGX GSX1, GSX2, RL = 50 kW
VOFGX Pre–OPAMPs
—
—
VPP
mV
V
Input Offset Voltage
SG Output Voltage
–20
—
—
VSG
RSG
—
2.4
40
SG Output Impedance
—
—
80
kW
SG´GND 10 mF + 0.1 mF
(Rise time to 90% of max. level)
SG Rise Time
TSG
—
700
—
ms
*
–3 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 2.226 V (MSM7540)
PP
–3 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 2.226 V (MSM7560)
PP
9/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
Receive Analog Interface Characteristics
Parameter
Input Resistance
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
MW
kW
kW
pF
RINPW PWI
RLVF VFRO
50
—
—
Output Load Resistance
Output Capacitance
RLAO AOUT+, AOUT–
CLVF VFRO
1.2
—
—
—
—
100
CLAO AOUT+, AOUT–
—
—
100
pF
VOVF VFRO
RL = 50 kW
—
—
*2.226
*2.226
VPP
VPP
RL = 1.2 kW
—
—
Output Voltage Level
AOUT+,
VOAO
ZL = 350 W
AOUT–
—
—
—
—
*2.226
+100
+20
VPP
mV
mV
+ 120 nF(See Fig.1)
VOFVF VFRO
–100
–20
Offset Voltage
AOUT+, AOUT– (GAIN = 0 dB),
Power amp only
VOFAO
GDB
Power amp (0.3 to 3.4 kHz,
ZL = 350 W + 120 nF)(See Fig.1)
Open Loop Gain
40
—
—
dB
*
–3 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 2.226 V (MSM7540)
PP
–3 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 2.226 V (MSM7560)
PP
10/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
AC Chracteristics
(VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C)
Condition
Level
Parameter
Symbol
Freq.
(Hz)
Min.
Typ.
Max.
Unit
Others
(dBm0)
LOSS T1
0 to 60
25
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
LOSS T2 300 to 3000
–0.15
—
+0.20
Transmit Frequency
Response
LOSS T3
LOSS T4
LOSS T5
LOSS T6
1020
3300
Reference
0
0
—
–0.15
0
—
+0.80
0.80
—
3400
—
3968.75
14
—
LOSS R1 0 to 3000
–0.15
—
+0.20
LOSS R2
LOSS R3
LOSS R4
LOSS R5
SD T1
SD T2
SD T3
SD T4
SD T5
SD R1
SD R2
SD R3
SD R4
SD R5
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
1020
3300
Reference
Receive Frequency
Response
—
(*1)
(*1)
—
–0.15
0
—
+0.80
0.80
—
3400
—
3968.75
14
—
3
35
—
—
0
35
—
—
Transmit Signal
1020
1020
1020
1020
–30
–40
–45
3
35
—
—
to Distortion Ratio
28
—
—
23
—
—
35
—
—
0
35
—
—
Receive Signal
–30
–40
–45
3
35
—
—
to Distortion Ratio
28
—
—
23
—
—
–0.2
—
+0.2
–10
–40
–50
–55
3
Reference
Transmit Gain
Tracking
–0.2
–0.5
–1.2
–0.2
—
+0.2
+0.5
+1.2
+0.2
—
—
—
–10
–40
–50
–55
Reference
—
Receive Gain
Tracking
—
–0.2
–0.5
–1.2
+0.2
+0.5
+1.2
—
—
*1 Use the P-message weighted filter
11/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
AC Characteristics (Continued)
(VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C)
Condition
Level
Parameter
Symbol
Freq.
(Hz)
Min.
Typ.
Max.
Unit
Others
(dBm0)
–69
(–72)
–72
NIDLT
NIDLR
AVT
—
—
AIN = SG
—
(*1)
—
—
—
—
dBm0p
(dBmp)
Idle Channel Noise
(*1)
(*2)
(–75)
0.548
(*3)
0.548
(*3)
—
GSX2 0.488
VFRO 0.488
0.615 Vrms
0.615 Vrms
Absolute Signal
Amplitude
1020
0
AVR
PSRRT Noise Freq.
Noise Level
: 50 mVPP
30
—
dB
dB
ns
ns
ns
ns
ns
Power Supply Noise
Rejection Ratio
—
30
PSRRR : 0 to 50 kHz
—
—
tSDX
tSDR
50
50
—
200
200
200
200
200
—
Digital Output
Delay Time
1 LSTTL + 100 pF,
tXD1, tRD1
tXD2, tRD2
tXD3, tRD3
—
—
50
50
50
—
Pull-up: 500 W
—
—
*1 Use the P-message weighted filter
*2 PCMRI input code "11010101"(MSM7540)
"11111111"(MSM7560)
*3 0.548 Vrms = 0 dBm0= –3 dBm
Note: All ADPCM coder and decoder characteristics comply with ITU-T Recommendation
G.721.
12/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
TIMING DIAGRAM
Transmit Side PCM/ADPCM Data Interface
0
txs
t1sx
2
tws
3
4
5
6
7
8
9
10
11
12
13
14
BCLKB
XSYNC
PCMSO
txd1
txd2
txd3
MSB
MSB
LSB
txd3
tsdx
LSB
PCMSO
(during linear)
BCLKA
0
t1sx
2
3
4
5
6
7
8
9
10
txs
txd1
txd2
XSYNC
IS
txd3
MSB
LSB
tsdx
Receive Side PCM/ADPCM Data Interface
BCLKA
0
1
2
3
4
5
6
7
8
9
10
10
11
12
13
14
tsr
trs
tws
RSYNC
IR
tds
txd3
txd3
tdh
MSB
LSB
4
0
trs
1
2
3
5
6
7
8
9
BCLKB
RSYNC
PCMRO
tsr
trd1
trd2
MSB
LSB
trd3
tsdx
MSB
LSB
PCMRO
(during linear)
Note: Linear format
A code of an input/output level is determined by the 14-bit 2'compliment.
Refer to the table below for code format.
Input/Output level
MSB to LSB
01111111111111
00000000000000
10000000000000
+Full-scall
0
–Full-scall
13/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
APPLICATION CIRCUIT
VDD
MSM7540/7560GS
ADPCM Algorithm
Reset Input
1
2
28
27
VDD
RES
BCLKB
BCLKA
Shift Clock Input for
PCM, ADPCM Data
(64 kHz to 2048 kHz)
PCMRI
Receive
PCM Output
3
4
26
25
PCMRO
IR
XSYNC
RSYNC
8 kHz Sync Signal Input
Receive ADPCM Input
5
24
Transmit ADPCM Output
IS
MCK
X2
6
7
23
22
21
20
19
PCMSI
PCMSO
LPS
Transmit
PCM Output
10.368 MHz
X1
PDN
VDD
8
Power Down Input
9
DG
10
AG
AOUT+
AOUT–
PWI
11
12
13
18
17
16
15
SG
AIN1
GSX1
AIN2
Transmit Analog Input
VFRO
GSX2
14
Receive Analog Output
(Push-Pull)
14/16
FEDL7540-03
MSM7540/7560
¡ Semiconductor
PACKAGE DIMENSIONS
SOP28-P-430-1.27-K
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
Solder plate thickness
Package weight (g)
5 mm or more
0.75 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
15/16
FEDL7540-03
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
16/16
相关型号：
©2020 ICPDF网 联系我们和版权申明