概述
数据手册MSM7582 概述
pie/4 Shift QPSK MODEM 大饼/ 4移位QPSK调制解调器
MSM7582 数据手册
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PDF下载E2U0035-16-X2
This version: Jan. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7582/7582B
p/4 Shift QPSK MODEM
GENERAL DESCRIPTION
The MSM7582/7582B are CMOS ICs for the p/4 shift QPSK modem developed for the digital
cordless telephone systems.
The devices are designed for Personal and Cell station applications, the MSM7582B is the
improved MSM7582 in modulator burst rise-up and fall-down characteristics.
FEATURES
• Single Power Supply (VDD: 2.7 V to 3.6 V)
(Modulator Block)
• Built-in Root Nyquist Filter for Baseband Limiting (50% Roll-off)
• Ramp Bit for Burst Signal Rise-up:
MSM7582/1.75 symbols
MSM7582B/2.0 symbols
• Ramp Bit for Burst Signal Fall-down:
MSM7582/2.75 symbols
MSM7582B/2.0 symbols
• Built-in D/A converters for Analog Output of Quadrature Signal I/Q Components and Power
I2 + Q2
Envelope Output
• Differential I/Q Analog output format
• I/Q Output DC Offset / Gain Adjustable
(Demodulator Block)
• Full Digital System, p/4 shift QPSK Demodulation
• Input IF signal Frequency Selectable: 1.2/10.7/10.75/10.8 MHz
• Built-in Clock Recovery: 4 Circuits useful for Cell station
(Common)
• Various Power-down Modes: Tramsmit/Receive Independant
• Built-in Precise Analog Voltage Reference
• MCU Serial Interface for Mode setting and Built-in Test circuit
• Test Modes: Eye pattern / AFC Compensating Signal / Phase Detection Signal, possible to
monitor
• Transmission Speed: 384 kbps
• Low Power consumption
Operating mode : 15 mA Typ. / Modulator (V = 3.0 V)
DD
: 9 mA Typ. / Demodulator (V = 3.0 V)
DD
Whole system Power-down mode: 0.01 mA Typ. (V = 3.0 V)
DD
• Package:
32-pin plastic TSOP (TSOPI32-P-814-0.50-1K)(Product name : MSM7582TS-K)
(Product name : MSM7582BTS-K)
1/24
To monitor output
of each block
To modem ENV
PDN0
PDN1
PDN2
VDD
DGND
AGND
RXD
RXC
Decision
Unit
IFIN
Phase Detector
Delay Detector
AFC
IFSEL0
(From CR)
MCK
IFCK
S
E
L
IFSEL1
(From CR)
S
E
L
Decoder
DPLL
To each block
X2
X1
To each
block
DEN
EXCK
DIN
AFC
PS/CS
Control
Register (CR)
RPR
RCW
SLS1
SLS2
DOUT
+
-
1
1
1
1
I+
I–
Q+
Q–
I
D/A CONV
TXD
TXW
Root Nyquist
LPF
S/P
MAPPING
+
-
Q
D/A CONV
S
E
L
S
E
L
+
3.84 MHz
1
ENV
ENV D/A CONV
To
APLL
TXCI
To D/A
output of
Monitor
SG
VREF
To internal SG
each block
1/10
TXCO
384 kHz
TEST1, TEST0
(From CR)
TXCSEL
(From CR)
¡ Semiconductor
MSM7582/7582B
PIN CONFIGURATION (TOP VIEW)
AGND
SG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
DGND
IFIN
TXCI
TXCO
TXD
TXW
DEN
EXCK
DIN
I+
I–
Q+
Q–
ENV
PDN0
PDN1
PDN2
VDD
SLS1
SLS2
RCW
DOUT
22 MCK
21 RXD
20 RXC
19
18
17
IFCK
X2
X1
AFC 15
RPR 16
32-Pin Plastic TSOP
3/24
¡ Semiconductor
MSM7582/7582B
PIN AND FUNCTIONAL DESCRIPTIONS
TXD
Transmit data input for 384 kbps.
TXCI
Transmit clock input.
When the control register CR0 – B6 is “0”, a 384 kHz clock pulse synchronous with TXD should
be input to this pin. This clock pulse should be continuous because these devices use APLL to
generate the internal clock pulse.
When CR0 – B6 is “1”, a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz
clock pulse is applied, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the
3.84 MHz to TXCI by 10. The transmit data, synchronous 384 kHz clock pulse, should be input
to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse need not be
continuous. (Refer to Fig. 1.)
TXCO
Transmit clock output.
When CR0 - B6 is “0”, TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring
purposes. When CR0 – B6 is “1”, this pin outputs a 384 kHz clock pulse generated by dividing
the TXCI input by 10. (Refer to Fig. 1.)
When CR0 – B6 = “0” and CR5 – B7 = “1”, this pin outputs the burst timing position.
TXW
Transmit data window input.
The transmit timing signal for the burst data is input to the device pin. If TXW is “1”, the
modulation data is output. However, the MSM7582 is different from the MSM7582B in the ramp
response time for burst rise-up and burst fall-down of I, Q modulated outputs, as shown in the
table below. (Refer to Fig, 1-1 for the MSM7582 and Fig, 1-2 for the MSM7582B)
MSM7582
1.75 symbols
2.75 symbols
MSM7582B
2 symbols
Ramp Rise-up
Ramp Fall-down
2 symbols
The TXCO burst position output timing discribed before, is different, according to this table.
4/24
¡ Semiconductor
MSM7582/7582B
MSM7582
(1) CR0 – B6 = "0"
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(384 kHz)
TXW
TXCO
(384 kHz)
I, Q
Ramp rise-up
1.75 symbols
Ramp
Fall-down
2.75 symbols
Delay of 6.25 symbols
Delay of 6.25 symbols
(2) CR0 – B6 = "1"
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(3.84 MHz)
TXW
TXCO
(384 kHz)
I, Q
Ramp rise-up
Ramp
1.75 symbols
Fall-down
2.75 symbols
Delay of 6.25 symbols
Delay of 6.25 symbols
Figure 1-1 Transmit Timing Diagram
5/24
¡ Semiconductor
MSM7582/7582B
MSM7582B
(1) CR0 – B6 = "0"
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(384 kHz)
TXW
TXCO
(384 kHz)
I, Q
Ramp rise-up
2 symbols
Ramp fall-down
2 symbols
Delay of 6.25 symbols
Delay of 6.25 symbols
(2) CR0 – B6 = "1"
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(3.84 MHz)
TXW
TXCO
(384 kHz)
I, Q
Ramp rise-up
2 symbols
Ramp fall-down
2 symbols
Delay of 6.25 symbols
Delay of 6.25 symbols
Figure 1-2 Transmit Timing Diagram
I+, I–
Quadrature modulation signal I component differential analog outputs.
Theiroutputlevelsare500mV with1.6Vdcasthecentervalue. Theoutputpinloadconditions
pp
are: R ≥ 10 kW, C ≤ 20 pF. The gain of these pins can be adjusted using the control register CR1
– B7 to B4, and the offset voltage at the I– pin can be adjusted using CR3 – B7 to B3.
Q+, Q–
Quadrature modulation signal Q component differential analog outputs.
Theiroutputlevelsare 500mV with1.6Vdcasthecentervalue. Theoutputpinloadconditions
PP
are: R ≥ 10 kW, C ≤ 20 pF. The gain of these pins can be adjusted using the control register CR1
– B3 to B0, and the offset voltage at the Q– pin can be adjusted by using CR4 – B7 to B3.
6/24
¡ Semiconductor
MSM7582/7582B
ENV
I2 + Q2
Quadrature modulation signal envelope (
)output.
Its output level is 500 mV with 1.6 Vdc as a center value. The output pin load conditions are
PP
: R ≥ 10 kW, C ≤ 20 pF. The gain of this output can be adjusted using the control register CR2 – B7
to B4.
This pin is also used to monitor eye pattern, AFC Compensating signal, and phase defection of
the demodulator block during the test mode. Refer to the description of the control register for
details.
SG
Internal reference voltage output.
The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and
the AGND pin.
PDN0, PDN1, PDN2
Inputs for power-down control.
PDN0 controls the standby / communication modes, PDN1 controls the modulator, and PDN2
controls the demodulator. Refer to Table 1 for details.
Table-1 Power Down Control
PDN0 PDN2 PDN1
Function
Mode
Mode A
Mode B
0
0
0/1
0
1
0
All power-down. The control register is reset.
All power-down. The control register is not reset.
Modulator power is off (VREF and PLL power are also off).
Demodulator power is on.
Standby
Mode
0
1
1
1
1
1
0
0
1
1
0
0
1
0
1
Mode C
Mode D
Mode E
Mode F
Mode G
Modulator power is off (VREF and PLL power is on).
I and Q outputs are in a high-impedance state.
Only demodulator clock recovery block power is on.
Modulator power is on
Only demodulator clock recovery block power is on.
Modulator power is off (VREF and PLL power is on).
I and Q outputs are in a high-impedance state.
Demodulator power is on.
Communication
Mode
Modulator power is on
Demodulator power is on.
V
DD
+3 V power supply voltage.
AGND
Analog signal ground.
DGND
Digital signal ground.
AGND and DGND are not connected in the device. This pin should be tied to the AGND pin on
the PCB as close as possible from the device.
7/24
¡ Semiconductor
MSM7582/7582B
MCK
Master clock input.
The clock frequency is 19.2 MHz.
IFIN
Modulated signal input for the demodulator block.
Select the IF frequency from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz, based on CR0 – B4
and B3.
IFCK
Clock signal input for demodulator block IF frequencies (10.7 MHz or 10.75 MHz).
If the IF frequency is 10.7 MHz, 19.0222 MHz should be supplied. When it is 10.75 MHz, 19.1111
MHz should be supplied. When the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to “0” or
“1”. (Refer to Fig. 2.)
X1, X2
Crystal oscillator connection pins.
When supplying a 19.0222 MHz or 19.1111 MHz clock to IFCK, use these pins (Refer to Fig. 2.)
When IFIN = 10.7 MHz or 10.75 MHz
When IFIN = 1.2 MHz or 10.8 MHz
MSM7582/7582B
MSM7582/7582B
X1
X2 IFCK
X1
X2 IFCK
19.0222 MHz or 19.1111 MHz
Figure 2 How to Use IFCK, X1, and X2
RXD, RXC
Receivedataandclockoutput. Whenpoweristurnedon, theoutputsofcircuitsselectedby SLS1
and SLS2 appear at these pins. (Refer to Fig. 3)
RXD1
RXC
SLS2
SLS1
The recovery data and clock pulse are selected
asynchronously using the SLS signals.
Figure 3 RXD and RXC Timing Diagram
8/24
¡ Semiconductor
MSM7582/7582B
SLS2, SLS1
Receiver slot select signal inputs.
The devices have four sets of clock recovery circuit to each channel and four AFC information
storage registers. One these circuits is selected from a combination of the signals at these pins.
(SLS2, SLS1) = (0, 0): Slot 1, (0, 1): Slot 2
(1, 0): Slot 3, (1, 1): Slot 4
RPR
High-speed phase clock control signal input for the clock recovery circuit.
If this pin is “1”, the clock recovery circuit starts in the high-speed phase clock mode. When the
phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode
automatically. When this pin is “0”, the circuit is always in the low-speed phase clock mode.
AFC
AFC operation range specification signal input.
As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to “1”. AFC
operation starts after a fixed number of clock cycles and after the AFC information is reset. If RPR
is set to “1”, an average number of times that AFC turns on is low. If RPR is “0”, AFC is high. If
AFC is “0”, frequency error is not calculated, but the frequency is corrected using an error that
is held.
RCW
Clock recovery circuit operation ON/OFF control signal input. If RCW pin is “0”, DPLL does not
make any phase corrections.
(CASE1)
AFC
RPR
Average number of times
AFC is high.
AFC information Average
is reset. number of times
AFC is low.
AFC information
is maintained.
(CASE2)
AFC
"0"
Average number of times
RPR
The clock recovery circuit
starts with the previous
AFC information.
AFC information
is maintained.
AFC is high.
Figure 4 AFC Control Timing Diagram
9/24
¡ Semiconductor
MSM7582/7582B
DEN , EXCK, DIN, DOUT
Serial control ports for the microprocessor interface.
The MSM7582 and MSM7582B contain a 6-byte control register. An external CPU uses these pins
to read data from and write data to the control register. DEN is an enable signal input pin. EXCK
is a data shift clock pulse input pin. DIN is an address and data input pin. DOUT is a data output
pin. Figure 5 shows an input/output timing diagram.
DEN
EXCK
W
A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
DIN
DOUT
High Impedance
(a) Data Write Timing Diagram
DEN
EXCK
DIN
R
A2 A1 A0
DOUT
B7 B6 B5 B4 B3 B2 B1 B0
(b) Data Read Timing Diagram
High Impedance
Figure 5 MCU Interface Input/Output Timing Diagram
10/24
¡ Semiconductor
MSM7582/7582B
The register map is shown below
Table-2 Control Register Map
Address
Data
R/W
Register
CR0
A2 A1 A0
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
PS/CS
TXCSEL
MODOFF
IFSEL1
IFSEL0
ENVSEL
TEST1
TEST0 R/W
Ich
GAIN3
Ich
GAIN2
Ich
GAIN1
Ich
Qch
Qch
GAIN2
Qch
GAIN1
Qch
R/W
CR1
GAIN0
GAIN3
GAIN0
ENV
GAIN3
ENV
GAIN2
ENV
GAIN1
ENV
CR2
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
GAIN0
Ich
Ich
Ich
Ich
Ich
CR3
Offset4 Offset3 Offset2 Offset1 Offset0
Qch Qch Qch Qch Qch
Offset4 Offset3 Offset2 Offset1 Offset0
CR4
BSTO
ENBL
LOCAL LOCAL
INV1 INV0
CLK
SEL1
CLK
SEL0
CR5
ICT6
ICT5
ICT4
R/W : Read/Write enable R : Read-only register
11/24
¡ Semiconductor
MSM7582/7582B
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Digital Input Voltage
Operating Temperature
Storage Temperature
Symbol
VDD
Condtion
Rating
Unit
V
—
—
—
—
0 to 5
VDIN
Top
–0.3 to VDD +0.3
–25 to +70
V
°C
°C
TSTG
–55 to +150
RECOMMENDED OPERATING CONDITIONS
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Symbol
Parameter
Power Supply Voltage
Operating Temperature Range
Input High Voltage
Condtion
Min.
2.7
Typ.
—
Max.
3.6
Unit
V
VDD
—
—
Ta
–25
0.45 ¥ VDD
0
—
+70
°C
VIH All digital input pins
VIL All digital input pins
fMCK MCK
—
VDD
V
0.16 ¥ VDD
Input Low Voltage
—
V
Master Clock Frequency
—
19.2
384
3.84
—
MHz
kHz
MHz
fTXC1 TXCI (when CR0 – B6 = "0")
fTXC2 TXCI (when CR0 – B6 = "1")
fIFCK1 IFCK (when IFIN = 10.7 MHz)
fIFCK2 IFCK (when IFIN = 10.75 MHz)
DCCK MCK, IFCK, TXCI
—
—
Modulator Input Frequency
Demodulator Input Frequency
—
—
–
–
50 ppm 19.0222
50 ppm 19.1111
+
+
50 ppm MHz
50 ppm MHz
Clock Duty Cycle
40
45
50
50
60
55
%
%
IF Input Duty Cycle
DCIF IFCK
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Symbol
IDD1
Condition
Min.
—
Typ.
0.02
5.5
5.5
11.5
9.5
14.0
—
Max.
0.05
11.0
11.0
23.0
19.0
28.0
VDD
0.4
Unit
mA
mA
mA
mA
mA
mA
V
Mode A, Mode B (when VDD = 3.0 V)
Mode C (when VDD = 3.0 V)
Mode D (when VDD = 3.0 V)
Mode E (when VDD = 3.0 V)
Mode F (when VDD = 3.0 V)
Mode G (when VDD = 3.0 V)
IDD2
—
IDD3
—
Power Supply Current
IDD4
—
IDD5
—
IDD6
—
Output High Voltage
Output Low Voltage
VOH IOH = 0.4 mA
0.5 ¥ VDD
0.0
VOL
IIH
IOL = –1.2 mA
—
V
—
—
—
—
10
mA
mA
Input Leakage Current
IIL
—
—
10
12/24
¡ Semiconductor
MSM7582/7582B
Analog Interface Characteristics
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Output Resistance Load
Output Capacitance Load
Symbol
Condtion
Min.
1.0
Typ.
—
Max.
—
Unit
kW
pF
RLIQ I+, I–, Q+, Q–, ENV
CLIQ I+, I–, Q+, Q–, ENV
VDC1 I+, I–, Q+, Q– (TXW = 0)
VDC2 I+ (CR0 – B5 = 1)
when not modulated
—
—
20
1.55
1.6
1.65
V
—
—
1.77
1.67
—
—
V
V
VDC3 Q+ (CR0 – B5 = 1)
when not modulated
Output DC Voltage Level
VDC4 ENV (TXW = 0)
—
—
—
1.35
1.72
1.63
—
—
—
V
V
V
VDC5 ENV (TXW = 1, CR0 – B2 = 0, TXD = 0)
VDC6 ENV (TXW = 1, CR0 – B2 = 1, TXD = 0)
I+, I–, Q+, Q–
VAC
Output AC Voltage Level
—
360
—
mVPP
(TXD = 0)
Output DC Voltage Adjustment Level Range DCVL
Output AC Voltage Adjustment Level Range ACVL
—
—
—
—
60
65
—
0.5
—
—
—
—
45
4
—
—
mV
%
P600 600 kHz detuning (*)
P900 900 kHz detuning (*)
—
—
1.0
—
20
5
—
dB
Out-of-band Spectrum
—
dB
Modulation Accuracy
EVM
—
3.0
VDD
—
% rms
VPP
kW
pF
Demodulator IF Input Level
IFV IFIN input level
RIF
CIF
—
IFIN Input Impedance
—
—
—
—
SG Output Voltage
VSG
RSG
2.0
1.5
—
V
SG Output Impedance
—
kW
* Power attenuation at 600 kHz or 900 kHz ±96 kHz as referred to two times of the power in
frequency band of 0 to 96 kHz
13/24
¡ Semiconductor
MSM7582/7582B
Digital Interface Characteristics
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Condtion
Parameter
Symbol
Min.
Typ.
—
Max.
200
Unit
ns
Other
tSX
–200
tDS
tDH
0
0
0
—
200
ns
Transmitter Digital
C load = 50 pF
Fig. 6
Input/Output Setting Time
tXD1
tXD2
tXD3
tXD4
tRD1
tRD2
—
200
ns
—
200
ns
0
0
—
—
200
200
ns
ns
Receiver Digital Input/Output
Setting Time
tRS1 to C load = 50 pF
Fig. 7
10
—
—
ms
tRS4
tRW
10
50
50
50
50
100
50
50
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
—
—
50
10
ms
ns
tM1
tM2
ns
tM3
ns
tM4
ns
tM5
ns
Serial Port Digital
tM6 C load = 50 pF
Fig. 8
EXCK
ns
Input/Output Setting Time
tM7
tM8
ns
ns
tM9
50
50
0
ns
tM10
tM11
fEXCK
ns
ns
EXCK Clock Frequency
—
—
MHz
14/24
¡ Semiconductor
MSM7582/7582B
TIMING DIAGRAM
Transmit Data Input Timing
TXCI [TXCO*]
(384 kHz)
1
2
3
N-2
N-1
N
N+1
tSX
tSX
TXW
TXD
tDS tDH
1
2
3
N-2
N-1
N
* [ ]: When CR0 – B6 = "1", TXCO is indicated.
Transmit Clock (TXCO) Output Timing (when CR0 – B6 = 1)
TXCI
(3.84 MHz)
1
2
3
4
5
6
7
8
9
10
tXD1
tXD2
tXD1
TXCO
(384 kHz)
Transmit Burst Position Output (TXCO) Timing (when CR0 – B6 = 0 and CR5 – B7 = 1)
M7582
TXCI
(384 kHz)
1
2
8
9
N
N+1
N+17
N+18
N+19
TXW
tXD3
tXD4
TXCO
M7582B
TXCI
(384 kHz)
1
2
8
9
N
N+1
N+17
N+18
N+19
TXW
tXD3
tXD4
TXCO
Figure 6 Transmit (Modulator) Digital Input/Output Timing
15/24
¡ Semiconductor
MSM7582/7582B
SLS1
SLS2
tRS1 tRS2
tRS3 tRS4
RCW
AFC
RPR
RXC
tRW
tRD1
tRD2
RXD
Figure 7 Receiver (Demodulator) Digital Input/Output Timing
DEN
tM10
tM5
tM2
EXCK
1
2
3
4
5
6
11
12
tM6
tM7
tM4
tM1
tM3
tM4
W/R
DIN
A2
A1
A0
B7
B1
B1
B0
B0
tM11
tM8
B7
DOUT
Figure 8 Serial Control Port Interface
16/24
¡ Semiconductor
MSM7582/7582B
FUNCTIONAL DESCRIPTION
Control Registers
(1) CR0 (basic operation mode setting)
B7
PS/CS
0
B6
TXC SEL
0
B5
MOD OFF
0
B4
IFSEL 1
0
B3
IFSEL 0
0
B2
ENV SEL
0
B1
TEST 1
0
B0
TEST 0
0
CR0
Initial value (*)
* the initial value is set when a reset signal is supplied by a PDN.
B7: PS/CS selection
1/CS (4 Clock recovery DPLLs are on.)
0/PS (2 Clock recovery DPLLs are on.)
B6: Transmit timing clock selection
0/TXCI input: 384 kHz.
TXCO output: 384 kHz output from APLL. Transmit data TXD is input in synchronization
with the rising edge of TXCI (APLL is on.)
1/TXCI input: 3.84 MHz.
TXCO output: 384 kHz (one-tenth of the TXCI frequency). Transmit data TXD is input in
synchronization with the rising edge of TXCO (APLL is off.)
B5: Modulation on/off control
1/modulation OFF (with phase fixed)
0/modulation ON.
B4, B3: Receiver input IF frequency selection
(0, 0), (0, 1):
(1, 0):
1.2 MHz
10.8 MHz
(1, 1):
10.7 MHz/10.75 MHz
2
2
I2 + Q2
B2: Transmit envelope (I + Q or
)output selection
2
2
1/I + Q output
0/ output
I2 + Q2
B1, B0: Test mode selection bits. Each monitor output is output to the transmit ENV pin.
2
2
I2 + Q2
(0, 0): Transmit envelope (I + Q or
) output
(0, 1): receiver phase detection signal output
(1, 0): receiver delay detection signal output
(1, 1): receiver AFC information output
17/24
¡ Semiconductor
MSM7582/7582B
(2) CR1 (I, Q gain adjustment)
B7
B6
B5
B4
B3
B2
B1
B0
Ich
GAIN3
Ich
GAIN2
Ich
GAIN1
Ich
GAIN0
Qch
GAIN3
Qch
GAIN2
Qch
GAIN1
Qch
GAIN0
CR1
Initial value
0
0
0
0
0
0
0
0
B7 to B4: I+/I– output gain setting, in 3 mV steps (Refer to Table-3.)
B3 to B0: Q+/Q– output gain setting, in 3 mV steps (Refer to Table-3.)
(3) CR2 (ENV gain adjustment)
B7
B6
B5
B4
B3
—
0
B2
—
0
B1
—
0
B0
—
0
ENV
GAIN3
ENV
GAIN2
ENV
GAIN1
ENV
GAIN0
CR2
Initial value
0
0
0
0
B7 to B4: ENV output gain adjustment (Refer to Table-3.)
B3 to B0: Not used
Table-3 I, Q, and ENV Output Gain Values
CR1-B7
-B6 -B5 -B4
CR1-B3
-B2 -B1 -B0
-B6 -B5 -B4
Description
Amplitude 1.042 ¥ Reference value
CR2-B7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.036
1.030
1.024
1.018
1.012
1.006
1.000 (Reference value)
0.994
0.988
0.982
0.976
0.970
0.964
0.958
0.952
18/24
¡ Semiconductor
MSM7582/7582B
(4) CR3 (I– output offset voltage adjustment)
B7
B6
B5
B4
B3
B2
—
0
B1
—
0
B0
—
0
Ich
Offset4
Ich
Offset3
Ich
Offset2
Ich
Offset1
Ich
Offset0
CR3
Initial value
0
0
0
0
0
B7 to B3: I– output pin offset voltage adjustment (Refer to Table-4.)
B2 to B0: Not used
(5) CR4 (Q– output offset voltage adjustment)
B7
B6
B5
B4
B3
B2
—
0
B1
—
0
B0
—
0
Qch
Offset4
Qch
Offset3
Qch
Offset2
Qch
Offset1
Qch
Offset0
CR4
Initial value
0
0
0
0
0
B7 to B4: Q– output pin offset voltage adjustment (Refer to Table-4.)
B3 to B0: Not used
Table-4 I and Q Channel Offset Adjustment Values
CR3-B7 B6 B5 B4 B3
CR4-B7 B6 B5 B4 B3
CR3-B7 B6 B5 B4 B3
CR4-B7 B6 B5 B4 B3
Description
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Offset +45 mV
+42 mV
+39 mV
+36 mV
+33 mV
+30 mV
+27 mV
+24 mV
+21 mV
+18 mV
+15 mV
+12 mV
+9 mV
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Offset
–3 mV
–6 mV
–9 mV
–12 mV
–15 mV
–18 mV
–21 mV
–24 mV
–27 mV
–30 mV
–33 mV
–36 mV
–39 mV
–42 mV
–45 mV
–48 mV
+6 mV
+3 mV
0 mV
19/24
¡ Semiconductor
MSM7582/7582B
(6) CR5
B7
B6
ICT6
0
B5
ICT5
0
B4
ICT4
0
B3
B2
B1
B0
BSTO
ENBL
LOCAL
INV1
LOCAL
INV0
CLK
SEL1
CLK
SEL0
CR5
Initial value
0
0
0
0
0
B7: Modulator burst window output enable bit.
1/The timing of the I and Q baseband modulation output burst is output at the TXCO pin.
0/The 384 kHz transmit timing clock pulse is output at the TXCO pin.
B6 to B4: ICT6 to ICT4. Device test control bits.
B3, B2: Local inverting mode setting bits.
(1, 1) = local inverting mode
(0, 0) = normal mode
B1: Clock pulse shaping mode selection bit.
1/Clock pulse shaping mode (Refer to Fig 9.)
0/Oscillator circuit mode
B0: Power-on control bit for X1, X2 pins, when the clock pulse shaping mode.
1/ Always power-on
0/ Power-down in the whole device power-down state when Power on otherwise.
Note: CR5 – B6 to B4 are used to test the device. They should be set to “0” during normal
operation.
MSM7582/82B TS-K
X1
X2 MCK
TCXO
19.2 MHz
About
Pulse shape
To other input
0.7 to 1.0 VPP within about 3 VPP of 19.2 MHz
Figure 9 Example of Application Circuit when the Clock Pulse Shaping Mode is
Generated by CR5-B1
20/24
¡ Semiconductor
MSM7582/7582B
State Transition Time
Mode A
PDN1 = 1
Note: The transition time is 1 ms or
less unless otherwise stated
1 ms
Mode B
PDN1 = 0
5 ms
PDN2 = 0
Mode C
PDN1 = 0
PDN2 = 1
Standby mode (PDN0 = 0)
Communication mode (PDN0 = 1)
40 ms
5 ms
Mode E
Mode D
Mode F
PDN1 = 0
PDN2 = 1
PDN1 = 1
PDN2 = 0
PDN1 = 0
PDN2 = 0
5 ms
40 ms
Mode G
PDN1 = 1
PDN2 = 1
Figure 10 Power-Down State Transition Time
21/24
¡ Semiconductor
MSM7582/7582B
APPLICATION CIRCUIT
VDD
C1 C2 C3
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AGND
SG
I+
I–
Q+
DGND
IFIN
TXCI
TXCO
TXD
TXW
DEN
EXCK
DIN
DOUT
MCK
RXD
RXC
IFCK
X2
C4
Demodulator IF input
Modulator 384 kHz input
Modulator I component output
Modulator Q component output
Modulator input data
Modulator data window
Q–
ENV
PDN0
PDN1
PDN2
VDD
SLS1
SLS2
RCW
AFC
MSM7582TS-K
19.2 MHz input
Receive data output
Receive clock output
Power-down control signal
RPR
X1
Control register
control signal
Demodulator control signal
C1 = 10 mF
C2 = C3 = 0.1 mF
C4 = 1000 pF
Figure 11 Example of Circuit Configuration
22/24
¡ Semiconductor
MSM7582/7582B
Demodulator Control Timing Diagram (Example)
Democulator unit
Modulator
input data
Slot 1
R1
Slot 2
R2
Slot 3
R3
Slot 4
R4
G
G
G
G
G
Timing for CS
PDN2
SLS2
SLS1
AFC
"0"
"0"
"0"
"1"
"1"
"0"
"1"
"1"
R1
R2
R3
R4
RXD
RXC
Timing for PS
PDN2
SLS2
SLS1
AFC
"0"
"0"
R1
RXD
RXC
240 bits 625 ms
(1) Control channel / synchronous burst (SS + PR = 64 bits)
64 bits
RXD
AFC
G
G
G
G
G
G
G
G
R
R
R
R
SS SS PR PR
PR UW
CR CR G G G G G G G G
RPR
RCW
56 bits
(2) When synchronization is not established (for PS only)
AFC
RPR
RCW
For PS, the window is initially open to
wait for the control signal from CS.
RPR is closed after UW is detected.
(3) Communication channel (SS + PR = 8 bits)
8 bits
RXD
AFC
G
G
G
G
G
G
G
G
R
R
R
R
SS SS PR PR
PR UW
CR CR G G G G G G G G
RPR
RCW
"0"
When the strength of the received wave is large
Less than 30 bits
When the strength of the received wave is small.
G
R
:
:
Guard bit
Ramp bit
SS : Start symbol bit
PR : Preamble bit
UW : Unique word bit
CR : CRC bit
23/24
¡ Semiconductor
PACKAGE DIMENSIONS
TSOPI32-P-814-0.50-1K
MSM7582/7582B
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
Solder plate thickness
Package weight (g)
5 mm or more
0.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
24/24
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