MSM7586-01 [OKI]
pie/4 Shift QPSK MODEM/ADPCM CODEC; 大饼/ 4移位QPSK调制解调器/ ADPCM编解码器
| 型号： | MSM7586-01 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | pie/4 Shift QPSK MODEM/ADPCM CODEC |
| 文件： | 总42页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0034-28-82
This version: Aug. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7586-01/03
p/4 Shift QPSK MODEM/ADPCM CODEC
GENERAL DESCRIPTION
The MSM7586 is a CMOS IC developed for use with digital cordless telephones. The device
provides a p/4 shift QPSK modem function and a CODEC function which performs transcoding
between the voice band analog signal and 32 kbps ADPCM data.
TheMSM7586performsDTMFtoneandseveraltypesoftonegeneration, transmit/receivedata,
mute and gain control, side-tone pass and its gain control, and VOX function.
FEATURES
(p/4 Shift QPSK Modem Unit)
• 384 kbps transmission speed
• Built-in root Nyquist digital filter for the baseband band limiter
• Built-in D/A converters for the analog outputs of the quadrature signal component I and Q
• The DC offset and gain can be adjusted with respect to the differential I and Q analog outputs
• Completely digitized p/4 shift QPSK demodulator system
(ADPCM CODEC Unit)
• ADPCM system: built-in ITU-T Recommendations G.726 (32kbps, 24 kbps, 16 kbps)
• Transmit/receive full-duplex capability
• PCM interface code format: selectable between m-law and A-law
• Serial ADPCM and PCM transmission rate: 64 kbps to 2,048 kbps
• Transmit/receive mute function; transmit/receive programmable gain setting
• Side tone generator (8-step level adjustment)
• Built-in DTMF tone, ringing tone, and various ringing tone generators
• Built-in VOX function
(Common Unit)
• Operate with a single 3 V power supply (V : 2.7 V to 3.6 V)
DD
• Low power consumption
When entire system is operating: 20 mA Typ.
When powered down:
• Package:
0.02 mA Typ.
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7586-01TS-K)
(Product name: MSM7586-03TS-K)
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¡ Semiconductor
MSM7586-01/03
BLOCK DIAGRAM
PDN0
PDN1
PDN2
AFC
RXD
Phase
detector
Delay
detector
IFIN
AFC
Decision
RXC
MCK
IFCK
SL1
SL2
DEC
DPLL
To each block
X2
RPR
X1
EXCKM
DENM
DINM
RCW
SLS
MODEM
To each block
MCU
interface
DOUTM
4
R7, R6
R5, R4
BSTO
CRM1-B7 to B4
I+
+1
–1
+1
–1
TXD
D/A
D/A
LPF
LPF
S/P
I–
DC Adjust
TXW
ATT
Root Nyquist LPF
MAPPING
CRM1-B3 to B0
Q+
Q–
TXCI
DC Adjust
PLL
1/10
ATT
3.84M
To D/A
CRM0-B6
<MODEM Unit>
<CODEC Unit>
TXCO
SGM
VREF
384k
SGCR
Receiver
Transmitter
R
SGCT
IO1
SW1
SW2
T
CRC5-B7
CRC5-B6
VDAC
IO2
VOICE
DETECT
VOXO
–
+
AIN1–
AIN1+
XSYNC
IS
P
/
ADPCM
CODER
GSX1
S
CRC2-B6 to B4
CRC4-B6
A/D
Convertor
RC
S
/
–
+
AIN2–
BPF
COMPA
NDER
PCMSI
Filter
T
P
ATT
DTMF
P
/
GSX2
PCMSO
BCLK
S
AOUT+
–1
/Tone
Generator
S
/
PCMRI
ATT
P
–
+
Sign bit
AOUT–
CRC3-B7 to B5
P
/
CRC3-B3 to B0
CRC2-B2 to B0
ATT
R
PCMRO
S
PWI
VFRO
SAO
ADPCM
DE-
CODER
CRC4-B5
S
/
D/A
Convertor
EXPAN
DER
RC
IR
RSYNC
LPF
+
+
Filter
P
To each
block
AIN3
EXCKC
DENC
DINC
CODEC
Noise
generator
–
+
Power detect
GSX3
MCU
R
T
interface
DOUTC
AIN4
CRC5-B5
SW3
CRC5-B4
SW4 SW5
–
+
GSX4
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MSM7586-01/03
PIN CONFIGURATION (TOP VIEW)
VDAM
Q–
1
2
3
4
5
6
7
8
9
75 NC
74 TXW
73 TXD
72 TXCO
71 TXCI
70 NC
Q+
I–
I+
NC
SGM
AGM
AGC
69 BSTO
68 DGM
67 DGC
66 R7
SGCR 10
SGCT 11
AIN1+ 12
AIN1– 13
GSX1 14
IO5 15
65 R6
64 R5
63 R4
62 NC
61 BCLK
60 XSYNC
59 RSYNC
58 NC
IO6 16
IO7 17
AIN2 18
GSX2 19
IO1 20
57 PCMSO
56 PCMSI
55 IS
IO2 21
VFRO 22
PWI 23
54 NC
53 IR
AOUT– 24
AOUT+ 25
52 PCMRO
51 PCMRI
NC : No connect pin
100-Pin Plastic TQFP
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MSM7586-01/03
PIN AND FUNCTIONAL DESCRIPTIONS
(Modem Unit)
TXD
Transmit data input for 384 kbps.
TXCI
Transmit clock input.
When the control register CRM0 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should
be input to this pin. This clock pulse should be continuous because this device use APLL to
generate an internal clock pulse.
When CRM0 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz
clock pulse is applied to TXCL, TXCO outputs a 384 kHz clock pulse, which is generated by
dividing the TXCL input by 10. The transmit data, synchronous to the 384 kHz clock pulse,
shouldbeinputtotheTXD.InthiscasethedevicesdonotuseAPLL,andthe3.84MHzclockpulse
need not be continuous. (Refer to Fig. 1.)
TXCO
Transmit clock output.
When CRM0 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring
purposes. When CRM0 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing
the TXCI input by 10. (Refer to Fig. 1.)
TXW
Transmit data window signal input.
The transmit timing signal for the burst data is input to this pin. If TXW is "1", the modulation
data is output. (Refer to Fig. 1)
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MSM7586-01/03
(1) CRM0 – B6 = "0"
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(384 kHz)
TXW
TXCO
(384 kHz)
I, Q
Ramp rise-up
2 symbols
Ramp
Fall-down
2 symbols
Delay of 6.25 symbols
Delay of 6.25 symbols
(2) CRM0 – B6 = "1"
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(3.84 MHz)
TXW
TXCO
(3.84 kHz)
I, Q
Ramp rise-up
2 symbols
Ramp
Fall-down
2 symbols
Delay of 6.25 symbols
Delay of 6.25 symbols
Figure 1 Transmit Timing Diagram
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MSM7586-01/03
BSTO
BSTO is the modulator side burst window output.
The burst position of the I and Q baseband modulator output is output.
I+, I–
Quadrature modulation signal I Component differential analog output.
Their output levels are 500 mV (when TXD = "0": 360 mV typ.) with 1.6 Vdc as the center
pp
pp
value. The output pin load conditions are: R ≥ 10 kW, C £ 20 pF. The gain of these pins can be
adjusted using the control register CRM1 - B7 to B4, and the offset voltage at the I– pin can be
adjusted using CRM3 - B7 to B3.
Q+, Q–
Quadrature modulation signal Q component differential analog outputs.
Their output levels are 500 mV (when TXD = "0": 360 mV typ.) with 1.6 Vdc as the center
pp
pp
value. The output pin load conditions are: R ≥ 10 kW, C £ 20 pF. The gain of these pins can be
adjusted using the control register CRM1 - B3 to B0, and the offset voltage at the Q– pin can be
adjusted by using CRM4 - B7 to B3.
SGM
Internal reference voltage output.
The output voltage value is approximately 2.0 V. Insert a bypass capacitor between this pin and
the AGM pin. During power down, this output is at 0 V.
The external SG voltage if necessary should be used via a buffer.
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MSM7586-01/03
PDN0, PDN1, PDN2
Various power down control.
PDN0 controls the standby mode/communication mode; PDN1 controls the modulator unit;
and PDN2 controls the demodulator unit. Refer to Table 1 for details.
The control register reset input width should be 200ns or more.
Table 1: Description of Modem Power Down Control
PDN0 PDN2 PDN1
Operation State
Mode Name
0
0
0
1
0/1
1
0
0
0
Entire system is powered down. The control register is reset.
Mode A
Standby
Mode
0
Entire system is powered down. The control register is not reset.
Mode B
Mode C
Mode D
1
Modulator unit is powered off. (VREF and PLL also powered off.)
Demodulator unit is powered on.
0
Modulator unit is powered off. (VREF and PLL are powered on.)
I and Q outputs are in a high impedance state.
Only the demodulator clock regenerator unit is powered on.
Modulator unit is powered on.
Commu-
nication
Mode
1
1
0
1
1
0
Mode E
Mode F
Only the demodulator clock regenerator unit is powered on.
Modulator unit is powered off. (VREF and PLL are powered off.)
I and Q outputs are in a high impedance state.
Demodulator unit is powered on.
1
1
1
Modulator unit is powered on.
Mode G
Demodulator unit is powered on.
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MSM7586-01/03
VDDM, VDAM
+3 V power supply for the modem unit.
Supplied to the digital circuits through the VDDM pin and to the analog circuits through the
VDAM pin. VDDM and VDAM, and VDDC and VDAC should be connected as close as possible
on the PC board.
DGM, AGM
Ground pins for the modem unit.
DGM is the ground pin of the digital system, and AGM is the ground pin of the analog system.
Since DGM and AGM are isolated inside the IC, connect them as close as possible on the circuit
board.
MCK
Master clock input.
The clock frequency is 19.2 MHz.
IFIN
Modulated signal input for the demodulator block.
SelecttheIFfrequencycanbeselectedfrom1.2MHz, 10.7MHz, 10.75MHz, and10.8MHz, based
on CRM0 - B4 and B3.
IFCK
Clock frequency 19.0222 MHz input for demodulator block IF frequencies of 10.7 MHz.
If the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to "0" or "1". (Refer to Fig. 2.)
X1, X2
Crystal oscillator connection pins.
When supplying a 19.0222 MHz clock to IFCK, use these pins. (Refer to Fig. 2.)
When IFIN = 10.7 MHz
MSM7586
When IFIN = 1.2 MHz or 10.8 MHz
MSM7586
X1
X2
IFCK
X1
X2
IFCK
19.0222 MHz
Figure 2 How to Use IFCK, X1, and X2
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MSM7586-01/03
RXD, RXC, RXSC
Receive data and receive clock outputs.
When the modem unit is powered on, RXD, RXC and RXSC are selected based on SLS as shown
in Figure 3. These outputs are used by the clock regenerator circuit.
RXD
RXC
RXSC
1 Symbol
The regenerated data and clock are
selected asynchronously by the SLS signal.
SLS
Figure 3 Timing Diagram of RXD, RXC, and RXSC
SLS
Receive side operation slot selection signal.
This device has two clock regenerator circuits and two AFC data memory registers. If SLS is "0",
slot 1 is selected, if SLS is "1", slot 2 is selected.
RPR
High-speed phase clock control signal input for the clock recovery circuit.
If this pin is at "0", the circuit is always in the low-speed phase clock mode. If this pin is at "1",
the clock recovery circuit enters the high-speed phase clock mode. When the phase difference
is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically.
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MSM7586-01/03
AFC
AFC operation range specification signal input.
As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to "1". AFC
operation starts after a fixed number of clock cycles and the AFC information is reset. If RPR is
set to "1", an average number of times that AFC turns on is low. If RPR is "0", AFC is high. If AFC
is "0", frequency error is not calculated, but the frequency is corrected using an error that is held.
RCW
Clock recovery circuit operation ON/OFF control signal input.
If RCW this pin is "0", DPLL does not make any phase corrections.
(CASE1)
AFC
RPR
Average number of times
AFC is high.
AFC information Average
is reset. number of times
AFC is low.
AFC information
is maintained.
(CASE2)
AFC
"0"
Average number of times
RPR
The clock recovery circuit
starts with the previous
AFC information.
AFC information
is maintained.
AFC is high.
Figure 4 AFC Control Timing Diagram
DENM , EXCKM, DINM, DOUTM
Serial control ports for the microprocessor interface.
The device contains a 6-byte control register (CRM0 - 5). An external CPU uses these pins to read
data from and write data to the control register. DENM is the "Enable" signal input pin. EXCKM
is a data shift clock pulse input pin. DINM is an address and data input pin. DOUTM is a data
output pin. Figure 5 shows input/output timing diagram.
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MSM7586-01/03
DENM
EXCKM
W
A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
DINM
DOUTM
High Impedance
(a) Write Data Timing Diagram
DENM
EXCKM
DINM
R
A2 A1 A0
DOUTM
B7 B6 B5 B4 B3 B2 B1 B0
(b) Read Data Timing Diagram
High Impedance
Figure 5 Modem Unit MCU Interface I/O Timing
The register map is shown below.
Table 2: Modem Unit Control Register (CRM0 to 5) Map
Register
Name
Data Description
B4 B3
Address
R/W
B7
B6
TXC
SEL
B5
MOD
OFF
B2
B1
B0
A2 A1 A0
CRM0
CRM1
CRM2
CRM3
CRM4
CRM5
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
—
IFSEL1 IFSEL0
—
TEST1
TEST0 R/W
Ich
Ich
Ich
Ich
Qch
Qch
Qch
Qch
R/W
GAIN3
GAIN2
GAIN1
GAIN0
GAIN3
GAIN2
GAIN1
GAIN0
R7
Ich
R6
Ich
R5
Ich
R4
Ich
—
—
—
—
—
—
—
R/W
R/W
R/W
Ich
Offset4 Offset3 Offset2 Offset1 Offset0
Qch Qch Qch Qch Qch
Offset4 Offset3 Offset2 Offset1 Offset0
—
—
—
LOCAL LOCAL
INV1 INV0
ICT5
ICT4
ICT3
ICT2
ICT1
ICT0 R/W
R/W: Read/Write enable R: Read-only register
R7, R6, R5, R4
These are the control register data output pins.
These output the data CRM2 - B7, B6, B5, and B4, respectively.
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MSM7586-01/03
(CODEC Unit)
AIN1+, AIN1-, AIN2, GSX1, GSX2
The transmit analog input and the output for transmit gain adjustment.
The pin AIN1–(AIN2) connects to the inverting input of the internal transmit amplifier, and the
pin AIN1+ connects to the non-inverting input of the internal transmit amplifier. The pin GSX1
(GSX2) connects to output of the internal transmit amplifier. See Fig. 6 for gain adjustment.
VFRO, AOUT+, AOUT-, PWI
Used for the receive analog output and the output for receive gain adjustment.
VFROisanoutputofthereceivefilter. AOUT+andAOUT–aredifferentialanalogsignaloutputs
which can directly drive Z = 350 W+120 nF or the 1.2 kW load. See Fig. 6 for gain adjustment.
L
However, these outputs are in high impedance state during power down.
SAO, AIN3, AIN4, GSX3, GSX4
Input pins for the internal operational amp.
RefertoFig. 6forconnectioninformation. However,theseoutputpinsareinthehighimpedance
state during power down.
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MSM7586-01/03
AIN1–
–
+
Reference
voltage
generator
C1
R1
R2
Vi
Differential analog input signal
AIN1+
GSX1
C1
C2
R1
R3
R2
SGCT
AIN2
+
–
–
+
to ENCODER
R4
GSX2
AOUT+
–1
ZL = 120 nF
Analog output signal
Vo
+ 350 W
–
+
AOUT–
VFRO
R6
R5
Transmit gain : (VGSX2/Vi)
= (R2/R1) ¥ (R4/R3)
from
DECODER
Receive gain : (VO/VVFRO
= 2 ¥ (R6/R5)
)
+1
+1
SAO
R7
R8
AIN3
GSX3
Sounder output signal
–
+
Sounder output gain : (VGSX3
)
= VSAO ¥ (R8/R7)
Figure 6 CODEC Unit Analog Interface
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IO1 to IO7
I/O pins of the internal analog switch.
Refer to the control register description table (CRC5) and the block diagram for connection
information and control methods.
TOUT1 to TOUT3
Sign bit output pins of the tone generator.
Output control of each pin is performed by the control register. Refer to the control register
descriptiontable(CRC5)andtheblockdiagramforconnectioninformationandcontrolmethods.
SGCT, SGCR
Output pins of the CODEC unit analog signal ground voltage.
SGCT outputs the analog signal ground voltage of the transmit system, and SGCR outputs the
sameforthereceivesystem. Theoutputvoltagevalueisapproximately1.4V. Connect10mFand
0.1 mF bypass capacitors (ceramic type) between these pins and the AGC pin. During power
down,theoutputchangesto0V. TheexternalSGvoltageifnecessaryshouldbeusedviaabuffer.
VDDC, VDAC
CODEC unit +3 V power supply.
VDDC is supplied to the digital system power supply, and VDAC is supplied to the analog
systempowersupply. VDDCandVDAC, andVDDMandVDAMmustbeconnectedaspossible
on the PC board.
DGC, AGC
CODEC unit ground.
DGC is the digital system ground pin, and AGC is the analog system ground pin. Since DGC and
AGC are unconnected in the device, place them as close together as possible on the circuit board.
PDN3
CODEC unit power-down control input.
The CODEC unit changes to the power - down state when set to a digital "0." Since the power-
down control is handled by an OR with control register CRC0 - B5, set CRC0 - B5 to digital "0"
when using this pin.
RESET
Reset control input pin of the CODEC unit control register.
When set to digital "0," each bit of the control register is reset. During normal operation, set this
pin to digital "1." A more than 200ns reset signal should be input.
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PCMSO
Transmit PCM data output.
This PCM output signal is output from MSB synchronous with the rising edge of BCLK and
XSYNC.
PCMSI
Transmit PCM data input.
This signal is converted to the ADPCM data. The PCM signal is shifted on the falling edge of
BCLK. Normally, this pin is connected to PCMSO.
PCMRO
Receive PCM data output.
The PCM signal is the output signal after ADPCM decoder processing. This signal is serially
output from the MSB synchronous with the rising edge of BCLK and RSYNC.
PCMRI
Receive PCM data input.
The PCM input signal is shifted on the falling edge of BCLK and input from MSB. Normally, this
pin is connected to PCMRO.
IS
Transmit ADPCM signal output.
This signal is the output signal after ADPCM encoding, and is serially output from MSB
synchronous with the rising edge of BCLK and XSYNC. This pin is an open drain output which
remains in a high impedence state during power-down, and requires a pull-up resistor.
IR
Receive ADPCM signal input.
Input data is shifted serially from MSB on the falling edge of BCLK synchronous with RSYNC.
BCLK
Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI) and the ADPCM data(IS,
IR) .
The frequency ranges from 64 kHz to 2048 kHz.
XSYNC
Transmit PCM and ADPCM data 8 kHz synchronous signal input.
ThissignalshouldbesynchronouswithBCLK. XSYNCisusedforindicatingMSBofthetransmit
serial PCM and ADPCM data stream.
RSYNC
Receive PCM and ADPCM data 8 kHz synchronous signal input.
This signal should be synchronous with BCLK signal. RSYNC is used for indicating MSB of the
receive serial PCM and ADPCM data stream.
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MSM7586-01/03
VOXO
Transmit VOX function signal output.
VOX function is used to recognize the presence or absence of the transmit voice signal by
detecting the signal energy. "H" and "L" levels on this pin correspond to the presence and the
absence, respectively. This result also appears at the register data CRC7 - B7. The signal energy
detect threshold is set by the control register data CRC6 - B6, B5.
VOXI
Signal input for receive VOX function.
The "H" level on VOXI indicates the presence of voice signal, the decoder block processes normal
receive signal, and the voice signal appears at analog output pins . The "L" level indicates the
absenceofvoicesignal, thebackgroundnoisegeneratedinthisdeviceistransferredtotheanalog
output pins. The background noise amplitude is set by the control register CRC6. Because this
signal is ORed with the register data CRC6 - B3, the control register data CRC6 - B3 should be set
to digital "0".
Input voice signal
GSX2 pin
Voice
Silience
Voice
VOXO pin
Voice detection time
Tvxon
Silence detection time
(Hangover time) Tvxoff
(a) Transmission Side VOX Function Timing Diagram
Voice
Silience
Voice
VOXI pin
Regenerated voice
VFRO pin
Regenerated voice signal
generation time
Internal background
noise generation time
(b) Receive Side VOX Function Timing Diagram
Note: The VOXO and VOXI pin function are enabled when CRC6 - B7 is set to "1".
Figure 7 VOX Function
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DENC, EXCKC, DINC, DOUTC
Serial control ports for MCU interface.
Reading and writing data are performed by an external MCU through these pins. The 8-byte
controlregisters(CRC0- 7)areprovidedfortheCODECunitinthisdevice. DENCisthe"Enable"
controlsignalinput, EXCKCisthedatashiftclockinput, DINCistheaddressanddatainput, and
DOUTC is the data output. Figure 8 shows input/output timing diagram.
DENC
EXCKC
W
A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
DINC
DOUTC
High Impedance
(a) Write Data Timing Diagram
DENC
EXCKC
DINC
R
A2 A1 A0
DOUTC
B7 B6 B5 B4 B3 B2 B1 B0
(b) Read Data Timing Diagram
High Impedance
Figure 8 CODEC Unit MCU Interface I/O Timing
The register map is shown below.
Table 3: CODEC Unit Control Register (CRC0 to 7) Map
Register
Name
Data Description
Address
R/W
R/W
R/W
R/W
R/W
B7
A/m
SEL
B6
B5
PDN
ALL
TX
B4
B3
B2
B1
B0
PDN
A2 A1 A0
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
—
—
—
—
—
SAO/AOUT
RX
RX
TX
MUTE
RX
RX
MUTE
RX
MODE1 MODE0
—
RESET RESET
PAD
TX
TX
TX
TX
RX
RX
ON/OFF GAIN2
GAIN1
GAIN0 ON/OFF GAIN2
GAIN1
TONE
GAIN1
GAIN0
TONE
GAIN0
Side Tone Side Tone Side Tone TONE
TONE
TONE
GAIN2
GAIN1
TONE
SEND
SW2
CONT
ON
GAIN0 ON/OFF GAIN3
SAO/
GAIN2
DTMF/
OTHERS
SEL
TONE4 TONE3 TONE2 TONE1 TONE0 R/W
VFRO
SW3
CONT
ON
SW1
CONT
VOX
SW4/5
CONT
OFF
TOUT3 TOUT2 TOUT1
—
R/W
R/W
R
CONT
CONT
CONT
VOX RX NOISE RX NOISE RX NOISE
ON/OFF
LVL1
LVL0
TIME
IN
LEVEL SEL LVL1
LVL0
—
VOX TX NOISE TX NOISE
OUT LVL1 LVL0
—
—
—
—
R/W: Read/Write enable R: Read-only register
17/42
¡ Semiconductor
MSM7586-01/03
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
Rating
Unit
V
—
—
—
—
–0.3 to +5
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–55 to +150
VAIN
V
VDIN
V
TSTG
°C
RECOMMENDED OPERATING CONDITIONS
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Power Supply Voltage
Operating Temperature
Symbol
VDD
Ta
Conditon
Voltage must be fixed
—
Min.
2.7
Typ.
—
Max.
3.6
Unit
V
–25
+25
+70
°C
0.45 ¥
Input High Voltage
Input Low Voltage
VIH Input pins fully digital
VIL Input pins fully digital
—
—
VDD
V
V
VDD
0.16 ¥
VDD
0
Digital Input Rise Time
Digital Input Fall Time
tIr
tIf
Input pins fully digital
Input pins fully digital
—
—
—
—
—
—
50
50
ns
ns
W
RDL IS (Pull-up resistance)
CDL Input pins fully digital
500
—
—
Digital Output Load
100
pF
Between SGM and AGM,
CSG
Bypass Capacitor for SG
10 + 0.1
—
—
mF
and between SGCT/R and AGC
Master Clock Frequency
Master Clock Duty Ratio
Modulator Side Input
Frequency
FMCK MCK
–0.01%
40
19.2
50
+0.01% MHz
DMCK MCK
60
—
%
kHz
MHz
MHz
MHz
%
FTXC1 TXCI (When CRM0 - B6 = "0")
FTXC2 TXCI (When CRM0 - B6 = "1")
FIFCK1 IFCK (When IFIN = 10.7 MHz)
FIFCK2 IFCK (When IFIN = 10.75 MHz)
DCKM IFCK, TXCI, EXCKM
—
384
3.84
19.0222
19.1111
50
—
—
Demodulator Side
—
—
Input Frequency
—
—
Clock Duty Ratio
40
60
IFIN
IF Input Duty Ratio
DCIF
45
50
55
%
TXCI´TXW
TXCI´TXD
BCLK
Transmit Sync Pulse
Setting Time
tXSM tSXM
200
200
64
—
—
ns
,
Fig.9
tSDM tDHM
,
—
—
ns
FBCK
FSYNC
—
2048
—
kHz
kHz
%
Bit Clock Frequency
Synchronous Signal Frequency
Clock Duty Ratio
XSYNC, RSYNC
BCLK, EXCKC
BCLK´XSYNC
BCLK´RSYNC
XSYNC, RSYNC
—
—
8.0
50
DCKC
40
60
tXSC, tSXC
100
100
1 BCLK
100
100
—
—
ns
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
Synchronous Signal Width
PCM, ADPCM Set-up Time
PCM, ADPCM Hold Time
t
RSC, tSRC
—
—
ns
Fig.12
tWSC
—
100
—
ms
tDSC
—
ns
—
tDHC
—
—
ns
18/42
¡ Semiconductor
MSM7586-01/03
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Symbol
Condition
Min.
—
Typ.
0.02
5.5
Max.
0.1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
Mode A, Mode B (When VDD = 3.0 V)
IDD1
When V = 3.0 V
IDD2 Mode C (
IDD3 Mode D (
IDD4 Mode E (
IDD5 Mode F (
IDD6 Mode G (
)
—
11.0
11.0
23.0
19.0
28.0
16.0
19.0
DD
Power Supply Current
(Modem Unit)
When V = 3.0 V
)
—
5.5
DD
When V = 3.0 V
)
—
11.5
9.5
DD
* When CODEC Unit is in a
Power Down State
When V = 3.0 V
)
—
DD
When V = 3.0 V
)
—
14.0
8.0
DD
When operating *
(When no signal, and VDD = 3.0 V)
IDD7
IDD8
—
Power Supply Current (CODEC Unit)
—
12.0
When powered down
(When VDD = 3.0 V)
* When Modem Unit is in a Power
Down State
IDD9
—
0.02
0.1
mA
IIH VI = VDD
IIL VI = 0 V
—
—
—
—
—
2.0
0.5
mA
mA
V
Input Leakage Current
Output High Voltage
Output Low Voltage
—
IOH = 0.4 mA
0.5 ¥ VDD
0.8 ¥ VDD
VDD
VDD
VOH
VOL
IOH = 1 mA
V
IOL = –1.2 mA
0
0.2
0.4
V
(IS pin is 500 W pull-up)
Output Leakage Current
Input Capacitance
IO
IS pin
—
—
—
5
10
—
mA
CIN
—
pF
*
I
applies when CRC0 - B0 = "0" and CRC4 - B5 = "0"; I
applies when operating at other
DD7
DD8
times.
19/42
¡ Semiconductor
MSM7586-01/03
Analog Interface Characteristics (Modem Unit)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Output Resistance Load
Output Capacitance Load
Output DC Voltage Level
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
kW
pF
RLIQ I+, I–, Q+, Q–
CLIQ I+, I–, Q+, Q–
—
—
20
VDCM I+, I–, Q+, Q– (TXW = 0)
1.55
1.6
1.65
V
I+, I–, Q+, Q–
VACM
Output AC Voltage Level
Offset Voltage Difference
340
–20
—
360
—
380
+20
—
mVPP
mV
(For TXD = 0 continuous input)
Difference among
VOFF
I+, I–, Q+ and Q–
Modulator D/A
FSDA
FCDA
—
—
1.92
380
MHz
kHz
Conversion Sampling Frequency
Modulator D/A
—
—
Conversion Offset Frequency
Output DC Voltage Adjustment Level Range DCVL
Output AC Voltage Adjustment Level Range ACVL
—
—
—
—
60
65
45
4
—
—
—
—
mV
%
P600 600 kHz detuning (continuous)
P900 900 kHz detuning (continuous)
—
—
dB
dB
%
Out-of-band Spectrum
Modulation Accuracy
EVM
—
—
1.0
3.0
rms
VPP
kW
V
Demodulator Side IF Input Level
IFIN Input Impedance
IFV IFIN input level
RIF DC impedance
0.4
—
—
—
—
20
VDD
—
SGM Output Voltage
VSGM
RSGM
—
2.0
1.5
—
SGM Output Impedance
—
—
kW
X1 input level
IX11
IX12
1.5
0.7
—
—
VDD
VDD
VPP
VPP
(When CRM5 – B1 = "0")
Master Clock External Input Level
X1 input level
(When CRM5 – B1 = "1")
X1 Input Impedande
X1 Input Capacitance
RX1
CX1
—
—
—
—
2.0
10
—
—
MW
pF
20/42
¡ Semiconductor
MSM7586-01/03
Digital Interface Characteristics (Modem Unit)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Symbol
Condition
Reference Min.
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
200
400
200
—
Unit
ns
Transmit
0
tXDM1,2
Fig. 9
0
C load = 50 pF
Digital I/O Setting Time
tXDM3,4
ns
Receive Digital I/O Setting Time
tRDM1,2 C load = 50 pF
Fig. 10
Fig. 11
—
0
50
50
50
50
100
50
50
0
ns
tM1
tM2
tM3
tM4
tM5
ns
—
ns
—
ns
—
ns
—
ns
Serial Port
tM6
—
ns
C load = 50 pF
tM7
Digital I/O Setting Time
—
ns
tM8
100
—
ns
tM9
50
50
0
ns
tM10
—
ns
tM11
50
ns
tM12
200
—
—
ns
EXCK Clock Frequency
Feckm EXCKM
10
MHz
21/42
¡ Semiconductor
MSM7586-01/03
Analog Interface Characteristics (CODEC Unit)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Input Resistance
Symbol
Condition
AIN+, AIN–, AIN2, PWI,
AIN3, AIN4
Min.
Typ.
Max.
Unit
RINC
10
—
—
MW
RLC1 GSX1, GSX2, VFRO, SAO
RLC2 AOUT+, AOUT–, GSX4
RLC3 GSX3
20
1.2
150
—
—
—
—
—
—
—
—
—
kW
kW
W
Output Resistance Load
Output Capacitance Load
—
CLC1 GSX1, GSX2, VFRO, SAO
CLC2 AOUT+, AOUT–, GSX4
CLC3 GSX3
100
100
100
pF
pF
pF
—
—
GSX1, GSX2, VFRO,
VOC1
—
—
—
—
1.3
1.3
VPP
VPP
SAO(RL = 20 kW)
AOUT+, AOUT–, GSX4
VOC2
Output Voltage Level (*1)
(RL = 1.2 kW)
VOC3 GSX3(RL = 150 W)
—
—
—
1.3
VPP
mV
VOFC1 VFRO, SAO
–100
+100
GSX1, GSX2, AOUT+,
VOFC2
Offset Voltage
–20
—
+20
mV
AOUT–, GSX3, GSX4
SGCT, SGCR Output Voltage
SGCT Output Impedance
SGCR Output Impedance
VSGC SGCT, SGCR
RSGCT SGCT
—
—
—
1.4
40
4
—
80
8
V
kW
kW
RSGCR SGCR
For the Recommended Circuit
TSGCT
SGCT Rise Time
SGCR Rise Time
—
—
600
15
—
—
ms
ms
(Rise time to 90% of max. level)
For the Recommended Circuit
TSGCR
(Rise time to 90% of max. level)
Analog Switch OFF Resistance
Analog Switch ON Resistance
RSWof SW1 to SW5
RSWon SW1 to SW5
50
—
—
—
MW
100
400
W
Note : *1
–7.7 dBm (600 W) = 0 dBm0, +3.14 dBm0 = 1.30 V (A-law)
PP
–7.7 dBm (600 W) = 0 dBm0, +3.17 dBm0 = 1.30 V (m-law)
PP
22/42
¡ Semiconductor
MSM7586-01/03
Digital Interface Characteristics (CODEC Unit)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Symbol
Condition
Min.
0
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
Unit
Reference
1 LSTTL + 100 pF
pull-up : 500 W
Items in parenthesis
( ) mean C load = 10 pF,
and the pull-up £ 2 kW
200 (100) ns
200 (100) ns
200 (100) ns
200 (100) ns
tSDXC, tSDRC
tXDC1, tRDC1
tXDC2, tRDC2
tXDC3, tRDC3
tC1
Digital Output Delay Time
PCM, ADPCM Interface
0
Fig. 12
0
0
50
50
50
50
100
50
50
0
—
—
—
—
—
—
—
100
—
—
50
—
10
ns
ns
tC2
tC3
ns
tC4
ns
tC5
ns
Serial Port Digital I/O
Timing Characteristics
tC6
ns
C load = 50 pF
Fig. 13
tC7
ns
tC8
ns
tC9
50
50
0
ns
tC10
tC11
tC12
ns
ns
200
—
ns
EXCK Clock Frequency
Feckc EXCKC
—
MHz
23/42
¡ Semiconductor
MSM7586-01/03
AC Characteristics (CODEC Unit)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Condition
Parameter
Symbol
OSS T1
Min.
Typ.
Max.
Unit
Frequency (Hz)
Level dBm0
L
0 to 60
300 to 3 k
1020
25
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
LOSS T2
LOSS T3
LOSS T4
LOSS T5
LOSS T6
LOSS R1
LOSS R2
LOSS R3
LOSS R4
LOSS R5
SD T1
SD T2
SD T3
SD T4
SD T5
SD R1
SD R2
SD R3
SD R4
SD R5
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
–0.15
—
+0.20
Transmit Frequency
Response
Reference
0
3300
–0.15
0
—
+0.80
0.80
—
3400
—
3968.75
0 to 3000
1020
13
—
–0.15
—
+0.20
Reference
Receive Frequency
Response
3300
0
–0.15
0
—
+0.80
0.80
—
3400
—
3968.75
13
—
3
35
—
—
0
35
—
—
Transmit Signal to
1020
1020
1020
1020
–30
–40
–45
3
35
—
—
Distortion Ratio (*2)
28
—
—
23
—
—
35
—
—
0
35
—
—
Receive Signal to
–30
–40
–45
3
35
—
—
Distortion Ratio (*2)
28
—
—
23
—
—
–0.2
—
+0.2
–10
–40
–50
–55
3
Reference
Transmit Gain
Tracking
–0.2
–0.5
–1.2
–0.2
—
+0.2
+0.5
+1.2
+0.2
—
—
—
–10
–40
–50
–55
Reference
—
Receive Gain
Tracking
–0.2
–0.5
–1.2
+0.2
+0.5
+1.2
—
—
Note: *2
P-message filter used
24/42
¡ Semiconductor
MSM7586-01/03
AC Characteristics (CODEC Unit)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Condition
Symbol Frequency (Hz) Level dBm0 Other
Parameter
Min.
—
Typ.
—
Max.
Unit
–68
Idle Channel
Noise
NIDLT
—
—
AIN = SG
—
—
(–75.7) dBm0p
–72
(dBmp)
(*2)
NIDLR
(*3)
0
—
—
(–79.7)
AVT
AVR
GSX2 0.285
VFRO 0.285
0.320
0.320
—
0.359 Vrms
0.359 Vrms
Absolute Level (*4)
1020
Power Supply Noise
Rejection Ratio
PSRRT Noise frequency:
PSRRR 0 kHz to 50 kHz
Noise level:
50 mVpp
30
—
—
dB
dB
—
30
—
Notes: *2 P-message filter used
*3 PCMRI input: "11010101" (A-law), "11111111" (m-law)
*4 0.320 Vrms = 0 dBm0 = –7.7 dBm (600 W)
ADPCM unit characteristics are fully compliant with ITU-T Recommendation G.726.
AC Characteristics (DTMF and Other Tones)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Symbol
Condition
Min.
–7
Typ.
—
Max.
+7
Unit
Hz
DFT1 DTMF tones
Frequency Deviation
DFT2 Other various tones
–7
—
+7
Hz
VTL Transmit side tone DTMF (low group)
–18
–16
–10
–8
–16
–14
–8
–14
–12
–6
dBm0
dBm0
dBm0
dBm0
dB
Tone Reference
Output Level
(*5)
(Gain setting 0dB)
VTH
VRL
DTMF (high group), other
DTMF (low group)
Receive side tone
(Tone generator
VRH gain setting –6dB) DTMF (high group), other
–6
–4
DTMF Tone Level Relative Value RDTMF
V
TH/VTL, VRH/VRL
1
2
3
Note:
*5 Not including programmable gain set values
AC Characteristics (Gain Settings)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Transmit/Receive Gain
Setting Accuracy
Symbol
Condition
Min.
Typ.
Max.
Unit
DG
For all gain set values
–1
0
+1
dB
AC Characteristics (VOX Function)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Transmit VOX
Symbol
Condition
Min.
Typ.
Max.
Unit
*6
TVXON SilenceÆvoice
—
10
—
ms
VOXO pin: See Fig. 7
Detection Time
(Voice and Silence
Test Time)
Voice/silence
TVXOF VoiceÆsilence
140/300 160/320 180/340 ms
differential: 10 dB
Transmit VOX
For detection level set values by
CRM6 - B6, B5
DVX
Detection Level Accuracy
(Voice Detection Level)
–2.5
0
+2.5
dB
Note:
*6 When single tone is input at 1000Hz
25/42
¡ Semiconductor
MSM7586-01/03
TIMING DIAGRAM
(Modem Unit)
Transmit Data Input Timing
1
2
3
N-2
N-1
N
tXSM
N+1
TXCI [TXCO*]
(384 kHz)
tXSM
tSXM
tDHM
tSXM
TXW
TXD
tDSM
1
2
3
N-2
N-1
N
TXCO in brackets [ ] is when CRM0 - B6 = 1
Transmit Clock (TXCO) Timing (When CRM0 - B6 = 1)
1
2
3
4
5
6
7
8
9
10
tXDM1
TXCI
(3.84 MHz)
tXDM1
tXDM2
TXCO
(384 kHz)
Transmit Burst Position (BSTO) Output Timing (When CRM0 - B6 = 0)
1
2
9
10
N
N+1
N+16
N+17
N+18
TXCI
(384 kHz)
TXW
tXDM3
tXDM4
BSTO
Figure 9 Modem Unit Transmit Side (Modulator Side) Digital I/O Timing
Receive Side Data I/O Timing
SLS
RXC
tRDM2
tRDM1
RXD
Figure 10 Modem Unit Receive Side (Demodulator Side) Digital I/O Timing
Serial Port Timing for Microcontroller Interface
DENM
tM12
tM10
tM5
tM2
EXCKM
1
2
3
4
5
6
11
12
tM6
tM7
tM9
tM1
tM3
tM4
DINM
W/R
A2
A1
A0
B7
B1
B0
tM11
tM8
B7
DOUTM
B1
B0
Figure 11 Modem Unit Serial Control Port Interface
26/42
¡ Semiconductor
MSM7586-01/03
(CODEC Unit)
Transmit Side PCM, ADPCM Timing
0
1
2
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
BCLK
XSYNC
PCMSO
BCLK
XSYNC
IS
tSXC
tWSC
tXSC
tXDC1
tXDC2
tXDC3
LSB
MSB
tSDXC
0
1
2
3
tSXC
tXSC
tXDC1
tXDC2
tXDC3
LSB
MSB
tSDXC
Receive Side PCM, ADPCM Timing
1
2
3
tWSC
4
4
5
5
6
6
7
7
8
8
9
9
10
10
BCLK
tSRC
tRSC
RSYNC
IR
tDHC
tXDC3
tDSC
MSB
LSB
BCLK
0
1
2
3
tSRC
tRSC
RSYNC
tRDC1
tRDC2
tRDC3
LSB
MSB
PCMRO
tSDXC
Figure 12 CODEC Unit PCM, ADPCM Interface
Serial Port Timing for Microcontroller Interface
DENC
tC12
tC10
tC5
tC2
EXCKC
1
2
3
4
5
6
11
12
tC6
tC7
tC9
tC1
tC3
tC4
DINC
W/R
A2
A1
A0
B7
tC8
B1
B0
tC11
B7
DOUTC
B1
B0
Figure 13 CODEC Unit Serial Control Port Interface
27/42
¡ Semiconductor
MSM7586-01/03
Modem Unit Mode State Transition Time
Mode A*
PDN1 = 1
Note: Values not indicated are
less than 1 ms.
1 ms
Mode
B
Mode
Mode
C
F
PDN1 = 0
PDN2 = 0
PDN1 = 0
PDN2 = 1
Standby mode (PDN0 = 0)
Communication mode (PDN0 = 1)
40 ms
5 ms
Mode
E
Mode
Mode
D
PDN1 = 1
PDN2 = 0
PDN1 = 0
PDN2 = 0
PDN1 = 0
PDN2 = 1
5 ms
40 ms
G
PDN1 = 1
PDN2 = 1
*Note that this state
clears the register.
Figure 14 Modem Unit Power Down State Transition Time
28/42
¡ Semiconductor
MSM7586-01/03
Modem Unit Demodulator Control Timing Diagram (Example)
1st slot
R1
Demodulator unit
Modulator input data
G
G
PDN2
"0"
SLS
AFC
RXD
RXC
R1
(1) Control ch/
synchronous burst
(SS + PR = 64 bits)
240 bits
625 ms
64 bits
RXD
G
G
G
G
G
G
G
G
R
R
R
R
SS SS PR PR
PR UW
CR CR
G
G
G
G
G
G
G
G
AFC*
RPR
RCW*
56 bits
(2) When synchronization is not yet established
AFC*
RPR
RCW*
(3) Communication ch
(SS + PR = 8 bits)
8 bits
SS SS PR PR
RXD
AFC
G
G
G
G
G
G
G
G
R
R
R
R
PR UW
CR CR
G
G
G
G
G
G
G
G
"0"
RPR
RCW
G: Guard bit
R: Ramp bit
Less than 30 bits
*AFC and RCW may be controlled at the same timing.
SS: Start symbol bit
PR: Preamble bit
UW: Unique word bit
CR: CRC bit
Figure 15 Modem Unit Demodulator Timing Diagram Example
29/42
¡ Semiconductor
MSM7586-01/03
FUNCTIONAL DESCRIPTION
Control Register Description Table
(Modem Unit)
(1) CRM0 (Basic Operation Mode Setting)
B7
—
0
B6
TXC
SEL
0
B5
MOD
OFF
0
B4
IFSEL1
0
B3
IFSEL0
0
B2
—
0
B1
TEST1
0
B0
TEST0
0
CRM0
Initial Value (Note)
Note:
The initial value is the value set when a reset is applied by the RESET pin.
B7, B2: ..... Not used
B6: ............ Transmission timing clock selection
0: TXCI input: 384 kHz TXCO output: APLL 384 kHz output
Transmission data TXD is input synchronized to the rise of TXCI. APLL is
ON.
1: TXCI input: 3.84 MHz TXCO output: 384 kHz (TXCI divided by 10)
Transmission data TXD is input synchronized to the rise of TXCO. APLL
is OFF.
B5:
Modulation OFF/ON control
0: Modulation ON
1: Modulation OFF
B4, B3: ..... Receive side input IF frequency selection
(0,0), (0,1): 1.2 MHz
(1,0):
(1,1):
10.8 MHz
10.7 MHz/10.75 MHz
B1, B0: ..... Device test control bit
Since it is used for LSI testing, it is normally set to "0."
30/42
¡ Semiconductor
MSM7586-01/03
(2) CRM1 (I and Q Gain Adjustment)
B7
Ich
B6
Ich
B5
Ich
B4
Ich
B3
Qch
GAIN3
0
B2
Qch
GAIN2
0
B1
Qch
GAIN1
0
B0
Qch
GAIN0
0
CRM1
GAIN3
0
GAIN2
0
GAIN1
0
GAIN0
0
Initial Value
B7 to B4:....I+ and I- output gain setting: 3 mV steps (refer to Table 4)
B3 to B0:....Q+ and Q- output gain setting: 3 mV steps (refer to Table 4)
Table 4: I and Q Gain Setting Table
CRM1 - B7 B6 B5 B4
CRM1 - B3 B2 B1 B0
Description
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Amplitude value: 1.042 reference value
1.036
1.030
1.024
1.018
1.012
1.006
1.000 (Reference value)
0.994
0.988
0.982
0.976
0.970
0.964
0.958
0.952
(3) CRM2 (Output to R7 to R4 pins)
B7
R7
0
B6
R6
0
B5
R5
0
B4
R4
0
B3
—
0
B2
—
0
B1
—
0
B0
—
0
CRM2
Initial Value
B7 to B4: ....Output to R7 to R4 pin
31/42
¡ Semiconductor
MSM7586-01/03
(4) CRM3 (I- Output Offset Voltage Adjustment)
B7
Ich
B6
Ich
B5
Ich
B4
Ich
B3
Ich
B2
—
0
B1
—
0
B0
—
0
CRM3
Offset4
0
Offset3
0
Offset2
0
Offset1
0
Offset0
0
Initial Value
B7 to B3:....I- output pin offset voltage adjustment (refer to Table 5)
B2 to B0:....Not used
(5) CRM4 (Q- Output Offset Voltage Adjustment)
B7
Qch
B6
Qch
B5
Qch
B4
Qch
B3
Qch
B2
—
0
B1
—
0
B0
—
0
CRM4
Offset4
0
Offset3
0
Offset2
0
Offset1
0
Offset0
0
Initial Value
B7 to B3:....Q- output pin offset voltage adjustment (refer to Table 5)
B2 to B0:....Not used
Table 5: Ich and Qch Offset Adjustment Values
CRM3 - B7 B6 B5 B4 B3
CRM4 - B7 B6 B5 B4 B3
Offset Voltage
CRM3 - B7 B6 B5 B4 B3
CRM4 - B7 B6 B5 B4 B3
Offset Voltage
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+45 mV
+42 mV
+39 mV
+36 mV
+33 mV
+30 mV
+27 mV
+24 mV
+21 mV
+18 mV
+15 mV
+12 mV
+9 mV
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
–3 mV
–6 mV
–9 mV
12
–
mV
–15 mV
–18 mV
–21 mV
–24 mV
–27 mV
–30 mV
–33 mV
–36 mV
–39 mV
–42 mV
–45 mV
–48 mV
+6 mV
+3 mV
0 mV
32/42
¡ Semiconductor
MSM7586-01/03
(6) CRM5 (IC Test)
B7
B6
ICT4
0
B5
ICT3
0
B4
ICT2
0
B3
LOCAL
INV1
0
B2
LOCAL
INV0
0
B1
ICT1
0
B0
ICT0
0
CRM5
ICT5
0
Initial Value
B7 to B4:....LSI test control bit
Note:
Since B7 to B4 of CRM5 are used for LSI testing, they should normally be set to "0".
B3, B2: .......Local inverted mode setting bit
(Use if the phase of the demodulator side IF input is inverted due to the
system configuration.)
(0,0): Normal mode(1,1): Local inverted mode
B1:..............Waveform shaping mode switching bit of the oscillator circuit unit clock
(When using a master clock external input, increase the X1 pin input
sensitivity.)
0: Normal mode 1: Clock waveform shaping mode
B0:..............Oscillator circuit unit power on control bit
0: Normal mode 1: Oscillator circuit unit is always powered on
33/42
¡ Semiconductor
MSM7586-01/03
(CODEC Unit)
(1) CRC0 (Basic Operation Mode Settings)
B7
A/m
SEL
0
B6
—
0
B5
PDN
ALL
0
B4
—
0
B3
—
0
B2
B1
—
0
B0
PDN
CRC0
—
SAO/AOUT
0
Initial Value
0
B7:........................... PCM interface companding selection
B6, B4, B3, B2, B1: . Notused(Thesepinsareusedtotestthedevice. Theyshouldbeset
0: m-law
1: A-law
to "0" during normal operation.)
B5:........................... Power down (entire unit) 0: Power ON 1: Power down
ORed with the inverse of the external power down signal. When
using this data, set PDN3 to "1."
B0:........................... The sounder output amp (SAO, GSX3) and receiver system output
amp (VFRO, AOUT+, AOUT-) power down control
0: The output amp of the side not selected by CRC4 - B5 is powered
down.
1: The sounder system output amp and receiver system output
amp are both powered ON.
(2) CRC1 (ADPCM Unit Operation Mode Settings)
B7
MODE1
0
B6
MODE0
0
B5
TX RESET
0
B4
RX RESET
0
B3
B2
B1
—
0
B0
RX PAD
0
CRC1
TX MUTE RX MUTE
Initial Value
0
0
B7, B6: .......ADPCM unit compression algorithm selection
(0,0): 32 kbps
(1,0): 24 kbps
(0,1): 64 kbps (G.711 through)
(1,1): 16 kbps
B5:..............Transmit side ADPCM reset (according to the G.726
specifications): 1: Reset
The ADPCM reset input width should be 125 ms or more.
B4:..............Receive side ADPCM reset (according to the G.726
specifications): 1: Reset
The ADPCM reset input width should be 125 ms or more.
B3:..............Transmit side ADPCM data mute: 1: Mute
B2:..............Receive side ADPCM data mute: 1: Mute
B1:..............Not used
B0:..............Receive side PAD 0: No PAD
1: A PAD with a 12 dB loss is inserted in the receive side voice path
34/42
¡ Semiconductor
MSM7586-01/03
(3)CRC2(PCMCODECUnitOperationModeSettingsandTransmit/ReceiveGainAdjustment)
B7
TX
B6
TX
B5
TX
B4
TX
B3
RX
B2
RX
B1
RX
B0
RX
CRC2
ON/OFF
0
GAIN2
0
GAIN1
1
GAIN0
1
ON/OFF
0
GAIN2
0
GAIN1
1
GAIN0
1
Initial Value
B7:..............Transmit side PCM signal ON/OFF 0: ON 1: OFF
When OFF, transmits a PCM idle pattern.
B6, B5, B4: Transmit side signal gain adjustment (refer to Table 6)
B3:..............Receive side PCM signal ON/OFF 0: ON 1: OFF
When OFF transmits a PCM idle pattern.
B2, B1, B0: .Receive side signal gain adjustment (refer to Table 6)
Table 6: Receive/Transmit Gain Settings
• MSM7586-01
B6
0
B5
0
B4
0
Transmit Side Gain
B2
0
B1
0
B0
0
Receive Side Gain
–6 dB
–4 dB
–2 dB
0 dB
–6 dB
–4 dB
–2 dB
0 dB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
+2 dB
+4 dB
+6 dB
+8 dB
1
0
0
+2 dB
+4 dB
+6 dB
+8 dB
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
• MSM7586-03
B6
0
B5
0
B4
0
Transmit Side Gain
B2
0
B1
0
B0
0
Receive Side Gain
–6 dB
–4 dB
–2 dB
0 dB
–12 dB
–9 dB
–6 dB
–3 dB
0 dB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
+2 dB
+4 dB
+6 dB
+8 dB
1
0
0
1
0
1
1
0
1
+3 dB
+6 dB
+9 dB
1
1
0
1
1
0
1
1
1
1
1
1
The above gain settings table shows the transmit/receive voice signal gain settings and the
transmit side gain settings for DTMF tones and other tones. Tone signal transmission is enabled
by CRC4 - B6 (discussed later), and the gain setting is set to the levels shown below.
DTMF tones (low group):................................. –16 dBm0
DTMF tones (high group) and other tones: ... –14 dBm0
For example, if the transmit gain set value is set to +8 dB (B6, B5, B4) = (1, 1, 1), then the following
tones appear at the PCMSO pin.
DTMF tones (low group):................................. –8 dBm0
DTMF tones (high group) and other tones: ... –6 dBm0
35/42
¡ Semiconductor
MSM7586-01/03
However, the gain of the receive side tone and the gain of the side tones (path from transmit side
to receive side) are set by the CRC3 register.
(4) CRC3 (Side Tone and Tone Generator Gain Adjustment)
B7
B6
B5
B4
TONE
ON/OFF
0
B3
TONE
GAIN3
0
B2
TONE
GAIN2
0
B1
TONE
GAIN1
0
B0
TONE
GAIN0
0
Side Tone Side Tone Side Tone
CRC3
GAIN2
0
GAIN1
0
GAIN0
0
Initial Value
B7, B6, B5: ........ Side tone gain adjustment (refer to Table 7)
B4:..................... Tone generator ON/OFF 0: OFF 1: ON
B3, B2, B1, B0: . Tone generator
Receive side gain adjustment (refer to Table 8)
Table 7: Side Tone Gain Settings
• MSM7586-01
B7
0
B6
0
B5
0
Side Tone Gain
OFF
0
0
1
–21 dB
0
1
0
–19 dB
0
1
1
–17 dB
1
0
0
–15 dB
1
0
1
–13 dB
1
1
0
–11 dB
1
1
1
– 9 dB
• MSM7586-03
B7
0
B6
0
B5
0
Side Tone Gain
OFF
–15 dB
0
0
1
–13 dB
0
1
0
–11 dB
0
1
1
– 9 dB
1
0
0
– 7 dB
1
0
1
– 5 dB
1
1
0
– 3 dB
1
1
1
36/42
¡ Semiconductor
MSM7586-01/03
Table 8: Receive Side Tone Generator Gain Settings
• MSM7586-01
B3
0
B2
0
B1
0
B0 Tone Generator Gain B3
B2
0
B1
0
B0 Tone Generator Gain
0
1
0
1
0
1
0
1
–36 dB
–34 dB
–32 dB
–30 dB
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
–20 dB
–18 dB
–16 dB
0
0
0
0
0
0
0
1
0
1
–14
–12
–10
– 8
– 6
0
0
1
0
1
dB
dB
dB
dB
dB
–28
–26
–24
–22
0
1
0
dB
dB
dB
dB
1
0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
• MSM7586-03
B3
0
B2
0
B1
0
B0 Tone Generator Gain B3
B2
0
B1
0
B0 Tone Generator Gain
0
1
0
1
0
1
0
1
OFF
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
–20 dB
–18 dB
–16 dB
0
0
0
–34 dB
–32 dB
–30 dB
0
0
0
0
1
0
1
–14
–12
–10
– 8
– 6
0
0
1
0
1
dB
dB
dB
dB
dB
–28
–26
–24
–22
0
1
0
dB
dB
dB
dB
1
0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
The receive side tone generator gain settings shown in Table 8 are set with the following levels
as a reference.
DTMF tones (low group):................................. –2 dBm0
DTMF tones (high group) and other tones: ... 0 dBm0
For example, if the tone generator gain set value is set to -6 dB (B3, B2, B1, B0)=(1, 1, 1, 1), then
tones at the following levels appear at the SAO or VFRO pin.
DTMF tones (low group):................................. –8 dBm0
DTMF tones (high group) and other tones: ... –6 dBm0
37/42
¡ Semiconductor
MSM7586-01/03
(5) CRC4 (Tone Generator Operation Mode and Frequency Settings)
B7
DTMF/OT
HERS SEL
0
B6
TONE
SEND
0
B5
SAO/
VFRO
0
B4
TONE4
0
B3
TONE3
0
B2
TONE2
0
B1
TONE1
0
B0
TONE0
0
CRC4
Initial Value
B7:........................... Selection of DTMF signal and other tones
(S tone, F tone, R tone, etc.) 0: Other tones 1: DTMF tones
B6:........................... Transmission side tone transmit
0: Voice signal transmit 1: Tone transmit
B5:........................... Receive side tone output pin selection
0: VFRO output 1: SAO output
B4, B3, B2, B1, B0: . Tone frequency setting (refer to Table 9)
Table 9: Tone Generator Frequency Settings
(a) When B7 = 1 (DTMF Tones)
B4 B3 B2 B1 B0
Description
B4 B3 B2 B1 B0
Description
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
697 Hz + 1209 Hz
697 Hz + 1336 Hz
697 Hz + 1477 Hz
697 Hz + 1633 Hz
770 Hz + 1209 Hz
770 Hz + 1336 Hz
770 Hz + 1477 Hz
770 Hz + 1633 Hz
*
*
*
*
*
*
*
*
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
852 Hz + 1209 Hz
852 Hz + 1336 Hz
852 Hz + 1477 Hz
852 Hz + 1633 Hz
941 Hz + 1209 Hz
941 Hz + 1336 Hz
941 Hz + 1477 Hz
941 Hz + 1633 Hz
(b) When B7 = 0 (Outside of DTMF Tones)
B4 B3 B2 B1 B0
Description
B4 B3 B2 B1 B0
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2730 Hz/2500 Hz 8 Hz Wamble
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
2000 Hz/2667 Hz 8 Hz Wamble
1300 Hz Single tone
1000 Hz/1333 Hz 8 Hz Wamble
1333 Hz Single tone
—
—
—
—
—
2000 Hz Single tone
—
—
—
—
—
—
400 Hz Single tone
—
—
—
—
—
—
2667 Hz Single tone
—
—
—
2730 Hz Single tone
—
1000 Hz Single tone
38/42
¡ Semiconductor
MSM7586-01/03
(6) CRC5 (Control of Switches, etc.)
B7
SW1
CONT
0
B6
SW2
CONT
0
B5
SW3
CONT
0
B4
SW4/5
CONT
0
B3
—
0
B2
TOUT3
CONT
0
B1
TOUT2
CONT
0
B0
TOUT1
CONT
0
CRC5
Initial Value
B7, B6: .......SW1, SW2 control
B5:..............SW3 control
0: Open
0: Open
1: Closed
1: Closed
B4:..............SW4/5 control
0: SW4 open, SW5 closed
1: SW4 closed, SW5 open
0: TOUT3 to 1 disable
1: TOUT3 to 1 enable
B2, B1, B0: .TOUT3 to 1 control
(7) CRC6 (VOX Function Control)
B7
VOX
ON/OFF
0
B6
ON
B5
ON
B4
OFF
TIME
0
B3
VOX
IN
B2
RX NOISE
LEVEL SEL
0
B1
RX NOISE
LVL1
0
B0
RX NOISE
LVL0
0
CRC6
LVL1
0
LVL0
0
Initial Value
0
B7:..............VOX function ON/OFF
0: OFF
1: ON
B6, B5: .......Transmit side voice/silence detector level settings (For the signal of 1kHz)
MSM7586-01
(0,0): –30 dBm0
(1,0): –40 dBm0
(0,1): –35 dBm0
(1,1): –45 dBm0
MSM7586-03
(0,0): –20 dBm0
(1,0): –32 dBm0
(0,1): –26 dBm0
(1,1): –38 dBm0
B4:.............. Hangover time (refer to Fig. 7) settings 0: 160 ms
B3:..............Receive side VOX input signal
1: 320 ms
0: Internal background noise transmit
1:Voicereceivesignaltransmit
When using this data, set the VOXI pin to "0."
B2:..............Receive side background noise level setting
0: Internal automatic setting
1: External (by B1, B0) setting
Internal automatic setting Æ Sets to the voice signal level when B3 (VOXI)
changes from "1" to "0."
B1, B0: .......External setting background noise level
(0,0): No noise
(1,0): –45 dBm0
(0,1): –55 dBm0
(1,1): –35 dBm0
39/42
¡ Semiconductor
MSM7586-01/03
(8) CRC7 (Detect Register: Read-only)
B7
VOX
OUT
0
B6
B5
B4
—
*
B3
—
*
B2
—
*
B1
—
*
B0
Silent Level Silent Level
CRC7
—
*
1
0
0
0
Initial Value
B7:........................... Transmit side voice/silence detection
B6, B5: .................... Transmit side silence level (indicator)
MSM7586-01
0: Silence
1: Voice
(0,0):Below –60 dBm0
(1,0): –40 to –50 dBm0
(0,1): –50 to –60 dBm0
(1,1): Above –40 dBm0
MSM7586-03
(0,0):Below –50 dBm0
(1,0): –30 to –40 dBm0
(0,1): –40 to –50 dBm0
(1,1): Above –30 dBm0
Note:
These outputs are enabled when the VOX function is turned ON by CRC6 - B7.
B4, B3, B2, B1, B0: . Not used
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¡ Semiconductor
MSM7586-01/03
APPLICATION CIRCUIT
MSM7586
100
1
87
88
89
79
78
77
76
VDDM
VDAM
VDDC
VDAC
SGM
PDN2
PDN1
30
29
7
PDN0
DENM
EXCKM
DOUTM
DINM
10
11
SGCR
SGCT
+
–
+
–
+
–
9
67
8
69
71
72
73
74
81
82
83
84
85
98
99
AGC
DGC
AGM
DGM
BSTO
TXCI
TXCO
TXD
MODEM
CONT.
68
TXW
RXD
RXC
RPR
AFC
1000 pF
97
2
IFIN
Q–
Q+
I–
3
RF
4
5
I+
RCW
SLS
12
13
14
18
19
25
24
23
22
26
27
28
32
33
38
39
40
SGCT
R3
AIN1+
AIN1–
GSX1
AIN2
RXSC
1
mF
R1
MIC
R2
41
42
44
45
46
47
61
60
59
PDN3
RESET
DINC
R4
R5
GSX2
AOUT+
AOUT–
PWI
DOUTC
EXCKC
DENC
Speaker
R6
VFRO
SAO
BCLK
R7
XSYNC
RSYNC
R8
ADPCM
CODEC
AIN3
Sounder
Ringer
GSX3
AIN4
VDDC
500 W
57
56
55
53
52
51
PCMSO
PCMSI
IS
CONT.
GSX4
TOUT1
TOUT2
TOUT3
IR
PCMRO
PCMRI
90
91
95
92
19.2 MHz
MCK
IFCK
X1
49
50
VOXI
VOXO
X2
R1 ≥ Output drive resistance of MIC
R2//R3 ≥ 20 kW
R4, R5, R7 ≥ 20 kW
R6//Input resistance of speaker ≥ 1.2 kW
R8//Input resistance of sounder ≥ 150 W
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¡ Semiconductor
PACKAGE DIMENSIONS
TQFP100-P-1414-0.50-K
MSM7586-01/03
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
Solder plate thickness
Package weight (g)
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
42/42
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