MSM7602-001GS-K [OKI]
ISDN Echo Canceller, 1-Func, CMOS, PDSO28, 0.485 INCH, 0.65 MM PITCH, PLASTIC, SSOP-28;
| 型号： | MSM7602-001GS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | ISDN Echo Canceller, 1-Func, CMOS, PDSO28, 0.485 INCH, 0.65 MM PITCH, PLASTIC, SSOP-28 综合业务数字网 光电二极管 |
| 文件： | 总32页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7602-04
OKI Semiconductor
Issue Date: Jun. 1, 2005
MSM7602
Echo Canceler
GENERAL DESCRIPTION
The MSM7602 is an improved version of the MSM7520 with the same basic configuration. The
MSM7602 uses a 19.2 MHz clock frequency to meet PHS, the 3 V power supply (2.7 V to 5.5 V),
and compact packaging. Also, this device adds the howling detecter control pins and main clook
output pins. (See the Appendix)
The MSM7602 is a low-power CMOS IC device for canceling echo (in an acoustic system or
telephone line) generated in a speech path.
Echo is canceled, in digital signal processing, by estimating the echo path and generating a
pseudo echo signal.
When used as an acoustic echo canceler, the device cancels the acoustic echo between the loud
speaker and the microphone which occurs during hands free communication such as with a
cellular phone or a conference system phone.
When used as a line echo canceler, the device cancels the line echo caused by impedance
mismatching in a hybrid.
In addition, the MSM7602 makes possible a quality conversation by controlling the noise level
and preventing howling with howling detector, double talk detector, attenuation function, and
a gain control function. The devise also controls the low level noise with a center clipping
function.
Further, theMSM7602I/Ointerfacesupportsm-lawPCM. TheuseofasinglechipCODEC, such
as the MSM7566/7704 (3 V) or MSM7543/7533 (5 V), allows an economic and efficient echo
canceler configuration.
FEATURES
• Handles both acoustic echoes and telephone line echoes.
• Cancelable echo delay time:
MSM7602-001................. For a single chip: 23 ms (max.)
MSM7602-011................. For a cascade connection (can also be used for a single chip)
Master chip: 23 ms (max.)
Slave chip: 31 ms (max.)
Cancelable up to 209 ms (1 master plus 6 slaves)
For a single chip: 23 ms (max.)
• Echo attenuation
• Clock frequency
: 30 dB (typ.)
: 19.2 MHz
External input and internal oscillator circuit are provided.
• Power supply voltage : 2.7 V to 5.5 V
• Package options:
28-pin plastic SSOP (SSOP28-P-485-0.65-K) (Product name : MSM7602-001GS-K)
56-pin plastic QFP
(QFP56-P-910-0.65-2K) (Product name : MSM7602-011GS-2K)
1
¡ Semiconductor
MSM7602
BLOCK DIAGRAM
MSM7602-001 (Single chip only)
Non–linear/
Linear
Linear/
Non–linear
RIN
S/P
ATT
Gain
P/S
ROUT
Howling
Detector
Double Talk
Detector
Power
Calculator
Adaptive
FIR Filter
(AFF)
–
+
+
Linear/
Non–linear
Center
Clip
Non–linear/
Linear
SOUT
WDT
P/S
ATT
S/P
SIN
RST
VDD
VSS
PWDWN
*
Clock Generator
Mode Selector
I/O Controller
MCKO
X1/CLKIN
X2 SCKO SYNCO
NLP HCL ADP ATT GC HD
INT IRLD SCK SYNC
MSM7602-011 (Cascade connection or single chip)
Non–linear/
Linear
Linear/
Non–linear
RIN
S/P
ATT
Gain
P/S
ROUT
PD15
PD 0
OF1 *
OF2 *
SF1 *
SF2 *
*
*
Howling
Double Talk
Detector
Power
Parallel
I/O Port
Adaptive
Detector
Calculator
FIR Filter
(AFF)
Parallel
I/O
Controller
–
+
+
Linear/
Non–linear
Center
Clip
Non–linear/
Linear
SOUT
WDT
P/S
ATT
S/P
SIN
RST *
VDD
VSS
*
*
*
Clock Generator
Mode Selector
I/O Controller
* PWDWN
MCKO
X1/CLKIN
*
X2 SCKO SYNCO
NLP HCL ADP ATT GC MS HD
INT IRLD SCK SYNC
*
*
*
* If the MSM7602-011 is used in the slave mode, only the diagonally hatched blocks and
the pins marked with * are used.
2
¡ Semiconductor
MSM7602
PIN CONFIGURATION (TOP VIEW)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
3
4
5
6
7
8
9
10
11
12
13
14
28-Pin Plastic SSOP
Pin
1
Symbol
NLP
Pin
8
Symbol
SIN
Pin
15
16
17
18
19
20
21
Symbol
VSS
Pin
22
23
24
25
26
27
28
Symbol
SYNCO
SCKO
RST
2
HCL
9
RIN
HD
3
ADP
VDD
10
11
12
13
14
SCK
X1/CLKIN
X2
4
SYNC
SOUT
ROUT
VSS
WDT
5
ATT
VDD
GC
6
INT
PWDWN
VSS
VDD
7
IRLD
MCKO
3
¡ Semiconductor
MSM7602
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3
4
5
6
7
8
9
10
11
12
13
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
56-Pin Plastic QFP
Pin
1
Symbol
NLP
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
PD0
PD1
PD2
PD3
PD4
PD5
VSS
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
PD12
PD13
X1/CLKIN
X2
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Symbol
*
2
HCL
PD14
PD15
MCKO
SF2
OF1
VSS
3
ADP
MS
4
5
ATT
VDD
6
INT
PWDWN
VSS
7
IRLD
SIN
8
PD6
PD7
PD8
PD9
PD10
PD11
HD
SYNCO
SCKO
RST
*
9
RIN
VSS
10
11
12
13
14
SCK
SF1
OF2
VDD
VDD
*
SYNC
SOUT
ROUT
VSS
WDT
GC
VDD
VDD
*: No connect pin
4
¡ Semiconductor
MSM7602
PIN DESCRIPTIONS (1/6)
Pin
28-pin 56-pin
SSOP QFP
Symbol
Type
Description
Control pin for the center clipping function.
1
1
NLP
I
This pin forces the SOUT output to a minimum value when the SOUT
signal is below –54 dBm0. Effective for reducing low-level noise.
• Single Chip or Master Chip in a Cascade Connection
"H": Center clip ON
"L": Center clip OFF
• Slave Chip in a Cascade Connection
Fixed at "L"
This input signal is loaded in synchronization with the falling edge of the
INT signal or the rising edge of the RST signal.
Through mode control.
2
2
HCL
I
When this pin is in the through mode,
RIN and SIN data is output to ROUT and SOUT. At the same time, the
coefficient of the adaptive FIR filter is cleared.
• Single Chip or Master Chip in a Cascade Connection
"H": Through mode
"L": Normal mode (echo canceler operates)
• Slave Chip in a Cascade Connection
Same as master
This input signal is loaded in synchronization with the falling edge of the
INT signal or the rising edge of the RST signal.
AFF coefficient control.
3
3
ADP
I
This pin stops updating of the adaptive FIR filter (AFF) coefficient and sets
the coefficient to a fixed value, when this pin is configured to be the
coefficient fix mode.
This pin is used when holding the AFF coefficient which has been once
converged.
• Single Chip or Master Chip in a Cascade Connection
"H": Coefficient fix mode
"L": Normal mode (coefficient update)
• Slave Chip in a Cascade Connection
Fixed at "L"
This input signal is loaded in synchronization with the falling edge of the
INT signal or the rising edge of the RST signal.
—
4
MS
I
Select signal.
This pin selects between the master chip and slave chip when
used in a cascade connection.
"L": Single chip or master chip
"H": Slave chip
5
¡ Semiconductor
MSM7602
(2/6)
Pin
28-pin 56-pin
SSOP QFP
Symbol
Type
Description
Control for the ATT function.
5
5
ATT
I
This pin prevents howling by attenuators (ATT) for the RIN input and SOUT
output.
If there is input only to RIN, the ATT for the SOUT output is activated.
If there is no input to SIN, or if there is input to both SIN and RIN, the ATT
for the RIN input is activated.
Either the ATT for the RIN output or the ATT for the SOUT is always
activated in all cases, and the attenuation of ATT is 6 dB.
• Single Chip or Master Chip in a Cascade Connection
"H": ATT OFF
"L": ATT ON
"L" is recommended if performing echo cancellation.
• Slave Chip in a Cascade Connection
Fixed at "L"
This input signal is loaded in synchronization with the falling edge of the
INT signal or the rising edge of the RST signal.
6
6
INT
I
Interrupt signal which starts 1 cycle (8 kHz) of the signal processing.
Signal processing starts when "H"-to-"L" transition is detected.
• Single Chip or Master Chip in a Cascade Connection
Connect the IRLD pin.
• Slave Chip in a Cascade Connection
Connect the IRLD pin of the master chip.
INT input is invalid for 100 ms after reset due to initialization.
Refer to the control pin connection example.
7
7
IRLD
O
Load detection signal output when the SIN and RIN serial input data is
loaded in the internal registers.
• Single Chip
Connect to the INT pin.
• Master Chip in a Cascade Connection
Connect to the INT pin of the master chip and all the slave chips.
• Slave Chip in a Cascade Connection Leave open.
Refer to the control pin connection example.
Transmit serial data.
8
9
8
9
SIN
RIN
SCK
I
I
I
Input the PCM signal synchronized to SYNC and SCK. Data is read in at
the falling edge of SCK.
Receive serial data.
Input the PCM signal synchronized to SYNC and SCK. Data is read at the
falling edge of SCK.
10
10
Clock input for transmit/receive serial data.
This pin uses the external SCK or the SCKO.
Input the PCM CODEC transmit/receive clock (64 to 2048 kHz).
6
¡ Semiconductor
MSM7602
(3/6)
Pin
28-pin 56-pin
SSOP QFP
Symbol
Type
Description
Sync signal for transmit/receive serial data.
This pin uses the external SYNC or SYNCO.
Input the PCM CODEC transmit/receive sync signal (8 kHz).
11
12
13
—
11
12
13
15
SYNC
I
SOUT
ROUT
PD0
O
O
Transmit serial data.
Outputs the PCM signal synchronized to SYNC and SCK.
This pin is in a high impedance state during no data output.
Receive serial data.
Outputs the PCM signal synchronized to SYNC and SCK.
This pin is in a high impedance state during no data output.
I/O
This is the bidirectional bus pin for parallel data transfer between the
master chip and slave chip when used in a cascade connection.
The PD15 pin corresponds to MSB.
This pin is in a high impedance state during no data
output. Data is loaded in at the falling edge of SFx.
—
—
20
22
PD5
PD6
—
—
—
—
—
27
29
30
44
45
PD11
PD12
PD13
PD14
PD15
16
28
HD
I
Controls the howling detect function. This pin detets and cancels a howling
generated during hand-free talking for acoustic system.
This function is used to cancel acoustic echoes.
• Single Chip or Master Chip in a Cascade Connection
"L": Howling detector ON
"H": Howling detector OFF
• Slave Chip in a Cascade Connection
Fixed at "L"
17
18
31
32
X1/CLKIN
X2
I
External input for the basic clock (17.5 to 20 MHz) or for the crystal
oscillator.
When the internal sync signal (SYNCO, SCKO) is used, input the basic
clock of 19.2 MHz.
O
Crystal oscillator output.
Used to configure the oscilation circuit.
Refer to the internal clock generator circuit example.
When inputting the basic clock externally, insert a 5 pF capacitor with
excellent high frequency characteristics between X2 and GND.
7
¡ Semiconductor
MSM7602
(4/6)
Pin
28-pin 56-pin
SSOP QFP
Symbol
Type
Description
20
34
PWDWN
I
Power-down mode control when powered down.
"L": Power-down mode
"H": Normal operation mode
During power-down mode, all input pins are disabled and output pins are
in the following states :
High impedance : SOUT, ROUT, PD0 to 15
"L": SYNCO, SCKO, MCKO
"H": OF1, OF2, X2
Holds the last state : WDT, IRLD
Reset after the power-down mode is released.
8 kHz sync signal for the PCM CODEC.
Connect to the SYNC pin andthePCMCODEC transmit/receivesync pin.
Leave it open if using an external SYNC.
22
23
24
36
37
38
SYNCO
SCKO
RST
O
O
I
Transmit clock signal (256 kHz) for the PCM CODEC.
Connect to the SCK pin and the PCM CODEC transmit/receive clock pin.
Leave it open if using an external SCK.
Reset signal.
"L": Reset mode
"H": Normal operation mode
Due to initialization, input signals are disabled for 100 ms after reset
(after RST is returned from L to H).
Input the basic clock during the reset.
Output pins during the reset are in the following states :
High impedance: SOUT, ROUT, PD0 to 15
"L": WDT
"H": OF1, OF2
Not affected: X2, SYNCO, SCKO, IRLD, MCKO
After the power is turned on, initialize the LSI's internal registers by your
execution of HÆL sequence 1ms later than the master clock starts
normal oscilation.
This LSI starts a normal operation by releasing this pin to H after the
HÆL sequence above.
Here, this pin must stay L for 1ms or longer.
Test program end signal.
25
39
WDT
O
This signal is output when the one cycle (8kHz) of processing is completed.
Leave it open.
8
¡ Semiconductor
MSM7602
(5/6)
Pin
28-pin 56-pin
SSOP QFP
Symbol
Type
Description
26
40
GC
I
Input signal by which the gain controller for the RIN input is
controlled and the RIN input level is controlled and howling is
prevented.
The gain controller adjusts the RIN input level when it is –20 dBm0 or
above. RIN input levels from –20 to –11.5 dBm0 will be suppressed to
–20 dBm0 in the attenuation range from 0 to 8.5 dB.
RIN input levels above –11.5 dBm0 will always be attenuated by 8.5 dB.
• Single Chip or Master Chip in a Cascade Connection
"H": Gain control ON
"L": Gain control OFF
"H" is recommended for echo cancellation.
• Slave Chip in a Cascade Connection
Fixed at "L"
This pin is loaded in synchronization with the falling edge of the INT signal
or the rising edge of RST.
28
—
46
47
MCKO
O
I
Basic clock (19.2 MHz).
Parallel data transfer flag.
SF2
• Single Chip
Fixed at "H"
• Master Chip in a Cascade Connection
Fixed at "H"
• Slave Chip in a Cascade Connection
Connect OF2 of the master chip to the 1st stage slave chip.
Connect OF1 of the previous stage slave chip to the 2nd and later
stage slave chips.
Refer to the control pin connection example.
—
48
OF1
O
Parallel data transfer flag.
• Single Chip
Leave open.
• Master Chip in a Cascade Connection
Connect to the SF1 of all slaves.
• Slave chip in a Cascade Connection
Connect to the SF2 of the next stage slave chip.
Connect the last stage slave chip to the SF1 of the master chip.
Refer to the control pin connection example.
9
¡ Semiconductor
MSM7602
(6/6)
Pin
28-pin 56-pin
SSOP QFP
Symbol
Type
Description
Parallel data transfer flag.
• Single Chip
—
52
SF1
I
Connect OF2.
• Master Chip in a Cascade Connection
Connect OF1 of the last stage slave chip.
• Slave Chip in a Cascade Connection
Connect OF1 of master chip for all slave chips.
Refer to the control pin connection example.
Parallel data output flag.
—
53
OF2
O
• Single Chip
Connect to SF1.
• Master Chip in a Cascade Connection
Connect to SF2 of the 1st stage slave chip.
• Slave Chip in a Cascade Connection
Leave open.
Refer to the control pin connection example.
10
¡ Semiconductor
MSM7602
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Input Voltage
Symbol
VDD
Condition
Ta = 25˚C
—
Rating
–0.3 to +7
–0.3 to VDD + 0.3
1
Unit
V
VIN
V
Power Dissipation
Storage Temperature
PD
W
TSTG
–55 to +150
˚C
RECOMMENDED OPERATING CONDITIONS
(VDD = 2.7 V to 3.6 V)
Parameter
Power Supply Voltage
Power Supply Voltage
Symbol
VDD
Condition
Min.
2.7
—
Typ.
3.3
0
Max.
3.6
Unit
V
—
VSS
—
—
V
Pins other than X1
2.0
2.2
0
—
VDD
VDD
0.5
V
High Level Input Voltage
VIH
X1 pin
—
—
V
Low Level Input Voltage
Operating Temperature
VIL
Ta
—
V
—
–40
+25
+85
˚C
(VDD = 4.5 V to 5.5 V)
Parameter
Power Supply Voltage
Power Supply Voltage
Symbol
VDD
Condition
Min.
4.5
—
Typ.
5
Max.
5.5
Unit
V
—
VSS
—
0
—
V
Pins other than X1, SCK
2.4
3.5
0
—
—
—
+25
VDD
VDD
0.8
V
High Level Input Voltage
VIH
X1, SCK pins
V
Low Level Input Voltage
Operating Temperature
VIL
Ta
—
—
V
–40
+85
˚C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 V to 3.6 V, Ta = –40˚C to +85˚C)
Parameter
High Level Output Voltage
Low Level Output Voltage
Symbol
VOH
Condition
IOH = 40 mA
OL = 1.6 mA
IH = VDD
MS with pull-down
IL = VSS
Min.
2.2
0
Typ.
—
Max. Unit
VDD
0.4
1
V
I
VOL
—
V
V
—
6
0.1
60
mA
mA
mA
mA
mA
High Level Input Current
IIH
120
—
–6
1
V
–1
–60
—
–0.1
–33
0.1
Low Level Input Current
IIL
SF1, SF2 with pull-up
VOH = VDD
IOZH
High Level Output Leakage Current
PD15 to PD0
–60
–1
–33
–6
—
mA
mA
with pull-up
Input other than
the above
IOZL VOL = VSS
Low Level Output Leakage Current
–0.1
IDDO
—
—
—
—
—
20
10
—
—
30
50
15
20
mA
mA
pF
Power Supply Current (Operating)
Power Supply Current (Stand-by)
Input Capacitance
IDDS PWDWN = "L"
CI
—
CLOAD
—
pF
Output Load Capacitance
11
¡ Semiconductor
MSM7602
(VDD = 4.5 V to 5.5 V, Ta = –40˚C to +85˚C)
Typ.
—
Parameter
High Level Output Voltage
Low Level Output Voltage
Symbol
Condition
Min.
4.2
0
Max. Unit
VOH IOH = 40 mA
VDD
0.4
10
V
—
VOL IOL = 1.6 mA
V
0.1
VIH = VDD
MS with pull-down
IL = VSS
—
mA
mA
mA
mA
mA
IIH
High Level Input Current
Low Level Input Current
100
–0.1
–50
0.1
10
200
—
V
–10
–100
—
IIL
SF1, SF2 with pull-up
–10
10
High Level Output Leakage Current IOZH
VOH = VDD
PD15 to PD0
–100
–10
–50
mA
mA
–10
—
with pull-up
Input other than
the above
Low Level Output Leakage Current
IOZL VOL = VSS
–0.1
IDDO
IDDS
CI
—
—
—
—
—
30
10
—
—
45
50
15
20
mA
mA
pF
Power Supply Current (Operating)
Input Capacitance
PWDWN = "L"
—
—
Input Capacitance
CLOAD
pF
Output Load Capacitance
Echo Canceler Characteristics (Refer to Characteristics Diagram)
Parameter
Symbol
Condition
RIN = –10 dBm0
Min.
Typ.
Max.
Unit
(5 kHz band white noise)
E. R. L. (echo return loss)
= 6 dB
Echo Attenuation
LRES
—
30
—
dB
TD = 20 ms
ATT, GC, NLP: OFF
Cancelable Echo Delay Time for a
Single Chip or a Master Chip in a
Cascade
RIN = –10 dBm0
TD
—
—
—
—
23
31
ms
ms
(5 kHz band white noise)
E. R. L. = 6 dB
Cancelable Echo Delay Time for a
Slave Chip in a Cascade
ATT, GC, NLP: OFF
TDS
12
1Semiconductor
MSM7602
AC Characteristics
Parameter
(Ta = –40˚C to +85˚C)
VDD = 2.7 V to 3.6 V
VDD = 4.5 V to 5.5 V
Symbol
Unit
Min.
Typ.
19.2
—
Max.
Min.
Typ.
19.2
—
Max.
Clock Frequency
—
17.5
—
—
20
—
17.5
—
—
20
fC
MHz
When Internal Sync Signal is not used
Clock Cycle Time
52.08
—
—
52.08
—
—
tMCK
tDMC
tMCH
ns
ns
ns
When Internal Sync Signal is not used
Clock Duty Ratio
50
57.14
60
50
57.14
60
40
—
40
—
Clock "H" Level Pulse Width
fc = 19.2 MHz
20.8
20.8
—
—
31.3
31.3
20.8
20.8
—
—
31.3
31.3
Clock "L" Level Pulse Width
fc = 19.2 MHz
tMCL
ns
Clock Rise Time
tr
—
—
—
—
—
—
—
—
—
64
0.488
40
123
45
45
tSCK
45
45
—
—
—
—
—
1
—
—
5
5
—
—
—
—
—
—
—
—
—
64
0.488
40
123
45
45
tSCK
45
45
—
—
—
—
—
1
—
—
5
5
ns
ns
ns
kHz
ms
%
Clock Fall Time
tf
Sync Clock Output Time
Internal Sync Clock Frequency
Internal Sync Clock Output Cycle Time
Internal Sync Clock Duty Ratio
Internal Sync Signal Output Delay Time
Internal Sync Signal Period
tDCM
fCO
—
30
—
—
—
5
—
30
—
—
—
5
256
3.9
50
256
3.9
50
tCO
tDCO
tDCC
tCYO
—
—
ns
ms
ms
kHz
ms
%
125
tCO
—
—
—
2048
15.6
60
—
—
125
tCO
—
—
—
2048
15.6
60
—
—
Internal Sync Signal Output Width tWSO
Transmit/receive Operation Clock Frequency
Transmit/receive Sync Clock Cycle Time
Transmit/receive Sync Clock Duty Ratio
Transmit/receive Sync Signal Period
fSCK
tSCK
tDSC
tCYC
tXS
—
—
50
50
125
—
125
—
ms
ns
ns
ms
ns
ns
ms
ns
ms
ns
ns
ms
ns
ns
ms
Sync Timing
tSX
—
—
tCYC-tSCK
—
Sync Signal Width
tWSY
tDS
—
—
tCYC-tSCK
—
Receive Signal Setup Time
Receive Signal Hold Time
Receive Data Input Time
IRLD Signal Output Delay Time
IRLD Signal Output Width
—
—
tDH
—
—
—
—
tID
7tSCK
—
—
7tSCK
—
—
tDIC
tWIR
tSD
138
—
138
—
tSCK
—
tSCK
—
90
90
Serial Output Delay Time
tXD
—
90
—
90
Reset Signal Input Width
Reset Start Time
tWR
tDRS
tDRE
tDIT
—
—
—
—
5
—
—
5
—
—
Reset End Time
—
100
—
52
—
100
—
52
Processing Operation Start Time
—
—
—
—
13
¡ Semiconductor
MSM7602
AC Characteristics (Continued)
(Ta = –40˚C to +85˚C)
V
DD = 2.7 V to 3.6 V
VDD = 4.5 V to 5.5 V
Parameter
Symbol
Unit
Min.
—
Typ.
—
Max.
111
15
Min.
—
Typ.
—
Max.
111
15
Power Down Start Time
Power Down End Time
tDPS
tDPE
tDTS
tDTH
tDSR
tDHR
tWPD
tDF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
Control Pin Setup Time (INT)
Control Pin Hold Time (INT)
Control Pin Setup Time (RST)
Control Pin Hold Time (RST)
Parallel Data Output Signal Width
Flag Signal Output Time
Flag Signal Output Width
Flag Signal Input Width
20
—
—
20
—
—
120
20
—
—
120
20
—
—
—
—
—
—
10
—
—
10
—
—
—
2tMCK
tMCK
tMCK/2
tWFO
20
—
—
2tMCK
tMCK
tMCK/2
tWFO
20
—
—
—
—
—
tWFO
tWFI
tFS
—
—
—
—
—
—
—
—
Data Read Setup Time
—
—
—
—
Data Read Hold Time
fFH
—
10
—
—
10
—
14
¡ Semiconductor
MSM7602
TIMING DIAGRAM
Clock Timing
tr
tf
fC, tMCK, tDMC
tMCH
tMCL
X1/CLKIN
tDCM
tDCM
SCKO
fCO, tCO
SCKO
tDCO
tDCC
tDCC
tCYO
SYNCO
tWSO
Serial Input Timing
fSCK, tSCK
tDSC
SCK
tSX
tXS
tCYC
SYNC
tWSY
tDH
tDS
SIN
RIN
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
tID
tDIC
tDIC
IRLD
tWIR
15
¡ Semiconductor
MSM7602
Serial Output Timing
fSCK, tSCK
tDSC
SCK
tSX
tXS
tCYC
SYNC
tWSY
tXD
tSD
tXD
tXD
SOUT
ROUT
High-Z
High-Z
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
Operation Timing After Reset
tWR
*Reset timing can be asynchronous
tDIT
RST
tDRS
tDRE
Reset
Internal operaion
Initialization
Processing Start
Note: INT is invalid in the diagonally shaded interval.
Power Down Timing
PWDWN
tDPS
tDPE
Internal Operation
Power Down
Processing Start
16
¡ Semiconductor
MSM7602
Control Pin Load-in Timing
*tCYC
INT(IRLD)
tDTH
*For IRLD output timing, refer to Serial Input Timing
tDTS
NLP, HCL, HD,
ATT, ADP, GC
tWR
RST
tDHR
tDSR
NLP, HCL, HD,
ATT, ADP, GC
Parallel Output Timing
tWPD
PD15
High-Z
High-Z
Output Data
PD 0
tDF
tWFO
OF1
OF2
Parallel Input Timing
tWFI
SF1
SF2
tFS
tFH
PD15
PD 0
Input Data
17
¡ Semiconductor
MSM7602
HOW TO USE THE MSM7602
The MSM7602 cancels (based on the RIN signal) the echo which returns to SIN.
Connect the base signal to the R side and the echo generated signal to the S side.
Connection Methods According to Echos
Example 1:
Canceling acoustic echo (to handle acoustic echo from line input)
MSM7602
ROUT
SIN
RIN
Line input
AFF
H
Acoustic echo
CODEC
CODEC
–
SOUT
+
+
Example 2:
Canceling line echo (to handle line echo from microphone input)
MSM7602
Microphone input
RIN
ROUT
SIN
AFF
H
CODEC
CODEC
–
SOUT
+
+
Line echo
Example 3:
Canceling line echo in a cascade connection
(to handle line echo from microphone input)
MSM7602
Master
Microphone input
RIN
ROUT
AFF
H
H
CODEC
CODEC
–
+
SOUT
SIN
+
Line echo
PD0 - 15
Slave
AFF
18
¡ Semiconductor
MSM7602
Example 4: Canceling of both acoustic echo and line echo
(to handle both acoustic echo from line input and line echo from microphone input)
MSM7602
AFF
MSM7602
+
Line input
H
ROUT
SIN
RIN
SOUT
RIN
SIN
+
–
Acoustic echo
CODEC
CODEC
AFF
–
+
SOUT
ROUT
+
Line echo
Microphone input
For acoustic echo
For line echo
Control Pin Connection Example
Single chip connection
MS * * PD15
NLP
NLP
HCL
ADP
ATT
GC
HCL
ADP
ATT
GC
* PD 0
HD
HD
PWDWN
RST
PWDWN
RST
INT
SF1 *
SF2 *
IRLD
* OF1
* OF2
+5 V
Asterisk (*) indicates a pin only for the MSM7602-011
2-stage cascade connection
Master + (slave ¥ 1)
+5 V
Master chip
Slave chip
MS PD15
NLP
MS PD15
NLP
NLP
HCL
ADP
HCL PD 0
ADP
HCL PD 0
ADP
ATT
ATT
ATT
GC
GC
GC
HD
HD
HD
PWDWN
RST
PWDWN
RST
INT IRLD
PWDWN
RST
INT IRLD
SF1
SF2
OF1
OF2
SF1
SF2
OF1
OF2
+5 V
19
¡ Semiconductor
MSM7602
4-stage cascade connection
Master + (slave ¥ 3)
+5 V
+5 V
+5 V
Master chip
MS PD15
NLP
Slave chip 1
MS PD15
NLP
Slave chip 2
MS PD15
NLP
Slave chip 3
MS PD15
NLP
NLP
HCL
ADP
HCL PD 0
ADP
HCL PD 0
ADP
HCL PD 0
ADP
HCL PD 0
ADP
ATT
ATT
ATT
ATT
ATT
GC
GC
GC
GC
GC
HD
HD
HD
HD
HD
PWDWN
RST
PWDWN
RST
INT IRLD
PWDWN
RST
INT IRLD
PWDWN
RST
INT IRLD
PWDWN
RST
INT IRLD
SF1
SF2
OF1
OF2
SF1
SF2
OF1
OF2
SF1
SF2
OF1
OF2
SF1
SF2
OF1
OF2
+5 V
Internal Clock Generator Circuit Example
MSM7602
X1/CLKIN
X2
XTAL : 19.2 MHz
: 1 MW
C1 : 27 pF
C2 : 27 pF
R
R
XTAL
C1
GND
C2
GND
External Clock Input Circuit Example
MSM7602
X1/CLKIN
X2
5pF
CLK
GND
20
¡ Semiconductor
MSM7602
ECHO CANCELER CHARACTERISTICS DIAGRAM
ERL vs. echo attenuation
RIN input level vs. echo attenuation
40
30
20
10
0
40
30
20
10
0
40 30 20 10
ERL [dB]
0
–10
–50 –40 –30 –20 –10
0
RIN input level [dBm]
0 dBm = 2.2 dBm0
Measurement Conditions
RIN input = –10 dBm 5 kHz band white noise
(0 dBm = 2.2 dBm0)
Echo delay time TD = 20 ms
ATT, GC, NLP = OFF
Measurement Conditions
RIN input: 5 kHz band white noise
Echo delay time TD = 20 ms
ERL = 6 dB
ATT, GC, NLP = OFF
Power supply voltage 5 V
Power supply voltage 5 V
Echo delay time vs. echo attenuation
Measurement Conditions
RIN input = –10 dBm
5 kHz band white noise
(0 dBm = 2.2 dBm0)
30
20
10
0
ERL = 6 dB
ATT, GC, NLP = OFF
The second through seventh chips
are connected in a cascade.
Power supply voltage 5 V
1
2
3
4
5
6
7chip
0
50
100
150
200
Echo delay time [ms]
Note:
The characteristics above are for the MSM7543 (V
5 V, m-law interface). The
DD
MSM7566 (V 3 V, m-law interface) provides the same characleristics without input
DD
and output levels. Refer to are PCM CODEC data sheet.
MSM7543 (for both transmit and receive)
0 dBm0 = 0.6007 Vrms = –2.2 dBm (600 W)
MSM7566 (for transmit side)
0 dBm0 = 0.35 Vrms = –6.9 dBm (600 W)
(for receive side)
0 dBm0 = 0.5 Vrms = –3.8 dBm (600 W)
21
¡ Semiconductor
MSM7602
Measurement System Block Diagram
White noise generator
MSM7543
TD
MSM7543
PCM
m-law
L. P. F. RIN
5 kHz
A
PCM
m-law
RIN
ROUT
SIN
A
Delay
Echo delay time
ATT
MSM7602
CODEC
CODEC
A
PCM
SOUT
PCM
A
Level meter
SOUT
ERL
Power supply voltage 5 V
(echo return loss)
22
¡ Semiconductor
MSM7602
APPLICATION CIRCUIT
Bidirectional Connection Example
Use the MSM7704-01GS-VK for PCM CODEC when VDD 3V.
The MSM7533 and MSM7704 are pin compatible.
2ch CODEC
MSM7533VGS-K
Microphone input
Speaker output
C1
R1
R5
C5
21
22
4
24
23
2
AIN1
GSX1
AOUT1
AIN2
GSX2
AOUT2
Line input
R2
R6
Line output
R3
R7
DV
DV
13
12
15
10
16
19
5
14
11
DOUT1 DOUT2
DIN1
XSYNC
RSYNC
BCLK
A / m
DIN2
8
1
VDD
SGC
AV
+
C10 C11
18 C9
9
PDN
CHP
AG
DG
(AG)
6
DV
DV
DV
For cancellation
of acoustic echo
MSM7602-001GS-K
For cancellation
of line echo
MSM7602-001GS-K
DV
R4
DV
R8
R10 R11
8
12
9
12
9
8
SIN
ROUT
SOUT
RIN
SOUT
RIN
SIN
ROUT
13
13
DV
DV
11
10
1
2
3
5
26
16
25
17
R9
18
14
15
21
1
2
3
11
SYNC
NLP
NLP
HCL
ADP
ATT
GC
SYNC
10
22
23
6
7
20
SCK
SYNCO
SCKO
HCL
ADP
ATT
SCK
SYNCO
22
23
6
5
SCKO
26
16
25
INT
IRLD
PWDWN
RST
GC
HD
WDT
X1
INT
7
HD
WDT
IRLD
PWDWN
RST
20
PWDWN
RST
C12
C13
24
28
24
28
17
X1
C14
MCKO
18
14
15
21
X2
VSS
VSS
VSS
DV
X2
DV
4
19
27
4
19
27
X1
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
+
C2
C3
C6
C7
+
R1 = 20 kW
C1 = 1 mF
R5 = 20 kW
R6 = 20 kW
R7 = 2.2 kW
R8 = 10 kW
R11 = 10 kW
C5 = 1 mF
C9 = 0.1 mF
C10 = 10 mF
C11 = 0.1 mF
R9 = 1 MW
C12 = 27 pF
C13 = 27 pF
X1 = 19.2 MHz
C14 = 5 pF
R2 = 20 kW
R3 = 2.2 kW
R4 = 10 kW
R10 = 10 kW
C2 = 10 mF
C3 = 0.1 mF
C4 = 0.1 mF
C6 = 10 mF
C7 = 0.1 mF
C8 = 0.1 mF
23
R9
R10
R5
R4
Slave
MSM7543GS-VK
Master
MSM7543GS-VK
C1
R1
AIN+
C5
R6
23
6
PCMOUT 13
PCMIN 12
8
13
10
11
12
9
12
9
8
13
12
15
11
14
23
6
AIN +
VFRO
GSX
PCMOUT
SIN
SIN
SOUT
RIN
SOUT
RIN
SIN
ROUT
SCK
RIN
SOUT
VFRO
13
10
11
PCMIN
ROUT
SCK
ROUT
GSX
21
BCLOCK 15
RSYNC 11
XSYNC 14
45
44
30
29
27
26
25
24
23
22
20
19
18
17
16
15
53
47
48
52
6
45
44
30
29
27
26
25
24
23
22
20
19
18
17
16
15
53
47
48
52
6
21
BCLOCK
PD15
PD14
PD13
PD12
PD11
PD10
PD 9
PD 8
PD 7
PD 6
PD 5
PD 4
PD 3
PD 2
PD 1
PD 0
OF2
PD15
PD14
PD13
PD12
PD11
PD10
PD 9
PD 8
PD 7
PD 6
PD 5
PD 4
PD 3
PD 2
PD 1
PD 0
OF2
RSYNC
R2
R3
SYNC
SYNC
R7
R8
AIN
22
22
AIN–
SG
XSYNC
38
34
38
34
RST
PWDWN
RST
PWDWN
SG
1
3
5
PDM 10
TMC 19
10
19
1
PDM
AOUT–
PWI
3
5
TMC
AOUT–
1
2
1
NLP
HCL
ADP
MS
NLP
HCL
ADP
MS
PWI
24
2
SGC
24
SGC
C3
3
3
R12
C2
8
C7
V
DD
R13
4
4
8
+
V
DD
C9
16
+
C6
C10
AG
5
5
16
ATT
GC
ATT
DG
9
AG
9
40
28
37
36
31
R11
32
33
41
42
55
54
51
14
21
40
28
37
36
31
DG
GC
HD
HD
SCKO
SYNCO
X1
SCKO
SYNCO
X1
C11
C12
X1
R1 > 50 kW
R2 > 20 kW
R3 > 20 kW
R4 = 2.2 kW
R5 = 10 kW
R6 > 50 kW
C1 = 0.1 mF
C2 = 10 mF
C3 = 0.1 mF
C4 = 10 mF
C5 = 0.1 mF
R7 > 20 kW
R8 > 20 kW
R9 = 2.2 kW
R10 = 10 kW
R12 = 0-22 W
R13 = 0-22 W
C6 = 10 mF
C7 = 0.1 mF
C8 = 10 mF
C9 = 0.1 mF
C10 = 0.1 mF
C13
C8
32
33
41
42
55
54
51
14
21
X2
SF2
OF1
SF1
INT
SF2
OF1
SF1
INT
X2
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
+
+
C4
7
7
IRLD
IRLD
46
39
35
49
46
39
35
49
MCKO
WDT
MCKO
WDT
V
V
V
SS
SS
SS
V
V
V
V
SS
SS
SS
SS
56-Pin QFP
56-Pin QFP
R11 = 1 MW C13 = 5 pF
C11 = 27 pF
C12 = 27 pF
RST
PWDWN
X1 = 19.2 MHz
¡ Semiconductor
MSM7602
NOTES ON USE
1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be
amplified, the echo can not be eliminated.
Refer to the characteristics diagram for ERL vs. echo attenuation quantity.
2. Set the level of the analog input so that the PCM CODEC does not overflow.
3. The recommended input level is –10 to –20 dBm0. Refer to the characteristics
diagram for the RIN input level vs. echo attenuation quantity.
4. Applying the tone signal to this echo canceler for long duration may decrease echo
attenuation.
When used with the HD pin "L" (howling detector ON), this echo canceler may
operate faultily if, while a signal is input to the RIN pin, a tone signal with a higher
level than the signal being input to RIN is input to the SIN pin.
A signal should therefore be input either to the RIN pin or to the SIN pin. If,
however, thetonesignalisinputtotheSINpinwhileasignalisinputtotheRINpin,
the ADP, HD, or HCL pin must be set to "H".
5. Forchangesintheechopath(retransmit,circuitswitchingduringtransmission,and
so on), convergence may be difficult.
Perform a reset, to make it converge.
Ifthestateoftheechopathchangesafterareset, convergencemayagainbedifficult.
In cases such as a change in the echo path, perform a reset each time.
6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock
simultaneously with power ON.
IfpoweringdownimmediatelyafterpowerON, besurefastinput10ormoreclocks
of the basic clock.
7. After powering ON, be sure to reset.
8. After the power down mode is released (when the PWDWN pin is changed to "H"
from "L"), be sure to reset the device.
9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less
than 30 dB.
25
¡ Semiconductor
MSM7602
EXPLANATION OF TERMS
Attenuating Function :
Echo Attenuation :
This function prevents howling and controls the noise level with
the attenuator for the RIN input and SOUT output. Refer to the
explanation of pins (ATT pin).
If there is talking (input only to RIN) in the path of a rising echo
arises, the echo attenuation refers to the difference in the echo
return loss (canceled amount) when the echo canceler is not used
and when it is used.
Echo attenuation = (SOUT level during through mode operation)
– (SOUT level during echo canceler operation) [dB]
This is the time from when the signal is output from ROUT until it
returns to SIN as an echo.
When using a hands free phone, and so on, the signal output from
the speaker echoes and is input again to the microphone. The
return signal is referred to as acoustic echo.
Echo Delay Time :
Acoustic Echo :
Telephone Line Echo :
Gain Control Function :
This is a signal which is delayed midway in a telephone line and
returns as an echo, due to reasons such as a hybrid impedance
mismatch.
This function prevents howling and controls the sound level with
a gain controller for the RIN input. Refer to the explanation of pins
(GC pin).
Center Clipping Function : This function forces the SOUT output to a minimum value when
thesignalisbelow–54dBm0. Refertotheexplanationofpins(NLP
pin).
Double talk refers to a state in which the SIN and RIN signals are
input simultaneously. In a double talk state, a signal outside the
echo signal which is to be canceled can be input to the SIN input,
resulting in misoperation.
Double Talk Detection :
Thedoubletalkdetectorpreventssuchmisoperationofthecanceler.
Thisistheoscillatingstatecausedbytheacousticcouplingbetween
the loud speaker and the microphone during hands free talking.
Howling not only interferes with talking, but can also cause in
misoperation of the echo canceler.
Howling Detection :
The howling detector prevents such misoperation and prevents
howling.
Echo Return Loss (ERL) :
When the signal output from ROUT returns to SIN as an echo, ERL
refers to how much loss there is in the signal level during ROUT.
ERL = (ROUT level) – (SIN level of the ROUT signal which returns
as an echo) [dB]
IfERLispositive(ROUT>SIN),thesystemisanattenuatorsystem.
If ERL is negative (ROUT < SIN), the system is an amplifier system.
Personal Handy Phone System.
PHS :
26
¡ Semiconductor
MSM7602
APPENDIX Differences Between the MSM7602 and the MSM7520/7620
Introduction
The MSM7602 is the improved version of the MSM7520 with improved usage. Thus, there are no
differences in echo canceling characteristics.
Enhancements
• A new clock frequency of 19.2 MHz.
The basic clock frequency of the MSM7520/7620 was 18 or 38 MHz, while the basic clock
frequency of MSM7602 is 19.2 MHz. (MSM7602 can be applied at a frequency of 18 MHz.
However, external SYNC and SCK are required because the periods of SYNCO and SCKO are
varied.)
• Adoption of full-fledged 8-bit data through-mode
Inthethrough-modefortheMSM7520(HCLpin:"H"),aninternallyprocessedPCMsignalwas
used.Therefore,onlythenegativeminimumvalue(7F )wasconvertedintothecorresponding
HEX
positive minimum value (FF
).
HEX
Analog to analog conversion causes no problem since both values are the minimum ones, but
data transfer in the through-mode encounters problems. Hence, in the MSM7620/7602, the
complete data trough-mode has been implemented.
• Control of input timing to control pins (NLP, HCL, ADP, ATT and GC)
In MSM7520, asynchronous changes in a control pin may result in malfunctioning. This
problem stems from the fact that information on control pins is checked several times during
the execution of a program over one cycle and the state of a control pin is changed between the
first and second half periods.
The MSM7620/7602 provides an internal circuit for using an INT signal to hold control pin
information for one cycle. Thus, external timing control is not needed.
The howling detector control pin (HD) is added.
The MSM7602 can prevent the false detection of the howling detecter cause by tone signals by
providing the howling detecter control pins.
• Introduction of 256 kHz internal clock output (SCKO) for PCM transmission
Internal sync signals (SYNCO and SCKO) in MSM7520/7620 are rated at 8 kHz and 200 kHz,
respectively. At a frequency of 8 kHz, PCM multiplexing can be applied to no more than three
channels.
In the MSM7602, SCKO is rated at 256 kHz, while SYNCO at 8 kHz. Thus, PCM multiplexing
can be applied with up to four channels.
• Addition of basic clock output
The use of a crystal oscillator for a clock in the MSM7520/7620 requires an oscillating circuit
installed in each of two or more cascade-connected IC chips.
SincetheMSM7602supportsbasicclockoutput,onlyoneICchiprequiresanoscillatingcircuit.
(The MSM7602-001TS-K does not provide the basic clock output.)
27
¡ Semiconductor
MSM7602
• Small-sized package
MSM7602
Package code
Package size (mm)
MSM7602-001GS-K
MSM7602-011GS-2K
MSM7520 : 14.0 ¥ 14.0 ¥ 3.75 mm
MSM7620 : 14.0 ¥ 14.0 ¥ 2.1 mm
:28-pin SSOP :SSOP28-P-485-0.65-K :9.5 ¥ 10.5 ¥ 1.85
:56-pin QFP :QFP56-P-910-0.65-2K :9.5 ¥ 10.5 ¥ 1.85
• Supply voltage rated at 3 volts
MSM7520/7620
MSM7602
4.5 V to 5.5 V 5 V typ.
2.7 V to 5.5 V 3.3 V or 5 V typ.
28
1Semiconductor
PACKAGE DIMENSIONS
SSOP28-P-485-0.65-K
MSM7602
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
0.39 TYP.
Oki Electric Industry Co., Ltd.
3/Dec. 5, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method, temperature
and times).
29
1Semiconductor
MSM7602
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror fihish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
0.43 TYP.
Oki Electric Industry Co., Ltd.
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method, temperature
and times).
30
1Semiconductor
MSM7602
REVISION HISTORY
Page
Document No.
Date
Description
Previous Current
Edition
Edition
FEDL7602-03
FEDL7602-04
Nov. 2001
–
–
Final edition 3
Revised Max. values of “Sync Timing” and
“Sync Signal Width” in the Table in the “AC
Characteristics” Section.
Jun. 1, 2005
13
13
31
1Semiconductor
MSM7602
NOTICE
1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is
up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party’s right which may result
from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2005 Oki Electric Industry Co., Ltd.
32
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