MSM7617-002GS-BK [OKI]
ISDN Echo Canceller, 2-Func, CMOS, PQFP64, 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64;
| 型号： | MSM7617-002GS-BK |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | ISDN Echo Canceller, 2-Func, CMOS, PQFP64, 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 电信 综合业务数字网 电信集成电路 |
| 文件： | 总28页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0057-28-81
This version: Aug. 1998
Previous version: Sep. 1997
¡ Semiconductor
MSM7617
2-Channel Echo Canceler
GENERAL DESCRIPTION
The MSM7617 cancels echoes (acoustic or line echoes) generated in voice channels. It is a low-
power CMOS LSI device with two channels.
MSM7617 echo canceling is performed by digital signal processing. It negates echoes by
estimating the echo channel and then generating a pseudo-echo signal.
When used as an acoustic echo canceler, the MSM7617 can cancel acoustic echoes between
speaker and microphone that occur during hands-free speaking with car phones, conferencing
system phones, etc. When used as a line echo canceler, the MSM7617 can cancel line echoes
returned by hybrid impedance mismatches.
By setting its mode for use as a single cross-connected channel, the MSM7617 can cancel both
acoustic and line echoes.
Also, the MSM7617 can improve voice communication by using its howling detection, double-
talk detection, attenuation, and gain control functions to prevent and suppress howling levels,
and by using its center clipping function to suppress low level noise.
Furthermore, the MSM7617 can disable echo canceling during data communication with its 2100
Hztonedetectorand2100Hzphasereversaldetector. ItalsoprovidestheabilitytoattenuateSIN
levels, to amplify SOUT levels, and to adjust input/output levels.
An economical and highly efficient echo canceler unit can be constructed by using a 2-channel
single-chip CODEC like the MSM7533 together with the MSM7617.
1/28
¡ Semiconductor
MSM7617
FEATURES
•Echocancelerhastwochannels, whichcanbeusedforacousticandlineechoes. Setasasingle
cross-connected channel, it can be used for both acoustic and line echoes.
•ITU-T G164/G165 standard tone disabler.
•PCM line level adjustment possible with SIN level attenuator (SA pin) and SOUT level
amplifier (SG pin). Can also be used for ERL amplification with the SIN level attenuator (SA
pin).
•RGCpinprovidesinput/outputadjustmentmode(±6LRmode)thatcanpreventmalfunction
due to excessive inputs without changing the RIN-ROUT input/output levels.
•Excellent acquisition characteristics and fast acquisition time. Sudden changes in the echo
channel can be handled smoothly, eliminating the need for resetting for each calling.
•Cancelable echo delay time:
•Echo attenuation:
55 ms (max.)
30 dB (typ.)
•Clock frequency:
18 to 20 MHz
19.2 MHz if using internal clock signal
•Power supply voltage:
•Package:
4.5 to 5.5 V
64-pin plastic QFP (QFP64-P-1414-0.80-BK)
•Product name:
MSM7617-001GS-BK (m-law)
MSM7617-002GS-BK (A-law) under development
2/28
¡ Semiconductor
MSM7617
BLOCK DIAGRAM
Non-linear/
Linear
Linear/
Non-linear
S/P
–6LR
ATT
GC
+6LR
P/S
RIN1
ROUT1
DF1
Howling
Detector
Double Talk
Detector
Power
Calculator
Adaptive
FIR Filter
(AFF)
2100 Hz Tone,
Phase Reverse
Detector
WDT1
CH1
–
Non-linear/
Linear
Linear/
Non-linear
Center
Clip
+
+
SOUT1
RIN2
S/P
P/S
SIN1
P/S
S/P
SG
ATT
SA
+6LR
–6LR
+6LR
Non-linear/
Linear
Linear/
Non-linear
–6LR
ATT
GC
ROUT2
DF2
Howling
Detector
Double Talk
Detector
Power
Calculator
Adaptive
FIR Filter
(AFF)
2100 Hz Tone,
Phase Reverse
Detector
WDT2
CH2
–
Non-linear/
Linear
Linear/
Non-linear
Center
Clip
+
+
SOUT2
S/P
SIN2
P/S
SG
ATT
SA
+6LR
–6LR
SYNCO
SCKO
VDD
VSS
Clock Generator
PLL
EC-A Controller
EC-B Controller
I/O Controller
VDD (PLL)
VSS (PLL)
The above diagram shows internal connections for 2-channel parallel mode. The internal
connections for 2-channel serial I/O mode and 1-channel cross-connected mode are shown
below.
2-channel parallel I/O mode
2-channel serial I/O mode
1-channel cross-connected mode
CH1
CH1
CH1
RIN
ROUT
SIN
RIN
ROUT
SIN
RIN
ROUT
SIN
RIN1
SOUT1
RIN2
ROUT1
SIN1
RIN1
ROUT1
SIN1
ROUT1
SIN1
AFF
+
AFF
+
AFF
+
SOUT
RIN
SOUT
RIN
SOUT
RIN
SOUT1
CH2
CH2
CH2
ROUT
SIN
ROUT
SIN
ROUT
SIN
ROUT2
SIN2
ROUT2
SIN2
AFF
+
AFF
+
AFF
+
SOUT
SOUT
SOUT
SOUT2
3/28
¡ Semiconductor
MSM7617
PIN CONFIGURATION (TOP VIEW)
RST2
ADP2
HCL2
SYNC2
VDD
1
2
3
4
5
6
7
8
9
48 VSS(PLL)
47 VDD(PLL)
46 CLKIN
45 VSS
44 VSS
NLP2
IOM0
IOM1
SCK
43 TST
42 PWDWN
41 ECDM1
40 ECDM0
39 SCKO
38 SYNCO
37 VDD
ECM 10
NLP1 11
VSS 12
SYNC1 13
HCL1 14
ADP1 15
RST1 16
36 VDD
35 VDD
34 VDD
33 VDD
64-Pin Plastic QFP
4/28
¡ Semiconductor
MSM7617
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
Reset signal input pin for channel 2.
1
RST2
I
"L": Reset
"H": Normal operation
Input signals are invalid for 100 ms after reset (after RST returns to "H"
from "L") for setting initial values.
Input the basic clock during reset. Output pins will be placed in the
following states during reset.
Hi-Z: ROUT2, SOUT2
No effect: SYNCO, SCKO, ROUT1, SOUT1, DF1, WDT1
Previous state: DF2, WDT2
2
3
ADP2
HCL2
I
I
AFF coefficient control pin for channel 2.
This pin stops coefficient variation of the adaptive FIR filter (AFF), fixing the
coefficients. It allows once acquired AFF coefficients to be saved.
"H": Fixed coefficient mode
"L": Normal mode (variable coefficients)
Echo canceler disable pin for channel 2.
This pin disables the echo canceler and enables data from SIN to SOUT to be output
in "through mode". The input and output levels of SIN and SOUT are changed by the
setting of the SG and SA pins; therefore, to output data from SIN to SOUT in
"through mode", set the SA and SG pins to "0 dB".
It simultaneously clears the adaptive FIR filter coefficients.
"H": Disable mode
"L": Normal mode (echo canceller enabled)
4
6
SYNC2
NLP2
I
I
Sync signal input pin for channel 2 transmit/receive PCM data while in
parallel I/O mode.
Input the transmit/receive sync signal (8 kHz) of the PCM CODEC connected
to channel 2. Input "L" if not in parallel I/O mode.
NLP control pin for channel 2.
This pin controls center clipping, forcing SOUT2 output to the minimum
positive value when it is below –54 dBm0. It is effective for reducing
uncanceled echoes and low-level noise.
"H": Center clipping on
"L": Center clipping off
7
8
IOM0
IOM1
I
Sets I/O mode of PCM data.
IOM1
IOM0
Mode Setting
0
0
1
1
0
1
0
1
2-channel parallel I/O mode
2-channel serial I/O mode
1-channel cross-connected mode
Inhibited
5/28
¡ Semiconductor
MSM7617
PIN DESCRIPTIONS (Continued)
Pin
Symbol
Type
Description
9
SCK
I
Common pin for channel 1 and channel 2. Clock input pin for PCM data
transmission.
Input the same clock as the transmit/receive clock of the PCM CODEC.
Frequencies below 128 kHz cannot be used in serial mode.
Not used. Fix input to "H".
10
11
ECM
I
I
NLP1
NLP control pin for channel 1.
This pin controls center clipping, forcing SOUT1 output to the minimum
positive value when it is below –54 dBm0. It is effective for reducing
uncancelled echoes and low-level noise.
"H": Center clipping on
"L": Center clipping off
13
14
SYNC1
HCL1
I
I
Sync signal input pin for channel 1 transmit/receive PCM data while in 2-
channel parallel I/O mode, 2-channel serial I/O mode, or 1-channel cross-
connected mode.
Input the transmit/receive sync signal (8 kHz) of the PCM CODEC.
Echo canceler disable control pin for channel 1.
This pin disables the echo canceler and enables data from SIN to SOUT to be output
in "through mode". The input and output levels of SIN and SOUT are changed by the
setting of the SG and SA pins; therefore, to output data from SIN to SOUT in "through
mode", set the SA and SG pins to "0 dB".
It simultaneously clears the adaptive FIR filter coefficients.
"H": Disable mode
"L": Normal mode (echo canceler enabled)
15
16
ADP1
I
I
AFF coefficient control pin for channel 1.
This pin stops coefficient variation of the adaptive FIR filter (AFF), fixing the
coefficients. It allows once acquired AFF coefficients to be saved.
"H": Fixed coefficient mode
"L": Normal mode (variable coefficients)
Reset signal input pin for channel 1.
RST1
"L": Reset
"H": Normal operation
Input signals are invalid for 100 ms after reset (after RST returns to "H" from
"L") for setting initial values.
Input the base clock during reset. Output pins will be placed in the following
states during reset.
Hi-Z: ROUT1, SOUT1
No effect: SYNCO, SCKO, ROUT2, SOUT2, DF2, WDT2
Previous state: DF1, WDT1
6/28
¡ Semiconductor
MSM7617
PIN DESCRIPTIONS (Continued)
Pin
Symbol
Type
Description
17
HD1
I
Howling detection control pin for channel 1.
This pin controls detection and canceling of howling generated by the
acoustics of handsfree telephones.
"L": Howling detector on
"H": Howling detector off
18
ATT1
I
ATT control pin for channel 1.
This pin controls the ATT function for preventing howling with the
attenuators (ATT) provided on RIN and SOUT. When input is only on RIN,
the SOUT attenuator is activated. When there is no input on RIN or there is
input on both SIN and RIN, the RIN input attenuator is activated. Either the
ATT for the RIN output or the ATT for the SOUT is always activated in all
cases, and the attenuation of ATT is 6 dB.
"H": Attenuator off
"L": Attenuator on
Because the attenuator is inserted opposite the speaker, it is effective for
further reducing echo.
19
SOUT1
O
PCM data output pin. Output signal changes depending on the setting of
the IOM pins (refer to the block diagram).
Data is always output on the rising edge of SCK. This pin is put in high
impedance state while there is no data or during reset.
In 2-channel parallel I/O mode, this pin becomes SOUT for channel 1 and
outputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O
mode, this pin outputs the SOUT signal as a multiplexed PCM signal of
SOUT signal for channel 1 and channel 2 synchronous with SYNC1.
In 1-channel cross-connected mode, this pin becomes high impedance.
7/28
¡ Semiconductor
MSM7617
PIN DESCRIPTIONS (Continued)
Pin
Symbol
Type
Description
20
SIN1
I
PCM data input pin. Pin use changes depending on the setting of the IOM
pins (refer to the block diagram).
In 2-channel parallel I/O mode, this pin becomes SIN for channel 1 and
inputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O
mode, this pin sequentially inputs SIN as a multiplexed PCM signal from
channel 1 and channel 2 synchronous with SYNC1. In 1-channel cross-
connected mode, this pin becomes the cross-connected SIN pin for channel
1, and inputs the PCM signal synchronous with SYNC1.
Data is captured on the falling edge of SCK.
22
ROUT1
O
PCM data output pin. Output signal changes depending on the setting of
the IOM pins (refer to the block diagram).
Data is always output on the rising edge of SCK. This pin becomes high
impedance while there is no data or during reset.
In 2-channel parallel I/O mode, this pin becomes ROUT for channel 1 and
outputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O
mode, this pin outputs the ROUT signal as a multiplexed PCM signal of ROUT
signals for channel 1 and channel 2 synchronous with SYNC1.
In 1-channel cross-connected mode, this pin becomes the cross-connected
ROUT pin for channel 1, and outputs the PCM signal synchronous with SYNC1.
23
RIN1
I
PCM data input pin. Pin use changes depending on the setting of the IOM
pins (refer to the block diagram).
In 2-channel parallel I/O mode, this pin becomes RIN for channel 1 and
inputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O
mode, this pin sequentially inputs RIN as a multiplexed PCM signal from
channel 1 and channel 2 synchronous with SYNC1. In 1-channel cross-
connected mode, this pin is not used, and should be fixed at "L".
Data is captured on the falling edge of SCK.
8/28
¡ Semiconductor
MSM7617
PIN DESCRIPTIONS (Continued)
Pin
24
Symbol
SG11
Type
Description
I
S output gain control pins for channel 1 (refer to the block diagram).
These pins amplify the output level of SOUT. The gain level can be set even
during the echo canceler disable mode.
25
SG10
SG11 SG10 Gain Level
0
0
1
1
0
1
0
1
0 dB
+6 dB
+12 dB
+18 dB
26
27
SA11
SA10
I
S input attenuator control pins for channel 1 (refer to the block diagram).
These pins attenuate the input level of SIN. Use them if ERL is large.
The attenuation level can be set even during the echo canceler disable mode.
SA11 SA10 Attenuation Level
0
0
1
1
0
1
0
1
0 dB
–6 dB
–12 dB
–18 dB
29
30
RGC11
RGC10
I
R input level control pins for channel 1 (refer to the block diagram).
Excessive input (PCM level is at maximum value) causes a malfanction.
Use these pins when there is a possibility of excessive input.
RGC11 RGC10 Level Control Mode
0
0
0
1
Off
GC: On (control level = –20 dBm0)
By the R gain controller, levels from –20 to –11.5 dBm0 will
be suppressed to –20 dBm0 and those above –11.5 dBm0 will
always be attenuated by 8.5 dB. This is effective to prevent
excessive input and howling for hands-free applications.
Inhibited
1
1
0
1
6LR: On
Applies –6 dB to excessive inputs using the level adjuster
provided on R and S I/O. Since +6 dB also is applied at the
output, the total level will not change, making this effective
against line echo.
9/28
¡ Semiconductor
MSM7617
PIN DESCRIPTIONS (Continued)
Pin
Symbol
Type
Description
Tone disabler flag output pin for channel 1.
31
DF1
O
This pin outputs a disable flag when the ECDM pins are used for tone disabler
mode.
"H": Echo canceler disabled
"L": Echo canceler enabled
32
38
WDT1
O
O
Not used. Leave this pin open.
SYNCO
Output pin for internal SYNC signal (8 kHz).
This pin is used as the transmit/receive synchronization signal for PCM signals.
Connect it to the SYNC pin and PCM CODEC’s synchronization signal pin. Leave
this pin open if using an external SYNC.
39
SCKO
O
I
Output pin for internal SCK signal (256 kHz).
This pin is used for the transfer clock of PCM signals. Connect it to the PCM
CODEC’s synchronization signal pin. Leave open if using an external SYNC.
Tone disabler control pin common to channel 1 and channel 2.
These pins detect answer tones generated by modems (2100 Hz), and then
disable the echo canceler.
40
41
ECDM0
ECDM1
Tone Disabler Mode
ECDM1 ECDM0
Off
0
0
1
1
0
1
0
1
2100 Hz tone detection: On
2100 Hz and phase reversal detection: On
Inhibited
42
PWDWN
I
Common pin for channel 1 and channel 2.
This pin controls the power-down mode to reduce current consumption
when the device is not being used.
"L": Power down
"H": Normal operation
During power-down mode all input pins are invalid, and output pins will enter
the following states.
Hi-Z: SOUT1, SOUT2, ROUT1, ROUT2
"L": SYNCO, SCKO
Previous state: DF1, WDT1, DF2, WDT2
Reset the device after power-down mode is released.
10/28
¡ Semiconductor
MSM7617
PIN DESCRIPTIONS (Continued)
Pin
43
Symbol
TST
Type
Description
O
I
Not used. Leave this pin open.
Basic clock input pin.
46
CLKIN
Input a clock 18 to 20 MHz. Use 19.2 MHz if using internal synchronization
signals (SYNCO, SCKO).
47
48
VDD
I
I
Power supply for PLL circuit that uses the basic clock.
Insert a 0.1mF capacitor with excellent high frequency characteristics
between VDD (PLL) and VSS (PLL).
(PLL)
VSS
Ground for PLL circuit that uses the basic clock.
Insert a 0.1mF capacitor with excellent high frequency characteristics
between VDD (PLL) and VSS (PLL).
(PLL)
49
50
WDT2
DF2
O
O
Not used. Leave this pin open.
Tone disabler flag output pin for channel 2.
This pin outputs a disable flag when the ECDM pins are used for tone
disabler.
"H": Echo canceler disabled
"L": Echo canceler enabled
51
52
RGC20
RGC21
I
R input level control pins for channel 2 (refer to the block diagram).
Excessive input (PCM level is at maximum value) causes a malfunction.
Use these pins when there is a possibility of excessive input.
RGC21 RGC20 Level Control Mode
0
0
0
1
Off
GC: On (control level = –20 dBm0)
By the R gain controller, levels from –20 to –11.5 dBm0
will be suppressed to –20 dBm0 and those above –11.5
dBm0 will always be attenuated by 8.5 dB. This is
effective to prevent excessive input and howling for
hands-free applications.
1
1
0
1
Inhibited
6LR: On
Apply –6 dB to excessive inputs using the level
adjuster provided on R and S I/O. Since +6 dB also
is applied at the output, the total level will not
change, making this effective against line echo.
11/28
¡ Semiconductor
MSM7617
PIN DESCRIPTIONS (Continued)
Pin
54
Symbol
SA20
Type
Description
I
S input attenuator control pins for channel 2 (refer to the block diagram).
These pins attenuate the input level of SIN. Use them if ERL is large.
The attenuation level can be set even during the echo canceler disable mode.
55
SA21
SA21
SG20 Attenuation Level
0
0
1
1
0
1
0
1
0 dB
–6 dB
–12 dB
–18 dB
56
57
SG20
SG21
I
S output gain control pins for channel 2 (refer to the block diagram).
These pins amplify the output level of SOUT. The gain level can be set even
during the echo canceler disable mode.
SG21
SG20 Gain Level
0
0
1
1
0
1
0
1
0 dB
+6 dB
+12 dB
+18 dB
58
59
RIN2
I
PCM data input pin. Pin use changes depending on the setting of the IOM
pins (refer to the block diagram).
In 2-channel parallel I/O mode, this pin becomes RIN for channel 2 and
inputs the PCM signal synchronous with SYNC2. Data is captured on the
falling edge of SCK. In other modes, this pin is not used, and should be
fixed at "L".
ROUT2
O
PCM data output pin. Output signal changes depending on the setting of
the IOM pins (refer to the block diagram).
Data is always output on the rising edge of SCK. This pin becomes high
impedance while there is no data.
In 2-channel parallel I/O mode, this pin becomes ROUT for channel 2 and
outputs the PCM signal synchronous with SYNC2. In 2-channel serial I/O
mode, this pin is not used and should be left open. In 1-channel cross-
connected mode, this pin becomes the cross-connected ROUT pin for
channel 2, and outputs the PCM signal synchronous with SYNC1.
12/28
¡ Semiconductor
MSM7617
PIN DESCRIPTIONS (Continued)
Pin
Symbol
Type
Description
61
SIN2
I
PCM data input pin. Pin use changes depending on the setting of the IOM
pins (refer to the block diagram). Data is captured on the falling edge of SCK.
In 2-channel parallel I/O mode, this pin becomes SIN for channel 2 and
inputs the PCM signal synchronous with SYNC2. In 2-channel serial I/O
mode, this pin is not used and should be fixed at "L". In 1-channel cross-
connected mode, this pin becomes the cross-connected SIN pin for channel
2, and inputs the PCM signal synchronous with SYNC1.
PCM data output pin. Output signal changes depending on the setting of
the IOM pins (refer to the block diagram).
62
SOUT2
O
Data is always output on the rising edge of SCK. This pin becomes high
impedance while there is no data.
In 2-channel parallel I/O mode, this pin becomes SOUT for channel 2 and
outputs the PCM signal synchronous with SYNC2. In other modes, this pin
is not used and should be left open.
63
ATT2
I
ATT control pin for channel 2.
This pin controls the ATT function for preventing howling with the
attenuators (ATT) provided on RIN and SOUT. When input is only on RIN,
the SOUT attenuator is activated. When there is no input on SIN or there is
input on both SIN and RIN, the RIN input attenuator is activated. Either the
ATT for the RIN output or the ATT for the SOUT is always activated in all
cases, and the attenuation of ATT is 6 dB.
"H": Attenuator off
"L": Attenuator on
Because the attenuator is activated opposite the speaker, it is effective for
further reducing echo.
64
HD2
I
Howling detection control pin for channel 2.
This pin controls detection and canceling of howling generated by the
acoustics of handsfree telephones.
"L": Howling detector on
"H": Howling detector off
13/28
¡ Semiconductor
MSM7617
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Input Voltage
Symbol
VDD
Condition
Ta = 25°C
—
Rating
–0.3 to + 7
–0.3 to VDD + 0.3
1
Unit
V
VIN
V
Power Dissipation
Storage Temperature
PD
W
TSTG
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
(VDD = 4.5 V to 5.5 V)
Typ. Max. Unit
Parameter
Power Supply Voltage
Power Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Operating Temperature
Symbol
VDD
VSS
Condition
Min.
4.5
—
—
—
—
—
—
5
0
5.5
—
V
V
VIH
2.4
0
—
—
+25
VDD
0.8
+85
V
VIL
V
Ta
–40
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 4.5 V to 5.5 V, Ta = –40°C to +85°C)
Parameter
Symbol
VOH
VOL
Condition
IOH = 40 µA
IOL = 1.6 mA
VIH = VDD
Min.
4.2
0
Typ.
—
Max. Unit
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
VDD
0.4
10
—
10
—
130
2
V
V
—
IIH
—
0.1
–0.1
0.1
–0.1
80
µA
µA
µA
µA
mA
mA
pF
pF
Low Level Input Current
IIL
VIL = VSS
–10
—
IOZH
IOZL
IDDO
IDDS
CI
High Level Output Leakage Current
Low Level Output Leakage Current
Power Supply Current (operation mode)
Power Supply Current (power-down mode)
Input Capacitance
VOH = VDD
VOL = VSS
–10
—
—
PWDWN = "L"
—
0.5
—
—
—
—
15
20
CLOAD
Output Load Capacitance
—
—
14/28
¡ Semiconductor
MSM7617
Echo Canceler Characteristics (refer to characteristics diagram)
Parameter
Symbol
Condition
RIN = –10 dBm0
Min.
Typ.
Max. Unit
(5 kHz white noise band)
E. R. L. = 6 dB
Echo Reduction
LRES
—
30
—
55
dB
(Common to Channel 1 and
Channel 2)
TD = 50 ms
ATT, GC, NLP: OFF
RIN = –10 dBm0
(5 kHz white noise band)
E. R. L. = 6 dB
Cancelable Echo Delay Time
(Common to Channel 1 and
Channel 2)
TD
—
—
ms
ATT, GC, NLP: OFF
Tone Disabler Characteristics
Parameter
Min.
Typ.
Max.
2125
—
Unit
Hz
Detection frequency
2075
–32
2100
—
Tone Detection
Detection level
Detection time
dBm0
ms
380
—
—
Detection condition
Detection frequency
Detection level
2100Hz. 180° out-of-phase detected before and after 450 25ms.
2075
–32
135
—
2100
—
2125
—
Hz
dBm0
°
Phase Reversal Detection
Release
Phase reversal
180
—
225
–32
Detection level
dBm0
15/28
¡ Semiconductor
MSM7617
AC Characteristics
(VDD = 4.5 V to 5.5 V, Ta = –40°C to +85°C)
Parameter
Clock Frequency
Symbol
Min.
—
Typ.
19.2
—
Max.
Unit
—
fC
MHz
If Used Without Internal Sync Signal
Clock Cycle Time
18
20
—
52.08
—
—
tMCK
ns
If Used Without Internal Sync Signal
Clock Duty Cycle
50
55.56
tDMC
tMCH
tMCL
tr
40
—
60
%
ns
ns
ns
ns
ns
kHz
µs
%
Clock High Level Pulse Width
Clock Low Level Pulse Width
Clock Rise Time
tMCK ¥ 0.4
tMCK ¥ 0.4
—
—
tMCK ¥ 0.6
—
tMCK ¥ 0.6
—
5
5
Clock Fall Time
tf
—
—
tDCM
fCO
Internal Sync Clock Output Time
Internal Sync Clock Frequency
Internal Sync Clock Cycle Time
Internal Sync Clock Duty Cycle
Internal Sync Signal Output Time
Internal Sync Signal Period
Internal Sync Signal Pulse Width
Transmit/Receive Sync Clock Frequency
In Serial I/O Mode
—
—
40
—
256
3.9
50
—
tCO
—
—
tDCO
tDCC
tCYO
tWSO
—
—
—
—
5
ns
µs
µs
—
125
tCO
—
—
—
—
64
2048
2048
15.62
7.81
60
fSCK
tSCK
kHz
µs
128
0.488
0.488
40
—
Transmit/Receive Sync Clock Cycle Time
In Serial I/O Mode
—
—
tDSC
tCYC
tXS
Transmit/Receive Sync Clock Duty Cycle
Transmit/Receive Sync Signal Period
50
%
µs
ns
ns
µs
ns
ns
µs
µs
—
125
—
—
45
—
Sync Timing
tSX
45
—
—
tWSY
tDS
tDH
tID
Sync Signal Width
tSCK
45
—
tCYC–tSCK
—
Receive Signal Setup Time
Receive Signal Hold Time
Receive Signal Input Time
In 2-Channel Serial Mode
—
45
—
—
—
7tSCK
15tSCK
—
tID2
—
—
16/28
¡ Semiconductor
MSM7617
AC Characteristics (Continued)
(VDD = 4.5 V to 5.5 V, Ta = –40°C to +85°C)
Parameter
Symbol
tSD
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
90
Unit
ns
ns
µs
ns
ns
µs
ns
ns
ms
ns
ns
ns
ns
Serial Output Delay Time
tXD
—
90
tWR
Reset Signal Input Width
Reset Start Time
1
—
tDRS
tDRE
tDIT
5
—
Reset End Time
—
52
Process Operation Start Time
Power-Down Start Time
Power-Down End Time
RST Width After Power-Down
RST Control Pin Setup Time
RST Control Pin Hold Time
SCK Control Pin Setup Time
SCK Control Pin Hold Time
100
—
—
tDPS
tDPE
tWPR
tDSR
tDHR
tDCS
tDCH
111
15
—
10
—
20
—
20
—
120
120
—
—
17/28
¡ Semiconductor
MSM7617
TIMING DIAGRAMS
Clock Timing
tr
tf
fC, tMCK, tDMC
tMCH
tMCL
CLKIN
SCKO
SCKO
tDCM
tDCM
tDCO
fCO, tCO
tDCC
tDCC
tCYO
SYNCO
tWSO
18/28
¡ Semiconductor
MSM7617
Serial Data Input Timing (Parallel Mode, FTF Mode)
fSCK, tSCK
tDSC
SCK
tSX
tXS
tCYC
SYNC
tWSY
tDH
tDS
SIN
RIN
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
tID
Serial Data Input Timing (Serial Mode)
Note: Refer to parallel mode for detailed timing
fSCK, tSCK
SCK
tCYC
tWSY
SYNC1
tID2
tDH
tDS
RIN1
SIN1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
CH1 data
CH2 data
19/28
¡ Semiconductor
MSM7617
Serial Data Output Timing (Parallel Mode, FTF Mode)
fSCK, tSCK
tDSC
SCK
tXS
tSX
tCYC
SYNC
tWSY
tXD
tXD
tSD
tXD
SOUT
ROUT
High-Z
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
High-Z
Serial Data Output Timing (Serial Mode)
Note: Refer to parallel mode for detailed timing
fSCK, tSCK
SCK
tCYC
tWSY
SYNC1
ROUT1 High-Z
SOUT1
High-Z
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
CH1 data
CH2 data
Operation Timing After Reset
tWR
Note: Reset timing can be asynchronous.
tDIT
RST
tDRS
tDRE
Reset
Internal operation
Initial setting
Proccessing starts
20/28
¡ Semiconductor
MSM7617
Power-Down Timing
Note: All inputs are invalid during power-down. Always reset the device after power-down.
PWDWN
tDPS
tDPE
Internal operation
Power-down
tWPR
RST
Capture Timing of Control Pins
Controlpinstatesarecapturedduringresetandduringeachperiod’sserialdatacapture.
tWR
RST
tDHR
tDSR
Control Pin
SCK
tID2
tID
SYNC
tDCH
tDCS
Channel 1 Control Pin
Channel 2 Control Pin
(when not in serial mode)
tDCH
tDCS
Channel 2 Control Pin (when in serial mode)
21/28
¡ Semiconductor
MSM7617
HOW TO USE THE MSM7617
The echo canceler cancels the echo on the RIN signal as returned by SIN. Connect the original
signal to the R side, and the signal generating the echo to the S side.
Connection Methods According to Echoes
Example 1. Cancel Acoustic Echo (applies to acoustic echo from line input)
ROUT
RIN
Input
AFF
H
Acoustic echo
CODEC
CODEC
–
SIN
SOUT
+
+
Example 2. Cancel Line Echo (applies to line echo from microphone input)
SOUT
SIN
+
H
CODEC
CODEC
AFF
Input
RIN
ROUT
Line echo
Example 3. Cancel Both Acoustic Echo And Line Echo
MSM7617
ROUT1
Input
SIN2
+
AFF
H
Acoustic echo
CODEC
CODEC
AFF
SIN1
+
ROUT2
Line echo
Input
CH1
CH2
22/28
¡ Semiconductor
MSM7617
ECHO CANCELER CHARACTERISTICS DIAGRAM
Characteristics of m-law and A-law are identical. (Characteristic graphs below are reference
data.)
ERL vs. Echo Attenuation
RIN Input Level vs. Echo Attenuation
40
30
20
10
0
40
30
20
10
0
40 30 20 10
E. R. L. [dB]
0
–10
–50 –40 –30 –20 –10
RIN Input level [dBm0]
0
10
Measuring Conditions:
RIN input level = –10 dBm0 white noise
Echo delay time = 50 ms
Measuring Conditions:
RIN input = white noise
Echo delay time = 50 ms
E.R.L. = 6 [dB]
ATT, GC, NLP, LR all off
ATT, GC, NLP, LR all off
Echo Delay Time vs. Echo Attenuation
Measuring Conditions:
40
30
20
10
0
RIN input level = –10 dBm0 white noise
Echo delay time = 50 ms
E.R.L = 6 dB
ATT, GC, NLP, LR all off
0
10
20
30
40
50
60
Echo Delay Time [ms]
Note: regarding dBm0:
The "dBm0" unit used in the characteristic graphs is a unit that expresses PCM CODEC digital
values. Therefore, be aware that the same value 0 [dBm0] might correspond to different analog
input levels depending on the PCM CODEC being used. Please check the data sheet of the PCM
CODEC being used.
Example
MSM7533
0 [dBm0] = 0.85 [Vrms] = 2.4 [Vp-p] = 0.8 [dBm] 600 W
–10 [dBm0] = 0.27 [Vrms] = 0.76 [Vp-p] = –9.2 [dBm] 600 W
MSM7543
0 [dBm0] = 0.6007 [Vrms] = 1.7 [Vp-p] = –2.2 [dBm] 600 W
–10 [dBm0] = 0.19 [Vrms] = 0.54 [Vp-p] = –12.2 [dBm] 600 W
23/28
¡ Semiconductor
MSM7617
Measurement System Block Diagram
White noise generator
MSM7617
RIN ROUT
Echo Delay Time
Delay
L. P. F.
5 kHz
CH1 or CH2
SOUT SIN
Level Meter
ATT
E. R. L.
2ch CODEC
MSM7533
24/28
¡ Semiconductor
MSM7617
NOTES ON USE
1. Set echo return loss (E. R. L) to be attenuated. If the echo return loss is set to be amplified, the
echo cannot be canceled. (Refer to the "E. R. L vs Echo Attenuation" characteristic graph.)
When the echo return loss is amplified, adjust the input level to be attenuated by setting the
mode with the SA pin. If the level from the SA pin is too low by setting the mode with the SA
pin, then amplify the output level by setting the mode with the SG pin.
2. SetRINinputsothatthereisnotexcessiveinput(above0dBm0)fromthePCMCODEC. Echo
cancellation is not possible with excessive input. (Refer to the "RIN vs Echo Attenuation"
characteristic graph.)
Recommended input levels are –10 to –20 dBm0. If there is a possibility of excessive input,
then set GC mode or 6LR mode with the RGC pins.
3. Applying the tone signals to this echo canceler will decrease echo attenuation.
4. If a clock is not input after power is applied, then the internal circuits will not stabilize,
possibly damaging the device.
When power is applied, set the PWDWN pin to "H" and input the basic clock.
If the device is put into PWDWN immediately after power has been applied, be sure to input
10 or more clocks of the basic clock before setting to the power down mode.
5. Always reset after power is applied or power-down is released.
For power-on reset operation, an external oscillator may require a certain setting time after
powered on. Allow 10 ms for a reset time after the oscillator has settled.
6. Whenthedeviceisusedasanacousticechocanceler,equipmentnoiseandenvironmentnoise
from the microphone amp may be amplified, and echo attenuation may be below 30 dB.
25/28
¡ Semiconductor
MSM7617
APPLICATION CIRCUITS
4-Channel Serial Interface
Line Echo Canceler Example
26/28
¡ Semiconductor
Cross-Connection Example
Microphone Input
MSM7617
2ch CODEC
MSM7533VGS-K
C1
R1
R5
C2
21
22
4
24
23
2
AIN1
AIN2
Line Input
R2
R6
GSX1
GSX2
AOUT1 AOUT2
Line Output
R3
R7
DV
DV
13
14
11
Speaker Output
DOUT1 DOUT2
12
15
10
16
19
DIN1
DIN2
XSYNC
8
1
RSYNC
VDD
AV
+
BCLK
A/m
SGC
C4 C5
18 C3
9
5
6
PDN
CHP
AG
DG
(AG)
DV
DV
R4
DV
MSM7617
23
22
RIN1
ROUT1
R8
19
58
62
20
59
61
SOUT1
RIN2
SIN1
ROUT2
SIN2
SOUT2
13
9
4
SYNC1
SCK
SYNC2
32
31
11
14
15
49
50
6
3
2
WDT1
DF1
NLP1
HCL1
ADP1
HD1
WDT2
DF2
NLP2
HCL2
ADP2
HD2
DV
R1 = 20 kW
R2 = 20 kW
R3 = 2.2 kW
R4 = 10 kW
R5 = 20 kW
R6 = 20 kW
R7 = 2.2 kW
R8 = 10 kW
17
64
18
24
25
26
27
29
63
57
56
55
54
52
ATT1
ATT2
SG21
SG20
SA21
SG11
SG10
SA11
SA10
RGC11
RGC10
DV
DG
SA20
RGC21
30
16
41
40
51
1
RGC20
RST2
RST1
ECDM1
RST
8
IOM1
IOM0
ECM
7
DG
ECDM0
10
38
39
43
46
42
TST
CLKIN
PWDWN
C1 = 1 mF
SYNC0
SCK0
CLK
C2 = 1 mF
PWDWN
47
48
5
12
28
44
DV
DG
VDD(PLL)
VSS
VSS
VSS
C3 = 0.1 mF
C4 = 10 mF
C5 = 0.1 mF
C6 = 0.1 mF
C7 = 0.1 mF
C8 = 10 mF
C6
V
SS(PLL)
VDD
21
33
34
35
36
45
60
VDD
VDD
VDD
VDD
VDD
VSS
DG
C8
C7
37
53
+
VDD
VDD
DV
27/28
¡ Semiconductor
PACKAGE DIMENSIONS
QFP64-P-1414-0.80-BK
MSM7617
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.87 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
28/28
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