MSM7716PMB [OKI]
Single Rail Linear CODEC; 单铁线性编解码器
| 型号： | MSM7716PMB |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Single Rail Linear CODEC |
| 文件： | 总23页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7716P-01
This issue: June 17, 2004
OKI Semiconductor
MSM7716P
Single Rail Linear CODEC
GENERAL DESCRIPTION
The MSM7716P is an extended temperature range version for the MSM7716 which is a single-channel CODEC
CMOS IC for voice signals that contains filters for linear A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is optimized for
applications for the analog interfaces of audio signal processing DSPs and digital wireless systems.
The analog output signal can directly drive a ceramic type handset receiver. In addition, levels for analog outputs
can be set by external control.
FEATURES
• Single power supply
• Operating temperature
: +3.0V to +3.6 V
: -40°C to +85 °C
Remarks : Standard operating temperature range version MSM7716 (without “P”)
- Power Supply Voltage : +2.7V to +3.6 V
- Operating temperature : -30°C to +85 °C
•Low power consumption
Operating mode
: 30 mW Typ.
Power down mode
: 0.05 mW Typ.
• Digital signal input/output interface : 14-bit serial code in 2's complement format
•Sampling frequency(fs)
• Transmission clock frequency
• Filter characteristics
: 4 to 16 kHz
: fs × 14 min., 2048 kHz max.
: when fs = 8 kHz, complies with ITU-T Recommendation G. 714
• Built-in PLL eliminates a master clock
• Two input circuits in transmit section
• Two output circuits in receive section
• Transmit gain adjustable using an external resistor
• Receive gain adjustable by external control 8 steps, 4 dB/step
•Transmit mic-amp is eliminated by the gain setting of a maximum of 36 dB.
• Analog outputs can drive a load of a minimum of 1 kΩ ; an amplitude of a maximum of 4.0 VPP with push-pull
driving.
• Built-in reference voltage supply
•Package options:
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (MSM7716PMB)
1/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
BLOCK DIAGRAM
MAO
SW1
PCMOUT
SYNC
RC
8th
14BIT
SW 1
SW 2
MAIN
SW 1
SW 2
TCONT
LPF
BPF
ADCONV
PBO
BCLK
SW2
AUTO
ZERO
PBIN
PLL
SG
VR
RT IM
SGC
VFO
GEN
GEN
SG
SW 3
SW 4
SW3
RC
5th
14BIT
VOL
RCONT
LPF
LPF
DACONV
PCMIN
PDN
PWD Logic
SW4
SW4
PWD
SW
SW 4
AUXO
PWI
SG
CONT
DEN
CONT
Logic
SG
CDIN
VOL
SW3
DCLK
CONT
SW 3
AOUT-
AOUT+
VDD
AG
SG
DG
SG
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FEDL7716P-01
OKI Semiconductor
MSM7716P
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
AG
AUXO
SGC
PBIN
PBO
NC
AOUT+
AOUT–
PWI
VFO
NC
NC
NC
VDD
DCLK
NC
NC
MAO
MAIN
NC
NC
PDN
SYNC
NC
BCLK
PCMOUT
PCMI
CDIN
DEN
DG
NC : No connect pin
30-Pin Plastic SSOP
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FEDL7716P-01
OKI Semiconductor
MSM7716P
PIN AND FUNCTIONAL DESCRIPTIONS
MAIN, MAO
Transmit microphone input and the level adjustment.
MAIN is connected to the noninverting input of the op-amp, and MAO is connected to the output of the op-amp.
The level adjustment should be configured as shown below.
During power saving and power down modes, the MAO output is in high impedance state.
MAO
MAIN
R1 : variable
R2 > 20 kΩ
C1 > 1/ (2 × 3.14 × 30 × R3) (F)
C1
R2
–
+
Microphone input
R1
Gain = R2/R1 < 63
SG
PBIN, PBO
Transmit handset input and the level adjustment.
PBIN is connected to the noninverting input of the op-amp, and PBO is connected to the output of the op-amp. The
level adjustment should be configured as shown below.
During power saving and power down, the PBO output is in high impedance state.
R4
R3 : variable
R4 > 20 kΩ
C2 > 1/ (2 × 3.14 × 30 × R3) (F)
PBO
PBIN
C2
Handset
microphone input
–
+
R3
Gain = R4/R3 < 63
SG
VDD
Power supply pin for +3.0 to 3.6 V (Typically 3.3 V).
AG
Analog signal ground.
DG
Ground pin for the digital signal circuits.
This ground is separated from the analog signal ground in this device. The DG pin must be connected to the AG pin
on the printed circuit board.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
VFO
Receive filter output.
The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage when the digital signal of
+3 dBm0 is input to PCMIN. VFO can drive a load of 20 kΩ or more.
This output can be externally controlled in the level range of 0 to –28 dB in 4 dB increments.
During power saving or power down, VFO output is at the voltage level (VDD/2) of SG with a high impedance
state.
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Thus, a receive level can be adjusted with the pins PWI,
AOUT–, and VFO described above.
The output of AOUT+ is inverted with respect to the output of AOUT– with a gain of 1.
The output signal amplitudes are a maximum of 2.0 VPP.
These outputs, above and below the signal ground voltage (VDD/2), can drive a load of a minimum of 1 kΩ with
push-pull driving (a load connected between AOUT+ and AOUT–).
The output amplitudes are 4 VPP maximum during push-pull driving. These outputs can be mute controlled
externally. These outputs are operational during power saving and output the SG voltage (VDD/2) in the high
impedance state.
AUXO
Auxiliary receive filter output.
The output signal is inverted with respect to the VFO output with a gain of 1. The output signal swings above and
below the SG voltage (VDD/2), and can drive a minimum load of 0.5 kΩ with respect to the SG voltage.
The output can be mute controlled externally.
During power saving and power down, AUXO outputs the SG voltage (VDD/2) in the high impedance state.
BCLK
Shift clock signal input for PCMIN and PCMOUT.
The frequency is equal to the data rate. Setting this signal to logic “1” or “0” drives both transmit and receive
circuits to the power-saving state.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
SYNC
Synchronizing signal input.
In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously with this
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the
transmit section.
In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN pin by the
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in
phase with the BCLK.
When this signal frequency is 8 kHz, the transmit and receive section have the frequency characteristics specified
by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in this data sheet.
For different frequencies of the SYNC signal, the frequency values in this data sheet should be translated
according to the following equation:
Frequency values described in the data sheet
× the SYNC frequency values to be actually used
8 kHz
Setting this signal to logic “1” or “0” drives the device to power-saving state.
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal synchronously with the SYNC signal and
BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal. The PCM signal is latched into the internal register
when shifted by 14 bits.
The top of the data (MSD) is identified at the rising edge of SYNC.
The input signal should be input in the 14-bit 2’s complement format.
The MSD bit represents the polarity of the signal with respect to the signal ground.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
PCMOUT
PCM signal output.
The PCM output signal is output from MSD in sequential order, synchronously with the rising edge of the BCLK
signal.
MSD may be output at the rising edge of the SYNC signal, depending on the timing between BCLK and SYNC.
This pin is in high impedance state except during 14-bit PCM output, and is in either in high impedance or in “L”
output state during power down and power saving mode.
A pull-up resistor must be connected to this pin, because its output is configured as an open drain.
The output coding format is in 14-bit 2’s complement.
The MSD represents a polarity of the signal with respect to the signal ground.
Table 1
Input/Output Level
PCMIN/PCMOUT
MSD
+Full scale
0
0
0
1
1
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
+1
0
0
1
0
0
–1
–Full scale
PDN
Power down control signal input.
A digital “L” level drives both transmit and receive circuits to a power down state.
The control registers are set to the initial state.
Be sure to initialize the control registers by to execute this power down by keeping this pin to digital '0' level for
100 ns or longer after the power is turned on the power and the VDD exceeds 3.0 V.
SGC
Connection of a bypass capacitor for generating the signal ground voltage level.
Connect a 0.1 µF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
DEN, DCLK, CDIN
Serial control ports for the microcontroller interface.
Writing data to the 8-bit control register enables control of the receive output level and the signal path.
DEN is the “Enable” signal pin, DCLK is the data shift clock input pin, and CDIN is the control data input pin.
When powered down (PDN = 0), the initial values are set as shown in Tables 2, 3, and 4. The initial values are held
unless the control data is written after power-down release.
The control data is shifted at the rising edge of the DCLK signal and latched into the internal control register at the
rising edge of the DEN signal.
When the microcontroller interface is not used, these pins should be connected to DG.
The bit map of the 8-bit control register is shown below.
B7
B6
B5
B4
B3
—
B2
B1
B0
SW1
SW2
SW3
SW4
VOL1
VOL2
VOL3
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FEDL7716P-01
OKI Semiconductor
MSM7716P
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
AG = DG = 0 V
AG = DG = 0 V
AG = DG = 0 V
—
Rating
Unit
V
–0.3 to +7.0
VAIN
–0.3 to VDD +0.3
–0.3 to VDD +0.3
–55 to +150
V
VDIN
V
TSTG
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Analog Input Voltage
High Level Input Voltage
Symbol
Condition
Min.
3.0
–40
—
Typ.
3.3
+25
—
Max.
Unit
V
VDD
—
—
3.6
+85
1.4
Ta
°C
VPP
V
VAIN Gain = 1
VIH
SYNC, BCLK, PCMIN, PDN, 0.45×VD
—
VDD
DEN, DCLK, CDIN
D
Low Level Input Voltage
VIL
0
—
0.16×VD
V
D
Clock Frequency
FC
FS
DC
tlr
BCLK
SYNC
BCLK
14 × FS
4.0
—
8.0
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
128 × FS kHz
Sync Pulse Frequency
Clock Duty Ratio
16
60
50
50
—
kHz
%
40
Digital Input Rise Time
Digital Input Fall Time
—
ns
ns
ns
ns
—
SYNC, BCLK, PCMIN, PDN,
DEN, DCLK, CDIN
tlf
—
tXS, tRS BCLK → SYNC, See Fig. 1
100
100
1 BCLK
1 BCLK
100
100
0.5
Sync Pulse Setting Time
t
SX, tSR SYNC → BCLK, See Fig. 1
tWSH SYNC, See Fig. 1
—
High Level Sync Pulse Width *1
Low Level Sync Pulse Width *1
PCMIN Setup Time
—
tWSL SYNC, See Fig. 1
—
—
tDS
tDH
Refer to Fig. 1
Refer to Fig. 1
Pull-up resistor
—
ns
ns
kΩ
pF
PCMIN Hold Time
—
RDL
CDL
—
Digital Output Load
DCLK Pulse Width
DEN Setting Time 1
DEN Setting Time 2
—
—
100
—
tWCL DCLK Low width, See Fig. 2
tWCH DCLK High width, See Fig. 2
50
ns
ns
ns
ns
50
—
tCDL
tDCL
tCDH
tDCH
tCDS
tCDH
DCLK → DEN, See Fig. 2
DEN → DCLK, See Fig. 2
DCLK → DEN, See Fig. 2
DEN → DCLK, See Fig. 2
See Fig. 2
50
—
50
—
50
—
50
—
CDIN Setup Time
CDIN Hold Time
50
—
See Fig. 2
50
—
Transmit gain stage, Gain = 0 dB –100
+100
+10
1000
mV
mV
ns
Analog Input Allowable DC Offset
Allowable Jitter Width
Voff
—
Transmit gain stage, Gain = 20 dB
–10
—
SYNC, BCLK
*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is 2048 kHz.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
RECOMMENDED OPERATING CONDITIONS (Continued)
Parameter
Symbol
tSD
Condition
Min.
20
Typ.
—
Max.
100
100
100
100
Unit
ns
tXD1
20
—
CL = 50 pF + 1 LSTTL
Pull-up resistor = 500 Ω
Digital Output Delay Time
tXD2
20
—
tXD3
20
—
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(Fs = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
IDD1
Condition
VDD = 3.6 V
DD = 3.0 V
Min.
—
Typ.
10.0
8.0
Max.
17.0
13.0
Unit
Operating mode
No signal
mA
V
—
Power Supply Current
Power-saving mode, PDN = 1,
SYNC, BCLK → OFF
IDD2
IDD3
VIH
—
6.0
0.01
—
11.0
0.05
VDD
mA
mA
V
Power-down mode, PDN = 0
—
0.45×VD
High Level Input Voltage
Low Level Input Voltage
SYNC, BCLK, PCMIN, DEN,
CDIN, DCLK, PDN
D
0.16×VD
VIL
0.0
—
V
D
High Level Input Leakage Current
Low Level Input Leakage Current
Digital Output Low Voltage
Digital Output Leakage Current
Input Capacitance
IIH
IIL
—
—
—
—
—
—
0.2
—
5
2.0
µA
µA
V
0.5
0.4
10
—
VOL
IO
PCMOUT pull-up resistor = 500
Ω
0.0
—
—
—
µA
pF
CIN
—
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FEDL7716P-01
OKI Semiconductor
MSM7716P
Transmit Analog Interface Characteristics
(Fs = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Parameter
Input Resistance
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
MΩ
kΩ
pF
RINX MAIN, PBIN
Output Load Resistance
Output Load Capacitance
Output Amplitude
RLGX MAO, PBO with respect to SG
20
—
—
CLGX
VOGX
—
—
30
–0.7
–20
—
+0.7
+20
V
Offset Voltage
VOSGX
Gain = 1
—
mV
Receive Analog Interface Characteristics
(Fs = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Parameter
Output Resistance
Symbol
Condition
Min.
—
Typ.
—
Max.
10
Unit
Ω
ROAO AUXO, AOUT+, AOUT–
ROVO VFO
—
—
100
Ω
AUXO, AOUT+, AOUT–
RLAO
0.5
—
—
kΩ
(each) with respect to SG
Output Load Resistance
RLVO VFO with respect to SG
CLAO Output open
20
—
—
—
—
kΩ
Output Load Capacitance
Output Amplitude
50
pF
AUXO, AOUT+, AOUT–, VFO
with respect to SG
VOAO
–1.0
—
—
+1.0
V
AUXO, AOUT+, AOUT–, VFO
with respect to SG
Offset Voltage
VOSA
–100
+100
mV
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FEDL7716P-01
OKI Semiconductor
MSM7716P
AC Characteristics
(FS = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
Unit
Loss 1
Loss 2
Loss 3
Loss 4
Loss 5
Loss 6
Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
Loss R1
Loss R2
Loss R3
Loss R4
Loss R5
SD 1
60
300
20
—
—
–0.2
—
+0.4
Analog
to
Analog
1020
2020
3000
3400
60
Reference
Overall Frequency Response
0
dB
–0.2
—
+0.4
+0.4
1.6
–0.2
0
—
—
20
—
—
300
–0.15
—
+0.2
1020
2020
3000
3400
300
Reference
Transmit Frequency Response
(Expected Value)
0
0
dB
dB
–0.15
–0.15
0
—
—
+0.2
+0.2
0.8
—
–0.15
—
+0.2
1020
2020
3000
3400
Reference
—
Receive Frequency Response
(Expected Value)
–0.15
–0.15
0.0
+0.2
+0.2
0.8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
55.9
—
SD 2
0
55.9
Analog
55.9
—
SD 3
–10
–20
–30
–40
–50
3
—
to
Analog
*1
Overall Signal to Distortion Ratio
1020
1020
1020
dB
dB
dB
SD 4
45.9
—
SD 5
35.9
—
SD 6
25.9
15.9
58
—
SD 7
—
SD T1
SD T2
SD T3
SD T4
SD T5
SD T6
SD T7
SD R1
SD R2
SD R3
SD R4
SD R5
SD R6
SD R7
—
0
58
—
–10
–20
–30
–40
–50
3
58
—
Transmit Signal to Distortion Ratio
(Expected Value)
*1
48
38
28
18
58
58
58
48
38
28
18
—
—
—
—
—
0
—
–10
–20
–30
–40
–50
—
Receive Signal to Distortion Ratio
(Expected Value)
*1
—
—
—
—
*1 Psophometric filter is used.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
AC Characteristics (Continued)
(FS = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
+0.4
Unit
GT 1
GT 2
3
–0.4
+0.01
Reference
0.00
–10
–40
–50
–55
3
Analog
Overall Gain Tracking
1020
1020
1020
to
Analog
dB
GT 3
–0.3
–1.3
–1.6
–0.3
+0.8
+1.3
+1.6
+0.3
GT 4
–0.03
GT 5
–0.15
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
+0.01
–10
–40
–50
–55
3
Reference
0.00
Transmit Gain Tracking
(Expected Value)
dB
dB
–0.3
–0.6
–1.2
–0.3
+0.3
+0.6
+1.2
+0.3
–0.03
+0.15
–0.06
–10
–40
–50
–55
Reference
–0.02
Receive Gain Tracking
(Expected Value)
–0.3
–0.6
–1.2
+0.3
+0.6
+1.2
–0.02
–0.27
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FEDL7716P-01
OKI Semiconductor
MSM7716P
AC Characteristics (Continued)
(FS = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
Unit
AIN: no signal
Overall Idle Channel Noise
Nidle A
Nidle T
Nidle R
—
—
—
—
—
—
—
*1
–70
–71
–76
–66
–67
–74
dBm0p
Transmit Idle Channel Noise
(Expected Value)
—
AIN: no signal
dBm0p
Vrms
*1
—
Receive Idle Channel Noise
(Expected Value)
VDD=3.0 V
AV T
AV R
0.338 0.350 0.362
0.483 0.500 0.518
Absolute Level (Initial Level)
1020
0
Ta=25°C
*2
VDD = +3.0
to 3.6 V
Ta = –40
to 85°C
AV Tt
AV Rt
–0.2
–0.2
—
—
+0.2
+0.2
dB
dB
Absolute Level
(Deviation of Temperature and
Power)
A to A
Absolute Delay
tD
1020
500
0
0
BCLK
= 64 kHz
—
—
0.6
ms
ms
tGD T1
—
—
—
—
—
75
70
—
—
0.325
0.175
0.325
0.125
0.325
—
Transmit Group Delay
*3
*3
tGD T2 600 to 2600
t
GD T3
2800
—
tGD R1 500 to 2600
0.00
0.12
85
Receive Group Delay
Crosstalk Attenuation
0
0
ms
dB
tGD R2
CR T
CR R
2800
TRANS→RECV
RECV→TRANS
1020
80
—
*1 Psophometric filter is used.
*2 AVT is defined at MAO and PBO-PCMOUT.
AVR is defined at PCMIN-VFO.
VOL = 0 dB
*3 Minimum value of the group delay distortion
14/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
AC Characteristics (Continued)
(FS = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
Unit
4.6 to
72 kHz
0 to
30
Discrimination
DIS
S
0
0
32
–37.5
–52
30
—
–35
–40
—
dB
4000 Hz
300 to
3400
4.6 to 100
—
Out-of-band Spurious
Intermodulation Distortion
dBm0
dBm0
kHz
fa = 470
fb = 320
IMD
–4
2fa – fb
*1
—
—
PSR T
PSR R
GAUX
GV2
Power Supply Noise Rejection
Ratio
0 to
50 kHz
50 mVPP
0
dB
dB
Auxiliary Output Gain
1020
VFO to AUXO –1.0
0
+1.0
–3
Set at –4 dB
–8 dB
–5
–9
–4
GV3
–8
–7
GV4
–12 dB –13
–16 dB –17
–20 dB –21
–24 dB –25
–28 dB –29
–12
–16
–20
–24
–28
–11
–15
–19
–23
–27
VOL Gain Setting Value
1020
0
dB
GV5
Referenced
to 0 dB
setting
GV6
GV7
GV8
*1 Measured inband.
15/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
TIMING DIAGRAM
PCM Data Output Timing
Transmit Timing
BCLK
SYNC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
tXS
tSX
tWSL
tWSH
tSD
tXD1
tXD2
tXD3
PCMOUT
MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
When tXS ≤ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1
When tSX < 1/2 • Fc, the Delay of the MSD bit is defined as tSD
.
.
Receive Timing
BCLK
tRS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
tSR
tWSL
tWSH
SYNC
tDH
tDS
PCMIN
MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
Figure 1 Basic Timing Diagram
MCU Interface Timing
DCLK
DEN
1
2
3
4
5
6
7
8
9
10
11
12
13
tCDL
tDCL
tCDH
tDCH
tWCL tWCH
tCDH
B1
tCDS
CDIN
B7
B6
B5
B4
B3
B2
B0
Figure 2 MCU Interface Timing Diagram
16/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
FUNCTIONAL DESCRIPTION
Control Data Description
SW1, SW2······Control bits for the transmit speech path switch.
The AD converter input is selected according to the bit data shown in Table 2.
Table 2
State SW
2
SW
1
AD Converter Input
MAO
Output
PBO
Output
Remarks
—
T1
T2
T3
T4
0
0
1
1
0
1
0
1
No signal (muting state)
Input signal to MAIN
Input signal to PBIN
SG
SG
Effective
SG
SG
At initial setting
Effective
Effective
—
Addition signal of both
MAIN and PBIN
Effective
The gain of each input drops by 6dB
SW3, SW4······Control bits for the receive speech path switch.
The control should be performed according to Table 3.
Table 3
State
R1
SW4
SW3
AOUT+, AOUT– Output
AUXO Output
Remarks
0
0
1
1
0
1
0
1
SG
SG
SG
DA
DA
—
R2
PWI
At initial setting
R3
SG
PWI
—
—
R4
DA: DA converter output.
SG: signal ground voltage.
VOL1, VOL2, VOL3········Control bits for the receive signal output level.
By controlling these bits, the output levels of VFO and AUXO can be controlled
according to Table 4.
Table 4
VOL1
VOL2
VOL3
Receive Signal Gain
0 dB
Remarks
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
At initial setting
–4 dB
—
—
—
—
—
—
—
–8 dB
–12 dB
–16 dB
–20 dB
–24 dB
–28 dB
17/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
APPLICATION CIRCUIT
1 kΩ
+3.3V
MSM7716P
Microphone
analog input
MAIN PCMOUT
PCM output
PCM input
20 kΩ
20 kΩ
20 kΩ
20 kΩ
1 µF
MAO
PCMIN
BCLK
Handset
analog input
PCM shift clock input
PBIN
PBO
1 µF
SYNC
8 kHz SYNC pulse input
Addition
signal input
VFO
PWI
20 kΩ
20 kΩ
1 µF
PDN
Power down control input
“1” = Operation
20 kΩ
“0” = Power down
AOUT
AOUT
AUXO
Analog output*
Analog inverted
output*
Auxiliary output*
DCLK
DEN
0.1 µF
1 µF
Controller
SGC
AG
CDIN
0 V
+3.3 V
DG
10 µF
0 to 10 Ω
+
VDD
* The swing of the analog output signal is a maximum of ±1.0 V above and below the VDD/2 offset level.
18/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
APPLICATION INFORMATION
Digital pattern for 0 dBm0
The digital pattern for 0 dBm0 is shown below.
(SYNC frequency = 8 kHz, signal frequency = 1 kHz)
S2
S3
S1
S4
SG
S5
S8
S6
S7
Sample No. MSD D2
D3
1
D4
0
D5
D6
0
D7
D8
0
D9
D10 D11 D12 D13 D14
S1
S2
S3
S4
S5
S6
S7
S8
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
0
1
1
1
19/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
NOTES ON USE
• To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for
the power supply and keep them as close as possible to the device pins.
•Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance.
•Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is
unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power
supply transformers surround the device.
• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-up that may otherwise
occur when power is turned on.
•Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid
erroneous operation and the degradation of the characteristics of these devices.
20/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
PACKAGE DIMENSIONS
(Unit: mm)
SSOP30-P-56-0.65-K
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.19 TYP.
5/Dec. 5, 1996
5
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
21/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
REVISION HISTORY
Page
Previous Current
Document
No.
Date
Description
Edition
Edition
FEDL7716P-01
Jun. 17, 2004
–
–
First edition
22/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2004 Oki Electric Industry Co., Ltd.
23/23
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