MSM80C49 [OKI]

CMOS 8-Bit Microcontroller; 8位CMOS微控制器


型号：	MSM80C49
厂家：	OKI ELECTRONIC COMPONETS
描述：	CMOS 8-Bit Microcontroller 8位CMOS微控制器微控制器
文件：	总20页 (文件大小：149K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

E2E1022-27-Y4

This version: Jan. 1998

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

Previous version: Nov. 1996

¡ Semiconductor

MSM80C48/49/50

MSM80C35/39/40

CMOS 8-Bit Microcontroller

GENERAL DESCRIPTION

The OKI MSM80C48/MSM80C49/MSM80C50 are 8-bit, low-power, high-performance micro-

controllersimplementedinsilicon-gatecomplementarymetal-oxidesemiconductortechnology.

Integratedwithinthesechipsare8K/16K/32KbitsofmaskprogramROM,512/1024/2048bits

of data RAM, 27 I/O lines, built-in 8 bit timer/counter, and oscillator. Program memory and data

paths are byte wide. Eleven new instructions have been added to the NMOS version's instruction

set, thereby optimizing power down, port data transfer, decrement and port float functions.

Available in 40-pin plastic DIP (RS) or 44-pin plastic flat packages QFP (GSK).

FEATURES

• Lower power consumption enabled by CMOS silicon gate process

• Completely static operation

• Improved power-down feature

• Instruction cycle

1.36 ms (11 MHz) V =4.5 to 6.0 V (MSM80C48/49)

2.5 ms (6 MHz) V =3.5 to 6.0 V (MSM80C50)

• 111 instructions

• All instructions are usable even during execution of external ROM instructions.

• Operation facility

Addition, logical operations, and decimal adjust

• Program memory (ROM)

1K words ¥ 8 bits (MSM80C48)

2K words ¥ 8 bits (MSM80C49)

4K words ¥ 8 bits (MSM80C50)

64 words ¥ 8 bits (MSM80C48)

128 words ¥ 8 bits (MSM80C49)

256 words ¥ 8 bits (MSM80C50)

• Data memory (RAM)

• Two sets of working registers

• External and timer interrupts

• Two test inputs

• Built-in 8-bit timer counter

• Extendable external memory and I/O ports

• I/O port

Input-output port

2 ports ¥ 8 bits

1 port ¥ 8 bits

Data bus input-output port

• Single-step execution function

• Wide range of operating voltage, from + 2.5 V to + 6 V of V

• High noise margin action

• Compatible with Intel's 8048, 8049 and 8050

• Package

40-pin plastic DIP (DIP40-P-600-2.54)

(MSM80C48-¥¥¥RS)

(MSM80C49-¥¥¥RS)

(MSM80C50-¥¥¥RS)

(MSM80C35RS)

(MSM80C39RS)

(MSM80C40RS)

44-pin plastic QFP(QFP44-P-910-0.80-2K)

(MSM80C48-¥¥¥GS-2K)

(MSM80C49-¥¥¥GS-2K)

(MSM80C50-¥¥¥GS-2K)

(MSM80C35GS-2K)

(MSM80C39GS-2K)

(MSM80C40GS-2K)

¥¥¥ indicates the code number.

1/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

BLOCK DIAGRAM

DECODER

2/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

PIN CONFIGURATION (TOP VIEW)

XTAL1

XTAL2

RESET

40 V_CC

39 T1

38 P2₇

37 P2₆

36 P2₅

V_DD

P1₀

P1₁

P1₂

P1₃

P1₄

P1₅

33 DB₃

32 DB₂

31 DB₁

30 DB₀

29 ALE

28 WR

27 PSEN

26 RD

25 EA

INT

35 P2₄

34 P1₇

33 P1₆

32 P1₅

31 P1₄

30 P1₃

29 P1₂

28 P1₁

27 P1₀

26 V_DD

25 PROG

24 P2₃

23 P2₂

22 P2₁

21 P2₀

PSEN

WR 10

ALE 11

DB₀12

DB₁13

DB₂14

DB₃15

DB₄16

DB₅17

DB₆18

DB₇19

V_SS20

P1₆

P1₇10

P2₄11

24 INT

23 SS

NC: No-connection pin

40-Pin Plastic DIP

44-Pin Plastic QFP

3/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

PIN DESCRIPTIONS

Symbol

Type

Description

P1₀-P1₇

(PORT 1)

I/O

8-bit quasi-bidirectional port

The high-order four bits of external program memory addresses can be output

from P2.0-P2.3, to which the I/O expander MSM82C43RS may also be connected.

P2₀-P2₇

(PORT 2)

I/O

DB₀-DB₇

(BUS)

Bidirectional port

The low-order eight bits of external program memory address can be output

from this port, and the addressed instruction is fetched under the control of

PSEN signal. Also, the external data memory address is output, and data is

read and written synchronously using RD and WR signals.

The port can also serve as either a statically latched output port or a

non-latching input port.

(Test 0)

I/O

The input can be tested with the conditional jump instructions JT0 and JNT0.

The execution of the ENT0 CLK instruction causes a clock output.

(Test 1)

The input can be tested with the conditional jump instructions JT1 and JNT1.

The execution of a STRT CNT instruction causes an internal counter input.

INT

(Interrupt)

Interrupt input. If interrupt is enabled, INT input initiates an interrupt.

Interrupt is disabled after a reset.

Also testable with a JNI instruction. Can be used to terminate the power-down

mode. (Active "0" level)

A signal to read data from external data memory. (Active "0" level)

A signal to write data to external data memory. (Active "0" level)

(Read)

(Write)

ALE

This signal is generated in each cycle. It may be used as a clock output.

External data memory or external program memory is addressed upon the

falling edge. For the external ROM, this signal is used to latch the bus port data

upon the ALE signal rise-up after the execution of the OUTL BUS, A instruction.

Address &

Data Latch

Clock

A signal to fetch an instruction from external program memory

(Active "0" level)

PSEN Program

Store Enable

RESET

RESET input initialize the processor. (Active "0" level)

Used to terminate the power-down mode.

A program is executed step by step. This pin can also be used to control

internal oscillation when the power-down mode is reset.

(Active "0" level)

(Single Step)

When held at high level, all instructions are fetched from external memory.

(Active "1" level)

(External Access)

PROG

(Expander Strobe)

This output strobes the MSM82C43RS I/O expander.

4/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

PIN DESCRIPTIONS (Continued)

Symbol

Type

Description

XTAL1

One side of the internal crystal oscillator. An external clock can also be input.

(Crystal 1)

XTAL2

Other side of the internal crystal oscillator.

(Crystal 2)

V_CC

V_DD

—

Power supply pin

Standby control input. Normally, "1" level. When set to "0" level, oscillation is

stopped and prosessor goes into standby mode.

V_SS

—

GND

Note: A minimum of two machine cycles are required in RESET pulse duration under the

specified power supply and stable oscillator frequency.

5/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

ABSOLUTE MAXIMUM RATINGS

Parameter

Supply Voltage

Symbol

V_CC

Condition

Ta=25°C

—

Rating

–0.5 to 7

Unit

Input Voltage

V_I

–0.3 to V_CC+0.5

–65 to +150

Storage Temperature

T_STG

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage

Symbol

V_CC

Condition

f_OSC=DC to 11MHz*

—

Range

+2.5 to +6

–40 to +85

Unit

Ambient Temperature

T_a

°C

MOS load

—

Fan Out

TTL load

Minimum operating voltage is dependent on frequency.

6/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

MSM80C48/49/50 guaranteed operating range

Ta=–40 to +85°C

(msec)

100

Guaranteed Operating Range

1.5MHz

MSM80C40/80C50

6MHz

11MHz

MSM80C35/80C48/80C39/80C49

(V)

Supply Voltage (V_CC

)

7/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

ELECTRICAL CHARACTERISTICS

DC Characteristics

(V_CC=5 V 10ꢀ, Ta=–40 to +85°C)

Mea-

Min. Typ. Max. Unit suring

Circuit

Parameter

"L" Input Voltage

Symbol

Condition

V_IL

V_IH

V_OL

V_OH

I_IL

—

–0.5

0.4 V_CC

0.7 V_CC

—

–50

–8

–15

0.13 V_CC

V_CC

0.45

—

"H" Input Voltage *1

"H" Input Voltage *2

"L" Output Voltage *3

"L" Output Voltage *4

"H" Output Voltage *3

"H" Output Voltage *4

"H" Output Voltage *3

"H" Output Voltage *4

Input Leakage Curent

Output Leakage Current *5

—

I_OL=2 mA

I_OL=1.6 mA

I_OH=–400 mA

I_OH=–50 mA

I_OH=–20 mA

I_OH=–10 mA

V_SS£ V_IN£ V_CC

V_SS£ V_O£ V_CC

V_IN=0.7 V_CC

V_IN=0.13 V_CC

Pull-up (V_IN=V_IL)

Pull-down (V_IN=V_IH)

V_IN=V_IH

—

0.75 V_CC

0.93 V_CC

—

I_OL

—

–20

–80

–15

I_R

I_SS

RESET Input current

SS Input current *6

P1, P2 input current

–3

–6

–25

–300 –600 –900

I_P1, I_P2

V_IN=V_IL

–10

–40

–80

At hardware power down ^*7

—

Ta=25°C, V_CC=2.0 V

Power Down Mode

Standby Current

I_CCS

At HLTS execution ^*7

Ta=25°C, V_CC=2.0 V

—

V_CC=4 V, f=1 MHz

V_CC=4 V, f=6 MHz

V_CC=4 V, f=11 MHz

V_CC=5 V, f=1 MHz

V_CC=5 V, f=6 MHz

V_CC=5 V, f=11 MHz

V_CC=6 V, f=1 MHz

V_CC=6 V, f=6 MHz

V_CC=6 V, f=11 MHz

V_CC=4 V, f=1 MHz

V_CC=4 V, f=6 MHz

V_CC=4 V, f=11 MHz

V_CC=5 V, f=1 MHz

V_CC=5 V, f=6 MHz

V_CC=5 V, f=11 MHz

V_CC=6 V, f=1 MHz

V_CC=6 V, f=6 MHz

V_CC=6 V, f=11 MHz

—

0.5

1.0

2.0

1.0

2.0

3.0

1.5

3.0

5.0

1.5

5.0

Power Supply Current

(Halt Mode)

I_CC

2.5

7.5

I_CC

Power Supply Current

5.0

8/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

This does not apply to RESET, XTAL1, XTAL2, V , and EA.

RESET, XTAL1, XTAL2, V , and EA.

BUS, RD, WR, PSEN, ALE, PROG

Other outputs

High-impedance state

Thisoperatesasapull-downresistorwhentheoscillationisstoppedintheHLTSorV

power-down mode and as a pull-up resistor in other states.

This does not contain flow out current from I/O ports and signal pins.

9/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

AC Characteristics

(V_CC=2.5V to 6V (*1), Ta=–40 to +85°C)

_CC=5 V±±10

Variable clock

1 to ±± MHz

Parameter

Symbol ±± MHz Clock

Min. Max.

Unit

Min.

3.5t–170

2t–110

t–40

Max.

—

t_LL

t_AL

150

—

ALE Pulse Width

—

Address Setup Time (up to ALE)

Address Hold Time (from ALE)

Bus Port Latch Data Setup Time (up to ALE Rising Edge)

Bus Port Latch Data Hold Time (from ALE Rising Edge)

Control Pulse Width (RD, WR)

Control Pulse Width (PSEN)

Data Setup Time (before WR)

Data Hold after Time (after WR)

Data Hold Time (after RD, PSEN)

RD to Data-in

t_LA

—

t_BL

110

—

2.5t –115

1.5 t–45

7t–155

6t–200

6t–155

2t–140

—

t_LB

—

t_CC1

t_CC2

t_DW

t_WD

t_DR

480

350

390

—

110

350

190

—

1.5t–30

5t–265

—

t_RD1

t_RD2

t_AW

t_AD1

t_AD2

t_AFC1

t_AFC2

t_LAFC2

t_LAFC1

t_CA1

t_CA2

t_CP

—

PSEN to Data-in

300

—

6t–245

—

Address Setup to WR

730

460

—

12t–360

8t–265

—

Address Setup to Data-in

—

Address Setup to Instruction

Address Float to RD, WR

140

2t–40

—

Address Float to PSEN

—

t–30

—

Control Pulse Setup Time from ALE (PSEN)

Control Pulse Setup Time from ALE (RD, WR)

Control Pulse up to ALE (RD, WR, PROG)

Control Pulse up to ALE (PSEN)

Port Control Setup Time (up to PROG Falling Edge)

Port Control Hold Time (from PROG Falling Edge)

PROG to Input Data Valid

200

—

3t–75

1.5t–85

4.5t–90

2t–130

4t–260

—

320

—

t_PC

100

—

t_PR

650

140

—

9t–170

1.5t

—

t_PF

Input Data Hold Time

t_DP

250

6t–290

3t–230

10t–210

4.5–250

1.5t–120

—

Output Data Setup Time

t_PD

—

Output Data Hold Time

t_PP

700

160

—

PROG Pulse Width

t_PL

—

Port 2 I/O Setup Time

t_LP

—

Port 2 I/O Hold Time

t_PV

—

510

—

4t+145

—

Port Output Data (from ALE)

T0 Cycle

t_OPRR

t_CY

270

1.36

—

15t

—

Instruction Execution Time

Note : Control output : C =80pF

Bus output : C =150pF [for 20 pF (t , t

, t

)]

AL AFC1 AFC2

*1 Minimum operating voltage is dependent on frequency.

10/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

Measuring circuits

V_CC

GND

(*2)

(*1)

V_CC

GND

V_IH

(*3)

I_O

V_IL

V_CC

V_IH

V_IL

(*3)

V_IL

GND

V_IH

V_CC

(*2)

V_IL

V_IH

(*3)

V_OH

V_IL

V_OL

GND

V_OH

V_OL

t_XXX

*1 This is repeated for each specified input pin.

*2 This is repeated for each specified output pin.

*3 Input logic for setting the specified state

11/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

Timing Diagram

Instruction fetch (from external program memory)

t_CY

t_LL

ALE

t_AFC

t_CC

PSEN

t_ALt_LA

t_RD

t_DRt_BLt_LB

LATCH DATA ADDRESS

FLOATING

INSTRUCTION

LATCH DATA ADDRESS

BUS

t_AD

Read (from external data memory)

ALE

t_CC

AFC t_RD

t_DR

FLOAT-

ING

FLOAT-

ING

ADDRESS

DATA

ADDRESS

BUS

t_AD

12/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

Write (to external memory)

ALE

t_CC

t_AW

t_DW

t_WD

FLOAT-

ING

BUS

ADDRESS

DATA

ADDRESS

Low-order 4 bits input/output of port 2 when expanded I/O port is used

(in external program memory access mode)

ALE

t_LP

t_PL

t_DP

t_PD

P2_0-3

(Output mode)

PCH

PORT DATA PORT CONTROL

OUTPUT DATA

t_PF

t_PR

P2_0-3

(Input mode)

INPUT

DATA

PORT DATA PORT CONTROL

t_CP

t_PC

t_PP

PROG

13/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

FUNCTIONAL DESCRIPTION

Added Functions of MSM80C48, MSM80C49 and MSM80C50

The MSM80C48, MSM80C49 and MSM80C50 are basically incorporated with the capabilities of

Intel's 8048, 8049, and 8050 plus the following new functions:

1. Power-Down Mode Enhancements

1.1 Power-down by software

(1) Clock (See item 4, "Power-down mode", for details.)

a. Crystal oscillator halt (HLTS instruction)

Power requirements can be minimized.

b. Clock supply halt (HALT instruction)

Restart is accomplished without oscillator wait.

(2) I/O ports

I/O port floating instructions

Power consumption resulting from inputs/outputs can be minimized with FLT and FLTT

instructions.

Port floating is cancelled by executing FRES instruction, "0" level at INT pin or "0" level at

RESET pin.

(3) Six types of power-down can be done by a combination of HLTS/HALT and FLT/FLTT

instructions.

1.2 Power-down by hardware (See 4.3, Power-down mode by V pin utilization for

details.)

Crystal oscillators can be halted by controlling the V pin, thereby floating all I/O ports

for minimum power consumption.

2. Additional Instructions (11)

HLTS

MOV A, P2

HALT

FLT

FLTT

MOVP1, @ R3

MOVP1 P, @R3

DEC @Rr

FRES

DJNZ @ Rr, addr

MOV A, P1

3. Improved Uses of BUS P - , P1 - , P2 - , and SS pins

0 7

3.1 BUS P -

0 7

The MSM80C48, MSM80C49, and MSM80C50 remove the limitation on the use of OUTL

BUS, A instructions during the external ROM access mode by having an independent data

latch and external ROM mode address latch in BUS P - .

0 7

Consequently, there is no need to relocate bus port instructions when in the external ROM

access mode.

3.2 P - and P2 -

10 7

0 7

TheMSM80C48,MSM80C49andMSM80C50aredesignedtominimizepowerconsumption

when P1 - and P2 - are used as input/output ports, to maximize the performance of

0 7

CMOS.

When these ports are used as output ports, the acceleration circuit is actuated only when

14/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

output data changes from "0" to "1", thus speeding up the rise time of the output signals.

Whentheseportsareusedasinputports,theinternalpull-upresistorbecomesapproximately

9 kW when input data is "1".

The internal pull-up resistor rises to approximately 100 kW when input data is "0".

Thus, a high noise margin can be obtained by selecting the impedance and thus the outflow

of current is minimized whenever these ports are used as output or input ports.

3.3 Clock generation control via the SS pin

When the crystal oscillator is halted in the HLTS or hardware power-down mode, the SS

pin is pulled down by a resistor of 20 to 50 kW, while its internal pull-up resistor of 200 to

500kW is isolated from V . When the power-down mode is cancelled, the internal resistor

of the SS pin is changed from pull-down to pull-up. Consequently, the CPU can be halted

for any period of time until the crystal oscillator resumes normal oscillation when a

capacitor is connected to the SS pin.

4. Power-Down Mode

The MSM80C48, MSM80C49, and MSM80C50 power-down mode can be enabled in two

different ways through software by a combination of clock control and port floating

instructions, and through hardware by control of the V

pin.

4.1 Software power-down mode

Power-down mode can be done by a combination of the following instructions.

(1) HALT (clock supply halt to control circuit)

Instruction code :

Description :

Although crystal oscillator operation is continued, the clock supply to

the CPU control circuit is halted and CPU operations are suspended.

When cancelling this software mode, restart is accomplished without

oscillator wait.

(2) HLTS (oscillation stop)

Instruction code :

Description :

The oscillator operation is halted and CPU operations are suspended. In

cancelling this power down mode, connecting a capacitor to the SS pin

enables a reasonable wait period to be accomplished before normal

operation is resumed. [Except in the case of using the RESET pin]

(3) FLT (floating P1 - , P2 - , and BP - )

0 7

Instruction code :

Description :

Internal ROM mode

Floating

External ROM mode

Floating

P2₀-₃operation

Operation

Floating

15/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

Details of IC pin status as a result of executing the FLT instruction are shown in the above table.

(4) FLTT (floating of all output pins)

Instruction code :

Description :

Internal ROM mode

Floating

External ROM mode

Operation

ALE

PSEN

PROG

Floating

Operation

Floating

T0 OUT

Floating

P2₀-₃operation

Operation

Floating

XTAL

Operation

Details of IC pin status as a result of executing the FLTT instruction are shown in above

Table.

Example 1 : Power-down mode accomplished by stopping oscillation.

m Can be set by execution of HLTS [82H] instruction.

Example 2 : Power-down mode accomplished by stopping the clock supply to the CPU

control circuit.

m Can be set by execution of HALT [01H] instruction.

Example 3 : Power-down mode by floating of P1 - , P2 - and BP - , and subsequent

0 7

stopping of CPU oscillation.

m Can be set by first executing the FLT [A2H] instruction, followed by the

HLTS [82H] instruction.

Example 4 : Power-down mode by floating P1 - , P2 - and BP - , and then stopping the

0 7

clock supply to the CPU control circuit.

m Can be set by first executing the FLT [A2H] instruction, and then the HALT

[01H] instruction.

Example 5 : Power-downmodebyfloatingalloutputpins,followedbystoppingoscillation.

m Can be set by first executing the FLTT [C2H] instruction followed by

execution of the HLTS [82H] instruction.

Example 6 : Power-down mode by floating all output pins, followed by stopping of the

clock supply to the CPU control circuit.

m Can be set by first executing the FLTT [C2H] instruction, followed by

execution of the HALT [01H] instruction. Connect the pull-up resistor or

pull-down resistor to port pin and fix the output port pin level to either 1or

0 when output port is set to floating.

16/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

4.2 Cancellation of software power-down mode

The power-down mode status outlined above in examples 1 to 6 can be cancelled by using

either the interrupt pin or the RESET pin.

(1) Use of the INT pin during external interrupt enable mode (i.e. following execution of

EN I instruction).

m The clock generator is activated and the CPU is started up when a "0" level is

applied to the INT pin. If this "0" level is maintained until the occurrence of at least

2 ALE output signals, an external interrupt is generated, and execution proceeds

from address 3. If, however, the power-down is entered during the interrupt

processing routine, execution resumes just after the power-down instruction.

(2) Use of the INT pin during external interrupt disable mode (i.e. following execution of

DIS I instruction or hardware reset)

m The clock generator is activated and the CPU is started up when a "0" level is

applied to the INT pin. When "0" level is maintained until the occurrence of at least

2 ALE output signals, execution is resumed just after the power-down instruction.

(3) Use of the RESET pin

m The clock generator is activated and the CPU started up when a "0" level is applied

totheRESETpin. Ifthis"0"levelismaintaineduntiltheoccurrenceofatleast2ALE

output signals, the CPU is reset and execution proceeds from address 0. In case

cancellation is done in oscillation stop mode, the "0" level must be input to the

RESET pin until oscillation is stabilized.

17/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

4.3 Hardware power-down mode

In the MSM80C48, MSM80C49 and MSM80C50, forcing the level at the V

pin to a "0"

during either external ROM or internal ROM mode results in suspension of the oscillator

function and subsequent floating (high impedance) of all the I/O pins except the RESET,

SS and XTAL 1/2 pins. The CPU is thereby stopped while maintaining internal status.

4.4 Cancellation of hardware power-down mode

(1) Use of RESET pin

The clock generator is activated and the CPU started up when a "1" level is applied to

the V pin while a "0" level is input to the RESET pin. If this "0" level is kept applied

to the RESET pin until oscillation become stable, the CPU will be reset and will start

executing from address 0.

(2) Use of the INT pin during external interrupt enable status (i.e. following execution of EN

I instruction)

The clock generator is activated and the CPU started up when a "1" level is applied to

the V

pin while a "0" level is applied to the INT pin. If this "0" level is maintained

until the occurrence of at least 2 ALE output signals, an external interrupt is generated,

and execution starts from address 3.

However, if the power-down mode is started during an interrupt processing routine,

execution will be continued on the next instruction after the present instruction.

(3) Use of the INT pin during external interrupt disable mode (i.e. following excution of DIS

I instruction or hardware reset)

The clock generator is activated and the CPU started up when a "1" level is applied to

the V pin while a "0" level is applied to the INT pin. If this "0" level is maintained

until the occurrence of at least 2 ALE output signals, execution is continued on the next

instruction after the present instruction.

(4) Use of V

pin only

The clock generator is activated and the CPU started up when a "1" level is applied to

the V pin while a "1" level is also applied to both the RESET and INT pins. In this

case, execution is resumed from the stopped position.

18/20

¡ Semiconductor

PACKAGE DIMENSIONS

DIP40-P-600-2.54

MSM80C48/49/50, MSM80C35/39/40

(Unit : mm)

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

6.10 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which

are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the

product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

19/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

(Unit : mm)

QFP44-P-910-0.80-2K

Mirror finish

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

0.41 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which

are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the

product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

20/20

MSM80C49 [OKI]

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SI9130_11

SI9137

SI9137DB

SI9137LG

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