74AUP1G98L6X [ONSEMI]

双输入、低功耗、通用可配置逻辑门;
74AUP1G98L6X
型号: 74AUP1G98L6X
厂家: ONSEMI    ONSEMI
描述:

双输入、低功耗、通用可配置逻辑门

栅 光电二极管 逻辑集成电路 触发器
文件: 总13页 (文件大小:684K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
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October 2010  
74AUP1G98  
TinyLogic® Low Power Universal Configurable  
Two-Input Logic Gate  
Description  
Features  
The 74AUP1G98 is a universal configurable 2-input  
logic gate that provides a high performance and low  
power solution ideal for battery-powered portable  
applications. This product is designed for a wide low  
voltage operating range (0.8V to 3.6V) and guarantees  
very low static and dynamic power consumption across  
the entire voltage range. All inputs are implemented with  
hysteresis to allow for slower transition input signals and  
better switching noise immunity.  
ƒ
ƒ
0.8V to 3.6V VCC Supply Operation  
3.6V Over-Voltage Tolerant I/Os at VCC  
from 0.8V to 3.6V  
ƒ
High Speed tPD  
- 3.0ns: Typical at 3.3V  
ƒ
ƒ
Power-Off High-Impedance Inputs and Outputs  
Low Static Power Consumption  
- ICC=0.9µA Maximum  
The 74AUP1G98 provides for multiple functions as  
determined by various configurations of the three inputs.  
The potential logic functions provided are MUX, AND,  
OR, NAND, and NOR, inverter and buffer. Refer to  
Figures 5 to 11.  
ƒ
ƒ
Low Dynamic Power Consumption  
- CPD=2.5pF Typical at 3.3V  
Ultra-Small MicroPak™ Packages  
Ordering Information  
Part Number  
Top Mark  
Package  
Packing Method  
5000 Units on  
Tape & Reel  
74AUP1G98L6X  
AE  
AE  
6-Lead Micropak™, 1.0mm Wide  
5000 Units on  
Tape & Reel  
74AUP1G98FHX  
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
Logic Diagram  
3
A
4
Y
1
B
6
C
Figure 1. Logic Diagram (Positive Logic)  
Pin Configurations  
B
GND  
A
C
V
1
2
3
6
5
4
CC  
Y
Figure 2. MicroPak™ (Top Through View)  
Pin Definitions  
Pin # MicroPak™  
Name  
Description  
1
2
3
4
5
6
B
GND  
A
Data Input  
Ground  
Data Input  
Output  
Y
VCC  
C
Supply Voltage  
Data Input  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
2
Function Table  
Inputs  
74AUP1G98  
Y=Output  
C
B
A
L
L
L
L
L
H
L
H
H
L
L
H
H
L
L
H
L
L
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H = HIGH Logic Level  
L = LOW Logic Level  
Function Selection Table  
2-Input Logic Function  
Connection Configuration  
2-to-1 MUX with Inverted Output  
2-Input NAND Gate  
Figure 3  
Figure 4  
Figure 5  
Figure 5  
Figure 6  
Figure 6  
Figure 7  
Figure 8  
Figure 9  
2-Input NOR Gate with One Inverted Input  
2-Input AND Gate with One Inverted Input  
2-Input NAND Gate with One Inverted Input  
2-Input OR Gate with One Inverted Input  
2-Input NOR Gate  
Buffer  
Inverter  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
3
74AUP1G98 Logic Configurations  
Figure 3 through Figure 9 show the logical functions that  
can be implemented using the 74AUP1G98. The  
diagrams show the DeMorgan’s equivalent logic duals  
implementation is next to the board-level physical  
implementation of how the pins of the function should be  
connected.  
for  
a
given two-input function. The logical  
VCC  
VCC  
C
B
A
1
2
3
6
5
4
C
Y
B
A
Y
1
2
3
6
5
4
C
Y
C
A
Y
A
GND  
Note:  
1. When C is L, Y=B.  
2. When C is H, Y=A.  
Figure 3. 2-to-1 MUX with Inverted Output  
GND  
Figure 4. 2-Input NAND Gate  
VCC  
VCC  
C
B
Y
C
A
Y
Y
1
2
3
6
5
4
C
Y
B
1
2
3
6
5
4
C
Y
C
B
Y
C
A
A
GND  
GND  
Figure 5. Input NOR Gate with One Inverted Input Figure 6. 2-Input NAND Gate with One Inverted Input  
2-Input AND Gate with One Inverted Input  
2-Input OR Gate with One Inverted Input  
VCC  
VCC  
1
2
3
6
5
4
C
Y
C
B
C
Y
1
2
3
6
5
4
C
Y
B
Y
GND  
GND  
Figure 8. Buffer  
Figure 7. 2-Input NOR Gate  
VCC  
B
1
6
5
4
B
Y
2
3
Y
GND  
Figure 9. Inverter  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
4
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
VCC  
Parameter  
Min.  
-0.5  
-0.5  
-0.5  
-0.5  
Max.  
4.6  
Unit  
V
Supply Voltage  
VIN  
DC Input Voltage  
4.6  
V
HIGH or LOW State(3)  
VCC + 0.5  
4.6  
VOUT  
IIK  
DC Output Voltage  
V
VCC=0V  
DC Input Diode Current  
DC Output Diode Current  
DC Output Source / Sink Current  
VIN < 0V  
-50  
mA  
mA  
VOUT < 0V  
VOUT > VCC  
-50  
IOK  
+50  
IOH / IOL  
ICC or IGND  
TSTG  
±50  
mA  
mA  
°C  
DC VCC or Ground Current per Supply Pin  
Storage Temperature Range  
±50  
-65  
+150  
+150  
+260  
130  
TJ  
Junction Temperature Under Bias  
Junction Lead Temperature, Soldering 10s  
°C  
TL  
°C  
MicroPak-6  
Power Dissipation at +85°C  
MicroPak2-6  
mW  
120  
Human Body Model, JEDEC:JESD22-A114  
Charged Device Model, JEDEC:JESD22-C101  
5000+  
2000  
ESD  
V
Note:  
3. IO absolute maximum rating must be observed.  
Recommended Operating Conditions(4)  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to Absolute Maximum Ratings.  
Symbol  
VCC  
Parameter  
Supply Voltage  
Conditions  
Min.  
0.8  
0
Max.  
3.6  
Unit  
V
VIN  
Input Voltage  
3.6  
V
V
CC=0V  
0
3.6  
VOUT  
Output Voltage  
V
HIGH or LOW State  
VCC=3.0V to 3.6V  
VCC=2.3V to 2.7V  
VCC=1.65V to 1.95V  
VCC=1.4V to 1.6V  
VCC=1.1V to 1.3V  
VCC=0.8V  
0
VCC  
±4.0  
±3.1  
±1.9  
±1.7  
±1.1  
±20.0  
mA  
IOH/IOL  
Output Current  
µA  
°C  
TA  
Operating Temperature, Free Air  
Thermal Resistance  
-40  
+85  
MicroPak-6  
500  
560  
MicroPak2-6  
Note:  
4. Unused inputs must be held HIGH or LOW. They may not float.  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
74AUP1G98 • Rev. 1.0.4  
5
DC Electrical Characteristics  
TA=25°C  
Min.  
TA=-40 to 85°C  
Symbol  
Parameter  
VCC  
Conditions  
Units  
Max.  
0.60  
0.90  
1.11  
1.29  
1.77  
2.29  
0.60  
0.65  
0.75  
0.84  
1.04  
1.24  
0.50  
0.46  
0.56  
0.66  
0.92  
1.31  
Min.  
0.30  
Max.  
0.60  
0.90  
1.11  
1.29  
1.77  
2.29  
0.60  
0.65  
0.75  
0.84  
1.04  
1.24  
0.50  
0.46  
0.56  
0.66  
0.92  
1.31  
0.80  
0.30  
0.53  
1.10  
0.53  
1.40  
0.74  
0.74  
Positive Threshold  
Voltage  
VP  
V
1.65  
0.91  
0.91  
2.30  
1.37  
1.37  
3.00  
1.88  
1.88  
0.80  
0.10  
0.10  
1.10  
0.26  
0.26  
1.40  
0.39  
0.39  
Negative  
Threshold Voltage  
VN  
V
1.65  
0.47  
0.47  
2.30  
3.00  
0.69  
0.69  
0.88  
0.88  
0.80  
0.07  
0.07  
1.10  
0.08  
0.08  
1.40  
0.18  
0.18  
VH  
Hysteresis Voltage  
V
1.65  
0.27  
0.27  
2.30  
0.53  
0.53  
3.00  
0.79  
0.79  
IOH=-20µA  
IOH=-1.1mA  
IOH=-1.7mA  
VCC-0.1  
0.75 x VCC  
1.11  
VCC-0.1  
0.70 x VCC  
1.03  
0.80 VCC 3.60  
1.10 VCC 1.30  
1.40 VCC 1.60  
1.65 VCC 1.95  
I
OH=-1.9mA  
1.32  
1.30  
HIGH Level Output  
Voltage  
VOH  
V
IOH=-2.3mA  
IOH=-3.1mA  
IOH=-2.7mA  
IOH=-4.0mA  
IOL=20µA  
2.05  
1.97  
2.30 VCC 2.70  
3.00 VCC 3.60  
1.90  
1.85  
2.72  
2.67  
2.60  
2.55  
0.10  
0.30 x VCC  
0.31  
0.10  
0.30 x VCC  
0.37  
0.80 VCC 3.60  
1.10 VCC 1.30  
1.40 VCC 1.60  
1.65 VCC 1.95  
IOL=1.1mA  
I
I
OL=1.7mA  
OL=1.9mA  
0.31  
0.35  
LOW Level Output  
Voltage  
VOL  
V
IOL=2.3mA  
IOL=3.1mA  
IOL=2.7mA  
IOL=4.0mA  
0.31  
0.33  
2.30 VCC 2.70  
2.70 VCC 3.60  
0.44  
0.45  
0.31  
0.33  
0.44  
0.45  
Input Leakage  
Current  
IIN  
0V to 3.6V  
0V  
±0.1  
0.2  
±0.5  
0.6  
µA  
µA  
0 VIN 3.6  
Power Off Leakage  
Current  
IOFF  
0 (VIN,VO)3.6  
Additional Power  
Off Leakage  
Current  
VIN or VO=0V to  
3.6V  
0V to 0.2V  
0.2  
0.5  
0.6  
µA  
ΔIOFF  
VIN - VCC or GND  
0.9  
Quiescent Supply  
Current  
ICC  
0.8V to 3.6V  
3.3V  
µA  
µA  
±0.9  
VCC VIN 3.6  
Increase in ICC per  
Input  
VIN=VCC -0.6V  
40.0  
50.0  
ΔICC  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
6
AC Electrical Characteristics  
TA=25°C  
TA=-40 to 85°C  
Symbol Parameter  
VCC  
Conditions  
Units Figure  
Min. Typ. Max. Min.  
Max.  
0.80  
25.3  
2.9  
2.4  
2.2  
2.0  
1.5  
8.7  
5.1  
4.4  
3.5  
3.1  
26.7  
8.5  
5.8  
4.7  
3.6  
3.1  
29.8  
9.9  
6.2  
5.3  
4.1  
3.3  
27.5  
9.1  
5.7  
4.7  
3.5  
3.0  
12.9  
7.7  
6.3  
4.8  
4.2  
2.7  
2.4  
1.9  
1.8  
1.5  
13.2  
8.3  
7.0  
5.4  
4.5  
1.10 VCC 1.30  
1.40 VCC 1.60  
1.65 VCC 1.95  
2.30 VCC 2.70  
3.00 VCC 3.60  
0.80  
CL=5pF, RL=1MΩ  
3.3  
2.7  
2.5  
1.9  
1.5  
14.5  
8.8  
7.2  
5.3  
4.7  
3.0  
2.8  
2.3  
1.9  
1.5  
15.1  
9.5  
8.0  
5.9  
4.9  
1.10 VCC 1.30  
1.40 VCC 1.60  
1.65 VCC 1.95  
2.30 VCC 2.70  
3.00 VCC 3.60  
0.80  
CL=10pF,  
RL=1MΩ  
Propagation  
tPHL, tPLH  
Figure 10  
ns  
Delay  
Figure 11  
3.6  
3.0  
2.8  
2.5  
1.7  
16.1  
9.7  
7.9  
5.9  
5.2  
3.3  
3.1  
2.5  
2.5  
1.7  
16.9  
10.5  
8.9  
1.10 VCC 1.30  
1.40 VCC 1.60  
1.65 VCC 1.95  
2.30 VCC 2.70  
3.00 VCC 3.60  
0.80  
CL=15pF,  
RL=1MΩ  
6.6  
5.5  
3.4  
3.1  
2.7  
1.7  
1.3  
18.5  
10.5  
8.7  
3.4  
3,1  
2.7  
1.7  
1.3  
19.0  
11.0  
9.5  
1.10 VCC 1.30  
1.40 VCC 1.60  
1.65 VCC 1.95  
2.30 VCC 2.70  
3.00 VCC 3.60  
CL=30pF,  
RL=1MΩ  
6.5  
7.1  
5.6  
6.3  
Input  
CIN  
0
0
2.1  
3.0  
pF  
pF  
Capacitance  
Output  
COUT  
Capacitance  
0.80  
1.7  
1.8  
1.10 VCC 1.30  
1.40 VCC 1.60  
1.65 VCC 1.95  
2.30 VCC 2.70  
3.00 VCC 3.60  
Power  
1.81  
1.84  
2.1  
VIN=0V or VCC  
f=10MHz  
,
CPD  
Dissipation  
pF  
Capacitance  
2.5  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
7
AC Loadings and Waveforms  
Figure 10. AC Test Circuit  
Figure 11. AC Waveforms  
VCC  
Symbol  
1.8V ±  
0.15V  
1.5V ±  
1.2V ±  
0.10V  
3.3V ± 0.3V  
2.5V ± 0.2V  
0.8V  
0.10V  
VCC/2  
VCC/2  
Vmi  
VCC/2  
VCC/2  
VCC/2  
VCC/2  
VCC/2  
VCC/2  
VCC/2  
VCC/2  
VCC/2  
VCC/2  
Vmo  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
8
Physical Dimensions  
2X  
0.05 C  
1.45  
B
(1)  
2X  
0.05 C  
(0.49)  
5X  
(0.254)  
1.00  
(0.75)  
(0.52)  
1X  
A
TOP VIEW  
PIN 1 IDENTIFIER  
5
0.55MAX  
(0.30)  
6X  
PIN 1  
0.05 C  
0.05  
0.00  
RECOMMENED  
LAND PATTERN  
0.05 C  
C
0.45  
0.35  
0.10  
6X  
0.00  
0.25  
6X  
0.15  
1.0  
DETAIL A  
0.10  
C B A  
0.40  
0.30  
0.05  
C
0.35  
0.25  
5X  
5X  
0.40  
0.30  
DETAIL A  
PIN 1 TERMINAL  
0.075 X 45  
CHAMFER  
0.5  
BOTTOM VIEW  
(0.05)  
6X  
(0.13)  
4X  
Notes:  
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD  
2. DIMENSIONS ARE IN MILLIMETERS  
3. DRAWING CONFORMS TO ASME Y14.5M-1994  
4. FILENAME AND REVISION: MAC06AREV4  
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY  
OTHER LINE IN THE MARK CODE LAYOUT.  
Figure 12. 6-Lead, MicroPak™, 1.0mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the  
warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
Tape and Reel Specifications  
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:  
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.  
Package Designator  
Tape Section  
Leader (Start End)  
Carrier  
Cavity Number  
125 (Typical)  
5000  
Cavity Status Cover Type Status  
Empty  
Filled  
Sealed  
Sealed  
Sealed  
L6X  
Trailer (Hub End)  
75 (Typical)  
Empty  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
9
Physical Dimensions  
0.89  
0.35  
0.05 C  
2X  
1.00  
B
A
5X 0.40  
1X 0.45  
PIN 1  
0.66  
MIN 250uM  
1.00  
6X 0.19  
0.05 C  
TOP VIEW  
RECOMMENDED LAND PATTERN  
FOR SPACE CONSTRAINED PCB  
2X  
0.90  
0.35  
0.05 C  
0.55MAX  
C
5X 0.52  
SIDE VIEW  
0.73  
0.57  
1X  
(0.08) 4X  
DETAIL A  
0.09  
0.19  
6X  
1
2
3
0.20 6X  
ALTERNATIVE LAND PATTERN  
FOR UNIVERSAL APPLICATION  
(0.05) 6X  
0.35  
5X  
0.25  
0.60  
6
5
4
0.10  
.05 C  
C B A  
0.40  
0.30  
0.35  
(0.08)  
4X  
BOTTOM VIEW  
NOTES:  
A. COMPLIES TO JEDEC MO-252 STANDARD  
B. DIMENSIONS ARE IN MILLIMETERS.  
0.075X45°  
CHAMFER  
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994  
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC  
DESIGN.  
DETAIL A  
PIN 1 LEAD SCALE: 2X  
E. DRAWING FILENAME AND REVISION: MGF06AREV3  
Figure 13. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch  
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Package Designator  
Tape Section  
Cavity Number  
Cavity Status Cover Type Status  
Leader (Start End)  
Carrier  
125 (Typical)  
5000  
Empty  
Filled  
Sealed  
Sealed  
Sealed  
FHX  
Trailer (Hub End)  
75 (Typical)  
Empty  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
10  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G98 • Rev. 1.0.4  
www.fairchildsemi.com  
11  
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