74LCX125MTCX [ONSEMI]
带 5V 耐受输入和输出的低压四路缓冲器;
| 型号： | 74LCX125MTCX |
| 厂家： | 
ONSEMI |
| 描述： | 带 5V 耐受输入和输出的低压四路缓冲器 PC 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Low Voltage Quad Buffer
with 5 V Tolerant Inputs
and Outputs
SOIC14,
74LCX125
CASE 751EF
Description
The LCX125 contains four independent non−inverting buffers with
3−STATE outputs. The inputs tolerate Voltages up to 7 V Allowing the
interface of 5 V Systems to 3 V Systems.
14
The 74LCX125 is fabricated with an advanced CMOS technology
to achieve high Speed operation while Maintaining CMOS Low
Power Dissipation.
1
TSSOP−14, WB
CASE 948G
Features
• 5 V Tolerant Inputs and Outputs
• 2.3 V–3.6 V V Specifications Provided
CC
• 6.0 ns t max. (V = 3.3 V), 10 mA I max.
PD
CC
CC
QFN14, 3.0X2.5, 0.5P
CASE 510CB
• Power Down High Impedance Inputs and Outputs
• Supports Live Insertion/Withdrawal*
•
24 mA Output Drive (V = 3.0 V)
CC
• Latch−up Performance Exceeds JEDEC 78 Conditions
MARKING DIAGRAM
• ESD Performance:
ZXYKK
LCX125
♦ Human body model > 2000 V
♦ Machine model > 100 V
• Leadless DQFN Package
*To ensure the High−Impedance State During Power up or down, OE Should be
Z
XY
KK
= Assembly Plan Code
= Date Code (Year & Week)
= Lot Run Traceability Code
tied to V
through a pull−up resistor: the minimum value of the resistor is
CC
determined by the current−sourcing capability of the driver.
LCX125 = Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
September, 2022 − Rev 2
74LCX125/D
74LCX125
Connection Diagrams
Logic Symbol
IEEE/IEC
Pin Assignments for SOIC, SOP, and TSSOP
(Top View)
Pad Assignments for DQFN
Truth Table
Inputs
Output
OE
L
A
L
O
n
n
n
L
L
H
X
H
Z
H
= HIGH Voltage Level
= HIGH Voltage Level
= HIGH Impedance
= Immaterial
H
L
Z
X
(Top Through View)
(Bottom View)
Pin Description
Description
Inputs
Pin Names
A
n
Output Enable Inputs
Outputs
OE
On
n
DAP
No Connect
Note: DAP (Die Attach Pad)
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2
74LCX125
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Ratings
Unit
V
V
CC
Supply Voltage
−0.5 to +7.0
−0.5 to +7.0
V
I
DC Input Voltage
V
V
O
DC Output Voltage,
− Output in 3−STATE
−0.5 V to +7.0
−0.5 V to V + 0.5
CC
V
V
− Output in HIGH or LOW State (Note 1)
I
IK
DC Input Diode Current, V < GND
−50
mA
I
I
DC Input Diode Current
OK
− VO < GND
−50
+50
mA
mA
− VO > V
CC
I
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50
50
mA
mA
mA
°C
O
I
CC
I
100
GND
T
−65 to +150
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I Absolute Maximum Rating must be observed.
O
RECOMMENDED OPERATING CONDITIONS (Note 4)
Symbol
Parameter
Min.
Max.
Unit
V
CC
Supply Voltage
− Operating
− Data Retention
V
2.0
1.5
3.6
3.6
V
Input Voltage
0
5.5
V
V
I
V
O
Output Voltage
− HIGH or LOW State
− 3−STATE
0
0
V
CC
5.5
I
/ I
Common−mode Input Voltage
mA
OH OL
− V = 3.0 V − 3.6 V
24
12
8
CC
− V = 2.7 V − 3.0 V
CC
− V = 2.3 V − 2.7 V
CC
T
Free−Air Operating Temperature
−40
85
10
°C
A
Dt / DV
Input Edge Rate, V = 0.8 V – 2.0 V, V = 3.0 V
0
ns/V
IN
CC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Unused inputs must be held HIGH or LOW. They may not float..
DC ELECTRICAL CHARACTERISTICS
T
A
= –40°C to +85°C
Min.
1.7
Max.
Symbol
Parameter
V
(V)
Test Conditions
Unit
CC
VIH
HIGH Level Input Voltage
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
V
2.0
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
−
0.7
0.8
−
V
V
−
VOH
VCC – 0.2
1.8
I
I
I
I
I
= −100 mA
= −8 mA
OH
OH
OH
OH
OH
−
2.7
= −12 mA
= −18mA
= −24 mA
2.2
−
3.0
2.4
−
2.2
−
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3
74LCX125
DC ELECTRICAL CHARACTERISTICS (continued)
T
A
= –40°C to +85°C
Min.
−
Max.
0.2
Symbol
Parameter
V
(V)
Test Conditions
= 100 mA
= 8 mA
Unit
CC
VOL
LOW Level Output Voltage
2.3–3.6
2.3
V
I
I
I
I
I
OL
OL
OL
OL
OL
−
0.6
2.7
= 12 mA
−
0.4
3.0
−
0.4
= 16 mA
= 24 mA
−
0.55
5.0
II
Input Leakage Current
2.3–3.6
2.3–3.6
0 ≤ V ≤ 5.5 V
−
mA
mA
I
IOZ
3−STATE Output Leakage
0 ≤ V ≤ 5.5 V,
−
5.0
O
V = V or VIL
I
IH
IO
Power−Off Leakage Current
0
V or V = 5.5 V
−
−
−
10
10
10
mA
mA
FF
I
O
ICC
Quiescent Supply Current
2.3–3.6
VI = V or GND
CC
3.6 V ≤ V , V ≤ 5.5 V
I
O
(Note 3)
Increase in ICC per Input
2.3–3.6
V
IH
= V – 0.6 V
−
500
mA
DICC
CC
3. Outputs disabled or 3−STATE only.
AC ELECTRICAL CHARACTERISTICS
TA = –405C to +855C, R = 500 W
L
V
CC
= 3.3 V 0.3 V,
V
= 2.7 V,
V = 2.5 V 0.2 V,
CC
CC
C
= 50 pF
C
= 50 pF
C = 30 pF
L
L
L
Min.
1.5
1.5
1.5
−
Max.
Min.
1.5
1.5
1.5
−
Max.
Min.
1.5
1.5
1.5
−
Max.
Symbol
Parameter
Unit
tPHL, tPLH
Propagation Delay
6.0
7.0
6.0
1.0
6.5
8.0
7.0
−
7.2
9.1
7.2
−
ns
tPZL, tPZH
tPLZ, tPHZ
Output Enable Time
Output Disable Time
ns
ns
ns
tOSHL, tOSLH Output to Output Skew (Note 4)
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
) or LOW−to−HIGH (t
).
OSHL
OSLH
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= 25°C
Typical
0.8
Symbol
Parameter
V
(V)
Test Conditions
C = 50 pF, V = 3.3 V, V = 0 V
Unit
CC
V
OLP
Quiet Output Dynamic Peak V
3.3
V
OL
L
IH
IL
2.5
3.3
2.5
C = 30 pF, V = 2.5 V, V = 0 V
0.6
L
IH
IL
V
OLV
Quiet Output Dynamic Peak V
C = 50 pF, V = 3.3 V, V = 0 V
−0.8
−0.6
V
OL
L
IH
IL
C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
CAPACITANCE
Symbol
Parameter
Test Conditions
Typical
7.0
Unit
pF
C
Input Capacitance
Output Capacitance
V
CC
V
CC
V
CC
= Open, V = 0 V or V
IN
I
CC
CC
C
= 3.3 V, V = 0 V or V
8.0
pF
OUT
I
C
Power Dissipation Capacitance
= 3.3 V, V = 0 V or V
f = 10 MHz
25.0
pF
PD
I
CC,
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4
74LCX125
AC LOADING AND WAVEFORMS (GENERIC FOR LCX FAMILY)
Test
Switch
t
t
t
PLH, PHL
Open
t
PZL, PLZ
6V at V = 3.3 0.3 V
CC
V
CC
x 2 at V = 2.5 0.2 V
CC
t
t
PZH, PHZ
GND
Figure 1. AC Test Circuit (CL includes probe and jig capacitance)
3−STATE Output High Enable and
Waveform for Inverting and Non−Inverting Functions
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3−STATE Output Low Enable and
trise and tfall
Disable Times for Logic
V
CC
Symbol
3.3 V + 0.3 V
2.7 V
2.5 V + 0.2 V
V
/ 2
/ 2
1.5 V
1.5 V
1.5 V
1.5 V
V
V
mi
CC
CC
V
mo
V
V
V
+ 0.3 V
V
V
+ 0.3 V
V
V
+ 0.15 V
x
OL
OL
OL
V
− 0.3 V
− 0.3 V
− 0.15 V
OH
y
OH
OH
Figure 2. Waveforms (Input Characteristics; f = 1 MHz, tr = tf = 3 ns)
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5
74LCX125
SCHEMATIC DIAGRAM (GENERIC FOR LCX FAMILY)
Figure 3. Schematic Diagram
Package
ORDERING INFORMATION
Product Number
†
Shipping
74LCX125M
SOIC−14
1150 Units / Tube
2500 / Tape and Reel
2500 / Tape and Reel
3000 / Tape and Reel
2350 Units / Tube
(Pb−Free/Halide Free)
74LCX125MX
SOIC−14
(Pb−Free/Halide Free)
74LCX125MTCX
74LCX125BQX (Note 5)
74LCX125MTC
TSSOP−14 WB
(Pb−Free/Halide Free)
QFN−14
(Pb−Free/Halide Free)
TSSOP−14 WB
(Pb−Free/Halide Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
5. DQFN package available in Tape and Reel only.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN14 3.0x2.5, 0.5P
CASE 510CB
ISSUE O
DATE 31 AUG 2016
4.00 MAX
2.20 MAX
1.40 MAX
B
3.00
0.05 C
A
2X
1.00
MAX
1.70
MAX
3.50
MAX
2.50
2X
0.50 TYP
(0.90)
0.05 C
TOP VIEW
PIN #1 QUADRANT
0.80 0.05
0.50 TYP
0.24 TYP
RECOMMENDED LAND PATTERN
0.10
C
0.20 0.05
C
0.08
0.025 0.025
C
SIDE VIEW
SEATING
PLANE
3.00 0.05
1.65 0.05
0.370 0.05
(14X)
A. CONFORMS TO JEDEC REGISTRATION
MO−241, VARIATION AA
PIN #1 IDENT
0.50
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
1.15 0.05
2.50 0.05
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
0.25 0.05
(14X)
0.50
0.10
0.05
C A B
C
2.00
BOTTOM VIEW
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13643G
QFN14 3.0X2.5, 0.5P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC14
CASE 751EF
ISSUE O
DATE 30 SEP 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13739G
SOIC14
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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