74LCX240WMX [ONSEMI]

带 5V 耐压输入和输出的低压八路缓冲器/线路驱动器;
74LCX240WMX
型号: 74LCX240WMX
厂家: ONSEMI    ONSEMI
描述:

带 5V 耐压输入和输出的低压八路缓冲器/线路驱动器

驱动 光电二极管 逻辑集成电路 驱动器
文件: 总14页 (文件大小:553K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
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January 2008  
74LCX240  
Low Voltage Octal Buffer/Line Driver with 5V Tolerant  
Inputs and Outputs  
Features  
General Description  
5V tolerant inputs and outputs  
The LCX240 is an inverting octal buffer and line driver  
designed to be employed as a memory address driver,  
clock driver and bus oriented transmitter or receiver. The  
2.3V–3.6V V specifications provided  
CC  
6.5ns t max. (V = 3.3V), 10µA I max.  
PD  
CC  
CC  
device is designed for low voltage (2.5V or 3.3V) V  
CC  
Power-down high impedance inputs and outputs  
applications with capability of interfacing to a 5V signal  
environment.  
(1)  
Supports live insertion/withdrawal  
24mA output drive (V = 3.0V)  
CC  
The LCX240 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintain-  
ing CMOS low power dissipation.  
Implements proprietary noise/EMI reduction circuitry  
Latch-up performance exceeds 500mA  
ESD performance:  
– Human body model > 2000V  
– Machine model > 200V  
Note:  
1. To ensure the high-impedance state during power up  
or down, OE should be tied to V through a pull-up  
CC  
resistor: the minimum value or the resistor is  
determined by the current-sourcing capability of the  
driver.  
Ordering Information  
Order  
Number  
Package  
Number  
Package Description  
74LCX240WM  
74LCX240SJ  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
74LCX240MSA  
74LCX240MTC  
MSA20  
MTC20  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
Connection Diagram  
Logic Diagram  
Pin Description  
Pin Names  
Description  
OE , OE  
3-STATE Output Enable Inputs  
1
2
I –I  
Inputs  
0
7
Truth Tables  
O –O  
Outputs  
0
7
Inputs  
Outputs  
OE  
L
I
(Pins 12, 14, 16, 18)  
1
n
L
H
L
L
H
X
H
Z
Inputs  
Outputs  
OE  
L
I
(Pins 3, 5, 7, 9)  
2
n
L
H
L
L
H
X
H
Z
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
2
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
Parameter  
Rating  
V
Supply Voltage  
–0.5V to +7.0V  
CC  
V
DC Input Voltage  
DC Output Voltage  
Output in 3-STATE  
–0.5V to +7.0V  
I
V
O
–0.5V to +7.0V  
(2)  
Output in HIGH or LOW State  
–0.5V to V + 0.5V  
CC  
I
DC Input Diode Current, V < GND  
–50mA  
IK  
I
I
DC Output Diode Current  
OK  
V
< GND  
–50mA  
+50mA  
O
V
> V  
CC  
O
I
DC Output Source/Sink Current  
DC Supply Current per Supply Pin  
DC Ground Current per Ground Pin  
Storage Temperature  
50mA  
O
I
100mA  
CC  
I
100mA  
GND  
T
–65°C to +150°C  
STG  
Note:  
2. I Absolute Maximum Rating must be observed.  
O
(3)  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to absolute maximum ratings.  
Symbol  
Parameter  
Min.  
Max.  
Units  
V
Supply Voltage  
Operating  
CC  
2.0  
1.5  
0
3.6  
3.6  
5.5  
V
V
V
Data Retention  
Input Voltage  
Output Voltage  
3-STATE  
V
I
V
O
0
0
5.5  
HIGH or LOW State  
Output Current  
V
CC  
I
/ I  
OH OL  
V
V
V
= 3.0V–3.6V  
= 2.7V–3.0V  
= 2.3V–2.7V  
24  
12  
8
mA  
CC  
CC  
CC  
T
Free-Air Operating Temperature  
Input Edge Rate, V = 0.8V–2.0V, V = 3.0V  
–40  
0
85  
10  
°C  
A
t / V  
ns/V  
IN  
CC  
Note:  
3. Unused inputs must be held HIGH or LOW. They may not float.  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
3
DC Electrical Characteristics  
T = –40°C to +85°C  
A
Symbol  
Parameter  
V
(V)  
Conditions  
Min.  
1.7  
Max.  
Units  
CC  
V
HIGH Level Input Voltage  
2.3–2.7  
2.7–3.6  
2.3–2.7  
2.7–3.6  
2.3–3.6  
2.3  
V
IH  
2.0  
V
LOW Level Input Voltage  
HIGH Level Output Voltage  
0.7  
0.8  
V
V
IL  
V
I
I
I
I
I
I
I
I
I
I
= –100µA  
= –8mA  
= –12mA  
= –18mA  
= –24mA  
= 100µA  
= 8mA  
V
– 0.2  
OH  
OH  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
OL  
CC  
1.8  
2.2  
2.4  
2.2  
2.7  
3.0  
V
LOW Level Output Voltage  
2.3–3.6  
2.3  
0.2  
0.6  
0.4  
0.4  
0.55  
5.0  
10  
V
OL  
2.7  
= 12mA  
= 16mA  
= 24mA  
3.0  
I
Input Leakage Current  
2.3–3.6  
2.3–3.6  
2.3–3.6  
0 V 5.5V  
µA  
µA  
µA  
I
I
I
Power-Off Leakage Current  
Quiescent Supply Current  
V or V = 5.5V  
I O  
OFF  
I
V = V or GND  
10  
CC  
I
CC  
(4)  
3.6V V , V 5.5V  
10  
I
O
I  
Increase in I per Input  
V
= V = 0.6V  
500  
µA  
CC  
CC  
IH  
CC  
Note:  
4. Outputs disabled or 3-STATE only.  
AC Electrical Characteristics  
T = –40°C to +85°C, R = 500Ω  
A
L
V
= 3.3V 0.3V,  
V
= 2.7V,  
V = 2.5V 0.2V,  
CC  
CC  
CC  
C = 50pF  
C = 50pF  
C = 30pF  
L
L
L
Symbol  
Parameter  
Propagation Delay  
Output Enable Time  
Output Disable Time  
Output to Output Skew  
Min.  
1.5  
Max.  
6.5  
Min. Max.  
Min.  
1.5  
Max.  
7.8  
Units  
ns  
t
, t  
1.5  
1.5  
1.5  
7.5  
9.0  
8.0  
PHL PLH  
t
t
, t  
1.5  
8.0  
1.5  
10.0  
8.4  
ns  
PZL PZH  
, t  
1.5  
7.0  
1.5  
ns  
PLZ PHZ  
(5)  
t
, t  
1.0  
ns  
OSHL OSLH  
Note:  
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate  
outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-  
LOW (t  
) or LOW-to-HIGH (t  
).  
OSHL  
OSLH  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
4
Dynamic Switching Characteristics  
T = 25°C  
A
Symbol  
Parameter  
V
(V)  
Conditions  
Typical  
0.8  
Unit  
CC  
V
Quiet Output Dynamic Peak V  
3.3  
C = 50pF, V = 3.3V, V = 0V  
V
OLP  
OL  
L
IH  
IL  
2.5  
3.3  
2.5  
C = 30pF, V = 2.5V, V = 0V  
0.6  
L
IH  
IL  
V
Quiet Output Dynamic Valley V  
C = 50pF, V = 3.3V, V = 0V  
–0.8  
–0.6  
V
OLV  
OL  
L
IH  
IL  
C = 30pF, V = 2.5V, V = 0V  
L
IH  
IL  
Capacitance  
Symbol  
Parameter  
Conditions  
Typical  
Units  
pF  
C
Input Capacitance  
V
= Open, V = 0V or V  
CC  
7
8
IN  
CC  
CC  
CC  
I
C
Output Capacitance  
V
V
= 3.3V, V = 0V or V  
CC  
pF  
OUT  
I
C
Power Dissipation Capacitance  
= 3.3V, V = 0V or V , f = 10MHz  
25  
pF  
PD  
I
CC  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
5
AC Loading and Waveforms (Generic for LCX Family)  
Test  
Switch  
t
t
, t  
Open  
PLH PHL  
, t  
6V at V = 3.3 0.3V  
PZL PLZ  
CC  
V
x 2 at V = 2.5 0.2V  
CC  
CC  
t
, t  
GND  
PZH PHZ  
Figure 1. AC Test Circuit (C includes probe and jig capacitance)  
L
3-STATE Output High Enable and  
Waveform for Inverting and Non-Inverting Functions  
Disable Times for Logic  
Setup Time, Hold Time and Recovery Time for Logic  
Propagation Delay. Pulse Width and t Waveforms  
rec  
3-STATE Output Low Enable and  
Disable Times for Logic  
t
and t  
fall  
rise  
V
CC  
Symbol  
3.3V 0.3V  
1.5V  
2.7V  
1.5V  
1.5V  
2.5V 0.2V  
V
V
V
/ 2  
/ 2  
mi  
CC  
CC  
V
1.5V  
mo  
V
V
+ 0.3V  
– 0.3V  
V
+ 0.3V  
V
+ 0.15V  
– 0.15V  
x
y
OL  
OL  
OL  
V
V
V
– 0.3V  
V
OH  
OH  
OH  
Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns)  
r
f
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
6
Schematic Diagram (Generic for LCX Family)  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
7
Physical Dimensions  
13.00  
12.60  
A
11.43  
20  
11  
B
9.50  
10.65 7.60  
10.00 7.40  
2.25  
1
PIN ONE  
INDICATOR  
10  
0.65  
0.51  
0.35  
1.27  
1.27  
M
0.25  
C B A  
LAND PATTERN RECOMMENDATION  
SEE DETAIL A  
2.65 MAX  
0.33  
0.20  
C
0.10  
C
0.30  
0.10  
SEATING PLANE  
0.75  
0.25  
X 45°  
NOTES: UNLESS OTHERWISE SPECIFIED  
(R0.10)  
(R0.10)  
A) THIS PACKAGE CONFORMS TO JEDEC  
MS-013, VARIATION AC, ISSUE E  
GAGE PLANE  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C) DIMENSIONS DO NOT INCLUDE MOLD  
FLASH OR BURRS.  
0.25  
8°  
0°  
D) CONFORMS TO ASME Y14.5M-1994  
1.27  
0.40  
SEATING PLANE  
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L  
F) DRAWING FILENAME: MKT-M20BREV3  
(1.40)  
DETAIL A  
SCALE: 2:1  
Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
8
Physical Dimensions (Continued)  
Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
9
Physical Dimensions (Continued)  
Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
10  
Physical Dimensions (Continued)  
Figure 6. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
11  
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR  
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which, (a) are intended for surgical implant into the body or  
(b) support or sustain life, and (c) whose failure to perform  
when properly used in accordance with instructions for use  
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device, or system whose failure to perform can be  
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PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
This datasheet contains the design specifications for product  
development. Specifications may change in any manner without notice.  
Advance Information  
Formative or In Design  
This datasheet contains preliminary data; supplementary data will be  
published at a later date. Fairchild Semiconductor reserves the right to  
make changes at any time without notice to improve design.  
Preliminary  
First Production  
Full Production  
Not In Production  
This datasheet contains final specifications. Fairchild Semiconductor  
reserves the right to make changes at any time without notice to improve  
the design.  
No Identification Needed  
Obsolete  
This datasheet contains specifications on a product that has been  
discontinued by Fairchild Semiconductor. The datasheet is printed for  
reference information only.  
Rev. I33  
©1994 Fairchild Semiconductor Corporation  
74LCX240 Rev. 1.6.0  
www.fairchildsemi.com  
12  
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