74LCX74MTCX [ONSEMI]
低压双通道D型正边沿触发式触发器，带5V容差输入;
| 型号： | 74LCX74MTCX |
| 厂家： | 
ONSEMI |
| 描述： | 低压双通道D型正边沿触发式触发器，带5V容差输入 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：980K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
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December 2013
74LCX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop with 5V Tolerant Inputs
Features
General Description
■ 5V tolerant inputs
The LCX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
■ 2.3V–3.6V V specifications provided
CC
■ 7.0ns t max. (V = 3.3V), 10µA I max.
PD
CC
CC
■ Power down high impedance inputs and outputs
24mA output drive (V = 3.0V)
■
CC
■ Implements proprietary noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
Asynchronous Inputs:
– Human body model > 2000V
■ LOW input to S (Set) sets Q to HIGH level
D
– Machine model > 200V
■ LOW input to C (Clear) sets Q to LOW level
D
■ Leadless Pb-Free DQFN package
■ Clear and Set are independent of clock
■ Simultaneous LOW on C and S makes both Q
D
D
and Q HIGH
Ordering Information
Package
Order Number
Number
Package Description
74LCX74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
74LCX74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
(1)
74LCX74BQX
MLP14A
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 3.0mm
74LCX74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
Connection Diagrams
Logic Symbols
Pin Assignments for SOIC, SOP, and TSSOP
IEEE/IEC
Pad Assignment for DQFN
Truth Table
(Each Half)
(Bottom View)
(Top View)
Inputs
Outputs
S
C
CP
D
Q
Q
L
D
D
L
H
X
X
X
X
X
X
H
L
H
L
Pin Description
H
L
L
L
H
H
L
Pin Names
Description
H
H
L
D , D
Data Inputs
H
H
H
H
H
H
1
2
CP , CP
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
H
Q
1
2
C
, C
D2
L
X
Q
0
D1
0
S
, S
D2
D1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Q , Q , Q , Q
1
1
2
2
DAP
No Connect
Note: DAP (Die Attach Pad)
= LOW-to-HIGH Clock Transition
Q (Q ) = Previous Q(Q) before LOW-to-HIGH Transition
0
0
of Clock
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
Supply Voltage
–0.5V to +7.0V
–0.5V to +7.0V
CC
V
DC Input Voltage
I
(2)
V
DC Output Voltage, Output in HIGH or LOW State
–0.5V to V + 0.5V
O
IK
CC
I
DC Input Diode Current, V < GND
–50mA
I
I
DC Output Diode Current
OK
V
< GND
–50mA
+50mA
O
V
> V
CC
O
I
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50mA
O
I
100mA
CC
I
100mA
GND
T
–65°C to +150°C
STG
Note:
2. I Absolute Maximum Rating must be observed.
O
(3)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Units
V
Supply Voltage
Operating
CC
2.0
1.5
0
3.6
3.6
5.5
V
Data Retention
Input Voltage
V
V
V
I
V
Output Voltage, HIGH or LOW State
Output Current
0
V
CC
O
I
/ I
OH OL
V
V
V
= 3.0V–3.6V
= 2.7V–3.0V
= 2.3V–2.7V
24
12
8
mA
CC
CC
CC
T
Free-Air Operating Temperature
Input Edge Rate, V = 0.8V–2.0V, V = 3.0V
–40
0
85
10
°C
A
∆t / ∆V
ns/V
IN
CC
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
3
DC Electrical Characteristics
T = –40°C to +85°C
A
Symbol
Parameter
V
(V)
Conditions
Min.
1.7
Max.
Units
CC
V
HIGH Level Input Voltage
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
V
IH
2.0
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
V
V
IL
V
I
I
I
I
I
I
I
I
I
I
= –100µA
= –8mA
= –12mA
= –18mA
= –24mA
= 100µA
= 8mA
V
– 0.2
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
CC
1.8
2.2
2.4
2.2
2.7
3.0
V
LOW Level Output Voltage
2.3–3.6
2.3
0.2
0.6
0.4
0.4
0.55
5.0
10
V
OL
2.7
= 12mA
= 16mA
= 24mA
3.0
I
Input Leakage Current
2.3–3.6
0
0 ≤ V ≤ 5.5V
µA
µA
µA
I
I
I
Power-Off Leakage Current
Quiescent Supply Current
V or V = 5.5V
I O
OFF
I
2.3–3.6
V = V or GND
10
CC
I
CC
3.6V ≤ V ≤ 5.5V
10
I
∆I
Increase in I per Input
2.3–3.6
V
= V – 0.6V
500
µA
CC
CC
IH
CC
AC Electrical Characteristics
T = –40°C to +85°C, R = 500Ω
A
L
V
= 3.3V 0.3V,
V
= 2.7V,
V = 2.5V 0.2V,
CC
CC
CC
C = 50pF
C = 50pF
C = 30pF
L
L
L
Symbol
Parameter
Maximum Clock Frequency
Propagation Delay,
Min.
150
1.5
Max.
Min. Max.
Min.
150
1.5
Max.
Units
MHz
ns
f
150
MAX
t
t
, t
7.0
7.0
1.5
8.0
8.0
8.4
8.4
PHL PLH
CP to Q or Q
n
n
n
, t
Propagation Delay,
or S to Q or Q
n
1.5
1.5
1.5
ns
PHL PLH
C
Dn
Dn
n
t
Setup Time
Hold Time
2.5
1.5
3.3
3.3
2.5
2.5
1.5
3.3
3.6
3.0
4.0
2.0
4.0
4.0
4.5
ns
ns
ns
ns
ns
ns
S
t
H
t
t
Pulse Width CP
W
W
Pulse Width and C , S
D
D
t
Recovery Time
REC
(4)
t
, t
Output to Output Skew
1.0
OSHL OSLH
Note:
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSHL
OSLH
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
4
Dynamic Switching Characteristics
T = 25°C
A
Symbol
Parameter
V
(V)
Conditions
Typical
0.8
Unit
CC
V
Quiet Output Dynamic Peak V
3.3
C = 50pF, V = 3.3V, V = 0V
V
OLP
OL
L
IH
IL
2.5
3.3
2.5
C = 30pF, V = 2.5V, V = 0V
0.6
L
IH
IL
V
Quiet Output Dynamic Valley V
C = 50pF, V = 3.3V, V = 0V
–0.8
–0.6
V
OLV
OL
L
IH
IL
C = 30pF, V = 2.5V, V = 0V
L
IH
IL
Capacitance
Symbol
Parameter
Conditions
Typical
Units
pF
C
Input Capacitance
V
= Open, V = 0V or V
CC
7
8
IN
CC
CC
CC
I
C
Output Capacitance
V
V
= 3.3V, V = 0V or V
CC
pF
OUT
I
C
Power Dissipation Capacitance
= 3.3V, V = 0V or V , f = 10MHz
25
pF
PD
I
CC
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
5
AC Loading and Waveforms (Generic for LCX Family)
Test
Switch
t
t
, t
Open
PLH PHL
, t
6V at V = 3.3 0.3V
PZL PLZ
CC
V
x 2 at V = 2.5 0.2V
CC
CC
t
, t
GND
PZH PHZ
Figure 1. AC Test Circuit (C includes probe and jig capacitance)
L
3-STATE Output Low Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and t Waveforms
rec
3-STATE Output High Enable and
Disable Times for Logic
t
and t
fall
rise
V
CC
Symbol
3.3V 0.3V
1.5V
2.7V
1.5V
1.5V
2.5V 0.2V
V
V
V
/ 2
/ 2
mi
CC
CC
V
1.5V
mo
V
V
+ 0.3V
– 0.3V
V
+ 0.3V
V
+ 0.15V
– 0.15V
x
y
OL
OL
OL
V
V
V
– 0.3V
V
OH
OH
OH
Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns)
r
f
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
6
Schematic Diagram (Generic for LCX Family)
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
7
Tape and Reel Specification
Tape Format for DQFN
Package Designator
Tape Section
Number of Cavities
125 (Typ.)
Cavity Status
Empty
Cover Tape Status
Sealed
BQX
Leader (Start End)
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (Typ.)
Empty
Sealed
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
12mm
13.0 (330.0)
0.059 (1.50)
0.512 (13.00) 0.795 (20.20) 2.165 (55.00)
0.488 (12.4)
0.724 (18.4)
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
8
0.65
A
ꢀꢁꢂꢂꢂꢁꢃꢂ
0.43TYP
14
8
B
6.4
ꢄꢁꢄꢂꢂꢁꢃꢂ
6.10
3.2
1.65
0.2 C B A
ALL LEAD TIPS
1
7
PIN#1 IDENT
TOP VIEW
0.45
RECOMMENDED LAND PATTERN
SEE DETAIL A
1.2 MAX
+0.15
-0.10
0.90
0.20
0.09
ꢂꢁꢃꢂꢂꢁꢂꢀ
0.30
0.19
ALL LEAD TIPS
C
0.1 C
0.13
A B
C
0.65
ꢃꢅꢁꢂꢂꢆ723ꢆꢇꢆ%27720
FRONT VIEW
0.09 MIN
NOTES:
GAGE PLANE
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
0.25
0.09 MIN
ꢂꢉꢆꢊ
ꢂꢁꢈꢂꢁꢃ
1.00
SEATING PLANE
DETAIL A
E. LANDPATTERN STANDARD: SOP65P640X110-14M.
F. DRAWING FILE NAME: MKT-MTC14rev7.
8.75
8.50
A
0.65
7.62
14
8
14
8
B
4.00
3.80
5.60
6.00
1.70
1
7
PIN #1
IDENT.
1
7
1.27
0.51
0.35
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
TOP VIEW
1.75 MAX
A
0.25
0.19
C
0.10 C
NOTES:
1.50
1.25
0.25
0.10
SIDE VIEW
FRONT VIEW
A. CONFORMS TO JEDEC MS-012,
VARIATION AB, ISSUE C
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS
0.50
0.25
x 45
R0.10
GAGE
PLANE
D. LAND PATTERN STANDARD:
SOIC127P600X145-14M
R0.10
E. CONFORMS TO ASME Y14.5M, 2009
D. DRAWING FILENAME: MKT-M14Arev14
0.36
8°
0°
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE 16 : 1
4.00 MAX
2.20 MAX
1.40 MAX
B
3.00
0.05 C
A
2X
1.00
MAX
1.70
MAX
2.50
0.50 TYP
3.50
MAX
(0.90)
0.05 C
TOP VIEW
2X
PIN #1 QUADRANT
0.50 TYP
0.24 TYP
ꢀꢁꢈꢀꢀꢁꢀꢃ
RECOMMENDED LAND PATTERN
0.10 C
ꢀꢁꢂꢀꢀꢁꢀꢃ
0.08 C
ꢀꢁꢀꢂꢃꢀꢁꢀꢂꢃ
C
SIDE VIEW
SEATING
PLANE
ꢄꢁꢀꢀꢀꢁꢀꢃ
ꢅꢁꢆꢃꢀꢁꢀꢃ
ꢀꢁꢄꢇꢀꢀꢁꢀꢃ
(14X)
A. CONFORMS TO JEDEC REGISTRATION
MO-241, VARIATION AA
PIN #1 IDENT
0.50
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
ꢅꢁꢅꢃꢀꢁꢀꢃ
ꢂꢁꢃꢀꢀꢁꢀꢃ
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP14Arev2.
ꢀꢁꢂꢃꢀꢁꢀꢃ
(14X)
0.50
0.10
0.05
C A B
C
2.00
BOTTOM VIEW
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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