74LVC540A [ONSEMI]
Low-Voltage CMOS Octal Buffer Flow Through Pinout;
| 型号： | 74LVC540A |
| 厂家： | 
ONSEMI |
| 描述： | Low-Voltage CMOS Octal Buffer Flow Through Pinout |
| 文件： | 总9页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC540A
Low-Voltage CMOS
Octal Buffer
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Inverting)
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MARKING
The 74LVC540A is a high performance, inverting octal buffer
operating from a 1.2 to 3.6 V supply. This device is similar in function
to the MC74LCX240, while providing flow through architecture.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
DIAGRAMS
20
20
1
LVC540A
switching noise performance. A V specification of 5.5 V allows
AWLYYWWG
I
SOIC−20 WB
DW SUFFIX
CASE 751D
74LVC540A inputs to be safely driven from 5 V devices. The
74LVC540A is suitable for memory address driving and all TTL level
bus oriented transceiver applications.
1
Current drive capability is 24 mA at the outputs. The Output Enable
(OE1, OE2) inputs, when HIGH, disables the outputs by placing them
in a HIGH Z condition.
20
20
LVC
540A
ALYW G
G
1
Features
TSSOP−20
DT SUFFIX
CASE 948E
• Designed for 1.2 to 3.6 V V Operation
CC
1
• 5 V Tolerant − Interface Capability With 5 V TTL Logic
• Supports Live Insertion and Withdrawal
A
= Assembly Location
= Year
• I
Specification Guarantees High Impedance When V = 0 V
CC
L, WL = Wafer Lot
OFF
Y, YY
• 24 mA Output Sink and Source Capability
W, WW = Work Week
• Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 250 mA
G or G = Pb−Free Package
(Note: Microdot may be in either location)
• ESD Performance:
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
♦ Human Body Model > 2000 V
♦ Machine Model > 200 V
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
December, 2015 − Rev. 0
74LVC540A/D
74LVC540A
1
OE1
OE2
19
V
OE2 O0
O1
17
O2
16
O3
15
O4
14
O5
13
O6
12
O7
11
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
CC
D0
O0
O1
O2
O3
O4
O5
O6
O7
20
19
18
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
9
8
10
OE1 D0
D1
D2
D3
D4
D5
D6
D7 GND
Figure 1. Pinout: 20−Lead (Top View)
PIN NAMES
Pins
OEn
Dn
Function
Output Enable Inputs
Data Inputs
On
3−State Outputs
Figure 2. Logic Diagram
TRUTH TABLE
Inputs
Outputs
OE1
L
OE2
L
Dn
L
On
H
L
L
L
H
X
X
H
Z
H
X
X
Z
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High or Low Voltage Level and Transitions are Acceptable
For I reasons, DO NOT FLOAT Inputs
CC
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2
74LVC540A
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
V
V
CC
DC Supply Voltage
−0.5 to +6.5
V
I
DC Input Voltage
−0.5 ≤ V ≤ +6.5
V
I
V
O
DC Output Voltage
−0.5 ≤ V ≤ +6.5
Output in 3−State
V
O
−0.5 ≤ V ≤ V + 0.5
Output in HIGH or LOW State
(Note 1)
V
O
CC
I
DC Input Diode Current
DC Output Diode Current
−50
V < GND
mA
mA
mA
mA
mA
mA
°C
IK
I
I
−50
+50
50
V < GND
O
OK
V
O
> V
CC
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
O
I
100
100
CC
I
GND
T
−65 to +150
STG
T
L
Lead Temperature, 1 mm from Case for
10 Seconds
T = 260
L
°C
T
Junction Temperature Under Bias
Thermal Resistance (Note 2)
T = 135
°C
J
J
q
SOIC = 65.8
TSSOP = 110.7
°C/W
JA
MSL
Moisture Sensitivity
Level 1
250
I
Latch−up Performance at V = 3.6 V
mA
LATCHUP
CC
and 125°C (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I absolute maximum rating must be observed.
O
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
3. Tested to EIA/JES078.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage
Operating
Functional
V
1.65
1.2
3.6
3.6
V
Input Voltage
0
5.5
V
V
I
V
O
Output Voltage
HIGH or LOW State
3−State
0
0
V
CC
5.5
I
HIGH Level Output Current
mA
mA
OH
V
CC
V
CC
= 3.0 V − 3.6 V
= 2.7 V − 3.0 V
−24
−12
I
LOW Level Output Current
OL
V
CC
V
CC
= 3.0 V − 3.6 V
= 2.7 V − 3.0 V
24
12
T
Operating Free−Air Temperature
Input Transition Rise or Fall Rate, V from 0.8 V to 2.0 V, V = 3.0 V
−40
0
+125
10
°C
A
Dt/DV
ns/V
IN
CC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
74LVC540A
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
−405C to +1255C
Typ
Typ
(Note 4)
(Note 4)
Min
Max
−
Min
Max
−
Symbol
Parameter
Conditions
= 1.2 V
Unit
VIH
HIGH−level input
voltage
V
1.08
−
−
1.08
−
−
V
CC
V
CC
= 1.65 V to 1.95 V
0.65 x
VCC
−
0.65 x
VCC
−
V
V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
1.7
2.0
−
−
−
−
−
−
−
1.7
2.0
−
−
−
−
−
−
−
CC
CC
V
LOW−level input
voltage
V
CC
= 1.2 V
0.12
0.35 x
0.12
V
V
IL
V
CC
= 1.65 V to 1.95 V
−
−
0.35 x
VCC
V
CC
V
V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
−
−
−
−
0.7
0.8
−
−
−
−
0.7
0.8
CC
CC
V
OH
HIGH−level output
voltage
V = V or V
I
IH
IL
I
= −100 mA;
V
−
−
−
V −
CC
−
−
O
CC
V
= 1.65 V to 3.6 V
0.2
1.2
1.8
2.2
2.4
2.2
0.3
CC
I
= −4 mA; V = 1.65 V
−
−
−
−
−
−
−
−
−
−
1.05
1.65
2.05
2.25
2.0
−
−
−
−
−
−
−
−
−
−
O
CC
I
= −8 mA; V = 2.3 V
CC
O
I
I
I
= −12 mA; V = 2.7 V
CC
O
O
O
= −18 mA; V = 3.0 V
CC
= −24 mA; V = 3.0 V
CC
VOL
LOW−level output
voltage
V = V or V
IL
V
I
IH
I
O
= 100 mA;
−
−
0.2
−
−
0.3
V
CC
= 1.65 V to 3.6 V
I
= 4 mA; V = 1.65 V
−
−
−
−
−
−
−
0.45
0.6
0.4
0.55
5
−
−
−
−
−
−
−
0.65
0.8
0.6
0.8
20
O
CC
I
= 8 mA; V = 2.3 V
−
−
O
CC
I
O
= 12 mA; V = 2.7 V
−
−
CC
I
O
= −24 mA; V = 3.0 V
−
−
CC
II
Input leakage current
V = 5.5V or GND V = 3.6 V
0.1
0.1
0.1
0.1
mA
mA
I
CC
I
OFF−state output
current
VI = VIH or VIL;
5
20
OZ
V
O
= 5.5 V or GND; V = 3.6 V
CC
I
Power−off leakage
current
V or V = 5.5 V; V = 0.0 V
−
−
−
0.1
0.1
5
10
10
−
−
−
0.1
0.1
5
20
40
mA
mA
mA
OFF
I
O
CC
I
Supply current
V = V or GND; I = 0 A;
I CC O
CC
V
CC
= 3.6 V
DI
Additional supply
current
per input pin;
V = V − 0.6 V; I = 0 A;
500
5000
CC
I
CC
O
V
CC
= 2.7 V to 3.6 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. All typical values are measured at T = 25°C and V = 3.3 V, unless stated otherwise.
A
CC
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4
74LVC540A
AC ELECTRICAL CHARACTERISTICS (t = t = 2.5 ns)
R
F
−405C to +855C
Min
Typ5
Max
Typ5
Symbol
Parameter
Conditions
Unit
t
Propagation Delay (Note 6)
nDn to nOn
V
= 1.2 V
−
18.0
−
−
−
−
−
ns
pd
CC
V
= 1.65 V to 1.95 V
1.0
1.0
1.0
1.0
−
16.4
7.8
7.1
5.3
−
1.0
1.0
1.0
1.0
−
−
16.4
7.8
7.1
5.3
−
CC
V
= 2.3 V to 2.7 V
−
−
CC
V
CC
= 2.7 V
−
−
V
= 3.0 V to 3.6 V
= 1.2 V
−
−
CC
t
en
Enable Time (Note 7)
nOE to nOn
V
CC
20.0
−
−
ns
ns
ns
V
CC
= 1.65 V to 1.95 V
1.0
1.0
1.0
1.0
−
16.5
10.5
8.0
6.6
−
1.0
1.0
1.0
1.0
−
−
16.5
10.5
8.0
6.6
−
V
= 2.3 V to 2.7 V
−
−
CC
V
CC
= 2.7 V
−
−
V
= 3.0 V to 3.6 V
= 1.2 V
−
−
CC
t
dis
Disable Time (Note 8)
nOE to nOn
V
CC
18.0
−
−
V
CC
= 1.65 V to 1.95 V
1.0
1.0
1.0
1.0
−
15.9
9.0
8.2
7.4
1.0
1.0
1.0
1.0
1.0
−
−
15.9
9.0
8.2
7.4
1.5
V
= 2.3 V to 2.7 V
−
−
CC
V
CC
= 2.7 V
−
−
V
= 3.0 V to 3.6 V
−
−
CC
t
Output Skew Time (Note 9)
−
−
sk(0)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
6. t is the same as t
and t
.
pd
PLH
PHL
7. t is the same as t
and t
.
en
PZL
PZH
8. t is the same as t
and t
.
dis
PLZ
PHZ
9. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= +25°C
Min
Typ
Max
Symbol
Characteristic
Condition
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
Unit
V
OLP
Dynamic LOW Peak Voltage (Note 10)
V
CC
V
CC
0.8
0.6
V
L
IH
IL
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
V
OLV
Dynamic LOW Valley Voltage (Note
10)
V
CC
V
CC
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
−0.8
−0.6
V
L
IH
IL
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
10.Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Condition
= 3.3 V, V = 0 V or V
Typical
5.0
Unit
pF
CIN
V
V
CC
I
CC
CC
COUT
CPD
Output Capacitance
= 3.3 V, V = 0 V or V
7.0
pF
CC
I
Power Dissipation Capacitance
(Note 11)
Per input; V = GND or V
pF
I
CC
V
= 1.65 V to 1.95 V
7.7
11.3
14.4
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
11. C is used to determine the dynamic power dissipation (P in mW).
PD
D
2
2
P
= C * V
x fi * N + S (C x V
x fo) where:
D
PD
CC
L
CC
fi = input frequency in MHz; fo = output frequency in MHz
C = output load capacitance in pF V = supply voltage in Volts
L
CC
N = number of outputs switching
2
S(C * V
x fo) = sum of the outputs.
L
CC
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5
74LVC540A
2.7 V
0 V
1.5 V
1.5 V
Dn
t
t
PLH
PHL
V
OH
OL
1.5 V
1.5 V
On
V
WAVEFORM 1 - PROPAGATION DELAYS
t
R
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
F W
2.7 V
0 V
1.5 V
OEn
t
t
PHZ
PZH
V
V
CC
- 0.3 V
OH
1.5 V
On
≈ 0 V
t
t
PLZ
PZL
≈ 3.0 V
1.5 V
On
V + 0.3 V
OL
GND
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
t
R
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
F W
Figure 3. AC Waveforms
V
CC
Symbol 3.3 V 0.3 V
2.7 V
1.5 V
1.5 V
V
CC
< 2.7 V
Vmi
1.5 V
1.5 V
V
CC
/2
/2
Vmo
V
CC
V
V
+ 0.3 V
− 0.3 V
V
+ 0.3 V
V
OL
+ 0.15 V
− 015 V
HZ
OL
OL
V
V
OH
V
OH
− 0.3 V
V
OH
LZ
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6
74LVC540A
V
CC
V
EXT
V
I
V
O
OPEN
GND
R
1
PULSE
GENERATOR
DUT
R
T
C
R
L
L
C includes jig and probe capacitance
L
R = Z
T
of pulse generator (typically 50 W)
OUT
R = R
1
L
Supply Voltage
Input
Load
V
EXT
V
CC
(V)
V
I
t , t
C
R
t
, t
t
, t
t
, t
r
f
L
L
PLH PHL
PLZ PZL
PHZ PZH
1.2
V
V
V
≤ 2 ns
≤ 2 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 kW
1 kW
Open
Open
Open
Open
Open
2 x V
GND
CC
CC
1.65 − 1.95
2.3 − 2.7
2.7
2 x V
GND
GND
GND
GND
CC
CC
CC
≤ 2 ns
500 W
500 W
500 W
2 x V
CC
2.7 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
2 x V
CC
3 − 3.6
2 x V
CC
Figure 4. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
74LVC540ADWR2G
SOIC−20
(Pb−Free)
1000 / Tape & Reel
2500 / Tape & Reel
74LVC540ADTR2G
TSSOP−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
74LVC540A
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
20X K REF
K
M
S
S
V
0.10 (0.004)
T
U
S
T U
K1
0.15 (0.006)
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
S
0.15 (0.006)
T U
DETERMINED AT DATUM PLANE −W−.
A
−V−
N
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
C
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
J
J1
K
G
D
H
DETAIL E
K1
L
0.100 (0.004)
−T− SEATING
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
74LVC540A
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE G
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
20X B
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
A1
C
q
T
_
_
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
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74LVC540A/D
相关型号：
74LVC540AT20-13
Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO20, 6.40 X 6.50 MM, 1.20 MM HEIGHT, 0.65 MM PITCH, GREEN, TSSOP-20
DIODES
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