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January 1999

Revised June 2005

74LVT16374 • 74LVTH16374

Low Voltage 16-Bit D-Type Flip-Flop

with 3-STATE Outputs

General Description

Features

■ Input and output interface capability to systems at

The LVT16374 and LVTH16374 contain sixteen non-invert-

ing D-type flip-flops with 3-STATE outputs and is intended

for bus oriented applications. The device is byte controlled.

A buffered clock (CP) and Output Enable (OE) are com-

mon to each byte and can be shorted together for full 16-bit

operation.

5V V_CC

■ Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16374),

also available without bushold feature (74LVT16374)

■ Live insertion/extraction permitted

The LVTH16374 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

■ Power Up/Power Down high impedance provides

glitch-free bus loading

■ Outputs source/sink 32 mA/ 64 mA

■ Functionally compatible with the 74 series 16374

■ Latch-up performance exceeds 500 mA

■ ESD performance:

These flip-flops are designed for low-voltage (3.3V) V_CC

applications, but with the capability to provide a TTL inter-

face to a 5V environment. The LVT16374 and LVTH16374

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Human-body model 2000V

Machine model 200V

Charged-device model 1000V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Order Number

Package Number

Package Description

74LVT16374G

BGA54A

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

(Note 1)(Note 2)

(Preliminary)

74LVT16374MEA

(Note 2)

MS48A

MTD48

BGA54A

MS48A

MTD48

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVT16374MTD

(Note 2)

74LVTH16374G

(Note 1)(Note 2)

74LVTH16374MEA

(Note 2)

74LVTH16374MTD

(Note 2)

Note 1: Ordering code “G” indicates Trays.

Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

DS012022

www.fairchildsemi.com

Connection Diagrams

Pin Descriptions

Pin Assignment for SSOP and TSSOP

Pin Names

Description

OE_n

Output Enable Input (Active LOW)

Clock Pulse Input

Inputs

CP_n

I₀–I₁₅

O₀–O₁₅

NC

3-STATE Outputs

No Connect

FBGA Pin Assignments

1

2

3

4

5

6

A

B

C

D

E

F

O₀

O₂

NC

O₁

OE₁

NC

CP₁

NC

I₁

I₀

I₂

O₄

O₃

V_CC

GND

V_CC

NC

V_CC

GND

V_CC

NC

I₃

I₄

O₆

O₅

I₅

I₆

O₈

O₇

I₇

I₈

O₁₀

O₁₂

O₁₄

O₉

I₉

I₁₀

I₁₂

I₁₄

G

H

O₁₁

O₁₃

I₁₁

I₁₃

J

O₁₅

NC

OE₂

CP₂

NC

I₁₅

Truth Tables

Inputs

Outputs

CP₁

OE₁

I₀–I₇

O₀–O₇

Pin Assignment for FBGA

L

H

L

H

L

X

O_o

Z

X

H

Inputs

OE₂

Outputs

CP₂

I₈–I₁₅

O₈–O₁₅

L

H

L

H

L

X

O_o

Z

(Top Thru View)

X

H

L

X

Z

O

HIGH Voltage Level

LOW Voltage Level

Immaterial

HIGH Impedance

Previous O before HIGH to LOW of CP

o

Functional Description

The LVT16374 and LVTH16374 consist of sixteen

edge-triggered flip-flops with individual D-type inputs and

3-STATE true outputs. The device is byte controlled with

each byte functioning identically, but independent of the

other. The control pins can be shorted together to obtain

full 16-bit operation. Each byte has a buffered clock and

buffered Output Enable common to all flip-flops within that

byte. The description which follows applies to each byte.

Each flip-flop will store the state of their individual D-type

inputs that meet the setup and hold time requirements on

the LOW-to-HIGH Clock (CP_n) transition. With the Output

Enable (OE_n) LOW, the contents of the flip-flops are avail-

able at the outputs. When OE_nis HIGH, the outputs go to

the high impedance state. Operation of the OE_ninput does

not affect the state of the flip-flops.

www.fairchildsemi.com

2

Logic Diagrams

Byte 1 (0:7)

Byte 2 (8:15)

Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.

3

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Absolute Maximum Ratings(Note 3)

Symbol

V_CC

V_I

Parameter

Supply Voltage

Value

0.5 to 4.6

0.5 to 7.0

50

Conditions

Units

V

DC Input Voltage

V_O

DC Output Voltage

Output in 3-STATE

V

Output in High or Low State (Note 4)

V_IGND

I_IK

I_OK

I_O

DC Input Diode Current

DC Output Diode Current

DC Output Current

mA

50

V_OGND

64

V_OV_CCOutput at High State

V_OV_CCOutput at Low State

mA

128

I_CC

DC Supply Current per Supply Pin

DC Ground Current per Ground Pin

Storage Temperature

64

mA

C

I_GND

T_STG

128

65 to 150

Recommended Operating Conditions

Symbol

V_CC

V_I

Parameter

Min

2.7

0

Max

3.6

5.5

32

Units

Supply Voltage

V

Input Voltage

I_OH

High-Level Output Current

Low-Level Output Current

mA

C

I_OL

64

T_A

Free-Air Operating Temperature

40

0

85

t/ V

Input Edge Rate, V_IN0.8V–2.0V, V_CC3.0V

10

ns/V

Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.

Note 4: I Absolute Maximum Rating must be observed.

O

DC Electrical Characteristics

V

T

40 C to 85 C

CC

A

Symbol

Parameter

Units

Conditions

(V)

2.7

Min

Max

V

Input Clamp Diode Voltage

1.2

V

I

18 mA

0.1V or

IK

I

Input HIGH Voltage

Input LOW Voltage

Output HIGH Voltage

2.7–3.6

2.7

2.0

V

IH

IL

O

0.8

V

0.1V

A

O

CC

V

0.2

I

100

OH

CC

OH

OL

2.4

2.0

V

8 mA

3.0

32 mA

V

Output LOW Voltage

2.7

0.2

0.5

100 A

OL

2.7

24 mA

16 mA

32 mA

64 mA

0.8V

3.0

0.4

3.0

0.5

3.0

0.55

I

Bushold Input Minimum Drive

75

V

I(HOLD)

I

3.0

A

(Note 5)

2.0V

I

Bushold Input Over-Drive

Current to Change State

Input Current

500

(Note 6)

(Note 7)

I(OD)

(Note 5)

I

3.6

10

1

V

5.5V

0V or V

0V

I

Control Pins

Data Pins

CC

A

5

3.6

0

1

V

CC

I

Power Off Leakage Current

Power Up/Down 3-STATE

Output Current

100

A

0V V or V

5.5V

OFF

I

O

V

0.5V to 3.0V

PU/PD

O

I

0–1.5V

100

GND or V

0.5V

CC

I

3-STATE Output Leakage Current

3.6

5

A

OZL

OZH

O

CC

3.0V

10

V

5.5V

O

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4

DC Electrical Characteristics (Continued)

V

T

40 C to 85 C

CC

A

Symbol

Parameter

Power Supply Current

Units

Conditions

Outputs HIGH

(V)

3.6

Min

Max

0.19

5

I

mA

CCH

Power Supply Current

Outputs LOW

CCL

CCZ

0.19

Outputs Disabled

V

5.5V,

Outputs Disabled

One Input at V

CC

O

I

Increase in Power Supply Current

(Note 8)

3.6

0.2

mA

0.6V

CC

Other Inputs at V or GND

CC

Note 5: Applies to bushold versions only (74LVTH16374).

Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.

Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.

Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.

CC

Dynamic Switching Characteristics (Note 9)

V

T

25 C

Typ

Conditions

CC

A

Symbol

Parameter

Units

C

50 pF, R

500

(V)

3.3

Min

Max

L

V

Quiet Output Maximum Dynamic V

0.8

V

(Note 10)

OLP

OL

Quiet Output Minimum Dynamic V

OLV

OL

Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.

Note 10: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.

AC Electrical Characteristics

T

40 C to 85 C, C

3.3V 0.3V

Max

50 pF, R

L

500

2.7V

A

L

Symbol

Parameter

V

Units

CC

Min

160

1.9

1.6

1.3

1.0

1.5

2.0

1.8

0.8

3.0

Min

160

1.9

1.6

1.3

1.0

1.5

2.0

0.1

3.0

Max

f

t

Maximum Clock Frequency

Propagation Delay

CP to O

MHz

ns

MAX

4.3

4.5

4.4

4.5

4.6

5.0

4.6

5.2

5.0

5.4

4.8

5.4

PHL

PLH

PZL

PZH

PLZ

PHZ

S

n

Output Enable Time

ns

Output Disable Time

Setup Time

ns

Hold Time

H

Pulse Width

W

Output to Output Skew (Note 11)

1.0

OSHL

OSLH

ns

Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

) or LOW-to-HIGH (t

).

OSLH

OSHL

Capacitance (Note 12)

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions

Typical

Units

pF

C

V

Open, V 0V or V

4

8

IN

CC

I

CC

C

3.0V, V

0V or V

pF

OUT

CC

O

Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.

5

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Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA54A

www.fairchildsemi.com

6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS48A

7

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

8

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

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1


型号：	74LVT16374MTDX
厂家：	ONSEMI
描述：	带 3 态输出的低电压 16 位 D 型触发器驱动信息通信管理光电二极管逻辑集成电路触发器
文件：	总10页 (文件大小：218K)
中文：	中文翻译
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