74LVTH125MTC [ONSEMI]

带 3 态输出的低压四路缓冲器;
74LVTH125MTC
型号: 74LVTH125MTC
厂家: ONSEMI    ONSEMI
描述:

带 3 态输出的低压四路缓冲器

驱动 信息通信管理 光电二极管 逻辑集成电路
文件: 总9页 (文件大小:377K)
中文:  中文翻译
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January 2008  
74LVTH125  
Low Voltage Quad Buffer with 3-STATE Outputs  
Features  
General Description  
Input and output interface capability to systems at  
The LVTH125 contains four independent non-inverting  
buffers with 3-STATE outputs.  
5V V  
CC  
Bushold data inputs eliminate the need for external  
These buffers are designed for low-voltage (3.3V) V  
CC  
pull-up resistors to hold unused inputs  
applications, but with the capability to provide a TTL  
interface to a 5V environment. The LVTH125 is fabri-  
cated with an advanced BiCMOS technology to achieve  
high speed operation similar to 5V ABT while maintain-  
ing a low power dissipation.  
Live insertion/extraction permitted  
Power Up/Down high impedance provides glitch-free  
bus loading  
Outputs source/sink –32mA/+64mA  
Functionally compatible with the 74 series 125  
Latch-up performance exceeds 500mA  
ESD performance:  
– Human-body model > 2000V  
– Machine model > 200V  
– Charged-device model > 1000V  
Ordering Information  
Package  
Order Number  
74LVTH125M  
Number  
Package Description  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LVTH125SJ  
74LVTH125MTC  
M14D  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
©1998 Fairchild Semiconductor Corporation  
74LVTH125 Rev. 1.4.0  
www.fairchildsemi.com  
Connection Diagram  
Logic Symbol  
IEEE/IEC  
Pin Description  
Truth Table  
Pin Names  
Description  
Inputs  
Output  
A , B  
Inputs  
n
n
O
3-STATE Outputs  
A
B
O
n
n
n
n
L
L
L
L
H
Z
H
X
H
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = HIGH Impedance  
©1998 Fairchild Semiconductor Corporation  
74LVTH125 Rev. 1.4.0  
www.fairchildsemi.com  
2
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
Parameter  
Rating  
V
Supply Voltage  
–0.5V to +4.6V  
CC  
V
DC Input Voltage  
DC Output Voltage  
Output in 3-STATE  
–0.5V to +7.0V  
I
V
O
–0.5V to +7.0V  
–0.5V to +7.0V  
–50mA  
(1)  
Output in HIGH or LOW State  
I
DC Input Diode Current, V < GND  
I
IK  
I
DC Output Diode Current, V < GND  
–50mA  
OK  
O
I
DC Output Current, V > V  
O
O
CC  
Output at HIGH State  
Output at LOW State  
64mA  
128mA  
I
DC Supply Current per Supply Pin  
DC Ground Current per Ground Pin  
Storage Temperature  
64mA  
CC  
I
128mA  
GND  
T
–65°C to +150°C  
STG  
Note:  
1. I Absolute Maximum Rating must be observed.  
O
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to absolute maximum ratings.  
Symbol  
Parameter  
Min  
2.7  
0
Max  
3.6  
5.5  
–32  
64  
Units  
V
V
Supply Voltage  
Input Voltage  
CC  
V
V
I
I
HIGH-Level Output Current  
LOW-Level Output Current  
Free-Air Operating Temperature  
mA  
mA  
°C  
OH  
I
OL  
T
–40  
0
85  
A
t / V  
Input Edge Rate, V = 0.8V–2.0V, V = 3.0V  
10  
ns/V  
IN  
CC  
©1998 Fairchild Semiconductor Corporation  
74LVTH125 Rev. 1.4.0  
www.fairchildsemi.com  
3
DC Electrical Characteristics  
TA = –40°C to +85°C  
Min.  
Typ.(2) Max.  
Symbol  
Parameter  
Input Clamp Diode Voltage  
Input HIGH Voltage  
VCC (V)  
2.7  
Conditions  
Units  
V
V
I = –18mA  
–1.2  
0.8  
V
V
V
V
IK  
IH  
I
2.7–3.6  
2.7–3.6  
2.7–3.6  
2.7  
V
V
0.1V or  
2.0  
O
V – 0.1V  
V
Input LOW Voltage  
O
CC  
IL  
V
Output HIGH Voltage  
I
I
I
I
I
I
I
I
= –100µA  
= –8mA  
= –32mA  
= 100µA  
= 24mA  
= 16mA  
= 32mA  
= 64mA  
V
– 0.2  
CC  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
OL  
2.4  
2.0  
3.0  
V
Output LOW Voltage  
2.7  
0.2  
0.5  
V
OL  
3.0  
0.4  
0.5  
0.55  
I
Bushold Input Minimum Drive  
3.0  
3.0  
V = 0.8V  
75  
–75  
µA  
µA  
µA  
I(HOLD)  
I
V = 2.0V  
I
(3)  
I
Bushold Input Over-Drive  
Current to Change State  
500  
I(OD)  
(4)  
–500  
I
Input Current  
Control Pins  
Data Pins  
3.6  
3.6  
3.6  
V = 5.5V  
10  
1
I
I
V = 0V or V  
I
CC  
V = 0V  
–5  
1
I
V = V  
I
CC  
I
Power Off Leakage Current  
0
0V V or V 5.5V  
100  
100  
µA  
µA  
OFF  
I
O
I
Power up/down 3-STATE  
Output Current  
0–1.5  
V = 0.5V to 3.0V,  
O
PU/PD  
V = GND or V  
I
CC  
I
3-STATE Output Leakage Current  
3-STATE Output Leakage Current  
3-STATE Output Leakage Current  
Power Supply Current  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
V
V
V
= 0.5V  
= 3.0V  
–5  
5
µA  
µA  
OZL  
O
I
OZH  
O
I
+
< V 5.5V  
10  
µA  
OZH  
CC  
O
I
Outputs HIGH  
Outputs LOW  
0.19  
5
mA  
mA  
mA  
mA  
CCH  
I
Power Supply Current  
CCL  
I
Power Supply Current  
Outputs Disabled  
0.19  
0.19  
CCZ  
I
+
Power Supply Current  
V
V 5.5V,  
CC O  
CCZ  
Outputs Disabled  
One Input at V – 0.6V,  
I  
Increase in Power Supply  
Current  
3.6  
0.2  
mA  
CC  
CC  
(5)  
Other Inputs at V or  
CC  
GND  
Notes:  
2. All typical values are at V = 3.3V, T = 25°C.  
CC  
A
3. An external driver must source at least the specified current to switch from LOW-to-HIGH.  
4. An external driver must sink at least the specified current to switch from HIGH-to-LOW.  
5. This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.  
CC  
©1998 Fairchild Semiconductor Corporation  
74LVTH125 Rev. 1.4.0  
www.fairchildsemi.com  
4
Dynamic Switching Characteristics(6)  
Conditions  
T = 25°C  
A
Symbol  
Parameter  
V
(V) C = 50 pF, R = 500Min.  
Typ.  
Max.  
Units  
CC  
L
L
(7)  
V
Quiet Output Maximum  
3.3  
0.8  
V
OLP  
Dynamic V  
OL  
(7)  
V
Quiet Output Minimum  
Dynamic V  
3.3  
–0.8  
V
OLV  
OL  
Notes:  
6. Characterized in SOIC package. Guaranteed parameter, but not tested.  
7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.  
AC Electrical Characteristics  
T = –40°C to +85°C,  
A
C = 50pF, R = 500Ω  
L
L
V
Min.  
1.0  
= 3.3V 0.3V  
V
= 2.7V  
CC  
CC  
(8)  
Symbol  
Parameter  
Typ.  
Max.  
3.5  
3.9  
4.0  
4.0  
4.5  
4.5  
1.0  
Min.  
1.0  
1.0  
1.0  
1.1  
1.5  
1.3  
Max.  
Units  
t
t
Propagation Delay, Data to Output  
4.5  
4.9  
5.5  
5.4  
5.7  
4.0  
1.0  
ns  
PLH  
PHL  
PZH  
1.0  
t
Output Enable Time  
Output Disable Time  
1.0  
ns  
ns  
ns  
t
1.1  
PZL  
PHZ  
t
1.5  
t
1.3  
PLZ  
(9)  
t
, t  
Output to Output Skew  
OSHL OSLH  
Notes:  
8. All typical values are at V = 3.3V, T = 25°C.  
CC  
A
9. Skew is defined as the absolute value of the difference between the actual propagation delay for any two  
separate outputs of the same device. The specification applies to any outputs switching in the same direction,  
either HIGH-to-LOW (t  
) or LOW-to-HIGH (t  
).  
OSHL  
OSLH  
(10)  
Capacitance  
Symbol  
Parameter  
Conditions  
Typical  
Units  
pF  
C
Input Capacitance  
Output Capacitance  
V
V
= 0V, V = 0V or V  
CC  
4
8
IN  
CC  
I
C
= 3.0V, V = 0V or V  
CC  
pF  
OUT  
CC  
O
Note:  
10. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883B, Method 3012.  
©1998 Fairchild Semiconductor Corporation  
74LVTH125 Rev. 1.4.0  
www.fairchildsemi.com  
5
0.65  
A
ꢀꢁꢂꢂ“ꢂꢁꢃꢂ  
0.43TYP  
14  
8
B
6.4  
ꢄꢁꢄꢂ“ꢂꢁꢃꢂ  
6.10  
3.2  
1.65  
0.2 C B A  
ALL LEAD TIPS  
1
7
PIN#1 IDENT  
TOP VIEW  
0.45  
RECOMMENDED LAND PATTERN  
SEE DETAIL A  
1.2 MAX  
+0.15  
-0.10  
0.90  
0.20  
0.09  
ꢂꢁꢃꢂ“ꢂꢁꢂꢀ  
0.30  
0.19  
ALL LEAD TIPS  
C
0.1 C  
0.13  
A B  
C
0.65  
ꢃꢅꢁꢂꢂƒꢆ723ꢆꢇꢆ%27720  
FRONT VIEW  
0.09 MIN  
NOTES:  
GAGE PLANE  
A. CONFORMS TO JEDEC REGISTRATION MO-153,  
VARIATION AB, REF NOTE 6  
B. DIMENSIONS ARE IN MILLIMETERS.  
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,  
MOLD FLASH, AND TIE BAR EXTRUSIONS  
D. DIMENSIONING AND TOLERANCES PER ANSI  
Y14.5M, 2009.  
0.25  
0.09 MIN  
ꢂƒꢉꢆꢊƒ  
ꢂꢁꢈ“ꢂꢁꢃ  
1.00  
SEATING PLANE  
DETAIL A  
E. LANDPATTERN STANDARD: SOP65P640X110-14M.  
F. DRAWING FILE NAME: MKT-MTC14rev7.  
8.75  
8.50  
A
0.65  
7.62  
14  
8
14  
8
B
4.00  
3.80  
5.60  
6.00  
1.70  
1
7
PIN #1  
IDENT.  
1
7
1.27  
0.51  
0.35  
1.27  
(0.33)  
M
0.25  
C B A  
LAND PATTERN RECOMMENDATION  
TOP VIEW  
1.75 MAX  
A
0.25  
0.19  
C
0.10 C  
NOTES:  
1.50  
1.25  
0.25  
0.10  
SIDE VIEW  
FRONT VIEW  
A. CONFORMS TO JEDEC MS-012,  
VARIATION AB, ISSUE C  
B. ALL DIMENSIONS ARE IN MILLIMETERS  
C. DIMENSIONS DO NOT INCLUDE MOLD  
FLASH OR BURRS  
0.50  
0.25  
x 45  
R0.10  
GAGE  
PLANE  
D. LAND PATTERN STANDARD:  
SOIC127P600X145-14M  
R0.10  
E. CONFORMS TO ASME Y14.5M, 2009  
D. DRAWING FILENAME: MKT-M14Arev14  
0.36  
8°  
0°  
0.90  
0.50  
SEATING PLANE  
(1.04)  
DETAIL A  
SCALE 16 : 1  
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
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ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,  
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or  
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