74LVTH162373MEX [ONSEMI]
Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs, SSOP 48L, 1000-TAPE REEL;
| 型号： | 74LVTH162373MEX |
| 厂家： | 
ONSEMI |
| 描述： | Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs, SSOP 48L, 1000-TAPE REEL 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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October 2000
Revised June 2005
74LVTH162373
Low Voltage 16-Bit Transparent Latch with
3-STATE Outputs and
25: Series Resistors in the Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVTH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs include equivalent series resistance of 25 to
make external termination resistors unnecessary and
reduce overshoot and undershoot
The LVTH162373 is designed with equivalent 25 series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
■ Functionally compatible with the 74 series 16373
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The LVTH162373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
Human-body model 2000V
Machine model 200V
These latches are designed for low-voltage (3.3V) VCC
Charged-device model 1000V
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH162373 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Ordering Code:
Package
Order Number
Package Description
Number
74LVTH162373MEA
MS48A
MS48A
MTD48
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBES]
74LVTH162373MEX
(Note 1)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LVTH162373MTD
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74LVTH162373MTX
(Note 1)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500354
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
LEn
I0–I15
O0–O15
3-STATE Outputs
Truth Tables
Inputs
Outputs
O0–O7
LE1
OE1
I0–I7
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
Oo
Inputs
OE2
Outputs
O8–O15
LE2
I8–I15
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
Oo
H
L
X
Z
O
HIGH Voltage Level
LOW Voltage Level
Immaterial
HIGH Impedance
Previous output prior to HIGH-to-LOW transition of LE
o
Functional Description
The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each
byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation.
The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the
latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes.
When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW
transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the
standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but
this does not interfere with entering new data into the latches.
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2
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Symbol
VCC
Parameter
Supply Voltage
Value
0.5 to 4.6
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
50
Conditions
Units
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
Output in HIGH or LOW State (Note 3)
VI GND
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
mA
mA
50
VO GND
64
VO VCC Output at HIGH State
VO VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
64
mA
mA
C
IGND
TSTG
128
65 to 150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
12
Units
Supply Voltage
Input Voltage
V
V
VI
IOH
IOL
TA
HIGH Level Output Current
mA
mA
C
LOW Level Output Current
12
Free-Air Operating Temperature
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V
40
85
t/ V
0
10
ns/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: I Absolute Maximum Rating must be observed.
O
DC Electrical Characteristics
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
2.7
Min
Max
V
V
V
V
Input Clamp Diode Voltage
1.2
V
V
V
I
18 mA
0.1V or
IK
I
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
2.7–3.6
2.7–3.6
2.7–3.6
3.0
2.0
V
V
IH
IL
O
O
0.8
0.2
V
0.1V
A
CC
V
I
I
I
I
100
OH
CC
OH
OH
OL
OL
V
V
A
A
2.0
12mA
100
V
Output LOW Voltage
2.7
0.2
0.8
A
OL
3.0
12 mA
0.8V
I
I
I
Bushold Input Minimum Drive
3.0
75
75
V
V
I(HOLD)
I(OD)
I
I
I
2.0V
Bushold Input Over-Drive
Current to Change State
Input Current
3.0
500
(Note 4)
(Note 5)
500
3.6
3.6
10
1
V
V
V
V
5.5V
0V or V
0V
I
I
I
I
Control Pins
Data Pins
CC
A
5
3.6
0
1
V
CC
I
I
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
100
A
A
0V V or V
5.5V
OFF
I
O
V
V
V
V
V
0.5V to 3.0V
PU/PD
O
I
0–1.5V
100
GND or V
0.5V
CC
I
I
I
I
I
I
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
3.6
3.6
5
5
A
A
OZL
OZH
OZH
CCH
CCL
CCZ
O
O
CC
3.0V
10
A
V
5.5V
O
0.19
5
mA
mA
mA
Outputs HIGH
Outputs LOW
Power Supply Current
Power Supply Current
0.19
Outputs Disabled
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4
DC Electrical Characteristics (Continued)
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Power Supply Current
Units
Conditions
(V)
Min
Max
I
3.6
0.19
mA
V
V
O
5.5V,
CCZ
CC
Outputs Disabled
One Input at V
I
Increase in Power Supply Current
(Note 6)
0.6V
CC
CC
3.6
0.2
mA
Other Inputs at V or GND
CC
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.
CC
Dynamic Switching Characteristics (Note 7)
V
T
25 C
Conditions
CC
A
Symbol
Parameter
Units
C
50 pF, R
500
(V)
3.3
3.3
Min
Typ
Max
L
L
V
V
Quiet Output Maximum Dynamic V
0.8
0.8
V
V
(Note 8)
(Note 8)
OLP
OL
Quiet Output Minimum Dynamic V
OLV
OL
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
40 C to 85 C, C 50pF, R 500
L L
A
Symbol
Parameter
V
3.3V 0.3V
V
2.7V
Max
Units
CC
CC
Min
1.3
1.4
1.7
1.4
1.6
1.0
1.6
1.8
1.0
1.0
3.0
Max
4.8
4.8
5.0
5.1
5.0
5.4
5.1
5.4
Min
t
t
t
t
t
t
t
t
t
t
t
t
t
Propagation Delay
to O
1.3
1.4
1.7
1.4
1.6
1.0
1.6
1.8
0.8
1.1
3.0
5.3
5.1
5.1
5.8
6.0
6.6
5.0
5.7
PHL
ns
ns
ns
ns
D
PLH
PHL
PLH
PZL
PZH
PLZ
PHZ
S
n
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
Setup Time, D to LE
ns
ns
ns
n
Hold Time, D to LE
n
H
LE Pulse Width
W
Output to Output Skew (Note 9)
1.0
1.0
1.0
1.0
OSHL
OSLH
ns
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
Capacitance (Note 10)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
OPEN, V 0V or V
CC
Typical
Units
pF
C
C
V
V
4
8
IN
CC
I
3.0V, V
0V or V
CC
pF
OUT
CC
O
Note 10: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.
5
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
www.fairchildsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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