74LVXT4066 [ONSEMI]
Quad Analog Switch/Multiplexer/Demultiplexer High−Performance Silicon−Gate CMOS; 四路模拟开关/多路复用器/多路解复用器高性能硅栅CMOS
| 型号： | 74LVXT4066 |
| 厂家： | 
ONSEMI |
| 描述： | Quad Analog Switch/Multiplexer/Demultiplexer High−Performance Silicon−Gate CMOS |
| 文件： | 总12页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVXT4066
Quad Analog Switch/
Multiplexer/Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT4066 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
OFF−channel leakage current. This bilateral switch/multiplexer/
demultiplexer controls analog and digital voltages that may vary
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MARKING
DIAGRAMS
across the full power−supply range (from V to GND).
CC
The LVXT4066 is identical in pinout to the metal−gate CMOS
MC14066 and the high−speed CMOS HC4066A. Each device has four
independent switches. The device has been designed so that the ON
14
SOIC−14
D SUFFIX
CASE 751A
LVXT4066
AWLYWW
resistances (R ) are much more linear over input voltage than R
14
ON
ON
of metal−gate CMOS analog switches.
1
The ON/OFF control inputs are compatible with standard LSTTL
outputs. The input protection circuitry on this device allows
overvoltage tolerance on the ON/OFF control inputs, allowing the
device to be used as a logic−level translator from 3.0 V CMOS logic to
5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic
while operating at the higher−voltage power supply.
The MC74LVXT4066 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74LVXT4066 to be used to interface 5.0 V circuits to
3.0 V circuits.
1
14
TSSOP−14
DT SUFFIX
CASE 948G
LVXT
4066
ALYW
14
1
1
Features
• Fast Switching and Propagation Speeds
• High ON/OFF Output Voltage Ratio
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
14
74LVXT4066
ALYW
SOEIAJ−14
M SUFFIX
CASE 965
14
• Wide Power−Supply Voltage Range (V − GND) = 2.0 to 6.0 V
CC
1
1
• Analog Input Voltage Range (V − GND) = 2.0 to 6.0 V
CC
• Improved Linearity and Lower ON Resistance over Input Voltage
than the MC14016 or MC14066
A
=
=
=
=
Assembly Location
Wafer Lot
Year
• Low Noise
• Pb−Free Packages are Available*
WL or L
Y
WW or W
Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
March, 2005 − Rev. 2
MC74LVXT4066/D
MC74LVXT4066
LOGIC DIAGRAM
PIN CONNECTION (Top View)
1
2
V
X
Y
A
X
1
2
3
4
5
6
14
13
12
11
10
9
CC
A
A
A ON/OFF
CONTROL
13
4
Y
A
A ON/OFF CONTROL
D ON/OFF
CONTROL
Y
B
3
9
X
B
Y
B
Y
C
Y
D
X
B
X
D
5
ANALOG
B ON/OFF
CONTROL
B ON/OFF CONTROL
Y
D
Y
C
OUTPUTS/INPUTS
8
C ON/OFF
CONTROL
X
C
7
8
X
C
GND
6
C ON/OFF CONTROL
11
12
10
X
D
D ON/OFF CONTROL
ANALOG INPUTS/OUTPUTS = X , X , X , X
D
A
B
C
PIN 14 = V
CC
PIN 7 = GND
FUNCTION TABLE
On/Off Control
State of
Input
Analog Switch
L
H
Off
On
ORDERING INFORMATION
Device
†
Package
SOIC−14
SOIC−14
Shipping
MC74LVXT4066DR2
MC74LVXT4066DR2G
2500 Tape & Reel
2500 Tape & Reel
(Pb−Free)
TSSOP−14*
SOEIAJ−14
MC74LVXT4066DTR2
MC74LVXT4066M
2500 Tape & Reel
50 Units / Rail
50 Units / Rail
MC74LVXT4066MG
SOEIAJ−14
(Pb−Free)
MC74LVXT4066MEL
MC74LVXT4066MELG
SOEIAJ−14
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVXT4066
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
DC Current Into or Out of Any Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
IS
CC
V
– 0.5 to V + 0.5
V
in
CC
I
−20
mA
mW
cuit. For proper operation, V and
in
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
V
out
should be constrained to the
range GND v (V or V ) v V
.
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
T
stg
Storage Temperature
– 65 to + 150
260
_C
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
Max
Unit
V
V
CC
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
Input Rise and Fall Time, ON/OFF Control
5.5
V
IS
GND
GND
−
V
CC
V
CC
V
V
in
V
V *
IO
1.2
V
T
A
– 55
+ 85
_C
ns/V
t , t
r
f
Inputs (Figure 10)
V
CC
V
CC
= 3.3 V ± 0.3 V
= 5.0 V ± 0.5 V
0
0
100
20
*For voltage drops across the switch greater than 1.2 V (switch on), excessive V current may
CC
be drawn; i.e., the current out of the switch may contain both V and switch input components.
CC
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
– 55 to 25_C
v 85_C
v 125_C
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level Voltage
ON/OFF Control Inputs
(Note 1)
R
R
= Per Spec
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
on
on
V
IL
Maximum Low−Level Voltage
ON/OFF Control Inputs
(Note 1)
= Per Spec
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
I
Maximum Input Leakage Current
ON/OFF Control Inputs
V
V
= V or GND
5.5
± 0.1
± 1.0
± 1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND V = 0 V
5.5
4.0
40
160
CC
in
CC
IO
1. Specifications are for design target only. Not final specification limits.
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3
MC74LVXT4066
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
V
v 85_C
v 125_C
Symbol
Parameter
Test Conditions
Unit
R
Maximum “ON” Resistance
W
V
V
I
= V
2.0†
3.0
4.5
5.5
—
40
25
20
—
45
28
25
—
50
35
30
on
in
IH
= V to GND
IS
CC
v 2.0 mA (Figures 1, 2)
S
V
V
I
= V
2.0
3.0
4.5
5.5
—
30
25
20
—
35
28
25
—
40
35
30
in
IH
= V or GND (Endpoints)
v 2.0 mA (Figures 1, 2)
IS
CC
S
DR
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
I
= V
IH
= 1/2 (V − GND)
v 2.0 mA
= V
IL
3.0
4.5
5.5
15
10
10
20
12
12
25
15
15
W
on
in
IS
CC
S
I
off
Maximum Off−Channel Leakage
Current, Any One Channel
V
V
5.5
0.1
0.5
1.0
mA
mA
in
= V or GND
IO
CC
Switch Off (Figure 3)
I
on
Maximum On−Channel Leakage
Current, Any One Channel
V
V
= V
IH
5.5
0.1
0.5
1.0
in
= V or GND
IS
CC
(Figure 4)
†At supply voltage (V ) approaching 2 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage
CC
operation, it is recommended that these devices only be used to control digital signals.
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, ON/OFF Control Inputs: t = t = 6 ns)
L
r
f
Guaranteed Limit
V
CC
V
– 55 to 25_C v 85_C
v 125_C
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)
2.0
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
PLH
t
PHL
,
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 11)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
ns
pF
PLZ
t
PHZ
,
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 1 1)
2.0
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
PZL
t
PZH
C
Maximum Capacitance
ON/OFF Control Input
—
10
10
10
Control Input = GND
Analog I/O
—
—
35
1.0
35
1.0
35
1.0
Feedthrough
Typical @ 25°C, V = 5.0 V
CC
15
C
Power Dissipation Capacitance (Per Switch) (Figure 13)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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4
MC74LVXT4066
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
V
CC
Limit*
V
25_C
Symbol
Parameter
Test Conditions
= 1 MHz Sine Wave
Unit
BW
Maximum On−Channel Bandwidth or
Minimum Frequency Response
(Figure 5)
f
in
4.5
5.5
150
MHz
Adjust f Voltage to Obtain 0 dBm at V
160
in
OS
Increase f Frequency Until dB Meter Reads – 3 dB
in
R = 50 W, C = 10 pF
L
L
−
−
Off−Channel Feedthrough Isolation
(Figure 6)
f
ꢀ Sine Wave
4.5
5.5
− 50
− 50
dB
in
Adjust f Voltage to Obtain 0 dBm at V
in
IS
f
= 10 kHz, R = 600 W, C = 50 pF
L L
in
f
= 1.0 MHz, R = 50 W, C = 10 pF
4.5
5.5
− 37
− 37
in
L
L
Feedthrough Noise, Control to Switch
(Figure 7)
V
v 1 MHz Square Wave (t = t = 3 ns)
4.5
5.5
100
200
mV
in
r
f
PP
Adjust R at Setup so that I = 0 A
L
S
R = 600 W, C = 50 pF
L
L
R = 10 kW, C = 10 pF
4.5
5.5
50
100
L
L
−
Crosstalk Between Any Two Switches
(Figure 12)
f
ꢀ Sine Wave
4.5
5.5
– 70
– 70
dB
%
in
Adjust f Voltage to Obtain 0 dBm at V
in
IS
f
= 10 kHz, R = 600 W, C = 50 pF
L L
in
f
= 1.0 MHz, R = 50 W, C = 10 pF
4.5
5.5
– 80
– 80
in
L
L
THD
Total Harmonic Distortion
(Figure 14)
f
in
= 1 kHz, R = 10 kW, C = 50 pF
L
L
THD = THD
− THD
Measured
Source
V
IS
V
IS
= 4.0 V sine wave
4.5
5.5
0.10
0.06
PP
= 5.0 V sine wave
PP
*Guaranteed limits not tested. Determined by design and verified by qualification.
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5
MC74LVXT4066
400
350
300
250
200
150
100
50
250
200
150
100
I = 1mA
s
−55°C
25°C
85°C
I = 5mA
s
125°C
I = 9mA
s
50
0
I = 15mA
s
0
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
Vin (Volts)
Vin (Volts)
Figure 1a. Typical On Resistance, VCC = 2.0 V, T = 25°C
Figure 1b. Typical On Resistance, VCC = 2.0 V
35
30
25
25
20
15
10
125°C
20
85°C
25°C
125°C
85°C
25°C
15
−55°C
−55°C
10
5
0
5
0
0
1
2
3
4
0
1
2
3
4
5
Vin (Volts)
Vin (Volts)
Figure 1c. Typical On Resistance, VCC = 3.0 V
Figure 1d. Typical On Resistance, VCC = 4.5 V
18
16
PLOTTER
125°C
85°C
14
12
10
8
PROGRAMMABLE
POWER
SUPPLY
25°C
MINI COMPUTER
DC ANALYZER
−55°C
−
+
V
CC
DEVICE
6
UNDER TEST
4
2
ANALOG IN
COMMON OUT
0
0
1
2
3
4
5
6
GND
Vin (Volts)
Figure 2. On Resistance Test Set−Up
Figure 1e. Typical On Resistance, VCC = 5.5 V
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6
MC74LVXT4066
V
CC
V
CC
V
CC
V
CC
14
14
GND
N/C
A
ON
A
OFF
GND
V
CC
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
IL
V
IH
7
7
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 4. Maximum On Channel Leakage Current,
Test Set−Up
V
OS
V
OS
V
CC
V
CC
V
IS
14
14
f
in
f
in
ON
OFF
dB
dB
0.1mF
0.1mF
C *
L
C *
L
R
L
METER
METER
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
CC
7
7
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 5. Maximum On−Channel Bandwidth
Test Set−Up
Figure 6. Off−Channel Feedthrough Isolation,
Test Set−Up
V
CC
V
CC/2
V
CC/2
14
R
L
R
L
V
OS
I
S
OFF/ON
V
CC
C *
L
50%
ANALOG IN
SELECTED
CONTROL
INPUT
GND
7
V
≤ 1 MHz
t = t = 3 ns
t
t
PHL
in
PLH
r
f
V
IH
CONTROL
V
IL
50%
ANALOG OUT
*Includes all probe and jig capacitance.
Figure 7. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set−Up
Figure 8. Propagation Delays, Analog In to
Analog Out
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7
MC74LVXT4066
V
CC
t
r
t
f
14
V
CC
90%
50%
10%
CONTROL
ANALOG IN
ANALOG OUT
C *
TEST
ON
POINT
GND
L
t
t
t
PLZ
PZL
HIGH
IMPEDANCE
50%
50%
SELECTED
CONTROL
INPUT
V
IH
10%
90%
V
OL
ANALOG
OUT
7
t
PZH
PHZ
V
OH
HIGH
*Includes all probe and jig capacitance.
IMPEDANCE
Figure 9. Propagation Delay Test Set−Up
Figure 10. Propagation Delay, ON/OFF Control
to Analog Out
V
IS
1
POSITIONꢀꢀꢁWHEN TESTING t
AND t
PHZ
PZH
V
CC
2
POSITIONꢀꢀWHEN TESTING t AND t
PLZ
PZL
1
2
14
R
L
V
OS
V
CC
f
in
ON
V
CC
0.1 mF
1 kW
14
1
2
TEST
POINT
OFF
ON/OFF
V
IH
OR V
IL
R
L
C *
L
R
L
C *
L
C *
L
R
L
SELECTED
CONTROL
INPUT
V
SELECTED
CONTROL
INPUT
IH
V
CC/2
V
CC/2
V
IL
7
7
V
CC/2
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 11. Propagation Delay Test Set−Up
Figure 12. Crosstalk Between Any Two Switches,
Test Set−Up
V
CC
A
V
IS
V
CC
V
OS
14
0.1 mF
TO
N/C
N/C
OFF/ON
f
in
ON
DISTORTION
METER
C *
L
R
L
V
SELECTED
CONTROL
INPUT
CC/2
7
SELECTED
CONTROL
INPUT
V
IH
7
V
IH
ON/OFF CONTROL
V
IL
*Includes all probe and jig capacitance.
Figure 13. Power Dissipation Capacitance
Test Set−Up
Figure 14. Total Harmonic Distortion, Test Set−Up
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8
MC74LVXT4066
0
−ꢂ10
−ꢂ20
−ꢂ30
−ꢂ40
FUNDAMENTAL FREQUENCY
−ꢂ50
−ꢂ60
−ꢂ70
−ꢂ80
−ꢂ90
DEVICE
SOURCE
1.0
2.0
FREQUENCY (kHz)
3.0
Figure 15. Plot, Harmonic Distortion
APPLICATION INFORMATION
The ON/OFF Control pins should be at V or V logic
Therefore, using the configuration in Figure 16, a maximum
analog signal of six volts peak−to−peak can be controlled.
IH
IL
levels, V being recognized as logic high and V being
IH
IL
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is
When voltage transients above V and/or below GND
CC
are anticipated on the analog channels, external diodes (Dx)
are recommended as shown in Figure 17. These diodes
should be small signal, fast turn−on types able to absorb the
maximum anticipated current surges during clipping. An
alternate method would be to replace the Dx diodes with
Mosorbs (Mosorb is an acronym for high current surge
protectors). Mosorbs are fast turn−on devices ideally suited
for precise DC protection with no inherent wear out
mechanism.
advisable to tie unused analog inputs and outputs to V or
CC
GND through a low value resistor. This minimizes crosstalk
and feedthrough noise that may be picked−up by the unused
I/O pins.
The maximum analog voltage swings are determined by
the supply voltages V and GND. The positive peak analog
CC
voltage should not exceed V . Similarly, the negative peak
CC
analog voltage should not go below GND. In the example
below, the difference between V and GND is six volts.
CC
V
CC
V
CC
V
CC
= 6.0 V
D
D
D
D
14
x
x
16
+ 6.0 V
0 V
+ 6.0 V
0 V
ANALOG I/O
ANALOG O/I
ON
ON
x
x
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
IH
V
IH
OTHER CONTROL
OTHER CONTROL
INPUTS
(V OR V )
INPUTS
(V OR V )
7
7
IH
IL
IH
IL
Figure 16. 6.0 V Application
Figure 17. Transient Suppressor Application
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9
MC74LVXT4066
+
3 V
+ꢂ5 V
+3V
+3V
14
14
ANALOG
SIGNALS
ANALOG
SIGNALS
ANALOG
ANALOG
SIGNALS
SIGNALS
GND
GND
LVXT4066
LVXT4066
LSTTL/
NMOS/
ABT/
5
6
5
6
1.8 − 2.5V
CIRCUITRY
CONTROL
INPUTS
CONTROL
INPUTS
ALS
14
15
14
15
7
7
R* = 2 TO 10 kW
a. Low Voltage Logic Level Shifting Control
b. Using LVXT4066
Figure 18. Low Voltage CMOS Interface
1 OF 4
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
SWITCHES
1 OF 4
SWITCHES
COMMON I/O
1 OF 4
SWITCHES
−
1 OF 4
OUTPUT
1 OF 4
INPUT
SWITCHES
+
LF356 OR
SWITCHES
EQUIVALENT
0.01 mF
1
2
3
4
CONTROL INPUTS
Figure 19. 4−Input Multiplexer
Figure 20. Sample/Hold Amplifier
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10
MC74LVXT4066
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
14
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45
_
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T
B
A
1.27 BSC
0.19
0.10
0
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE A
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
−U−
L
N
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
K1
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
D
0
8
0
8
_
_
_
_
http://onsemi.com
11
MC74LVXT4066
PACKAGE DIMENSIONS
SOEIAJ−14
M SUFFIX
CASE 965−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
14
8
E
Q
1
H
E
_
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
7
1
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
A
e
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
−−−
0.05
0.35
0.18
9.90
5.10
2.05
b
A
1
A
1
b
c
0.20 0.002
0.50 0.014
0.27 0.007
M
0.13 (0.005)
0.10 (0.004)
D
E
e
10.50 0.390
5.45 0.201
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
0
10
0.90 0.028
10
_
0.035
0.056
0
_
_
_
Q
0.70
−−−
1
Z
1.42
−−−
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MC74LVXT4066/D
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