74VHC373MX [ONSEMI]
带 3 态输出的八路 D 型锁存;
| 型号： | 74VHC373MX |
| 厂家： | 
ONSEMI |
| 描述： | 带 3 态输出的八路 D 型锁存 |
| 文件： | 总11页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 2007
74VHC373
tm
Octal D-Type Latch with 3-STATE Outputs
Features
General Description
■ High Speed: t = 5.0ns (typ) @ V = 5V
The VHC373 is an advanced high speed CMOS octal
D-type latch with 3-STATE output fabricated with silicon
gate CMOS technology. It achieves the high speed oper-
ation similar to equivalent Bipolar Schottky TTL while
maintaining the CMOS low power dissipation. This 8-bit
D-type latch is controlled by a latch enable input (LE)
and an output enable input (OE). The latches appear
transparent to data when latch enable (LE) is HIGH.
When LE is LOW, the data that meets the setup time is
LATCHED. When the OE input is HIGH, the eight
outputs are in a high impedance state.
PD
CC
■ High Noise Immunity: V
= V
= 28% V (Min.)
NIH
NIL
CC
■ Power Down Protection is provided on all inputs
■ Low Noise: V = 0.6V (Typ.)
OLP
■ Low Power Dissipation: I = 4µA (Max) @ T = 25°C
CC
A
■ Pin and Function Compatible with 74HC373
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Ordering Information
Package
Order Number
74VHC373M
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC373SJ
74VHC373MTC
M20D
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
Description
D –D
Data Inputs
0
7
LE
Latch Enable Input
Output Enable Input
3-STATE Outputs
OE
O –O
0
7
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
Logic Symbol
Functional Description
IEEE/IEC
The VHC373 contains eight D-type latches with
3-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D inputs enters the latches.
n
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW, the latches store the information that
was present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the
2-state mode. When OE is HIGH, the standard outputs
are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
Truth Table
Inputs
Outputs
LE
X
OE
H
D
O
n
n
X
Z
L
H
L
L
H
X
H
L
H
L
L
O
0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O = Previous O before HIGH-to-LOW transition of
0
0
Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
Supply Voltage
–0.5V to +7.0V
–0.5V to +7.0V
CC
V
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
IN
V
–0.5V to V + 0.5V
OUT
CC
I
–20mA
20mA
IK
I
OK
I
25mA
OUT
I
DC V /GND Current
75mA
CC
CC
T
Storage Temperature
–65°C to +150°C
260°C
STG
T
Lead Temperature (Soldering, 10 seconds)
L
(1)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
2.0V to +5.5V
0V to +5.5V
0V to V
CC
V
Input Voltage
IN
V
Output Voltage
OUT
CC
T
Operating Temperature
Input Rise and Fall Time,
–40°C to +85°C
OPR
t , t
r
f
V
V
= 3.3V 0.3V
= 5.0V 0.5V
0ns/V ∼ 100ns/V
0ns/V ∼ 20ns/V
CC
CC
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
3
DC Electrical Characteristics
T =
A
25°C
Typ.
–40°C to +85°C
Symbol
Parameter
V
(V)
Conditions
Min.
Max.
Min.
Max.
Units
CC
2.0
V
HIGH Level
1.50
1.50
V
IH
Input Voltage
3.0–5.5
2.0
0.7 x V
0.7 x V
CC
CC
V
LOW Level Input
Voltage
0.50
0.50
V
V
IL
3.0–5.5
2.0
0.3 x V
0.3 x V
CC
CC
V
HIGH Level
Output
Voltage
V
= V
I
= –50µA
1.9
2.9
2.0
3.0
4.5
1.9
2.9
OH
IN
IH OH
or V
3.0
IL
4.5
4.4
4.4
3.0
I
= –4mA
= –8mA
= 50µA
2.58
3.94
2.48
3.80
OH
4.5
I
OH
V
LOW Level
Output Voltage
2.0
V
or V
=V
IL
I
0.0
0.0
0.0
0.1
0.1
0.1
0.1
V
OL
IN
IH OL
3.0
4.5
0.1
0.1
3.0
I
= 4mA
= 8mA
0.36
0.36
0.44
0.44
2.5
OL
4.5
I
OL
I
3-STATE Output
Off-State
5.5
V
= V or V ;
0.25
µA
OZ
IN
IH
IL
V
= V or GND
OUT
CC
Current
I
Input Leakage
Current
0–5.5
5.5
V
V
= 5.5V or GND
0.1
4.0
1.0
µA
µA
IN
IN
IN
I
Quiescent
= V or GND
40.0
CC
CC
Supply Current
Noise Characteristics
T = 25°C
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Limits
Units
CC
(2)
V
Quiet Output Maximum
Dynamic V
5.0
C = 50pF
0.6
0.9
–0.9
3.5
V
V
V
V
OLP
L
OL
(2)
V
Quiet Output Minimum
Dynamic V
5.0
5.0
5.0
C = 50pF
–0.6
OLV
L
OL
(2)
V
Minimum HIGH Level
Dynamic Input Voltage
C = 50pF
IHD
L
(2)
V
Maximum LOW Level
Dynamic Input Voltage
C = 50pF
1.5
ILD
L
Note:
2. Parameter guaranteed by design.
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
4
AC Electrical Characteristics
TA = –40°C to
TA = +25°C
+85°C
Symbol
Parameter
VCC (V)
Conditions
Min. Typ. Max.
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max. Units
t
, t
Propagation Delay
3.3 0.3
C = 15pF
7.0
9.5
4.9
6.4
7.3
9.8
5.0
6.5
7.3
9.8
5.5
7.0
9.5
6.5
11.0
14.5
7.2
13.0
16.5
8.5
ns
ns
ns
PLH PHL
L
Time (LE to O )
n
C = 50pF
L
5.0 0.5
3.3 0.3
5.0 0.5
C = 15pF
L
C = 50pF
9.2
10.5
13.5
17.0
8.5
L
t
, t
Propagation Delay
C = 15pF
11.4
14.9
7.2
PLH PHL
L
Time (D to O )
n
C = 50pF
L
C = 15pF
L
C = 50pF
9.2
10.5
13.5
17.0
9.5
L
t
t
, t
3-STATE Output
Enable Time
3.3 0.3 R = 1kΩ C = 15pF
11.4
14.9
8.1
ns
ns
ns
ns
PZL PZH
L
L
C = 50pF
L
5.0 0.5
C = 15pF
L
C = 50pF
10.1
13.2
9.2
11.5
15.0
10.5
1.5
L
, t
3-STATE Output
Disable Time
3.3 0.3 R = 1kΩ C = 50pF
PLZ PHZ
L
L
5.0 0.5
3.3 0.3
5.0 0.5
C = 50pF
L
(3)
t
,
Output to Output
Skew
C = 50pF
1.5
OSLH
L
t
OSHL
C = 50pF
1.0
1.0
L
C
Input Capacitance
Output Capacitance
V
V
= Open
= 5.0V
4
6
10
10
pF
pF
pF
IN
CC
CC
C
OUT
(4)
C
Power Dissipation
Capacitance
27
PD
Notes:
3. Parameter guaranteed by design. t
= |t
– t
|; t
= |t
– t
min|
OSLH
PLH max
PLH min
OSHL
PHL max
PHL
4. C is defined as the value of the internal equivalent capacitance which is calculated from the operating
PD
current consumption without load. Average operating current can be obtained by the equation:
I
(opr.) = C • V • f + I /8 (per Latch). The total C when n pcs. of the Latch operates can be
CC
PD CC IN CC PD
calculated by the equation: C (total) = 14 + 13n.
PD
AC Operating Requirements
T = +25°C
T = –40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
5.0
5.0
4.0
4.0
1.0
1.0
Max.
Units
CC
t (H)
Minimum Pulse Width
(LE)
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
5.0
5.0
4.0
4.0
1.0
1.0
ns
W
t
Minimum Set-Up Time
ns
ns
S
t
Minimum Hold Time
H
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
5
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 2. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
6
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 3. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
7
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
8
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.
ACEx®
TinyLogic®
TINYOPTO¥
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UniFET¥
VCX¥
Wire¥
HiSeC¥
i-Lo¥
Programmable Active Droop¥
QFET®
QS¥
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Quiet Series¥
RapidConfigure¥
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SPM®
STEALTH™
SuperFET¥
SuperSOT¥-3
SuperSOT¥-6
SuperSOT¥-8
SyncFET™
Across the board. Around the world.¥
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Bottomless¥
Build it Now¥
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ImpliedDisconnect¥
IntelliMAX¥
ISOPLANAR¥
MICROCOUPLER¥
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CTL™
Current Transfer Logic™
DOME¥
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EnSigna¥
OCXPro¥
OPTOLOGIC®
OPTOPLANAR®
PACMAN¥
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FASTr¥
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HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
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As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
9
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regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
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