ADM9240ARU-REEL7 [ONSEMI]
系统硬件监控器;
| 型号： | ADM9240ARU-REEL7 |
| 厂家： | 
ONSEMI |
| 描述： | 系统硬件监控器 监控 光电二极管 |
| 文件： | 总23页 (文件大小：5965K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Low Cost Microprocessor
System Hardware Monitor
ADM9240
FEATURES
T ESCRIPTION
Six Direct Voltage Measurement Inputs (IncludingTwo
Processor Core Voltages) with On-Chip Attenuators
On-Chip Temperature Sensor
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Fully Supports Intel’s LANDesk Client Manager (LDCM)
Register-Compatible with LM7x Products
Two Fan Speed Monitoring Inputs
I2C® Compatible System Management Bus (SMBus)
Chassis Intrusion Detect
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Interrupt Output
r
e
to any out-of-limit measurement.
Programmable RESET I/O Pin
Th ADM9240’s 2.85 V to 5.75 V supply voltage range,low
Shutdown Mode to Minimize Power Consumption
Limit Comparison of all Monitored Values
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Network Servers and Personal Computers
Microprocessor-Based Office Equipment
Test Equipment and Measuring Instruments
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equipment and office electronics.
CK AM
CC
VID0
NTEST_OUT/A0
A1
SERIABUS
ADDRESS
REGISER
VID1
VID2
VID3
VI0 - 3 AND
FAN DIVISOR
RISTERS
SERIAL BUS
INTERFACE
SDA
SCL
VID4 AND
DEVICE
REGISTER
VALUE AND LIMIT
REGISTERS
VID4
LIMIT
FAN1
FAN2
FAN SPED
COUNTER
COMPARATORS
CI
INTERRUPT
STATUS
REGISTERS
ADDRESS
POINTER
REGISTER
+V
CCP1
INT MASK
+2.5V
IN
TEMPERATURE
CONFIGURATION
REGISTER
REGISTERS
+3.3V
+5V
INT
IN
INPUT
ATTENUATORS
AND
CONFIGURATION
REGISTER
IN
ANALOG
9-BIT ADC
MULTIPLEXER
+12V
IN
ANALOG
OUTPUT REGISTER
AND 8-BIT DAC
NTEST_IN/AOUT
+V
CCP2
RESET
BANDGAP
TEMPERATURE
SENSOR
CHASSIS
INTRUSION
CLEAR REGISTER
ADM9240
GNDA
GNDD
IC is a registered trademark of Philips Corporation.
©2010 SCILLC. All rights reserved.
May 2010 - Rev. 2
Publication Order Number:
ADM9240/D
ADM9240–SPECIFICATIONS1, 2
(to , CC to , uess otherse oted)
M
ER SUPPLY
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Rev. 2 | Page 2 of 22 | www.onsemi.com
940
P
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ERIAL DATA BUS
OUTPUT (SD
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DDIGITAL INPUT GIC LEVELS
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SERIAL BUS TIMING
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NOTES
1All voltages are measured with respect to GND, unless otherwise noted.
2Typicals are at TA = +25
C and represent most likely parametric norm. Shutdown current typ is measured with V= 3.3 V.
3TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators, including an external series input
protection resistor value between zero and 1 k
Ω
4Total monitoring cycle time is the time taken to measure all six analog inputs plus the temperature sensor.
5The total fan count is based on 2 pulses per revolution of the fan tachometer output.
6A0 and A1 have internal 75 k
7Timing specifications are tested at logic levels of V= 0.3
Ω pull-down.
× VC for a falling edge and V= 0.7 × Vfor a rising edge.
Specifications subject to change without notice.
Rev. 2 | Page 3 of 22 | www.onsemi.com
940
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
A
P
0.3 V)
LUUM RATINGS
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CHARACTERISTICS
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Storage Temperature Range.............–65
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ture, Soldering
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cept Pin 15 . . . . . . . . . . . . . . . . 2000 V
i
00 V
Start
Condition
(S)
ATION
Bit 7
MSB
(A7)
PROTOCOL
Bit 6
(A6)
tSU;STA
tHIGH
NTEST_OUT/A0
1
24
23
VID0
VID1
tLOW
1/fSCL
1
S
SCL
SDA
22 VID2
21 VID3
20 VID4
tr
tf
SCL
4
tBUF
FAN1
FA
5
ADM9240
TOP VIEW
(Not to Scale)
+V
19
CCP1
7
18 +2.5V
tHD;DAT
tHD;STA
IN
tSU;DT
DD
+3.3V
8
17
16
15
IN
Bit 0
LSB
(R/W)
Stop
ition
()
V
+5V
IN
9
CC
PROTOCOL
SCL
Acknowledge
(A)
+12V
10
INT
IN
EST_IN/AOUT 11
12
14 +V
CCP2
GNDA
13
RESET
SDA
tVD;DAT
tSU;STO
gue 1. Diagram for SerialBus Timing
Rev. 2 | Page 4 of 22 | www.onsemi.com
940
N
um
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Description
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tachometer input.
6
F
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2
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.
l
i
tachometer input.
7
C
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t
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ac
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prnimum 20 ms pulse on this line,
e
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s of he powered state of
the ADM9240. The ADM9240 provides an internal oper in on this lincony
i
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8
G
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gital circuitry.
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t (open drain) The ut is enabled when Bit 1 of the
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atis disale.
analog output when NAD Tree is not sele
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p
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A
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e
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on
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ree testing. Also functions as a pro-
m
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et).
Analog Ground. Internally connected to all analog circuiThe efereall
inputs.
o
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on
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x
te
r
n
al
r
e
si
s
t
o
r
s
.
1
5
+
1
2
V
nput Monitors +12 V supply.
V
nput. Monitors +5 supply.
.
3
V
u
t
M
o
n
i
t
o
r
s
+
3
.
3
V
s
u
p
p
ly
.
5
I
n
p
u
t
M
on
i
t
o
r
s
+
2
.
5
V
s
u
p
p
ly
.
o
I
n
p
u
t
M
on
i
t
o
r
s
p
r
o
c
e
s
s
o
r
c
o
r
e
v
o
l
t
a
g
e
+
V
V
)
.
Digital nut. Core Voltage ID readouts from theprocessor.Thisvalue is read into the
tatus Register
2
1
g
i
t
a
l
I
n
p
u
t
.
C
o
r
e
agouts theprocessor. This value is read into the
–
V
D
i
I
n
ore Voltage IDreadoutsfromvue is rad into the
–
V
V
I
D
1
i
I
n
ore Voltage IDreadoutsfromvue is rad into the
–
V
V
I
D
0
i
I
n
o
r
e
V
o
l
t
a
g
e
I
D
r
e
a
d
o
ut
s
f
r
o
mv
u
e
i
s
r
a
d
i
n
t
o
th
e
egister.
Rev. 2 | Page 5 of 22 | www.onsemi.com
940
N
E
R
A
L
D
E
S
C
R
I
P
T
I
O
N
er is given in Tables V to XVII.
RGTERS OF THE ADM9240
A
D
0
a
c
m
l
e
t
e
s
y
s
t
e
m
h
a
r
d
w
a
r
e
m
on
i
t
o
r
f
b
r
9
2
4
0
’
s
p
r
i
n
c
i
p
a
l
i
n
t
ern
a
l
r
e
g
i
s
-
o
p
r
o
c
s
-
a
s
o
m
n
e s
ic
th
e AD24
c
a
e
o
r
e
d
e
t
a
i
l
e
d
i
n
f
o
r
m
a
t
i
o
n
o
n
th
e
f
un
c
t
ion
t
(
(
e
s
y
s
t
e
m
i
a
a
e
r
i
a
S
y
t
e
m
ag
e
m
e
n
t
B
u
s.
T
h
e
r
i
a
l
b
u
s
r
o
l
l
e
r
a
s
tw
h
a
d
w
re
d
ss
l
i
n
e
s
fo
r
d
ev
lection
ation Register: trol and configurat.
n
d
a
s
e
r
i
a
d
a
t
f
o
r
r
e
a
d
i
n
g
a
w
r
g
es the serial bus address of the
a (Pi3), and aninput line for eserialclock
240.
A
l
on
g
f
u
n
are performed overtheserialbus.
d
r
e
s
s
P
o
Contain the address that selects
oth
e
r
s
.
e
n
w
r
i
t
i
n
g
to
t
h
e
A
D
M9
2
4
0
,
A
n
i
p
a
n
a
l
g
-
to-
d
ig
ta
l
r
t
e
r
w
it
h
s
i
x
m
u
d
e
f
i
r
s
t
e
d
a
t
a
is
a
l
w
a
y
s
a
r
e
g
i
s
t
e
r
a
d
d
r
e
ss,
w
h
i
ch
i
s
w
r
i
t
t
e
n
a
n
n
p
t
s
m
s
u
r
s
p
e
r
ly
v
o
l
ta
g
e
s (+12 +5V,
r
ointer Register.
+
3
.
3
V
5
V
P
i
n
1
5
t
o
1
d
p
r
o
c
e
s
s
o
c
o
r
e
v
o
s
(
+
n
+
V
NT) Status Registers: o regi
input from an on-chip bandgap temperaturesensorthat moni-
each Interrupt event
ttors system ambient temperature.
t (NT) MasRegisters: Allow masking of indi-
T
w
o
c
o
u
n
t
i
n
p
u
t
s
(
P
i
n
s
5
a
n
d
6
)
a
r
e
p
r
o
v
i
d
e
d
f
o
r
m
o
fans with different speedsand different toutp
Interrupsources
C
o
n
f
i
g
u
r
a
t
i
on
R
e
g
i
s
t
er
:
m er
perature interrupt is controlled by the lowthreebitsof
register.
Five npPins 20 to 24) readthe
n one othese reisters
visor Registers: atus of the VID0 to VID4
p
r
o
c
e
s
s
o
r
V
o
l
t
a
g
e
I
D
c
o
d
e
,
w
h
i
l
e
a
c
h
a
s
s
i
s
of the processor can be written to and read fmthese
ro
(
P
i
n
7
)
i
o
v
i
d
e
d
t
o
d
e
t
e
c
t
u
n
a
u
t
h
o
r
i
z
e
d
t
a
m
p
e
r
i
n
g
w
i
he
sters. Divisor values for an-speed measurement arealso
equipment.
W
h
e
n
t
h
e
A
D
M
9
2
4
0
m
on
i
t
o
r
i
n
g
s
e
q
u
e
n
c
e
i
s
s
t
a
r
t
e
d
,
i
t
u
n s
th
ea
it
ge
e registers, along with their limit values.
t
e
g
i
s
t
e
r
s
:
s
o
f
a
n
a
s
e
q
n
t
o
f
o
g
n
p
d the
, temperature and fan speed measurements are storedin
t
e
m
e
s
e
n
s
o
r
,
w
h
i
l
e
a
t
t
t
h
e
f
a
inputs
are independently monitored. Measured values from
utput Regster: The code conng the analog
p
u
a
l
e
g
.
T
h
e
s
e
c
a
n
b
e
r
t over the
DAC is stored in this register.
serial us, or can be comparedwith programmed lim
i
n
e
r
e
s
u
of
ou
t-o
f
-
l
im
i
t c
o
isons are
s n C ea
I
t
r
u
s
i
on
l
r
R
e
g
i
s
t
e
r
:
s
t
o
d
i
n
t
e
r
r
u
p
t
s
t
a
t
u
s
r
e
g
is
te
r
s
a
n
d
w
i
l
t
iner-
s intrusion pin can be cleared by writing to thisregister.
r
u
t
h
e
I
N
10)
Any or all of theInterrupt Status Bits can be maske
priate programming ofthe Interrupt ask Register.
A
R
E
S
E
i
n
p
u
t
/
o
u
t
p
u
t (Pin 12) is provided. Pulling this pin
l
o
w
w
i
l
l
r
e
s
e
t
a
l
l
A
D
M9
2
4
0
i
n
t
e
r
n
a
l
r
e
g
i
s
t
e
r
s
to
d
ef
values.
The ADM9240 can also be programmedtogivea low-g
oi
20 ms reset pulse at is
T
h
e
A
D
M
9
2
4
0
c
o
n
t
a
i
n
s
a
n
o
n
-
c
h
i
p
,
8bit digital-to-an
-
c
o
g
e
o
t
o
1
.
2
5
V
(
Pi
n
1
1
)
.
T
h
i
s
i
s
t
r
l
fan by
c
o
n
d
e
n
t
u
p
o
n
th
e
t
e
erature
measp
T
e
o
f
b
o
a
r
d
l
e
v
e
l
c
o
n
n
e
c
t
i
v
i
t
y
i
s
s
by providing a
N
A
f
i
o
also doubles as
a
NA
t input, whilePin 1 doubles as a NAND treeoutput.
Rev. 2 | Page 6 of 22 | www.onsemi.com
9240
A
L
B
U
S
I
N
T
E
R
F
A
C
E
line mu
t
4
0
is
c
a
r
r
i
e
d
o
u
t
v
i
a
t
h
e
s
e
r
i
al
b
u
s
.
T
h
e
n the low period of the clock signal and
d
o
e
d
e
n
d
e
s
a
l
o
w
-
t
o
-
h
i
g
h
t
r
a
on
i
c
e
,
g
.
,
t
h
e
P
I
I
X
4
.
l
o
i
s
g
h
e
r
a
t
a
y
t
e
s
t
t
r
a
n
s
m
i
t
t
e
d
e
a 7-bit sebus address. When t e
b
in a single READ or WRITE operation is mited
e
d
u
i
t
w
i
l
l
d
o
s
o
w
i
t
h
a
d
e
f
a
u
l
t
s
e
r
i
a
l
dre
at
SBs of the address are set to 01011, thwoLSBs
e
d
e
t
e
r
m
i
n
e
d
b
y
t
h
e
l
o
g
i
c
a
l
s
t
a
t
e
s
o
f
P
i
n
1
(
N
T
E
S
T
_
O
U
T
/
A
0
)
W
h
e
n
a
l
l
bytes have been read or written, stop condi-
2
(
A
w
e
.
T
h
e
s
e
p
i
n
s
h
a
v
e
i
n
t
e
r
n
a
l
Ω
establisheIWRde, the masterwi
p
u
y
e
d
e
f
a
u
l
t
e data line high duringthetenth clock pulse to ssert a
a
d
s
w
i
ll
be
0
1
0
1
1
0
0
.
condition. In READ mode, the master device will
e
r
r
i
d
e
h
e
a
c
k
n
ow
l
e
d
g
e
b
i
t
b
y
p
u
l
l
i
n
g
t
h
e
d
a
t
a
l
in
. T
e t
e
h
i
g
h
T
h
e
e
d
c
h
a
n
g
e
s
t
o
A
1
a
n
d
A
0
e ADM9240 hasbeenpoweredup,thefiveMS
he
th
e
lo
w
p
e
r
o
d
b
e
f
o
r
e
th
e
n
in
t
h
c
lo
c
k
p
u
ls
e
hi
s
is
u
s
a
s
N
o
A
c
kn
ow
le
d
g
e.
T
h
e
m
a
s
te
r
w
il
l
t
h
e
n
t
a
k
h
e
b
u
e
l
o
w
d
u
r
i
n
g
t
h
e
lo
w
p
e
r
io
d
b
ef
o
r
e
t
he
t
e
nth
c
l
o
c
k
h
e
n
h
i
g
h
d
u
r
i
n
g
t
h
e
t
e
n
t
h
c
l
o
c
k
p
u
l
s
e
t
o
a
ss
e
r
t
a
o
f
ial bus address may bechanged bywritinga 7-bit word
condition.
t
o
e
r
t
h
ti
f
0
e
o
v
e
r
w
r
i
t
t
e
n
)
.
T
h
e
r
e
a
f
t
e
r
,
t
h
e
n
n
m
b
e
r
o
f
b
y
t
e
s
o
f
d
a
t
a
m
a
y
b
e
t
r
a
n
s
f
e
r
r
e
d
o
v
e
r t
h
e
s
e
r
i
a
l
u
e
s
o
t
h
e
A
D
M
4
0
,
u
n
l
it
is
o
n
e
op
e
r
a
t
i
on
,
b
u
t
it
i
s
no
t
o
ss
i
b
l
e
to
m
i
x r
e
a
d
a
n
d
w
r
i
t
e
h
a
o
r
t
d
e
i
s
p
o
w
e
r
e
d
o
f
f
.
o
p
e
r
a
t
i
o
n,
b
e
c
au
se
t
h
e
ty
p
e
o
f
o
p
e
r
a
t
i
on
i
s d
e
t
er
m
in
e
d
a
t
ginning and cannot subsequently be changed witho
h
tocol operates as follows:
n
g
a
n
ew
o
p
e
r
a
t
i
on
.
1
.
m
a
s
t
i
a
n
s
f
e
r
b
h
i
n
th
in
ll
et
RT
te following functions:
c
a
s
e
o
f
t
e
A
D
M
9
2
4
0
,
w
r
i
t
e
o
p
e
r
a
t
i
o
n
s
c
o
n
t
a
in
e
i
t
h
e
r
n
d
o
n
ria
t
w
o
y
t
e
s
,
a
n
r
e
a
d
o
p
e
ra
t
i
o
ns
c
on
t
a
i
n
on
e
by
t
e
a
n
d
t
a
l
i
n
S
D
A
w
h
i
l
e
t
h
e
s
e
r
i
a
l
c
l
o
c
k
l
i
n
e
S
C
L
r
e
m
a
s
gh.
am
w
i
l
l
o
l
p
p
h
e
r
a
l
s
o
c
t
e
t
o
t
h
e
s
e
r
i
a
l
b
u
s
r
e
s
p
o
t
h
e
d
a
t
a
t
o
o
n
e
o
f
t
h
e
d
e
v
i
c
e
d
a
t
a
r
e
g
i
s
t
e
r
s
or
so
be
a w
r
e
a
d
d
a
t
a
s
h
i
f
t
i
n
t
h
e
n
e
x
t
e
i
g
h
t
b
i
t
s
,
t
h
e
dd
re
ss
Po
in
t
e
r
R
e
g
i
s
te
r
mu
s
t
b
e
s
e
t
t
h
a
t
t
h
e
a
7
-
b
a
d
d
e
s
s
(
n
p
lu
s
a
n
/
h
d
e
t
e
r-
t
d
a
t
a
re
i
s
t
e
r
i
s
a
d
d
r
es
s
e
d
,
th
e
n
d
a
ta
c
a
n
w
r
i
tt
en
i
n
t
o
t
d
i
r
c
t
i
h
e
d
a
ta
tr
a
n
s
f
e
r
i
.
e
.
,
w
h
d
a
t
a
e
g
i
s
te
r
o
r
re
a
d
f
ro
m
i
t
.
T
h
e
f
i
r
s
t
b
yt
e
o
f
r
it
e
o
p
e
ra
t
i
on
i
t
o
r
r
e
a
d
f
r
o
m
t
h
e
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l
a
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e
d
e
v
i
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e
.
c
o
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ta
i
n
s
a
n
a
d
d
r
e
s
s
t
h
a
t
is
st
o
r
e
d
i
n
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h
e
A
dd
r
e
s
s
P
o
i
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te
r
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e
r
.
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f
d
a
ta
is
t
o
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e
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t
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t
o
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e
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e
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i
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e
,
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en
t
h
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r
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r
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e
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e
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r
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A
d
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R
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. This is followed by two data
R
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.
s thbe wr
data register
i
a
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o
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f data followed by an acknowledgebit
1
9
9
1
SCL
SDA
D6
D2
0
1
0
1
1
A1
A0
R/
D7
D5
D4
D3
D1
D0
START BY
MASTER
ACK. BY
ADM9240
ACK. BY
ADM9240
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
D2
SDA (CONTINUED)
D5
D4
D3
D1
D0
D7
D6
ACK. BY STOP BY
ADM9240 MASTER
FRAME 3
DATA BYTE
gue a. Writg a egsteddress to the Address oter Regster, ten Writing Data to the Selected Register
Rev. 2 | Page 7 of 22 | www.onsemi.com
940
e
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o
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2
.
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n
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r
to 2c, the serial bus address is shwe
lue 01011(A1)(A0),whereA1andA0are
t
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.
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A read operation is thenperformedconsistingofthe erial
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alog-to-digital erThis has
b
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s
followed bythedata byteread
t
o
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e measure-
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2
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A
a
data register without first writing to the
dy at the
0
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V, and the power supply inputs are scaledbyon-
a
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s
,
d
be read from the correspo
i
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nom
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-
Reigure 2b can beomitted.
l
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a
c
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neefor precision external resistors.
Notes:
1
.
A
l
o
u
e ead ta byte from a data re
w
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if the
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n
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the
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, beusthe first data byt of a
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1
9
1
9
SCL
SDA
D
0
1
0
1
A0
R/ W
D7
D3
D2
D1
1
A1
D5
D0
START BY
MASTER
ACK.
AD40
ACK. BY
ADM9240
STOP BY
MASTER
FRE 1
SL BUS DDRESS BYTE
FRAME 2
DRESS POINTER REGISTER BYTE
gue b. Writing to the Adress Pointer Register only
1
9
1
9
SCL
D6
D5
D0
0
1
0
1
A0
D7
D4
D3
D2
D1
SDA
START BY
1
A1
W
ACK. BY
ADM9240
NO ACK.
STOP BY
MASTER
BY MASTER MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADM9240
gue c. Reading ata oa eousy Selected Registe
Rev. 2 | Page 8 of 22 | www.onsemi.com
9240
42.7k
97.3k
input rangesoftheanaloginputsareshownine deil
+V
CCP2
+12V
50pF
35pF
d +Vinputs are used to measure pr
+
V
122.2k
c
o
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e
v
o
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t
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s
,
a
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it
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t
22.7k
be used to monitorthe–12Vsupply.This
91.6k
55.2k
u
s
e
s
i
s
t
di
+5V
s
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.
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h
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F
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.
25pF
25pF
25pF
MUX
PU
61.1k
80.9k
+3.3V
+2.5V
internal structure for the analoginputsis shon
Each input circuisists of aninputprotection diode, an
a
f
i
s
t
o
r
e
r-pass fi
36.7k⍀
givethe input immunity tohighfrequencynoise
112k
42.7k
97.3k
+
CP1
50pF
gure 3. Internal Structure of Analog Inputs
V
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Rev. 2 | Page 9 of 22 | www.onsemi.com
⍀
940
I
G
O
T
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R
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P
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A
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E
S
the 5 V supply increases theADCinput by the DV × R
a
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e
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e v
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e
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the A
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ly
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s
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is to
r, as mentioned earlier.
a
i
u
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tor
input rnges can e obtained.
c
a
n
b
e
a
p
ther unused i
voltage
l
e
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atter of
g an input with a lower full scale than the vo
dd g an external input attenuator, tbearin
E MEASUREMENT SYSTEM
i
n
p
u
s
i
s
t
a
n
t
n-chip attenua-
contains an on-chip bandgap temperature se
r
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i
t
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e
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e
or
s
o
r
.
T
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-
c
h
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p
ADC
p
e
r
f
o
r
m
s
9
-
b
i
t
c
o
n
v
e
r
s
i
on
s
on t
h
e
ou
t
p
u
t
l
a
o
n
,
b
u
t
h
t
t
e
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u
esis-
o
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a
n
d
ou
t
p
u
t
s
t
h
e
t
e
m
p
e
r
a
t
u
r
e
d
a
t
a
i
n 9
ca
bi
om
fr
s 4
-
b
i
t
t
wo
s
r
s
a
r
e
n
t
e
m
e
r
a
t
r
e
.
efore, the
c
o
o
r
m
a
t,
b
u
t
on
ly
h
e
e
i
g
h
t
mo
st
s
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f
i
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b
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a
r
e
e
t
t
e
r
n
s
o
u
ave a much lower outputresist
u
s
e
r
a
t
u
r
e
li
m
i
t
c
o
m
p
ar
is
o
n
.
T
h
e
fu
ll
9
-
t
te
m
p
e
ra-
n
i
z
e
t
h
e
l
o
a
d
g
.
I
f
t
h
is
i
s
no
t
c
ce
p
a
b
le
,
e
r
l
i
-
t
u
b
e
o
b
t
a
i
n
e
d
b
y
r
e
a
di
n
g
t
h
e
8
M
S
B
s
f
r
t
h
e
T
e
m-
f
I
t
sto measure a –12Vinput.Using
p
e
e
Re
g
i
s
t
er
(
f
A
d
d
r
e
s
s
2
7
h
)
a
n
d
t
h
e
L
S
B
o
m
B
i
t
7
t
t
i
m
u
o
n
v
e
r
t
ed
o
f
r
a
t
u
re
Co
n
i
gu
r
a
t
ion
R
e
i
st
e
r
(
A
d
d
re
s
B
h
)
.
a
p
o
s
i
t
e
l
t
e
.
h
e
t
o
d
t
h
i
s
t
T
h
o
f
t
h
e
t
e
m
p
e
r
a
t
u
r
e
d
a
t
a
is
s
h
own
in
T
a
b
le
I
I
.
T
h
e
o
-
r
e
c
a
l
l
y
,
t
h
e
t
e
m
p
e
r
a
t
u
r
e
s
e
n
s
o
r
a
n
d
ADC
c
a
n
m
e
a
s
ur
e
te
m-
o
w
s
t
h
e
+
V
s
p
e
r
e
s
f
rom
–
1
2
8
C
1
2
7
C
a resolution of 0.5
the values shown, the input rangeiszeroto–13.5Vwhich will
a
t
e
m
p
e
ra
t
u
r
e
s
b
e
l
ow
–
4
0
e +12 C are
aacate a +12.5% tolerance on the nominal value.
outs e the operating temperaure range of the deve.
+5V
blII
R2
1k
R1
2.7k
+V
CCP2
–13.2V TO 0V IN
1
R3
39k⍀
–
1
C
1
140⍀
0V TO 3.6V
–
1
1
1 01101010
gue 4. Scalig VCCto (+10%)
–
5
C
1 1001 1100
–
2
5
C
1 1100 1110
–
0
.
5
C
1 1111 1111
calculated as follows:
0
C
0 0000 0000
=
+
0
.
5
C
0 0000 000
+
1
0
C
0 0001 01
(
t
o
g
i
v
e
z
e
r
o
v
o
l
t
s
a
t
t
h
e
i
n
p
u
t
f
o
r
t
h
e
m
o
s
t
n
e
g
a
t
i
u
e
o
f
V–.
+
C
0 0011 00
f
c
t
n
d
i
s
o
i
s
t
h
e
v
o
l
t
a
g
e
it is
+
0 0110 01
+
0 1001 01
+
0
0
1
1
allel
+
5
0
1
1
1
1
1
11
o
l
g
e
e
i
n
u
t
n
te normal full-scale voltageoftheinputused).
T VALUES
a simple and cheap solution, butthefollowing points
alog me
soute
. n the case of voltage meas
the inpuvoltage to fall and givealoweroutputce fr
e
i
n
p
u
s
i
t
i
n
v
e
r
t
c
mag-
e
d
s
o
t
h
a
t
a
t
e
r
r
u
e
n
the –12Vsupply (going more negative), wi
d
e goes above or belocceptable
e of temperature, a Hot TemperateLimit
the ADC. Cona decrease in the magnitude ofthe
b
e
p
r
o
g
r
a
m
m
e
d
,
a
n
d
a
H
o
t
T
e
m
p
e
r
a
t
u
r
e
H
y
s
t
e
r
e
s
i
s
t,
2 V w u Th
p
p
l
y
i
l
l
c
a
s
e
t
h
e
A
D
C
c
o
d
e
to
i
n
c
r
e
a
s
e
.
usually be sodegrees lower. This can e us
at tand lower limitswillbetrans
e systto be shut down when thehotl
e offset voltage isderived fromthe+5Vly,
d when it has coo
is supply will affect the ADC code.
f
e
t
perature.
o oo-
e
r
e
f
r
e
a
g
d
i
d
e
a
t
o
r
e
a
d
t
h
e
v
a
l
u
e
of
th
ust the –12Vsupplyaccord
j
5
V
s
u
p
p
l
y
i
s
a
t
t
e
n
u
a
t
e
d
b
y
a
f
a
c
t
o
r
R
(
e parallel cation R1 and R3. An increase in
+
R
Rev. 2 | Page 10 of 22 | www.onsemi.com
940
NITORING CYCLE TIME
e Con-
If the op amp is powered from –12 V, precautionssuc
m
o
n
i
t
o
r
i
n
g
c
y
c
b
e
g
en a one iswrittento t
c
l
n
d
m
a
y
b
e
n
e
e
d
e
t
o
p
r
e
v
e
base-
V
n
d
a
z
e
r
o
t
o
t
h
e
e
m
i
t
t
e
r
j
u
o
t
r
a
n
ased in the
t
i
nable (Bit 1)should besettooneto
u
n
l
i
k
e
l
y
h
a
e
swin
A
t
i
ny reason.
,
s
t
a
r
t
and finishing withtheon-chiptem-
T
h
e
p
o
s
i
t
i
v
e
t swing of the op amp should be as c se t
is compted he result
+
1
2
V
a
s
h
a
l
t
e
e
e
from the t nsistor. Even if the op amp swings to he rail, the
d
-
r
o
b
i
n
”
m
o
n
i
t
o
r
i
n
g
c
y
c
l
e
c
t
m
a
x
i
m
u
l
t
a
g
e
f
r
o
m
t
r ill
i
t
to Bit 0 oftheConfigurationRegister.
about 11.4 V. typical values for this condition wodbe:
counter controlling the multiplexer is driveb
n actual gain of 9.2
11.4/1.25 = 9.12 = 1 + R
milly 22.5 kHz,sotheentiremeasurement
= 10 preferred valu
g
i
v
i
7 =
T
ha
n
s
i
s
t
o
r
s
h
ou
l
d
h
a
v
e
a
r
e
a
s
o
n
a
b
l
y
h
i
g
h
void its
chithat employ slower ADCs.
s
a
m
p
l
i
n
se urrent pulling down the output of the op amp, it must
s
s
e
v
e
ater than thmum fan current and be
m
X450
o
f
d
i
s
s
i
p
a
t
i
n
g
p
o
w
e
r
d
u
e
t
o
t
h
e
v
o
l
t
a
g
e
d
r
op
p
e
d
a
c
r
o
s
s
i
t
When a monitorin cycle is started, monitoringofthe fan speed
h
e
f
a
n
i
s
n
o
t
o
p
e
r
a
ti
n
g
a
t
f
u
l
l
s
p
e
e
d
.
D
e
p
e
ndin
g
on
t
h
e
i
i
n
a
t
a
s
m
o
n
i
t
o
r
i
n
g
o
f
t
h
e
e a
in-
meters, some suitable devices would be 2N2219A,
p
i
n
g
c
y
c
l
e
s
a
r
e
n
o
t
s
y
zed
i
w
a
y
,
a
n
d
t
h
e
m
o
ni
t
o
r
i
n
g
c
y
c
l
e
t
i
m
e
f
o
r
t
h
e
f
a
n
i
n
p
u
t
s
is
d
e
d
s
l
t
n
f
o
r
t
h
n
+12V
i
n
p
F
o
r
mo
r
e
d
e
t
a
i
l
s
s
e
e
t
h
e
F
a
n
S
p
e
e
d
a
s
u
r
e
m
e
ec on.
TEST_IN/AOU
PUSAFETY
R1
g
i
n
p
u
t
s
d
o
n-
c
h
i
p
, s
nc
pi
or
on
rnal
o
w
e
v
e
r
,
s
e
R2
w
e
v
o
l
t
a
a
t
t
h
e
,
i
t
i
s
a
d
v
i
s
-
s
m
a
l
l
es
w
i
t
h
pply
a
c
e
t
r
a
c
e
s
p
o
w
e
r
u
p
p
ro
e
c
n
e
two
w
e
s
u
p
p
l
i
gue 5. aog Output Driving Fan
suible.
rm part of the input attentoewill
ua
he
d a g an
t
he
a
n
a
l
o
g
m
e
a
s
u
r
e
m
e
n
t
i
f
t
value is
YOUT AND GROUNDING
o
h
i
.
T
h
e
a
n
a
l
o
g
i
n
p
ut
c
h
a
nn
e
l
s
a
r
e
c
a
l
i
b
r
a
t
e
s
s
r
e
0
e
a
c
cy will remain
G
A
s
e
p
a
r
a
t
e
,
l
o
w
i
m
p
e
d
a
n
c
e
g
r
n
d
r analog
or any valuefromzeroto 1 ktan-
the voltag divi
1
s
,
w
i
l
l
p
r
o
v
i
d
e
b
e
s
t
p
e
r
f
o
r
m
a
e
i
m
a
n
d
a
t
y.
w
o
r
s
t
s
u
c
h
a
c
c
i
d
e
n
t
w
o
u
l
d
b
e
c
o
nn
e
c
t
i
n
g
–
1
2
V
to
t
o
t
a
l
o
f
2
4
V
d
i
f
f
e
r
e
n
c
e
,
w
i
t
h
t
h
e
se
r
i
e
s
r
e
s
i
s
t
or
s
w
p
o
w
e
r
a
s
1F
a maximumcurrent ofapproximately 24 mA.
se s possible to the ADM9240.
a
0.1 (cer
r
s
cted between Pin 9 and ground, should alsbe lo
er-on resewhic
AL
A
D
0
h
a
s
a
s
i
n
g
l
e
a
n
a
l
o
g
o
u
t
p
u
t
f
r
o
m
a
n
u
n
s
i
buffered with external circuitry such as an op amp nd tns
8
-
b
i
The analogout ut
s
u
f
a
n
l
o
g
o
u
t
p
u
t
m
a
y
b
e
a
m
p
l
i
f
i
d
to provide fan speed con
A
s
u
i
t
a
b
l
e
n
re 5.
e
re that its
t
T
h
e
o
p
a
m
p
m
a
y
b
e
p
o
w
e
r
e
d
f
r
o
m
t
h
e
+
1
2
V
r
a
i
l
a
l
o
n
e
1
V
i
t
s
p
e
r
e
d
f
m
1
2
V
t
h
e
n
t
h
e
i
n
p
u
t
c
o
n-
m
e
g
e
s
l
i
nn
d
t
o
a
c
c
o
m
m
mini-
mum outputvoltage oftheDAC,andtheoutputvoltage should
swing below 0.6 Vtoensurethatthetransistorcanbe ned
fulloff.
Rev. 2 | Page 11 of 22 | www.onsemi.com
940
N INPU
V
+12V
CC
ts re rovide oncondition of cooling
S
i
ing in the ADM9240 accommodatesthe
< 1k⍀
i
s
a
n
d
f
a
l
l
t
t
i
c
chometer utputs. The
FAN1
OR FAN2
R1*
x
i
m
u
m
i
n
s
i
g
n
al
r
a
n
g
e
is
0
to
V
I
n
that th
FAN SPEED
COUNTER
t
s
a
r
e
s
d
f
r
om
f
a
n
o
u
t
p
u
t
s
t
h
a
t
e
x
c
e
e
d
o
TACHO
OUTPUT
R2*
ei er resisti
m
u
s
t
i
n
c
l
t
o
k
e
e
p
n
a
c
ange.
*SEE TEXT
F
i
s how uits fosmman tach
ou uts.
gure 6d. awitStog Tachometer Pull-Up to
>VCC ootem-Pole Output, Attenuated with R1/R2
I
u
t
p
u
a
r
e
s
i
s
t
n be
n
n
t
h
s shown inFigure 6a.
T LITING
+12V
V
CC
t
s
a
r
e
p
o
w
e
r
e
d
w
h
i
l
e
t
h
e
A
DM
9
2
4
0
i
s
un
p
ow
er
e
d
,
t
h
e
i
n
t
s
o
f
t
h
e
A
D
M
9
2
4
0
w
i
l
l
t
r
y
t
o
c
l
a
m
p
th
e
fa
n
ou
tpu
t
v
o
lt
-
PULL-UP
4.7k⍀
t
h
i
s
c
a
se
t
he
i
n
p
u
t
c
u
r
r
e
n
t
mu
st
b
e
l
im
i
t
e
d to
le
ss
th
a
n
FAN1
OR FAN2
TYP.
FAN SPEED
COUNTER
h
mum value in the Absolute Maximum Ratings ble.
ta
TACHO
OUTPUT
h
l
l
-
u
p
r
e
si
s
t
or
of
t
h
e
f
a
n
ta
ch
o
ou
tp
u
t
m
a
y
p
ro
v
i
d
e
t
s
u
t
l
im
it
i
n
g
b
u
t
,
if
i
t
s
v
a
l
u
e
i
s
too
lo
w
,
i
t
ma
y
b
e
n
e
c
e
s
s
a
r
y
o
a
d
d
it
i
o
na
l
r
e
s
i
s
t
a
n
c
e
in
se
r
i
e
s
w
i
t
h
t
h
e
fa
n in
p
u
t
p
i
n
s
.
gue 6a. FanwithTachometerPull-Up to +VCC
V
lt
ess than
t
h
e
f
a
n
o
u
t
r
e
s
i
(
other
N EN
g
r
e
a
e
r
t
h
a
n
the fan outputcanbeclamped wit
ter does not count the fan tacho output
a Zener diode, asshowninFigure6b.TheZener vo
d
i
c
t
ly
,
b
e
c
a
u
s
e
t
e
f
a
n
s
p
e
e
d
m
ay
b
e
l
e
ss
t
h
a
n
1
00
on
n r
0
rp
m
a
n
d
s
h
b
e
c
o
s
e
n
s
i
t
i
s
g
r
e
a
t
e
r
t
h
a
n
V
t
a
ke
s
e
v
e
r
a
s
e
c
on
d
s
to
a
c
c
um
u
l
a
te
a
r
e
as
ab
ly
la
rg
e
t
Z
e
n
er.
f
c
u
r
a
t
e
c
o
un
t
I
n
s
t
e
a
d
,
t
h
e
pe
r
i
o
d
o
f
t
h
e
f
a
ev
o
lu
t
ion
i
s
a
b
0
.
8
×
ed by gang an on-chip 22.5 kHz oscillator intothe
+12V
CC
of an 8-bit counter for two periods of the fantachoout-
*CHOOSE ZD1 VOLTAGE APPROX. 0.8 V
shown in Figure 7, so the accumulated count isactually
PULL-UP
onal to the fan tacho period and inversely proportional
FAN
OR FA2
TACHO
OUTPUT
4.7k⍀
fan speed
TYP.
FAN SPEED
CUNTER
oring cycle begins when a one is written tothestart
ZD1*
ZENE
b
i
i
t
0
)
,
a
n
d
a
z
e
r
o
t-but
h
e I
N
_
C
l
e
a
r
b
i
t
it 3) of the Con-
o
n
R
e
g
i
s
t
e
r
b
l
o
gue 6b. Fan withTachometer Pull-Up to Voltage >VCC
(e.g., ) Caped with Zener Diode
h
e
u
t
u
t
.
T
b
s
the rising
f
a
t
a
c
h
o
p
u
e
,
a
n
d
e
n
e
d
he fan speeds have been measured, they
tp
(
l
e
s
s
t
h
a
n
1
kΩ
)
t
o
V, or a
e
F
e
a
d
at
a
ny
t
t
i
s
t
o
r
c
a
n
b
e
a
d
d
the
t
i
T
h
e
m
p
d
a
t
e
d
as
l
o
n
g
as
th
e
m
o
n
i
-
z
e
n
e
r
s
s
h
o
w
n
i
n
F
i
g
u
r
e
6
c
.
A
l
t
e
r
na
t
i
v
e
l
y
res tive
toring cynues.
a
t
t
e
n
u
be used, as in Figure 6d.
R1 and
22.5kHz
CLOCK
+
+
t
h
e
v
a
l
u
e
e pull
CONFIG
REG. BIT 0
a
d
e
rge, but not so large that
i
n
p
u
t
l
e
a
k
e current will cause a largevoltagedrop ac
FAN1
INPUT
them.
With a pull-up voltage of12 Vandpull-upresistorlen
FAN2
INPUT
1
k
Ω
,
s
u
i
t
a
b
l
e
v
a
l
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e
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o
r
R
1
a
n
d
R
2
w
o
u
l
d
b
e
1
0
0
k
Ω
and
FAN1
MEASUREMENT
PERIOD
FAN2
MEASUREMENT
PERIOD
+12V
V
CC
*CHOOSE ZD1 VOLTAGE APPROX. 0.8 V
CC
START OF
FAN1
TACHO
MONITORING
CYCLE
OR FAN2
OUTPUT
FAN SPEED
COUNTER
PULL-UP
TYP. < 1k⍀
OR TOTEM-POLE
R1
10k⍀
ZD1*
ZENER
gue 7. Fan Speed easurement
gue 6c. Fan withStrong TachometerPull-Up to
>VCC oote-oe Output, Clamped with Zener and
Resistor
Rev. 2 | Page 12 of 22 | www.onsemi.com
9240
N MANUFACTURERS
ate fanof differe/
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5–40
T
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f
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d
a
n
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t
i
m
e
p
e
r
e
v
o
l
u
t
i
70% and 100%ofnominalrpmforfan
M
e
atronis Inc.
s
p
e
e
r
, 2200 rpm, 4400rpmand8800rpm, and
P
.
13
the divisor that would be used for ean
Pr ton, WA 98050
two tacho pulses per r
0
0
-
M
o
l
s
—Various sizes available with tach output option.
I
I
I
.
and Divisors
Saynki/Keymarc Electronics
4
6
8
A
m
a
p
o
l
a
e.
Time per
70% Rev
Time per
60% Rev
Time per
60% Rev
(ms)
A 90501
Nominal
rpm
Divisor
(ms)
rpm
(ms)
rpm
M
o
ls—09P Series
1
2
4
8
8800
4400
2200
1100
6.82
6160
3080
1540
770
9.74
5280
26
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11.36
22.7
45.45
90.9
13.64
27.27
54.54
19.48
38.96
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SIN T
s
i
s
n
t
r
u
s
i
on
(
C
I
)
i
n
p
u
t
i
s
a
n
a
c
t
i
v
e
h
i
g
h i
g o
it
n
p
u
t
/
o
p
e
n-
n
o
u
t
p
ut
i
n
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e
n
d
e
d
fo
r
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te
c
ti
o
n
a
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ig
n
a
l
l
i
n
f
un
a
u
t
h
o-
t
a
m
p
e
r
i
n
g
w
i
t
h
t
h
e
s
y
s
t
e
m
.
A
n
e
x
te
r
n
a
l
ci
r
c
u
p
ow
e
re
d
Fan 1andFan2Divisors are programmed into s 4
o
m
system’s CMOS backup battery is used to detectand
o
f
t
h
e
V
I
D
0–VID3/Fan Divisor Register
h
a
c
h
a
i
s
n
t
r
u
s
i
on
e
v
e
n
t
,
w
h
e
t
h
e
r
t
h
e
s
y
s
t
e
m
i
s
p
o
w
e
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d
u
p
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ot
.
O
n
c
e
a
c
h
a
s
s
i
s
i
n
t
r
an
d
l
a
t
c
h
e
d,
limit value.
T VALUES
i
u
t
i
l
g
i
n
t
e
t
stm is pow-
e
n
e
l
w
i
l
l
n
ot
o
v
e
r
s
p
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e
d
i
f
r
un
fr
om
t
h
e
on
th
volt-
e
,
s
e
f
a
i
l
o
n
d
it
i
o
n
of
i
n
t
er
e
s
t
is
un
de
r
sp
e
e
d
u
e
to
foratleast 20 ms. Thesareself-clearing.
ac al of chassis intrusion is perfored y an
f
lu
r
e
.
F
o
r
th
is
re
as
on
o
w
s
p
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e
d
a
l
c
i
r
c
u
i
t
t
h
a
t
w
i
ll
,
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a
m
p
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e,
d
e
t
e
c
t
w
h
e
as
t
l
i
m
i
t
e
g
i
s
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e
fo
r
ans. It
es m
o
t
e
t
,
s
i
n
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e
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a
n
p
e
r
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o
d
r
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an
is being
e
i
n
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e
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w
i
l
l
o
c
cur
wh
e
n
asure
o
p
e
n
covs rd.
fi
NITORING CYCLE TIME
al
ring cycle time depend on the fanspeed and
t
o
t
r
a
n
s
i
c
t
s
g
h
v
s
r
ved.
o
u
p
u
o
l
u
t
i
o
n
.
T
w
o
c
o
m
p
l
ods
t
g
e
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e
s
)
a
r
e
r
each
a
l
d
e
t
e
c
t
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o
n
c
i
r
c
ui
t
is
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es
e
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.
T
hi
s
ca
n
b
e
a
c
i
e
v
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s
t
a
o
ent
it 6 of theConfiguration Register, or Bit the Chassi
t
m
e
a
s
u
r
e
m
e
c
a
n
t
a
k
three
to one, which will cause the CI pin to be
lid re
m
o
n
i
t
o
r
in
g
t
i
m
e
a
ll
ow
ed
a
f
t
er
e
o
ore be three tacho per ds
re tacho periodof FAN2 at the lowest
ee .
m
o
n
e analog input mon
t
o
g
e
t
h
e
r
,
t
h
e
y
n
y.
Rev. 2 | Page 13 of 22 | www.onsemi.com
940
V
r
i
input of N4, resetting the latc
c
h
a
s
i
n
t
r
u
s
n
that can
C
R1
w
.
A
s
u
i
t
a
b
l
e
c
h
a
s
s
i
s
cir-
10k⍀
CI
n
s
i
h
o
w
n
i
n
F
i
g
u
r
e
.
ight falling
AD22105
TEMP.
SENSOR
Q1
P
C
c
o
v
e
r
i
s
r
e
o
v
e
d
c
a
u
s
e
R
SET
placed, a low reset oheCIoutput
1N914
1N914
gue 8b. Using the CI put th a epeatue Seso
pr
+5V
CMOS
MRD901
BACKUP
t
e
:
T
h
e
c
h
a
s
s
i
s
i
n
t
r
u
s
i
o
n
i
n
p
u
t
d
o
e
s
n
o
t
h
a
v
e
a
ve
BATTERY
74HC132
c
l
a
100k
CI
470k
INTERRUPT STRUCTURE
I
t
e
r
r
u
p
t
S
t
r
u
c
t
u
r
e
of
t
h
e
A
D
M
9
2
4
0
is
sh
own
i
n F
i
g
u
r
e
9
.
A
s
a
c
h
m
e
a
s
u
r
e
m
e
n
t
v
a
l
u
e
i
s
o
b
t
a
i
n
e
d
a
n
d
s
t
o
r
e
d
i
n t
h
e
10k⍀
p
r
o
p
v
a
l
u
e
r
e
g
i
s
t
e
r
,
t
h
e
v
a
l
u
e
a
n
d
t
h
e
l
i
m
i
ts
f
r
o
m
t
h
e
o
n
d
i
n
g
l
i
m
i
t
r
e
g
i
s
t
e
r
s
a
r
e
f
e
d
to
t
h
e
h
i
g
h
an
d
l
o
w
l
i
m
it
o
r
s
.
T
h
e
r
e
s
u
l
t
of
ea
ch
c
o
m
p
a
r
i
s
o
n (1 = out oflimit,
=
n
i
m
i
t
)
i
s
r
o
u
t
e
d
t
o
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
b
i
t
i
np
u
t
o
f
t
h
e
r
r
u
p
t
S
t
at
us
R
e
g
i
s
t
e
r
s
v
i
a
a
d
a
a
d
e
mu
l
t
i
p
l
e
x
e
r an
d
u
se
d
t
o
t
h
a
t
b
i
t
h
i
g
h
or
low
as
a
p
p
r
o
p
r
i
a
t
e
.
gue 8a. Chassis IntrusioDetectoand Latch
is
T
h
terrupMask Registers have bits correspondingtoeachof
a
a
C
h
a
s
I
n
t
r
u
s
i
o
n
i
n
p
u
t
c
a
n
a
l
s
o
b
e
u
s
e
d
f
o
r
o
t
h
e
r
of
terrupt Status Regster Bits. Setting an IntruptMask Bit
er
w,
ndg Status
h
i
g
ors the corresponding Status Bit output lowhileset-
s
e
produces
t
i
a
n
I
n
t
e
r
r
u
t
M
a
s
k
B
i
t
low
a
l
l
ow
s
t
h
e
c
o
r
r
e
s
p
o
m
p
a
t
u
r
e
i
s
e
x
c
e
ed
,
the
Bit to be asserted. After masking, the status bits areallORed
e
i
t
o
m
p
a
t
i
b
le
w
i
t
h t
t
o
e
r
t
o
p
r
o
d
u
c
e
t
h
e I
N
output, which will pull low if
i
1 can be almost any small-signal Ntrans
u
n
ed status it goes high, i.e., when any measuredvalue
C
b
us
e
d
i
f
o
n
e
is
a
e. ee
g
o
out of limit.
t
e
A
D
2
2
1
0
5
d
a
t
a
s
h
e
e
t
o
rm
io
n
o
n
s
el
e
c
t
i
n
T
h
N
o
t is enabled when Bit 1 of the Configuration
R
e
s
t
er
(
_
E
n
a
b
l
e
)
i
s
h
i
g
h
,
a
n
d
B
i
t
3
N
T
_
C
l
e
a
r) is low.
V
CCP2
+12V
HIGH LIMIT
1 = OUT
OF LIMIT
+3.3V
FROM VALUE
AND LIMIT
+2.5V
+5V
VALUE
HIGH AND
LOW LIMIT
COMPARATORS
REGISTERS
DATA
IPLEXER
INTERRUPT
STATUS
+V
CCP1
LOW LIMIT
REGISTERS
TEMP
FAN1
FAN2
MASK GATING 10
STATUS
BIT
MASK
BIT
CI (CHASSIS INTRUSION)
INTERRUPT
MASK
REGISTERS
MASKING DATA
FROM BUS
INT_ENABLE
INT_CLEAR
CONFIGURATION
REGISTER
gue 9. teupt egster Structure
Rev. 2 | Page 14 of 22 | www.onsemi.com
940
CLEARING
e
l
T
a
t
i
m
ster will output the nts of
i
n
.
A
g
l be
e Regist , then clear it.Itwillremaincleareduntil themoni-
s
h
o
w
n
a
s
e
i
o
er han th
r
e next readoperationbe
o
r
egister until thishashappened,or the result
T
t
a
k
e
n
f
o
r
a
c
o
m
p
le
t
e
m
o
ni
T
HOT
ent on the time taken to measure th
s b
bitwhich is it
TEMP
o
f
t
h
e
C
o
n
f
i
r
a
t
i
o
n
ecti
T
HOTHYST
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t
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S
t
u
s
R
e
g
hen thiitishigh,
e ADM9240 monitoring loopwillstop.Itwillresu e when
NT
e biis l
EAD
REA
READ
READ
READ
READ
READ
ERATUREINTERRUPTMODES
e
a
r
e
r
,
t
w
o
m
i
t
v
a
l
u
e
s
c
a
n
b
e
r
m
m
e
d
o
r
gure 11. Output in One-Time Interrupt Mode
te
er
t
a
n
H
o
t
T
e
m
p
e
r
a
t
u
r
e
H
y
s
t
e
r
e
s
i
s
L
i
m
i
t
(
T
T
lustrated in Figure 12.
OD
d
e
g
r
e
e
s
l
o
w
e
r
.
i
n
g
t
h
e I
N
u
t
t
T
red. In other words, Comparator Mode operates likea
il
r
e
L
o
w
u
n
t
i
l
t
h
e
t
e
m
p
e
r
a
t
u
r
e
g
o
e
s
b
e
l
o
w
T
n
the
rator” mode.
t
e
r
r
u
p
t
f
u
n
c
t
i
t
h
e
t
e
m
p
e
r
a
t
u
r
e
s
e
f
f
m
a
t
u
r
e
g
o
e
s
b
e
l
o
w
T
will go Hig
t
faut
it
h
n
o
h
y
s
t
e
r
e
s
i
s
.
Oeration in the comparator
o
d
e
ULT INTERRUPTMODE
T
HO
c
e
i
n
g
T
will remain active
i
n
r
upt Status ister 1 or
r
e
t
I
T
_
C
l
e
a
r
b
i
t
i
n
t
h
e
C
o
n
f
i
g
u
r
a
t
i
on
r
e
i
s
t
e
r
.
e
n
I
n
t
e
v
e
n
t
h
a
s
o
c
c
urr
ed
b
y
c
r
o
s
s
i
n
g
T
in
T
at
rt
en
TEMP
n
I
n
t
e
r
r
u
p
t
w
i
l
l
o
c
c
u
r
ag
a
i
n
onc
e
t
h
e
n
e
x
t
re
e
r
s
i
o
n
h
a
s
c
o
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p
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e
t
e
d
.
T
h
e
i
n
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e
r
r
u
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w
i
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c
o
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t
u
e
t
o
o
cc
u
r
e
m
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r
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t
u
r
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g
o
e
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e
l
o
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n
i
n
t
h
e
a
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i
n
t
e
r
r
u
t
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d
e
i
s
i
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s
t
r
e
d
i
g
u
r
e
gue . T Output in Comparator Mode
F
r
c
l
a
r
i
t
y
,
i
n
t
h
i
s
i
l
l
u
s
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r
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t
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on
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h
e
i
n
te
r
v
a
l b
e
t
en read
a
i
o
n
s
i
s
s
h
o
w
n
a
s
c
o
n
s
i
d
e
r
a
b
l
y
lo
n
g
er
t
h
a
n
t
h
e
toring
INPUT/OUTPUT
i
e
i
n
t
e
r
r
u
p
is
a
l
wa
y
s
r
e
a
s
s
e
b
e
in
g
) is an I/Opinthatcanfunctionasanopen
r
e
s
e
efore the next read operation occurs.
t
p
ut ul
ra on Register is set to 1, pvide the reset
T
e
t
t
i
n
g
B
i
t
7
o
n
t
HOT
r
#
bit is automatically clre
e
r
p
u
l
s
e
i
s
o
u
t
p
u
t
.
P
i
n
11
c
a
n
a
l
s
o
f
u
n
c
t
i
o
s
a
T
TEMP
by pulling this pin low to reset the internae sters of the
0
t
o
d
e
f
a
u
l
t
v
a
l
u
e
o
s
r
e
g
i
a
e
d
values as listed in Table VI are fect
INT
C
r
e
g
i
s
t
e
r
,
V
a
lu
e
a
n
d
L
i
m
it
R
e
g
i
s
t
are not
READ
READ
READ
READ
READ
READ
READ
N
D
S
gue 10. Temperature Output Default Interrupt
Mode
e
ded in the ADM9240 for AutomatTest
ed
Pi
nv
m
e
n
t (ATE) boardlevelconnectivitytesting. T
NANTeode by powering up with n11
-
TIME INTERRUPT MODE
T
l
y
a
e
r
-up and
c
e
ingT
n
t
d
h
i
g
h
,
th
en
t
h
e
N
A
ND
t
e
s
t
mo
d
e
i
s
i
o
k
e
d.
i
n
d
e
r
high.
D test mode, all digital inputs may be testes
d a
a NAND ee t
r
e
b
y
t
I
N
T_Clear bit in the ConfigurationRegister.
/
N
U
T
w
i
e
n
c
e
n
I
n
t
e
v
e
n
t
h
a
s
o
c
c
u
r
r
e
d
o
s
T
en
u
t
n
I
n
t
w
i
l
l
n
o
t
o
c
c
u
r
a
g
a
i
n
u
n
t
i
l
t
h
e
pe
e
N
A
N
D
Rev. 2 | Page 15 of 22 | www.onsemi.com
940
r
a
R
e
g
i
s
t
e
r
c
o
n
t
r
o
l
s
t
h
e
mo
ng lo
s
t
.
DM9240. Setting Bit 0 low stops the monitoringloop
n
d
h
e
h
the ADM9240 into a low power mode therebeduc-
y r
s s
th any register in the ADM9240 while in low
b
e
t
o
g
g
l
e
d
a resulting toggle can be ob
power conption. Serial bus communication itill pos-
r a typical propagation delayof500ns.
s
t
h
g
u
ister enables or disables the INT
A1
I
n
u
p
t
o
u
t
p
u
t
.
S
e
t
t
i
n
g
B
i
t
1
h
i
g
h
e
n
a
b
l
e
s
t
h
e I
N
T
utt,
SDA
SCL
e
g Bit 1 low disables the output.
FAN1
FAN2
VID0
VID1
VID2
VID3
VID4
i
t
o
n
t
i
e
g
r
i
s
u
s
e
d
l
e
a
hen set high. The ADM9240 monitoring
n
c
op until Bit 3 is set low. Interrupt Register
NTEST_OUT
o
n
n
ill not be affected.
B
i
the Conguration Register is used to initiateamini-
gue 3. NAND Tree
u
R
s
s
t
e
:
I
f
a
n
y
o
f
t
h
e
i
n
p
u
t
s
s
h
o
w
n
i
n
F
i
g
u
r
e
9
a
r
e
u
n
is nabled by t 7 in egister 44.
ount a a
Bi 6 of the Configuration Register is used to resetthe Chassis
k
T
h
i
s
ill allow the ATE(AutomaticTestEquip-
I
n
u
s
io
n (CI) output pin when set high.
e NAan
Bi 7 of the Configuration Register is used to startaConfigura-
t
i
Register Initialization when taken high.
USING THE ADM9240
A
R
NVERSIO
R
-
n
i
t
o
r
i
n
g
f
u
n
c
t
i
o
n analog inputs, temperaturndfan
e a
e C
bl(Bit 1)
e
n
w
e
r
i
s
f
i
r
s
t
a
p
p
l
i
e
d
,
t
h
e
A
D
M
9
2
4
0
p
e
r
f
o
r
m
s
a
s)
st
eg
-
s
p
in the ADM9240 is started by writing to thonfura-
o
n
se
e
er
a
n
d
s
e
t
t
i
n
g
t
a
r
t
(
B
i
t
0
)
,
h
i
g
h
,
l
i
a
r (Bit 3) low. Apart from initially starting
i
u
e
a
n
d
L
i
m
i
t
R
eg
s
t
e
r
ADC
e
e
a
n
a
l
o
g
m
e
a
s
u
r
e
m
e
n
t
s
a
n
d
f
a
n
s
p
e
e
d
m
e
asu
r
e
m
e
n
t
s
n
s
,
u
h
e
f
i
r
ion after
r
d
e
p
e
n
d
e
n
t
l
y
a
n
d
ar
e
no
t
s
y
n
c
h
r
on
i
z
e
d
in
any
w
a
y
.
o
l
i
m
i
t
s
i
n
to
t
h
e
L
im
i
t
R
rs.
Th analog measurements will be completed in no morethan
P
o
w
e
a
r
i
n
t
i
a
l
i
z
es
t
h
e
f
o
l
l
o
w
i
n
g
t
e
r
s (the
3
5
µ
time taken to complete the fan speed measurements
i
n
l
u
s
wn in Table VI:
nds on the fan sper of acho output pulses
–
Confiti
volution.
–
Sial AddressRegister
the measurements have been completed, the resultscanbe
– Interrupt (INT) Status Registers #1 and #2
V
a
l
u
e
R
e
– Interrupt (INT) Mask Registers #1 and #2
–
V
I
D
/
F
a
n
D
i
v
i
r Regi
IV shows themeasurementsequencefor the analog inputs.
–
VID4 Regist
–
Chassis Intrusion Clear Register
–
Temperature Configuration R
–
Test Regist
Parameter
–
Compatibi
log +V
–
A
l
o
g
ut Register
log +12
log +5
I
a
I
log +3.3
i
g
r
a
t
i
o
n
R
e
g
i
s
t
I
N
I
T
I
A
L
I
Z
A
T
I
O
N
p
e
r
f
o
r
m
s
a
s
i
log +2.5
i
d
t
i
u
n
log +
o
Output Register are not initialized.
s
y clears after being set
i
g
u
r
a
t
i
o
n
R
e
g
i
s
t
INITIALIZATIONisaccomplished
o
n
high. This
o.
R AND SHUTDOWN MODE
t
i
be cein a low power mode by se
s
a
f.
the ConfigurationRegister
B
i
t
0
t
o
n
0 This dislethe inter-
ab
9240 is provided through the Conguration
fi
s
h
u
t
w
n
e
n
a
c
settin
T
h
e
A
D
C
i
s
s
t
o
p
p
e
d
p
on
ow
e
r
-
u
p
an
d
t
h
e
0
o
f
t
h
e
T
t
e
t
o
s
o
f
an
a
l
i
s
a
s
s
e
r
t
e
d
,
c
l
e
a
r
i
n
g
t
h
e
u
t
.
h
e
C
o
n
f
i
g
u
r
a
t
i
on
nin , but it
ster is d stop the ADM9240; enleordis-
ab
the condition ofanyoftheregisters. The evice w
ts and modes, and provide th
s
d
e
s
c
r
i
b
a
Rev. 2 | Page 16 of 22 | www.onsemi.com
940
PLICATION CIRCUI
s
h
o
w
s
a
g
e
n
e
r
i
c
a
p
p
l
i
c
a
t
he
.
T
h
e
a
n
a
l
o
g
m
o
n
i
t
n
p
u
t
s
ed to the
wesuppli
D
in
T
e aretwotachoinputsfromfans,andtheanalo
e speed of athird fan.Achassisintrus n
tch with an opto-sensor is conneCI input
urse, in an actual application,
s
e
,
i
n
w
h
i
c
h
c
a
s
e
u
uts should
log or digital ground as appropriate.
+3.3V
+3.3V
+12V
VID0
VID1
VID2
VID3
NTEST_OUT/A0
A1
FROM VID PINS
OF PROCESSOR
DA
SERIAL B
SCL
1N914
1N914
FAN1
FA2
+3.3V
VID4
CMOS
BACKUP
BATTERY
MRD901
74HC132
510⍀
+V
CCP1
00k⍀
510⍀
510⍀
CI
ADM9240
+2.5V
+3.3V
470k⍀
IN
DD
IN
10k⍀
10F .1F
510⍀
510⍀
510⍀
+5V
IN
+3.3V
V
CC
INT
+12V
IN
+1
NTEST_IN/AOUT
+V
CCP2
2N2219A
OP295
82k⍀
GNDA
RESET
10k⍀
gue . ppication Circuit
Rev. 2 | Page 17 of 22 | www.onsemi.com
940
Re
N
a
me
R
of ADM9240 Registerstables below fo
i
s
t
e
r
0
0
0
0
0
0
0
0
Setting Bit 0 of this regterto1selects
is
d
o
w
n
m
o
d
e
.
u
t
Nwri
i
n
t
h
V
a
l
u
g
O
u
t
p
u
t
11111111
2
.
5
V
M
e
a
s
V
a
l
u
e
I
n
d
e
t
e
r
m
i
n
a
t
e
R
e
a
d
Only
V
M
I
R
e
a
d
Only
2
2
h
+
3
.
3
V
M
e
a
s
u
r
V
I
n
a
t
e
R
e
a
d
Only
2
3
h
+
5
V
M
e
a
s
u
r
e
d
t
e
r
m
i
n
a
t
e
R
e
a
d
Only
2
4
h
+
1
2
V
M
d
V
a
l
u
e
I
n
d
e
t
e
r
m
i
n
a
t
e
R
e
a
d
Only
2
5
h
V
m
i
n
a
t
e
R
e
a
d
Only
2
6
d
nderminate
2
7
I
n
d
e
t
e
r
m
i
n
a
t
e
R
e
a
d
Only
2
8
g
I
n
d
e
t
e
r
m
i
n
a
t
e
R
e
a
d
Only
9
g
I
n
d
e
t
e
r
m
i
n
a
t
e
R
e
a
d
nly
A
d
eminate
2
B
2
.
5
V
H
i
g
h
L
i
m
i
t
Indeterminate
2
C
+
2
.
5
V
L
o
w
L
i
m
i
t
Indeterminate
D
H
i
g
L
i
m
i
t
Indeterminate
E
+
L
L
i
m
terminae
2
F
h
+
3
.
3
V
H
i
g
h
L
im
it
Indeterminate
3
0
h
+
3
.
3
V
L
o
w
L
i
m
i
t
Indeterminate
3
1
h
+
5
V
H
i
h
L
Indeerminate
L
t
Indeterminate
h
m
i
t
Indeterminate
t
ndeterminate
3
5
h
V
h
t
Indeterminate
3
6
o
w
L
i
m
determinate
3
7
d
nd erminate
8
d
nd erminate
9
o
t
i
t
(
H
i
)
Indeterminate
A
m
i
t
(
o
w
Indeterminate
B
C
o
u
n
t
L
i
Indeterminate
C
F
2
F
a
n
Indeterminate
3
D
Indeterminate
3
E
C
o
m
p
a
n
y
I
D
N
u
m
b
e
r
0
0
1
0
0
0
1
1
Thislocationwillcontaithe company
c
a
t
i
o
n
n
u
m
b
e
r
(
R
e
a
d
Only).
the revision
3
F
h
R
o
n
N
um
b
e
r
D
i
e
R
e
v
i
s
i
on
T
h
i
s
l
o
c
a
t
i
o
n
w
i
l
l
c
on
n
u
m
b
e
r
o
f
t
h
e
p
a
r
t
.
(
R
d
4
0
h
C
o
n
R
0
0
See Table VII
4
1
h
I
n
t
r
u
I
N
T
S
t
a
t
u
e
r
n
t
e
r
u
p
t
u
s
R
e
g
i
s
t
2
0
0
0
0
0
0
0
0
See Table X
N
1
0000
N
2
0
0
0
0
0
0
ee Table XI
4
5
h
C
o
m
p
a
t
i
b
i
l
i
R
e
g
i
s
t
e
r
0
0
0
0
0
0
0
0
See Table XII
4
6
h
C
h
a
s
s
i
s
I
n
t
r
u
s
i
o
n
l
e
Re
g
i
s
t
e
r
0
0
0
0
0
0
0
0
See TableXIII
4
7
h
V
3
/
F
a
n
D
i
v
i
g
i
s
t
e
r
0
1
0
1
(
V
I
D
3
–
V
I
D
0
)
See bleXIV
Ta
XVII
S
i
a
l
)
S
XV
V
(VI
e
C
f
i
g
u
r
a
t
o
n
T
Rev. 2 | Page 18 of 22 | www.onsemi.com
9240
W
Description
/W
g
i
1
e
n
l
e
s
s
t
a
r
t
u
o
f
A
D
M9
2
4
0
,
L
o
g
i
c
0
p
l
a
c
e
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t
in
s
t
a
n
d
b
y
m
o
d
e
.
C
a
u
t
i
o
n
:
the
ou
t
-
e
I
n
t
e
r
t
p
i
h
e
u
s
e
r
w
r
i
t
e
s
a
z
e
r
o
t
o
t
h
i
s
l
o
c
a
t
i
o
n
ter an
o
c
I
N
b
e
g
i
n
l
l
l
o
w
l
i
t
h
to tng
/
g
i
1
e
n
l
e
t
h
e
u
t
1 = Enabled 0 = Disabled (Power-UpDefault 0).
2
R
3
I
N
_
C
l
e
a
r
R
W
D
u
I
r
ue
r
v
i
c
e
R
o
u
t
i
n
e
h
(
I
S
R
t
)
t
h
i
s
b
i
t
i
s a
at
s bit. (Powe
s
s
e
r
t
e
d
g
i
a
r I
N
output
w
i
t
o
u
t
a
f
f
e
i
n
g
t
h
e
c
o
n
t
e
n
t
s
o
f
t
e
I
n
e
r
r
u
p
t
S
t
i
n
I
w
i
e
4
R
E
S
E
T
R
/
W
C
r
e
a
t
e
a
R
E
S
E
(
o
L
o
w
s
i
g
n
a
l
f
o
r
2
0
ms
m
i
n
i
mu
m (Power-Up Default=0).
T
h
i
r
d
n
c
e
se goes active.
5
R
/W
Default = 0.
6
C
I
_
R
e
s
e
t
R
A
“
1
”
o
u
t
p
u
t
s
a
m
i
m
20
ms
a
c
t
i
v
e
low
p
u
l
s
e
on
the
C
h
a
ss
I
n
t
r
u
s
i
on
p
i
n
. (Power-Up
D
e
f
a
u
l
t
=
0
.
)
his bt performs the same functionasBit n Register 46h)
7
I
/W
Logic 1 restores power-up default values to the Coiguration register, Interrupt status regis-
nf
er
ce ower-on efault is zero.
t
e
I
nM
a
s
k
R
e
g
i
s
t
e
r
s
,
F
a
n
D
i
v
i
s
o
r
R
e
g
i
s
t
a
n
a
u
t
om
a
t
i
c
a
l
l
y
c
l
e
a
r
s
i
t
s
e
l
f
s
i
n
W
De
ion
5
V
_
E
r
r
o
r
R
e
a
d
O
n
l
y
A “1” indicates a high or low t has been exceeded.
o
r
R
e
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ly
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6
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A “1” indicates a high or low limit hasbeenexceeded.
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d.
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n
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A
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one
d.
d.
Note: Any time the STATUS Register is read out, the conditions (i.e., Register) that are read are automatically reset. In the case of the channel priority indication, if
two or more channels were out of limits, another indication would automatically be generated if it were not handled during the ISR. In the Mask Register, the errant
voltage interrupt may be disabled until the operator has time to clear the errant condition or set the limit higher/lower.
Rev. 2 | Page 19 of 22 | www.onsemi.com
940
T
N
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R W
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The VID[3:0]inputsfrom processorcore power supplies to indicate the
o
p
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r
a
t
i
n
ltage (e.g.3 V 3.5 V).
SeCou er Prescaler for FAN1 Speed Measurement
4
–
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:
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Divideby8
Rev. 2 | Page 20 of 22 | www.onsemi.com
940
s (Bits 0 and 1 are Set by A0, A1 and Bit 7 Oy)
t
N
a
me
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6
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om P
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d/
/W If Bit 0 and Bit 1 of this register are both zero one,this selects the default
RestPor-On Default = 01h)
W
Description
0
H
o
t
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e
m
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a
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r
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he temperature goes above
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e
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e
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o
t
l
i
m
i
t
.
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h
e
i
n
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e
r
r
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un
t
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t t
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t
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e
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o
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s
p
o
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d
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b
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l
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th
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it
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o
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.
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a
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r
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u
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a
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a
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or
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s)
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i
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s
a
n
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w
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r
e
go
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s
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el
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,
w
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n
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i
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tive
2
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e
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e
r
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e
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e
a
d/W
r
D
e
t = 00000
e
a
d
o
n
l
y
LSof Temperature Reading = 0.5
Rev. 2 | Page 21 of 22 | www.onsemi.com
940
E NSIONS
Dimensions shown in inches and (mm).
(
R
U-24)
24
13
12
1
.05)
N 1
.
ATING
E
0.20)
ORDERING GUIDE
Model
Temperatue Range
0to +125°C
-°C to +12C
-40°C to +5°
Paagcrit
4-LaSSOP
24ead TSSOP
-Lead TSSOP
24-Lead TSSOP
Package Option
ADM9240ARUR
ADM920ARUEEL7
ADM9240ARU1
RU-24
RU-24
RU-24
1
ADM924-R71
-40°C to 1
RU-24
1Z = Pb-Free part
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
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